{"ref":"refs/heads/master","commits":[{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"Removed all mentions of the 'overrange' port for the ASIAA ADC.\n\nThis port is left over from when Homin ported the iADC code; it's\nnot used and in fact not even supported by the board itself. In\naddition, the UCF pin constraints were colliding with the SPI reset\npin.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/45e360f49466c453c6f1057ed2cd729180ebeda5","sha":"45e360f49466c453c6f1057ed2cd729180ebeda5"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"Fixed a missing semi-colon discovered by Srikanth!\n\nThe DMUX 1:1 pcore should now compile successfully on ROACH 1, however\nI have not yet tested this in hardware.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/109356ff37c94aa78cf66247d1cc4b7a6fbf9219","sha":"109356ff37c94aa78cf66247d1cc4b7a6fbf9219"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"Fixed bug in ADC5G simulation logic (found by Srikanth).\n\nThis was incorrectly transforming the sim_{a,b} inputs from the\nrange [-1, 1) to [-BW+1, BW+1) which was then being truncated to\n[0, BW], this losing half the data. BW = 2^(adc_bit_width)\n\nThis has been fixed by changing the initial gain value to BW/2 =\n2^(adc_bit_width)-1 and the bias value to BW/2 as well. This should\nput the incoming simulation data in the correct range. Thanks to\nSrikanth for finding this.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/a47ada2f07de6bec66745bc6479a0b350a6c0326","sha":"a47ada2f07de6bec66745bc6479a0b350a6c0326"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"The DWE port on the MMCM for the ROACH2 DMUX 1:1 version had wrong default.\n\nThis needs to be kept in mind when migrating the DMUX 1:2 version to ROACH2.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/c13a06e0ec43a04481be803f936a0662c6964ff7","sha":"c13a06e0ec43a04481be803f936a0662c6964ff7"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"The 5G yellow block clock rate is now the physical clock frequency applied to the board.\n\nNote: this is the clock frequency provided over the clock in SMA connector\nand is not the actual sample rate. The sample rate depends on whether you are\nusing the boards in one- or two- channel mode, i.e. on how many cores you are\ninterleaving.\n\nAt some point this will be made clear in the Wiki and the yellow block\ndocumentation itself.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/03ab76cb90f9a4aa7d023d5f04d91c8b34d866f3","sha":"03ab76cb90f9a4aa7d023d5f04d91c8b34d866f3"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"The 5GSps yellow block now passes down the ADC input frequency to the pcore.\n\nThis is passed down to the PLL/MMCM which uses it to determine whether the VCO and\nPFD are within their operating ranges. An error will occur now during a build if\nthe specified frequency won't work with the fixed MMCM parameters. There is no\nquick fix for this but at least you get an error instead of being allowed to\nimplement the design.\n\nI will attempt to create a coregen script to generate appropriate PLL/MMCM\nparameters given the ADC input clock frequency and requested fabric clock rate.\n\nNote: in this commit I have also remove all DCM instantiations in favor of PLLs.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/9aa1ba7a4703d8cbaaba1f180e4c6f9383d676c6","sha":"9aa1ba7a4703d8cbaaba1f180e4c6f9383d676c6"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"Forgot to add the ROACH 1, DMUX 1:2 MPD file for 5GSps.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/fd4a42640644433218736ffca26501c323efd5dc","sha":"fd4a42640644433218736ffca26501c323efd5dc"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"Fixed pin constraint of SPI reset port for 5GSps ADC.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/84aee96a12de3f274dc1429c298a2f6f85c4d303","sha":"84aee96a12de3f274dc1429c298a2f6f85c4d303"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"Added flip-flops and a AREA_GROUP constraint for DMUX 1:2, ROACH 2 version.\n\nOne of the ZDOK pins is traced to a input/output pad that is on the other\nside of the FPGA from all the other data pins. This causes a problem occasion-\nally during place and route. To fix this I placed buffers (currently only in\nthe DMUX 1:2 core) before the core's output and used an AREA_GROUP constraint\nfor the outlying pin to place its buffer close to the pad.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/0930084948495148cb1140377c2d32380aa89205","sha":"0930084948495148cb1140377c2d32380aa89205"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"The ADC5G block still remains to be added to xps_library.\n\nMerge remote branch 'github/master'\n\nConflicts:\n\txps_library/xps_library.mdl","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/65ee7035c0ff96e22c3b687e30d93724097e1928","sha":"65ee7035c0ff96e22c3b687e30d93724097e1928"},{"author":{"name":"Rurik A Primiani","email":"377ceb2426fafd981b18a59da0ab691798a1c85c@cfa.harvard.edu"},"message":"Re-added the ASIAA 5Gps ADC yellow-block after the last merge.","url":"https://api.github.com/repos/sma-wideband/mlib_devel/commits/a2c0ba75ff9172885d7902f9cf52d4fa8581a48c","sha":"a2c0ba75ff9172885d7902f9cf52d4fa8581a48c"}],"head":"a2c0ba75ff9172885d7902f9cf52d4fa8581a48c","size":11,"push_id":49102928}