{"shas":[["5694e5c5df710322e145b34d9e56b0a1dfadbd30","a0515f392997f1b311cff3b900549f6eb4bad912@gmail.com","Modifications on  hpdmc to support 16 bit memories (not working), changes on bootloader to use burst length of 2, bootloader modified to execute a routine to adjust automatically the idelay and dqs_clk phase. Delay on hpdmc_ddrio is implemented using LUTs(spartan3 doesnt has a dedicated blok). IDDR2 and ODDR2 implemented using flip-flops due to problems on synthesis. LCD controller added. fmlbrg modified to support 16 bit memories. Another fmlbrg was made. included entity 16_bit_interface to make an interface between fml bus and the ddr controller. Some files of lm32 processor were modified in order to made simulations","Carlos Alfredo Barreto Suarez"]],"repo":"carlobar/milkymist","actor":"carlobar","ref":"refs/heads/master","size":1,"head":"5694e5c5df710322e145b34d9e56b0a1dfadbd30","actor_gravatar":"480b2f0c4c501c0d7448332d5cf78bee","push_id":30451258}