{"issue":{"created_at":"2011-12-01T05:09:34Z","state":"closed","updated_at":"2011-12-12T04:24:58Z","comments":1,"user":{"gravatar_id":"ad04b6e8d77dce1d1f6a27379a2a2fde","id":138719,"url":"https://api.github.com/users/cospan","login":"cospan","avatar_url":"https://secure.gravatar.com/avatar/ad04b6e8d77dce1d1f6a27379a2a2fde?d=https://a248.e.akamai.net/assets.github.com%2Fimages%2Fgravatars%2Fgravatar-140.png"},"body":"Somehow a clock master must be implemented.\r\n\r\nAs it is right now certain cores will not function correctly with any clock that is different than 50MHz\r\n\r\nPossible solutions:\r\n\r\n-always generate a 50MHz clock with something like a digital clock manager\r\n-find a way to 'tell' each core what the clock rate is... there must be something that defines this somewhere like a `define CLOCK_RATE or something... I could make a script that determines the clock rate from the constraints file\r\n\r\nThere are multiple cores that depend on a specific clock rate.","assignee":{"gravatar_id":"ad04b6e8d77dce1d1f6a27379a2a2fde","id":138719,"url":"https://api.github.com/users/cospan","login":"cospan","avatar_url":"https://secure.gravatar.com/avatar/ad04b6e8d77dce1d1f6a27379a2a2fde?d=https://a248.e.akamai.net/assets.github.com%2Fimages%2Fgravatars%2Fgravatar-140.png"},"id":2411194,"pull_request":{"patch_url":null,"html_url":null,"diff_url":null},"number":4,"labels":[],"title":"Clock Agnostic problem","html_url":"https://github.com/cospan/Sycamore_FPGA/issues/4","closed_at":"2011-12-12T04:24:58Z","url":"https://api.github.com/repos/cospan/Sycamore_FPGA/issues/4","milestone":null},"action":"created","comment":{"created_at":"2011-12-12T04:24:58Z","updated_at":"2011-12-12T04:24:58Z","user":{"gravatar_id":"ad04b6e8d77dce1d1f6a27379a2a2fde","id":138719,"url":"https://api.github.com/users/cospan","login":"cospan","avatar_url":"https://secure.gravatar.com/avatar/ad04b6e8d77dce1d1f6a27379a2a2fde?d=https://a248.e.akamai.net/assets.github.com%2Fimages%2Fgravatars%2Fgravatar-140.png"},"body":"Changed the gen_project_defines.py to extrapolate the clock information from the .ucf file. so far so good, the code could be polished so it will read the clock more reliably, but right now it reads two different types of clock in put.\r\n\r\nThe old PERIOD version which Xilinx is depreciating that method.\r\nThe newer TIMESPEC version with or without \"quotes\"","id":3101945,"url":"https://api.github.com/repos/cospan/Sycamore_FPGA/issues/comments/3101945"}}