{"shas":[["17f91d21a764603b9c482338e929390565f3bb72","6050ac38e168b9c48bd260f485ec2f5d125e78d6@apple.com","indvars -disable-iv-rewrite: ExprToMap lives in Pass data, so be more\ncareful about referencing values.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134537 91177308-0d34-0410-b5e6-96231b3b80d8","Andrew Trick"],["231a5ab746ca12000aa57208869a98f78781aa6b","429f501a9f7229f3ca0d9b531c9e5abf0c812b93@apple.com","Simplify. Consolidate dbg.declare handling in AllocaPromoter.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134538 91177308-0d34-0410-b5e6-96231b3b80d8","Devang Patel"],["806fcc040e0bc7962891f12d6e09fc86f0bc2184","01cbceb5bfe9a58ceeedb41a4f8d0878230a1bc5@apple.com","Don't require pseudo-instructions to carry encoding information.\n\nFor now this is distinct from isCodeGenOnly, as code-gen-only\ninstructions can (and often do) still have encoding information\nassociated with them. Once we've migrated all of them over to true\npseudo-instructions that are lowered to real instructions prior to\nthe printer/emitter, we can remove isCodeGenOnly and just use isPseudo.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8","Jim Grosbach"],["d1689ae4b1ae5af191f71dcb9c59640a6dca7ebc","01cbceb5bfe9a58ceeedb41a4f8d0878230a1bc5@apple.com","Mark ARM pseudo-instructions as isPseudo.\n\nThis allows us to remove the (bogus and unneeded) encoding information from\nthe pseudo-instruction class definitions. All of the pseudos that haven't\nbeen converted yet and still need encoding information instance from the normal\ninstruction classes and explicitly set isCodeGenOnly, and so are distinct\nfrom this change.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134540 91177308-0d34-0410-b5e6-96231b3b80d8","Jim Grosbach"],["298bc9a1a5161a5f6e5a0f35e8372d008ef6e812","3b9de09f2ff76afe9f0ad4fcae4ff68f52ec7fc4@mxc.ca","Add ImmutableList::contains(). Patch by Rui Paulo!\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134545 91177308-0d34-0410-b5e6-96231b3b80d8","Nick Lewycky"],["ed5e3552147830159a1d48d067dfbb49ac9cccfd","e78ac4148f37cf8527ceb02a7033f8e1e003a2f0@apple.com","Rename files for consistency.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134546 91177308-0d34-0410-b5e6-96231b3b80d8","Evan Cheng"],["78a9f138ae95458bf6d922f38706eed045691d5a","e78ac4148f37cf8527ceb02a7033f8e1e003a2f0@apple.com","Add ARM MC registry routines.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8","Evan Cheng"],["4fd3c5957e6a272b60d6446e745136187d07f812","429f501a9f7229f3ca0d9b531c9e5abf0c812b93@apple.com","Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to one alloca.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134549 91177308-0d34-0410-b5e6-96231b3b80d8","Devang Patel"],["9cbd7afb76f20ce874464c238764c54f86b3ce3b","c42303dc6c60847c4d174a1be2a4f1194758543f@mac.com","Fix a subtle issue in SmallVector.  The following code did not work as expected:\n  vec.insert(vec.begin(), vec[3]);\nThe issue was that vec[3] returns a reference into the vector, which is invalidated when insert() memmove's the elements down to make space.  The method needs to specifically detect and handle this case to correctly match std::vector's semantics.\n\nThanks to Howard Hinnant for clarifying the correct behavior, and explaining how std::vector solves this problem.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134554 91177308-0d34-0410-b5e6-96231b3b80d8","Owen Anderson"],["882e1e1c5d157a8bb2f001f2f4cacf0f0dd722a3","34e6c836575097c76965abe8873967ccff230386@apple.com","Grammar and 80-col.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134555 91177308-0d34-0410-b5e6-96231b3b80d8","Eric Christopher"],["2b2dc7c4bee01071410df0e3027117b47ce48ced","c456a2ba6ff3668d0a5bd99e46971965bfca48bb@gmail.com","Clean up the #includes.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134557 91177308-0d34-0410-b5e6-96231b3b80d8","Bill Wendling"],["a462d6e8ebe90f3732891b02a057a88038ac1228","429f501a9f7229f3ca0d9b531c9e5abf0c812b93@apple.com","Typo.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134559 91177308-0d34-0410-b5e6-96231b3b80d8","Devang Patel"],["90369eb209f5cfa52d683f4248b4c0a9cfd9b916","429f501a9f7229f3ca0d9b531c9e5abf0c812b93@apple.com","Remove dead code.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134561 91177308-0d34-0410-b5e6-96231b3b80d8","Devang Patel"],["66c9ee7e6d7072a5ecc0131b9dd78a20e72cb597","01cbceb5bfe9a58ceeedb41a4f8d0878230a1bc5@apple.com","Typo.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134563 91177308-0d34-0410-b5e6-96231b3b80d8","Jim Grosbach"],["a38cfb2fceb266bd78164021c08284dc59a1e8a3","8e0d94695c8087496e207d45916b5a6b810661a9@gmail.com","When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors.  They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF).\n\nUnfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.\n\n<rdar://problem/9716278>\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134565 91177308-0d34-0410-b5e6-96231b3b80d8","Eli Friedman"],["447c40c4028f1563826ea75f47fd3ec48c7a74ad","1edd93eee514ac2f5b15beb2e9b2ef164ef8aa9c@apple.com","Fix a bug in the \"expect\" intrinsic lowering.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134566 91177308-0d34-0410-b5e6-96231b3b80d8","Jakub Staszak"],["a4acb008cb2a9953d9cb4c90ecf6424bd32ebc0c","429f501a9f7229f3ca0d9b531c9e5abf0c812b93@apple.com","Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134568 91177308-0d34-0410-b5e6-96231b3b80d8","Devang Patel"],["94ca42ff0407d71bacc41de4032d8dbe6358d33d","e78ac4148f37cf8527ceb02a7033f8e1e003a2f0@apple.com","Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8","Evan Cheng"],["7986289a9cc99b45941adf98c64e6f3dbbc917cc","429f501a9f7229f3ca0d9b531c9e5abf0c812b93@apple.com","Add DEBUG messages.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134572 91177308-0d34-0410-b5e6-96231b3b80d8","Devang Patel"],["d0626aaccaeeaabbd32687e1d3f963e4d7555b0a","74486463aa8344ad78208a26153a7177f8db5983@gmail.com","Added a testcase for PR10220.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134573 91177308-0d34-0410-b5e6-96231b3b80d8","Lang Hames"]],"ref":"refs/heads/master","size":41,"head":"2091a0d8d2070e183c37757c4f9a5ecc512fd376","push_id":35983352}