{"shas":[["91b8efb876c65fd36660fb5d26302965dd8e8085","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","OMAP: Voltage: ABB notifiers should handle errors\n\nomap_voltage_get_voltdata returns error codes if target voltage does not\nmatch any voltage in the existing voltage table.  ABB voltage notifiers\npreviously did not handle these errors and such cases would cause a bad\naddress look-up and a panic.  Handle these errors and return early with the\nsame error code.\n\nChange-Id: Iec41ac65d66d7b8c0db54a7f6ad05e8b717e54de\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["282cfbf40538a22a1171219c7d6b6dfa9711698c","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","OMAP: Voltage: get_voltdata verbose error handling\n\nUnify error string onto one line, change verbage from incorrect \"current\nvoltage\" to \"target voltage\" and print the intended target voltage.\n\nChange-Id: Iaea0b9ed42d5f99b8cf93ec61fefea7943f9d4fa\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["3bd6c21794f70dd2c8dfe87750cf320c31e71375","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","OMAP4: OPP: add OPP_LP data for DPLL cascading\n\nDPLL cascading is a unique low power mode in which DPLL_ABE is driven by\nSYS_32K_CK, DPLL_CORE is driven by DPLL_ABE and all other DPLLs are driven\nby DPLL_CORE.  This allows SYS_CK to be gated and the entire system runs at\nlower clock frequencies while consuming less power.\n\nIn this configuration not all clock frequencies for each device are\nsupported.  Some devices simply should not run in this mode, others at\nreduced rate and a special few are unaffected.  Consult the PRCM functional\nspec for more detailed info.\n\nThe OPP data now has an OPP_LP entry for each device in the table.  These\nOPPs are disabled by default and are mutually exclusive with the other OPPs:\nonly during DPLL cascading mode will they be enabled while all of the\n\"normal operation\" OPPs are disabled.  When leaving DPLL cascading mode the\nOPP_LPs are again disabled and the \"normal operation\" are enabled.  This\nprevents the DVFS framework from exploding and respects the current\nlimitations of the system.  Specifically, DVFS transitions will not occur\nand clock frequencies will be reported properly in the clock framework.\n\nChange-Id: Icac891c166dc30e44750c029773fda656004bb92\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["1fc5def9dd6c22417c37cb34113ce0b49c076d60","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","ASoC: OMAP: use correct frequencies for AESS rate\n\nAESS clock is derived from DPLL_ABE running at 196.608MHz, which yields\npotential AESS clock frequencies of 98.304MHz and 49.152MHz.  Previous OPP\ndata truncated these frequencies into 98MHz and 45MHz.  Since OPP data has\nbeen updated so must the rate requested in the driver.\n\nChange-Id: Iadf5290521a7be35308c733cd22a6542d3c8a092\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["fba7d663c5289aca463eea9b9a571663f8a52b5b","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","OMAP: OPP: verbose error msg while setting rate\n\nSpecify the device name in the error message for instances where the\nfrequency found in the OPP look-up does not match the target frequency.\n\nChange-Id: I5c8d96d18fc9192e53f3c2705e346fe1a2e8a7fe\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["46e0627d84b4bc4090752f55b4df9fbdacb5ea1d","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","OMAP: Voltage: get_nom_volt verbose error message\n\nInclude the name of the voltage domain when reporting that the actual\nfrequency does not match the one in the table.\n\nChange-Id: I9e92935f12503514e9b16dfa0077189ad10d134a\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["2485521e3b9aa07fd9887cb24dd2bac9c9924a84","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","FIXME: OMAP4: OPP: add LP mode OPPs to the table\n\nLots of crap debug prints.  Not sure if these changes are even needed.\n\nChange-Id: Ide91061f77361cbc01cc297fdda55ceb041fce7c\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["24cdef854743490fa203fad2f3a5978251c39afa","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","HACK: OMAP4: prevent DVFS transitions in LP mode\n\nThis hack creates mutual exclusion between DVFS transitions via the\nomap_device_set_rate API and the DPLL cascading Low Power mode.  Once in\nDPLL cascading mode all calls to omap_device_set_rate will abort with no\nchange to clock frequencies.  Normal operation is restored after exiting\nDPLL cascading.\n\nChange-Id: I96bb9db035858c81a65bbfb0f07e6ce6cbed6f6f\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["175513bf497801be155cc74d34cfae305027a422","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","OMAP: OPP: allow searching for disabled OPPs\n\nThe comments for opp_find_freq_exact claim that it can search for enabled or\ndisabled OPPs.  This was not actually implemented in the code until now.\n\nChange-Id: I9543937b9e2852cf419f328fa4f901c2252548eb\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["ca0e7967a72efd5b6fa3e912e3eb88fdd874eac1","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","HACK: omap4_lpmode global flag & lots of DPLL_CORE re-locking struggles\n\nChange-Id: Ifde07679dd801f15ecf0231975729527765ca68e\nSigned-off-by: Mike Turquette <mturquette@ti.com>","Mike Turquette"],["d08a8620130c5a131e34677770b3063c19a3e86e","6dab61939fc5e23761050a66932f032dceda5ebf@ti.com","saving lots of work\n\nChange-Id: I22fb1e6720beee5676f96e6523e6c12cd49ca2e3","Mike Turquette"]],"repo":"mturquette/linux-omap","actor":"mturquette","ref":"refs/heads/p-android-omap-2.6.35-dpllcascadev10","size":11,"head":"d08a8620130c5a131e34677770b3063c19a3e86e","actor_gravatar":"351b5f1f519d6470646105bc62f51f0f","push_id":23994003}