{"shas":[["ad377c630864e2609c54385907493dbf68a34295","3883f8aab0424a154a3bcb43ff874b819786efbe@pengutronix.de","arm: mxs: include asm/processor.h for cpu_relax()\n\nI get this build error as of today:\n\narch/arm/mach-mxs/ocotp.c: In function 'mxs_get_ocotp':\narch/arm/mach-mxs/ocotp.c:54: error: implicit declaration of function 'cpu_relax'\nmake[2]: *** [arch/arm/mach-mxs/ocotp.o] Error 1\n\nLooks like it has been indirectly included before which broke now.\nInclude it directly.\n\nSigned-off-by: Wolfram Sang <w.sang@pengutronix.de>\nCc: Shawn Guo <shawn.guo@freescale.com>\nSigned-off-by: Sascha Hauer <s.hauer@pengutronix.de>","Wolfram Sang"],["5f85e931278ff80aa3ea7861a73a6c6ce940f2e9","288a049a20dc4091188b72022d411ad1375e6737@gmail.com","ARM: mx51/sdma: Check the chip revision in run-time\n\nCheck the MX51 chip revision in run-time so that the correct SDMA firmware can\nbe loaded.\n\nWhile at it also remove the silicon revision from the sdma_script_start_addrs\nstructure name for MX51. All the MX51 revisions share the same SDMA start addresses.\n\nSigned-off-by: Fabio Estevam <fabio.estevam@freescale.com>\nSigned-off-by: Sascha Hauer <s.hauer@pengutronix.de>","Fabio Estevam"],["7416401661fad5c7ee9edb17cb54e7bff7a74dfe","00e4cf8f46a57000a44449bf9dd8cbbcc209fd2a@linutronix.de","arm: davinci: Fix fallout from generic irq chip conversion\n\nThe code which does the chained handler setup was overwriting\nchip_data.\n\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>\nTested-by: Holger Hans Peter Freyther <holger@freyther.de>\nSigned-off-by: Kevin Hilman <khilman@ti.com>\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","Thomas Gleixner"],["7e9f1945213cdd7cd11f29346ded07a81854b5af","946cfb81282bb55c59f600e7ee3d3b2c6973f7a3@ti.com","davinci: make PCM platform devices static\n\nMake the PCM device structures used in devices.c\nand devices-da8xx.c static as they are used only\nin the respective files.\n\nThis was found when trying to build a single image\nfor DaVinci and DA8x devices using runtime P2V support.\n\nSigned-off-by: Sekhar Nori <nsekhar@ti.com>","Sekhar Nori"],["07989b7ad63af424886ff922fd3bcca9e00ffa78","f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","Revert \"ARM: 6943/1: mm: use TTBR1 instead of reserved context ID\"\n\nThis reverts commit 52af9c6cd863fe37d1103035ec7ee22ac1296458.\n\nWill Deacon reports that:\n\n In 52af9c6c (\"ARM: 6943/1: mm: use TTBR1 instead of reserved context ID\")\n I updated the ASID rollover code to use only the kernel page tables\n whilst updating the ASID.\n\n Unfortunately, the code to restore the user page tables was part of a\n later patch which isn't yet in mainline, so this leaves the code\n quite broken.\n\nWe're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW\nfrom ARM, so lets revert these until we can properly sort out what we're\ndoing with the ARM context switching.\n\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Russell King"],["a0a54d37b4b1d1f55d1e81e8ffc223bb85472fa3","f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","Revert \"ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks\"\n\nThis reverts commit 45b95235b0ac86cef2ad4480b0618b8778847479.\n\nWill Deacon reports that:\n\n In 52af9c6c (\"ARM: 6943/1: mm: use TTBR1 instead of reserved context ID\")\n I updated the ASID rollover code to use only the kernel page tables\n whilst updating the ASID.\n\n Unfortunately, the code to restore the user page tables was part of a\n later patch which isn't yet in mainline, so this leaves the code\n quite broken.\n\nWe're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW\nfrom ARM, so lets revert these until we can properly sort out what we're\ndoing with the context switching.\n\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Russell King"],["6075e9df471e35f2ebf4c73c95c304d0473bd4b2","9cd9d802d23c0ed5e224beabf4ae4a5c478746ef@linaro.org","ARM: 6949/2: mach-u300: fix compilaton warning in IO accessors\n\nThe IO accessors for U300 were using u32 rather than the nominal\nvoid __iomem * type, rectify this by properly defining the\nvirtual base for statically mapped peripherals to be\nvoid __iomem *. Requires fixing a field in struct clk as well.\n\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Linus Walleij"],["f506cd48a4236b7045d092c9b92709ae6b4bdaf0","408789a210b05fb3b46935e815320d62ba00a06e@linaro.org","ARM: 6953/1: DT: don't try to access physical address zero\n\nIf the DT physical address is zero, this is equivalent to no DT.\nEspecially when the actual RAM physical address is not located at zero,\nthe result of phys_to_virt() would point to la-la-land and crash the\nkernel, which crash is completely silent this early during boot.\n\nSigned-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>\nAcked-by: Grant Likely <grant.likely@secretlab.ca>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Nicolas Pitre"],["720c60e1943a06cfd9472ad5a9967dec304e4394","408789a210b05fb3b46935e815320d62ba00a06e@linaro.org","ARM: 6954/1: zImage: fix Thumb2 breakage\n\nCommit af3e4fd37a \"ARM: 6859/1: Add writethrough dcache support for\nARM926EJS processor\" broke Thumb2 compilation by omitting to maintain\nthe wide encoding for the added branch instructions which made the\nARM926EJ-S record smaller than expected, breaking the record walk code.\n\nSigned-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>\nCc: Mark A. Greer <mgreer@mvista.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Nicolas Pitre"],["373ce3020b03fb6199415ab866595c7d627bbc97","714421683462ba013f284525618577dbb214b1a6@faraday-tech.com","ARM: 6955/1: cmpxchg syscall should data abort if page not write\n\nIf the page to cmpxchg is user mode read only (not write),\nwe should simulate a data abort first.\n\nSigned-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>\nAcked-by: Nicolas Pitre <nicolas.pitre@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Po-Yu Chuang"],["a9011580a99cd4f21546381782582bfaf9e40675","f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","ARM: extend Code: line by one 16-bit quantity for Thumb instructions\n\nDump out the following 16-bit instruction to the faulting instruction\nin the Code: line.  This allows Thumb-2 instructions to be properly\nencoded.\n\nTested-by: Kevin Hilman <khilman@ti.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","Russell King"],["09e1e9c4a4009a75c1dd716b6f0797fae3ab4dfd","f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes","Russell King"],["099b4d3b473db012a55ce6bec9ef594d0508e782","f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","Merge branch 'davinci-next' of git://gitorious.org/linux-davinci/linux-davinci into fixes","Russell King"],["9559ec9bee650988819f406e3f4e8d06156efc81","f6aa0246ff943bfa8602cdf60d40c481b38ed232@arm.linux.org.uk","Merge branches 'fixes', 'misc' and 'pgt' into for-next","Russell King"],["ac356fea7e94a457bdf6c4a1f53afdd4accc225b","f0d4d86d9c7002e67e6ae7bb5596bc0afa7b4c3a@true.cz","ARM: ep93xx: force nF bit on\n\nARM clocking mode is determined by the iA(31) and nF(30) bits, which are\nusually set correctly by the bootloader or bootrom. If it is not set, then the\nCPU core will run from HCLK instead of FCLK, and performance will suffer. It's\nquite common case on some of the ts72xx boards.\n\n[LOCAL, not for mainline!]\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>","Petr Štetiar"],["bd2c80c26bf61116ce548ea27cc643b98951f032","f0d4d86d9c7002e67e6ae7bb5596bc0afa7b4c3a@true.cz","ARM: ep93xx: fix possibly wrong machine id passed from bootloader\n\nIn the early days Technologic Systems failed horribly and shipped some boards\n(ts-72xx and ts-7800 are well known examples) with broken bootloaders, so\nthey've passed wrong machine id to the kernel.\n\nWe're trying to fix it with this patch in a way, that if we detect the wrong\nmachine id 0x163 we force it to correct machine id 0x2a1 (ts72xx).  Maybe,\nthat there are some other wrong numbers in the wild, so the code might need\nsome more tweaking.\n\n[LOCAL, not for mainline!]\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>","Petr Štetiar"],["39fdca098e3e28bb619901637848898821e719c8","f0d4d86d9c7002e67e6ae7bb5596bc0afa7b4c3a@true.cz","ARM: ep93xx: add partial sparsemem support\n\nSome boards, like for example ts-7300 with 128MB RAM as it seems can't be used\nwith flat memory model correctly. This patch adds possibility to choose\nbetween flat/sparse memory models in kernel config and adds missing sparse\nmemory bits for ep93xx.\n\nPatch is based on the previous discussion and code:\n\n\thttp://marc.info/?l=linux-arm&m=122754446724900&w=2\n\nI've tested this patch on the boards with 32MB and 128MB RAM.\n\n[LOCAL, not for mainline!]\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>","Petr Štetiar"],["98ee01117b53b35c80e2813369fb127e596ca3b7","f0d4d86d9c7002e67e6ae7bb5596bc0afa7b4c3a@true.cz","ARM: ep93xx: use more reliable CPLD watchdog for reset on ts72xx\n\nOn all ep93xx based boards from Technologic Systems, there's CPLD watchdog\navailable, so use this one to reset the board instead of the soft reset in\nCPU.  I've seen some weird lockups with the soft reset on ep93xx in the past,\nwhile the reset via CPLD watchdog seems to be rock solid (tm) and works fine\nso far.\n\nCc: Ryan Mallon <ryan@bluewatersys.com>\nAcked-by: H Hartley Sweeten <hsweeten@visionengravers.com>\nSigned-off-by: Petr Štetiar <ynezz@true.cz>","Petr Štetiar"],["b822e943c1d661242591f15a427bf4a699a167eb","f0d4d86d9c7002e67e6ae7bb5596bc0afa7b4c3a@true.cz","ARM: ep93xx: add model detection for ts-7300 and ts-7400 boards\n\nCc: Ryan Mallon <ryan@bluewatersys.com>\nCc: Hartley Sweeten <hsweeten@visionengravers.com>\nSigned-off-by: Petr Štetiar <ynezz@true.cz>","Petr Štetiar"],["148f4900c22fa75f15958e7854f4db798cb248bf","f0d4d86d9c7002e67e6ae7bb5596bc0afa7b4c3a@true.cz","ARM: ep93xx: increase NR_BANKS to 16 for support of 128MB RAM\n\nI've got hands on one ts-7300 board, which is equiped with 128MB RAM in two\n64MB memory chips, so it's 16 banks/8MB each. Without this patch, the bootmem\ninit code complains about small NR_BANKS number and only lower 64MB is\naccessible.\n\nCc: Russell King <linux@arm.linux.org.uk>\nCc: Hartley Sweeten <hsweeten@visionengravers.com>\nCc: Ryan Mallon <ryan@bluewatersys.com>\nSigned-off-by: Petr Štetiar <ynezz@true.cz>","Petr Štetiar"]],"ref":"refs/heads/ts72xx-wip","size":42,"head":"131dbb3a50a43cb6eb1c3a83fac03072ce4b6adf","push_id":33714396}