{"ref":"refs/heads/devel","commits":[{"author":{"name":"Johannes Winter","email":"a4eae5f4795141255450569390bb8d533d7a7c2b@iaik.tugraz.at"},"url":"https://api.github.com/repos/jowinter/qemu-trustzone/commits/506ea63f2f5df0d4504a8e6bc55ade0847d8ba18","message":"Merge branch 'github-devel' into github-next","sha":"506ea63f2f5df0d4504a8e6bc55ade0847d8ba18"},{"author":{"name":"Johannes Winter","email":"a4eae5f4795141255450569390bb8d533d7a7c2b@iaik.tugraz.at"},"url":"https://api.github.com/repos/jowinter/qemu-trustzone/commits/6012cee1f8bdb22134dbd4279e424eb340fe177a","message":"Complain loudly on attempts to write the Interrupt Status Register.\n\nThanks to Andreas Niederl for catching this one.","sha":"6012cee1f8bdb22134dbd4279e424eb340fe177a"},{"author":{"name":"Johannes Winter","email":"a4eae5f4795141255450569390bb8d533d7a7c2b@iaik.tugraz.at"},"url":"https://api.github.com/repos/jowinter/qemu-trustzone/commits/32ba183874bfa630d9edcbb1a9b1c02d3bd54395","message":"Explicitly flush translation blocks on CPSR.M state change ...","sha":"32ba183874bfa630d9edcbb1a9b1c02d3bd54395"},{"author":{"name":"Johannes Winter","email":"a4eae5f4795141255450569390bb8d533d7a7c2b@iaik.tugraz.at"},"url":"https://api.github.com/repos/jowinter/qemu-trustzone/commits/95394864a679f20d3fd6946c18232976789c5098","message":"BUGFIX: ARM TrustZone: Properly handle the CP15 TLS registers in the translator.\n\nThis patch adds properly handling of secure/nonsecure world register\nbanks to the dynamic translator. The previous code only considered\nbanked registers which were implemented by means of helper functions\nin target-arm/helper.c.\n\nThe previous patches missed the CP15 TLS registers (which are directly\nhandled in the translator for efficieny reasons) which causes\nguests like modified Linux kernels or TU Dresden's Fiasco L4 micro-kernel\nto fail without this bugfix.","sha":"95394864a679f20d3fd6946c18232976789c5098"}],"head":"95394864a679f20d3fd6946c18232976789c5098","size":4,"push_id":49687323}