{"shas":[["2e3734e2d948af7c61c1957742811cdfca0e2516","e11ac465acb63ba34b2760c15a5e9874aa05e685@google.com","Fix asserts in CodeGen from:\n\n  assert(\"error\");\n\nto:\n\n  assert(0 && \"error\");\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139449 91177308-0d34-0410-b5e6-96231b3b80d8","Richard Trieu"],["543376743c900806109c75d4fd12c4ba01020cfe","6050ac38e168b9c48bd260f485ec2f5d125e78d6@apple.com","Set NSW/NUW flags on SCEVAddExpr when the operation is flagged as\nsuch.\n\nI'm doing this now for completeness because I can't think of/remember\nany reason that it was left out. I'm not sure it will help anything,\nbut if we don't do it we need to explain why in comments.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139450 91177308-0d34-0410-b5e6-96231b3b80d8","Andrew Trick"],["20151da8c38287b9fa181e9fef93f70bc2cd9fd2","6050ac38e168b9c48bd260f485ec2f5d125e78d6@apple.com","[disable-iv-rewrite] Allow WidenIV to handle NSW/NUW operations\nbetter.\n\nDon't immediately give up when an add operation can't be trivially\nsign/zero-extended within a loop. If it has NSW/NUW flags, generate a\nnew expression with sign extended (non-recurrent) operand. As before,\nif SCEV says that all sign extends are loop invariant, then we can\nwiden the operation.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139453 91177308-0d34-0410-b5e6-96231b3b80d8","Andrew Trick"],["2db8628085e92dc76852a922ab50bd3b76a5824f","e11ac465acb63ba34b2760c15a5e9874aa05e685@google.com","Fixed an assert from:\n\n  assert(\"not implemented for target shuffle node\");\n\nto:\n\n  assert(0 && \"not implemented for target shuffle node\");\n\nThis causes a test failure in CodeGen/X86/palignr.ll which has\nbeen marked as XFAIL for the time being.\nTest failure filed at PR10901.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8","Richard Trieu"],["81cbb0ad608af0839471b8d41ceac64047b41d68","e11ac465acb63ba34b2760c15a5e9874aa05e685@google.com","Fix the asserts in lib/Target/X86/X86ELFWriterInfo.cpp and\nlib/ExecutionEngine/MCJIT/MCJIT.cpp from:\n\n  assert(\"error\");\n\nto:\n\n  assert(0 && \"error\");\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139456 91177308-0d34-0410-b5e6-96231b3b80d8","Richard Trieu"],["106f6e7a27a055a353afecf395504dd7fa609f80","8e0d94695c8087496e207d45916b5a6b810661a9@gmail.com","r139454 activates an assert in a case where we were doing the right thing anyway.  Make that explicit, and un-XFAIL the testcase.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139458 91177308-0d34-0410-b5e6-96231b3b80d8","Eli Friedman"],["cfeb55cdbc48bafac63a79ea86eb66aca982e2a1","8e0d94695c8087496e207d45916b5a6b810661a9@gmail.com","Really un-XFAIL the testcase, like I said I would in r139458.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8","Eli Friedman"],["fbad25e12073e2cbe192b2c4cc4f0bbb26148c9c","bdd017bb4fbb7b247c96f2e2b7576634f75537bf@intel.com","CR fixes per Bruno's request.\n\nUndo the changes from r139285 which added custom lowering to vselect.\nAdd tablegen lowering for vselect.\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8","Nadav Rotem"],["5366ca4e06fc00efb3ce7d0841c4c66789fbddeb","3b9de09f2ff76afe9f0ad4fcae4ff68f52ec7fc4@mxc.ca","Fix verb tense agreement.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139480 91177308-0d34-0410-b5e6-96231b3b80d8","Nick Lewycky"],["e4481d8ce5aa333b0dc43f307bc8fb47c694e3e2","3b9de09f2ff76afe9f0ad4fcae4ff68f52ec7fc4@mxc.ca","s/SequeuentiallyConsistent/SequentiallyConsistent/g\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139481 91177308-0d34-0410-b5e6-96231b3b80d8","Nick Lewycky"],["842f58f9be82e1a0d2751e7982ef3641829acf87","0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8","Craig Topper"],["038197988bcd7619657633da7116c7292187d4ae","0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8","Craig Topper"],["136046c9a2dcb9b5bf539e6c6fcf100c68f9e621","0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8","Craig Topper"],["5ed098320029cfa6d26a46a13f333588aa18b6a7","bdd017bb4fbb7b247c96f2e2b7576634f75537bf@intel.com","Format patterns, remove unused X86blend patterns\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139491 91177308-0d34-0410-b5e6-96231b3b80d8","Nadav Rotem"],["2cb6c1bd20ddcf27da5fb50a8a74a97a9d3010fb","320bca71fc381a4a025636043ca86e734e31cf8b@xmos.com","Mark LDWCP as having no side effects.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139494 91177308-0d34-0410-b5e6-96231b3b80d8","Richard Osborne"],["a1d16b53e847a97846ad5df293ae1cfc3091a092","320bca71fc381a4a025636043ca86e734e31cf8b@xmos.com","Associate a MemOperand with LDWCP nodes introduced during ISel.\n\nThis information is required if we want LDWCP to be hoisted out of loops.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8","Richard Osborne"],["3d4ec14ffc6b957b9418578567a5751ef6f80fdb","9e01571d0adae2c18b4ca0578f54335c0bc01b66@2pi.dk","Update comments to reflect some (not so) recent changes.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139498 91177308-0d34-0410-b5e6-96231b3b80d8","Jakob Stoklund Olesen"],["708d06f7fb5dfd9c8559aea07b042a88c65645f8","9e01571d0adae2c18b4ca0578f54335c0bc01b66@2pi.dk","Add an interface for SplitKit complement spill modes.\n\nSplitKit always computes a complement live range to cover the places\nwhere the original live range was live, but no explicit region has been\nallocated.\n\nCurrently, the complement live range is created to be as small as\npossible - it never overlaps any of the regions.  This minimizes\nregister pressure, but if the complement is going to be spilled anyway,\nthat is not very important.  The spiller will eliminate redundant\nspills, and hoist others by making the spill slot live range overlap\nsome of the regions created by splitting.  Stack slots are cheap.\n\nThis patch adds the interface to enable spill modes in SplitKit.  In\nspill mode, SplitKit will assume that the complement is going to spill,\nso it will allow it to overlap regions in order to avoid back-copies.\nBy doing some of the spiller's work early, the complement live range\nbecomes simpler.  In some cases, it can become much simpler because no\nextra PHI-defs are required.  This will speed up both splitting and\nspilling.\n\nThis is only the interface to enable spill modes, no implementation yet.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139500 91177308-0d34-0410-b5e6-96231b3b80d8","Jakob Stoklund Olesen"],["a16a25ddeaf495b78b04e2a19feeac00d9824e63","9e01571d0adae2c18b4ca0578f54335c0bc01b66@2pi.dk","Remove the -compact-regions flag.\n\nIt has been enabled by default for a while, it was only there to allow\nperformance comparisons.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139501 91177308-0d34-0410-b5e6-96231b3b80d8","Jakob Stoklund Olesen"],["5443140021291121a1e9d11cc4d74428f259cd6f","429f501a9f7229f3ca0d9b531c9e5abf0c812b93@apple.com","Add DW_ATE_UTF, which clang started using in my previous commit!\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139503 91177308-0d34-0410-b5e6-96231b3b80d8","Devang Patel"]],"ref":"refs/heads/master","size":49,"head":"b5a457c4cbc71db6ae313ef1bf8eadac65767ab0","push_id":42492607}