{"shas":[["7691b48f7a47ed2b78f61ad68cd1a074f557efcf","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[CORE] Simplified vmm_hyperthreads and renamed it to vmm_threads. The new threads are just wrapper around orphan vcpus. This helps us remove tick counting from scheduler. Now our scheduler is tickless. Only timer subsystem is not tickless. In future even timer subsystem will be tickless.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["8cf55d2074e6f1e37d073a3df77f05bf05b5da8f","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[ARM] Updated ARM code to refect recent changes in implementation of hypervisor threads.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["1a1f95da6dbce790e21dbbc1ac0c773b8a62eba6","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[MIPS] Updated MIPS code to refect recent changes in implementation of hypervisor threads.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["5aa1881a31c60dbae8349861783c74793d2e4bce","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[CORE] Renamed vcpu number to vcpu id and guest number to guest id.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["fe52fabaf1cea2ad6e713516c023c304d8ce9c5e","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[EMULATORS] Update GIC emulator since vcpu number is now vcpu id.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["1fb051b4bd71d04a62da0bb09112b891562b836d","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[ARM] Fixed ARM code since vcpu number is now vcpu id.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["4ab9cac37cf3d2cb8a8821da519e8e7ceeae0652","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[CORE] Converted all signed references to vcpu id as unsigned. Also converted all signed references of guest id as unsigned.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["9903edf499487e5e2af7a7ab72a455768708ba8f","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[CORE] Fixed event start/restart functions. This were broken for multiple events.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["a330e5a6d164e5c67ef747db1de1701ecf7bfa90","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[ARM] Enabled two sp804 timer chips for Realview PB-A8 guest.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["f6c172dedc11495965e11d88b8219c56ab53d179","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[EMULATORS] Fixed sp804 timer emulator.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["e2be54b236aa3d69339e5d6088e9c7e01a1c1e2b","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[TESTS] Added support for reading time stamp in ARM test code.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["8caf29b49834409e663637da093488df1954cf96","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[TESTS] Updated ARM test code to support testing 'dhrystone 2.1' benchmark.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["3cd46cd4f4ed9e85dbde0a96e47e983546194118","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","[ARM] Updated ARM Realview PB-A8 DTS to increase buffer size of emulated UART.\n\nSigned-off-by: Anup Patel <anup@brainfault.org>","Anup Patel"],["a08ff4ebd7f825d4096c715d26329f85681fe284","8adb89029e19fc97b8d434cacc549347a87c0d95@brainfault.org","Merge pull request #36 from avpatel/master\n\nReplaced hyperthreads with simple hypervisor threads which are just a wrapper around orphan VCPUs. Added dhrystone in ARM test code.","Anup Patel"]],"ref":"refs/heads/master","size":14,"head":"a08ff4ebd7f825d4096c715d26329f85681fe284","push_id":39541828}