{"shas":[["0be7395e52c6366ce5818ab79be426edf740d9a1","6b31706989f3cf9466bfddbf48eab0c43e646ba8@gmail.com","Improve the handling of available_externally and llvm.global_ctors.","Rafael Espindola"],["0d9a6c1ea164234ae2b1197b9ab9eb98249c0283","34e6c836575097c76965abe8873967ccff230386@apple.com","Recommit r132764 since it didn't cause the windows buildbot failures.","Eric Christopher"],["6f5ff126f23178d1b7d0d2397b218abc46352b44","34e6c836575097c76965abe8873967ccff230386@apple.com","Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.","Eric Christopher"],["0e99f2fc17302dc1a79282c9071e5a94853b42e9","f972eb75d8fdce639ae72b4a758235ac085f358b@apple.com","Update CREDITS.TXT","Howard Hinnant"],["3f074575ad5f1f371c114b176c779291671f0938","9e01571d0adae2c18b4ca0578f54335c0bc01b66@2pi.dk","Remove custom allocation order boilerplate that is no longer needed.\n\nThe register allocators automatically filter out reserved registers and\nplace the callee saved registers last in the allocation order, so custom\nmethods are no longer necessary just for that.\n\nSome targets still use custom allocation orders:\n\nARM/Thumb: The high registers are removed from GPR in thumb mode. The\nNEON allocation orders prefer to use non-VFP2 registers first.\n\nX86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.\n\nSystemZ: Some of the allocation orders are omitting R12 aliases without\nexplanation. I don't understand this target well enough to fix that. It\nlooks like all the boilerplate could be removed by reserving the right\nregisters.","Jakob Stoklund Olesen"],["9b6d1afdb5d423d1cb709107d8b76c4fdc881526","dc51b16d27fbf10f33a2eb03e4a8e0980c8c8d30@apple.com","Add special-case range checking for VCVT_N intrinsic immediate operands.\nRadar 9558930.","Bob Wilson"],["8fd679ae83102663e535cbb4924b31a9f4c29590","dc51b16d27fbf10f33a2eb03e4a8e0980c8c8d30@apple.com","Add isVCVT_N flag to identify Neon VCVT_N intrinsics, which require special\nrange checking for immediate operands.  Radar 9558930.","Bob Wilson"],["5b73cf502e14416b641a444552bb08e3fdffe811","8800578b51f022c8d8adb9606a8b3db4fedbdac6@hanshq.net","Handle overloaded operators in ?: precedence warning\n\nThis is a follow-up to r132565, and should address the rest of PR9969:\n\nWarn about cases such as\n\nint foo(A a, bool b) {\n return a + b ? 1 : 2; // user probably meant a + (b ? 1 : 2);\n}\n\nalso when + is an overloaded operator call.","Hans Wennborg"],["9db2545a6ffcb862e2c618514fbcf4f95ffffd90","ca1b4e7c79c91422c3710135b78dfed0c674e2be@gmail.com","Added dg.exp to run FrontendC ARM-dependent tests; updated inline-asm-multichar.c test per this change.","Galina Kistanova"],["dc9ee0dcaa24aad224c215a3f16d168c23151a23","9e01571d0adae2c18b4ca0578f54335c0bc01b66@2pi.dk","Move TableGen's register bank classes to their own source file.\n\nI'll be moving some more code there to gather all of the\nregister-specific stuff in one place. Currently it is shared between\nCodeGenTarget and RegisterInfoEmitter.\n\nThe plan is that CodeGenRegisters can compute the full register bank\nstructure while RegisterInfoEmitter only will handle the printing part.","Jakob Stoklund Olesen"],["2b25bcebd7f9abc71a9edcc56b3a3b08a0734dcb","8e0d94695c8087496e207d45916b5a6b810661a9@gmail.com","Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.","Eli Friedman"],["245cfa66061c2eb8dcd76846eccc61a64acd11f9","12a98d018cc93a9f7eff075874242d90b0c3cee7@gmail.com","Remove an uneeded switch - Turns out reloc results are identical w/o the switch. (face+palm)","Jason W Kim"],["85fc6d6da89270cc6b5158e01d57e2d3b588ff13","821deb8805920bd073fd43c65afe4bc0baeae628@apple.com","Don't add objc method name mangling to locally declared function.\n// rdar://9566314","Fariborz Jahanian"],["0742b39723aef662bb6309737524b0ae67faee1a","8e0d94695c8087496e207d45916b5a6b810661a9@gmail.com","Revert 132789; it breaks tests.  My mistake.","Eli Friedman"],["7f45f2d02296015b1de5928ff6580000ea26ca05","d279088d79e357a153f8842902bcfc9d630ff5da@apple.com","Teach the CallGraph to ignore calls to intrinsics.","John McCall"],["3aebcee50dbe96700a8fa6b67ee26a9ad4dcb2e5","6b31706989f3cf9466bfddbf48eab0c43e646ba8@gmail.com","Refactor some checks into shouldTailDuplicate. Update comments.\nNo functionality change.","Rafael Espindola"],["273eba2c09428081cd5bb6d04ac05cf48052b4de","d279088d79e357a153f8842902bcfc9d630ff5da@apple.com","SplitCriticalEdge can sometimes split the edge from an invoke to a landing\npad, separating the exception and selector calls from the new lpad.  Teaching\nit not to do that, or to properly adjust the CFG afterwards, is out of\nscope because it would require the other edges to the landing pad to be split\nas well (effectively).  Instead, just recover from the most likely cases\nduring inlining.  The best long-term solution is to change the exception\nrepresentation and commit to either requiring or not requiring the more\ncomplex edge-splitting logic;  this is just a shorter-term hack.","John McCall"],["4c3a4deeeeb445bc93b31b631b072d0653d907d3","9d09450497b788fbc3f2861a336ffc776f8c892b@apple.com","Modify comment.","Johnny Chen"],["fc998659a5c9c5c78c3df4d81cbe842354a06d67","4f485a834a7b9fdaf713f4952822ad5bbbdb817b@free.fr","Avoid unused variable compiler warnings when assertions are\ndisabled.","Duncan Sands"],["e19a3fe7fb60ca47bbafea284c0c0b9eb19c5efa","2918cc624e3ca9d2a97173f546da76025d31e3c5@freebsd.org","Fix emission of PPC64 assembler on non-darwin platforms by splitting\nVK_PPC_{HA,LO}16 into darwin and gas variants.\n\nDarwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.","Roman Divacky"]],"ref":"refs/heads/chapuni","size":48,"head":"b4a7437a82fbdac205a130134de018ca5802931d","push_id":33722767}