{"shas":[["daac3974cb5552e6defef1d22e842cc2feaf6c3f","ee7c400e20ae7342b7ed2e541b29d3b8c7bd2d7c@gmail.com","moved a lot of files around. Added a roadmap for V 1.0 release\nstarted working on the master test bench. I got the rough idea out, but its gonna take some work to get the TEST BENCH debugged\nI might need a simulation wishbone slave, might be able to simulate the wishbone simulation slave right in the test bench... that might be the best approach becuase I can see the signals going in and out\n\nneed to figure out how to write a Makefile that will conditionally call all the simulations if I wanted to, as well as conditionally compile.\nIt is the goal that I can just run \"make sim\" and watch the test results come back, if there is a failure then I can go there and fix it.","Dave McCoy"],["3d4554da209d67765319997c69ac4c5e7f35d7d6","ee7c400e20ae7342b7ed2e541b29d3b8c7bd2d7c@gmail.com","forgot to add these files and folders","Dave McCoy"]],"ref":"refs/heads/master","size":2,"head":"3d4554da209d67765319997c69ac4c5e7f35d7d6","push_id":35776313}