{"shas":[["868c04205c3859a816593595aa513ee603f736ad","f2295d84e358395675bc8031be58672073ae065e@redhat.com","r600g: add workaround for buggy hw scissor on eg/cayman.\n\nThis is ported from the same fix to the DDX.\n\nSigned-off-by: Dave Airlie <airlied@redhat.com>","Dave Airlie"],["017cd5dcc36816e7aef5a7810b8a79d5c8ef777d","bf84f557a1e54fd62cd73c6847f7d9df60e9fbef@gmail.com","r600g: fix eg/cayman scissor workaround\n\nSigned-off-by: Alex Deucher <alexdeucher@gmail.com>","Alex Deucher"],["c44dad559af88c40bb8e626fe293319966d14394","bf84f557a1e54fd62cd73c6847f7d9df60e9fbef@gmail.com","egl_dri2: add new cayman pci ids\n\nSigned-off-by: Alex Deucher <alexdeucher@gmail.com>","Alex Deucher"],["a95ec18549b677b5e9912ca9e2c92df5cfef3b4e","4482611cc290c2ce1399431891dcb9221c95f994@redhat.com","glx: Don't refer to the request buffer outside of {L,Unl}ockDisplay\n\n... because that's not a safe thing to do.  The request buffer is shared\nstorage among all threads, and after UnlockDisplay the 'req' pointer may\npoint into someone else's request.\n\nNOTE: This is a candidate for the 7.10 branch.\n\nSigned-off-by: Adam Jackson <ajax@redhat.com>","Adam Jackson"],["76f77cb07edf9c6a548f782c709de70aa0a41458","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Add flags to intel_context for hiz and separate stencil\n\nAdd the following flags:\n    intel_context.has_separate_stencil\n    intel_context.must_use_separate_stencil\n    intel_context.has_hiz\n\nThe flags are currently set to false, and will be enabled for a given\nchipset once the feature is completely implemented.\n\nSince it may be some time before these features are completed, their\nvalues can be overridden with environment variables INTEL_HIZ and\nINTEL_SEPARATE_STENCIL. Valid values for these environment variables are\n\"0\" and \"1\".\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["4e0654ec2924c941fe03f57665fbf44e1b600db8","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","mesa: Add MESA_FORMAT_X8_Z24 to _mesa_choose_tex_format\n\nPrefer MESA_FORMAT_X8_Z24 over MESA_FORMAT_S8_Z24 for textures with\ninternal format GL_DEPTH_COMPONENT*.\n\ni965 needs MESA_FORMAT_X8_Z24 for HiZ and separate stencil.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["b5c847c7ca06823af3b72324056a2e478caca70b","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Change supported texture formats for separate stencil\n\nWhen hardware supports separate stencil, enable support for separate\ndepth/stencil texture formats in the table\nintel_context.ctx.TextureFormatsSupported. If the hardware must use\nseparate stencil, then disable support for combined depth/stencil formats.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["1a1411e09b23fce9977f7926dba4f1f0c8f3c5ec","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Allocate region for separate stencil buffer\n\n... in intel_alloc_renderbuffer_storage().  The stencil buffer has quirky\npitch requirements, so its region allocation is a special case.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["a9e65097855468529242f9076bd6ef2a6c8062c1","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Add is_hiz_depth_format() to intel_contex.vtbl\n\nGiven a format, is_hiz_depth_format() indicates if HiZ can be enabled on\na depthbuffer of that format.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["7c0e6d9bbc11f7802c81df048eb721b5e15e8ece","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Add hiz_region to intel_renderbuffer\n\nA hiz surface must be supplied to the hardware when rendering to a depth\nbuffer with hiz. There are three potential places to store that surface:\n    1. Allocate a larger intel_region for the depthbuffer, and let the\n       region's tail be the hiz surface.\n    2. Allocate a separate intel_region for hiz, and store it as\n       brw_context state.\n    3. Allocate a separate intel_region for hiz, and store it in\n       intel_renderbuffer.\n\nWe choose method 3.\n\nMethod 1 has not been chosen due to future complications it might cause\nwhen requesting a DRI drawable's depth buffer attachment from X.\n\nMethod 2 has not been chosen because storing the hiz region apart from\nthe depth region makes lazy hiz/depth resolves difficult to implement.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["6ed829fe5063f61f1ab2fcb39a441e17d89e622c","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Refactor the wrapping of textures with renderbuffers\n\nBefore this commit, the renderbuffer's region was updated in\nintel_renderbuffer_texture(). This commit moves the update into\nintel_update_wrapper(), which is a more logical location for updates.\n\nThis is in preparation for the next commit, which allocates and\nupdates the texture's hiz region in intel_update_wrapper(). Having the two\nregion updates located in the same function makes good form.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["c270f1a628a625ccc9f6d931f2921e3d92c31818","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Add hiz_region to intel_mipmap_tree\n\nWhen a texture is attached to multiple FBO's, a separate renderbuffer\nwrapper is created for each attachment. This necessitates storing the hiz\nregion for these renderbuffers in the texture itself instead of the\nrenderbuffer wrapper.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["ce8fdf666fc14aa5b9672be1711dfc1c0039efd0","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Fix intel_draw_buffer() to accomodate hiz and separate stencil\n\nThe logic of intel_draw_buffers() expected that stencil buffers were\nalways combined depth/stencil.\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["e7bcfadc2255e3417e03676837d248f4976419e2","c34c009102e60d77975598e1f414f8a701c22d0b@chad-versace.us","intel: Change FBO validation criteria to accomodate hiz and seprate stencil\n\nReviewed-by: Eric Anholt <eric@anholt.net>\nSigned-off-by: Chad Versace <chad@chad-versace.us>","Chad Versace"],["5ed7a7b7205b5680d617b77a8cf228b80cf15f5e","bf84f557a1e54fd62cd73c6847f7d9df60e9fbef@gmail.com","r600g: remove duplicate opcode in r600_opcodes.h\n\nV_SQ_CF_WORD1_SQ_CF_INST_HALT is 0x1f on both\nevergreen and cayman.\n\nReported-by: Gustaw Smolarczyk <wielkiegie@gmail.com>\nSigned-off-by: Alex Deucher <alexdeucher@gmail.com>","Alex Deucher"],["fa42de5ad7ebbc0b81ce6ba0553742f0413690a7","96f164ad4d9b2b0dacf8ebee2bb1eeb3aa69adf1@anholt.net","i965: Fix assertion failures in unused brw_reg setup by deleting it.\n\nI was using undefined values to create an unused value.  Go me.\n\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37366\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","Eric Anholt"],["b5846865deb20c54e88c7c1a7c732d29e9c47975","96f164ad4d9b2b0dacf8ebee2bb1eeb3aa69adf1@anholt.net","i965: Warnings cleanup.\n\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","Eric Anholt"],["1697dac64294aab73052541dab6763d660d088dc","2a58f49788865949713c2d2b613178059f899d6a@gmail.com","i915g: Bump texture sizes\n\nSpotted and tested by Christopher Egert.\n\nSigned-off-by: Jakob Bornecrantz <wallbraker@gmail.com>","Jakob Bornecrantz"],["bf14ab417c6638afd19206e11ee69bdb9fb93d9e","3cb4e1df5ec4da2c7c4af7c52cec8cf340a55a10@vmware.com","st/mesa: fix incorrect texture level/face/slice accesses\n\nIf we use FBOs to access mipmap levels with glRead/Draw/CopyPixels()\nwe need to be sure to access the correct mipmap level/face/slice.\nBefore, we were just passing zero in quite a few places.\n\nThis fixes the new piglit fbo-mipmap-copypix test.\n\nNOTE: This is a candidate for the 7.10 branch.","Brian Paul"],["3e06803c2c6cf83009708b23d3ebafc0ea3dc525","3cb4e1df5ec4da2c7c4af7c52cec8cf340a55a10@vmware.com","st/mesa: simplify some st_context(ctx)->pipe code","Brian Paul"]],"ref":"refs/heads/master","size":1500,"head":"29d7a0bb16dba1416e3a63f7f44cf82e307ac46a","push_id":40425078}