{"ref":"refs/heads/mem-partitioning","commits":[{"author":{"email":"288bf2beed161fcf8f5e8861dd8b1f1ae01ccf5f@eecs.berkeley.edu","name":"Martin Maas"},"sha":"62b6facd00a32f78c8847dac8487ddcb713d349f","message":"Fixed bug in the lookup table (swapped arguments of MuxLookup) and started on adapting vlsi test harness for multiple lookup table SRAMs.","url":"https://api.github.com/repos/ericlove/oram-chisel/commits/62b6facd00a32f78c8847dac8487ddcb713d349f"},{"author":{"email":"288bf2beed161fcf8f5e8861dd8b1f1ae01ccf5f@eecs.berkeley.edu","name":"Martin Maas"},"sha":"a918a4b82ead321a08123b0ada060664cf278e25","message":"RTL simulation seems to work now!","url":"https://api.github.com/repos/ericlove/oram-chisel/commits/a918a4b82ead321a08123b0ada060664cf278e25"}],"head":"a918a4b82ead321a08123b0ada060664cf278e25","size":2,"push_id":53246275}