During the formation of replacement metal gates in the manufacture of semiconductor devices, the gate length of a cavity formed by the removal of a dummy gate may increase as a result of processing steps prior to formation of the replacement metal gate. For example, during removal of a gate oxide layer from the bottom surface of the cavity above a substrate layer, an oxidized spacer layer formed as a spacer surrounding the dummy gate and defining sides of the cavity may also be at least partially removed, thereby increasing the gate length of the cavity as compared to a designed target. By way of another example, during a high-k metal pre-cleaning, additional oxidized spacer layer may be removed further increasing the gate length. Depending on the process conditions, 3 to 4 nm of the oxide spacer layer may be removed during each one of the above two steps. Accordingly, the gate length may increase from 6 to 8 nm beyond the designed target. The increase in the gate length can impact other semiconductor device parameters. For example, the increased gate length may degrade the yield by increasing trench silicide to polysilicon gate shorts.
A need therefore exists for controlling the gate length of a replacement metal gate to a designed target, and the resulting device.