The present invention relates in general to a semiconductor device and in particular to a semiconductor device incorporating a gate voltage testkey for selectively programming isolation transistor gate voltage.
DRAM memory has enjoyed popular success over other types of memory technology because of its low cost and simple memory cell layout which promotes scalability. A DRAM memory cell is capable of storing one bit of information, and is constructed using only one memory cell transistor and one memory cell capacitor. As such, this memory cell is often referred to as a one-transistor one-capacitor (1T1C) cell. A collection of memory cells are grouped together in bitlines and wordlines, forming a memory array.
While device density in DRAM memory is limited by the resolution capability of available photolithographic equipment, it is also limited by the area consumed by each of the memory cells. Referring to FIG. 1, a memory structure 10 is comprised of a plurality of memory cells 12. As identified herein, the minimum area of a memory cell 12 is defined with reference to a feature dimension (F) which refers to the dimension that is half the wordline WL pitch (width plus space) or half the digitline DL pitch (width plus space). To illustrate the determination of cell area, a box is drawn around the memory cell 12. Along the horizontal axis H of the memory cell 12, the box includes one-half digitline contact feature 14, one wordline feature 16, one capacitor feature 18 and one-half field oxide feature 20, totaling three features. Along the vertical axis V of the memory cell 12, the box contains one half field oxide feature 22, one active area feature 24, and a second half oxide feature 26 totaling two features. The structure of the memory cell 12 results in its area being 3F.multidot.2F or 6FSupp2. To conserve space on a die, memory cell pairs 28 are defined by adjacent memory cells 12 that share a single bitline contact 30.
While the 6Fsupp2 array may be implemented as an open bitline as well as a folded bitline, early memory devices incorporated the open bitline configuration. In the open bitline architecture, each wordline connects to memory cell transistors on every bitline. This is sometimes referred to as a crosspoint style array. Referring to FIG. 2, a memory structure 100 is illustrated for an open digitline architecture. The memory structure 100 includes a plurality of memory cells 102. Each memory cell 102 is comprised of a capacitor 104, having a common node 106 biased at a voltage of Vcc/2 volts. The capacitor 104 typically represents a binary logic level one by a charge of +Vcc/2 volts, and a binary logic level zero by a charge of -Vcc/2 volts. Each memory cell 102 is further comprised of a transistor 108 having a first source/drain region 110, a second source/drain region 112, and a gate 114. The gate 114 of each transistor 108 connects to a wordline (WL) 116, 118, 120, 122, 124 and 126. Further, the first source/drain region 110 of each transistor 108 connects to a bitline (BL) 128.
As demands for higher capacity memory devices continue to increase, memory cells are placed closer together. However, where memory cells of a conventional 6 Fsupp2 array are packed too closely, adjacent memory cells may be affected by subthreshold leakage. Excessive subthreshold leakage may affect data integrity. In an attempt to resolve the problems that are attributable to the conventional 6 Fsupp2 array, the industry adopted an 8 Fsupp2 array where improved noise performance is realized by providing a twisted configuration. The 8 Fsupp2 memory array is created by tiling a selected quantity of memory cells together such that memory cells along a given bitline do not share a common wordline and such that memory cells along a common wordline do not share a common bitline. Any given wordline forms a memory cell transistor on alternating bitlines. This structure allows the formation of bitline pairs and ensures that wordline activation enables transistors only on alternate bitlines. Further, the 8 Fsupp2 provides improved noise performance, which is derived from the adjacency of true and complement bitlines and the capability to twist these bitline pairs. However, since the wordlines have to pass alternate memory cells as field poly, the size is increased by approximately 25%, or by 2 features. As such, the 8 Fsupp2 array does not provide the same degree of packing density seen in the 6 Fsupp2 array described above. As the demand for memory devices with larger capacity continues to increase, the larger array size provided by the 8 Fsupp2 array become a limiting factor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a 6 Fsupp2 area array with improved subthreshold leakage characteristics, which allows for a higher packing density thus more densely populated memories.