1. Field of the Invention
The present invention relates to a power operation device for performing a power operation on an input base bit string and an input exponent bit string. More particularly, it relates to a power operation device having an improved means for substantially increasing the operation speed of the device.
2. Description of the Prior Art
Referring next to FIG. 3, there is illustrated a block diagram showing the structure of a prior art power operation device as disclosed in Japanese Patent Application Publication (TOKKAIHEI) No. 10-207694. In the figure, reference numeral 24 denotes a logarithm operation unit, numeral 25 denotes a multiplier, numeral 26 denotes an exponential operation unit, numeral 27 denotes a shift unit, numeral 28 denotes a logarithm table, numeral 29 denotes an addition section, numeral 30 denotes a subtraction section, numeral 31 denotes an exponential table, and numeral 32 denotes a shift section.
In operation, after the shift section 27 divides a base bit string X applied thereto into its fractional part and its integer part, the logarithm operation unit 24 acquires the logarithm of the fractional part using the logarithm table 28 and the addition section 29 then generates a logarithmic base bit string from the logarithm of the fractional part and the integer part of the input base bit string X. The multiplier 25 then multiplies the logarithmic base bit string by an exponent bit string Y applied thereto, and furnishes the multiplication result to the exponential operation unit 26. In the exponential operation unit 26, the subtraction section 30 divides the multiplication result from the multiplier 25 into its fractional part and its integer part. The exponential operation unit 26 then computes an exponential value in a specific floating-point representation, the exponential value corresponding to the fractional part of the output of the multiplier 25, using the exponential table 31. The exponent shift unit 32 then generates the power operation result from the exponential value and the integer part of the multiplication result from the multiplier 25.
In this manner, the prior art power operation device can compute the logarithm of the base bit string X and transform the power operation with the base bit string X and the exponent bit string Y into the multiplication of the logarithm of the base bit string X and the exponent bit string Y, thus reducing the time required for acquiring the power operation result as compared with a prior art method in which the Yth power of X is computed by iterating an arithmetic operation using logarithm and exponent functions which are expanded into power series.
A problem with the prior art power operation device is that it processes all power operations in the same way, and therefore it cannot speed up the power computation process beyond the operation speed of the multiplier built in the prior art power operation device.
The present invention is made to overcome the above problem. It is therefore an object of the present invention to provide a power operation device capable of speeding up some specific power operations frequently used, thus substantially increasing the power operation speed of the device.
In accordance with one aspect of the present invention, there is provided a power operation device for performing a power operation on an input base bit string X and an input exponent bit string Y so as to compute XY, the device comprising: a logarithm operation unit for performing a base-2 logarithm operation on the input base bit string X and for furnishing a logarithmic base bit string corresponding to the base-2 logarithm of the input base bit string X; a multiplier for multiplying the logarithmic base bit string by either a bit string equivalent to the input exponent bit string Y or the input exponent bit string Y, and for furnishing a multiplication result as a first multiplication bit string; a bit operation unit for performing a bit shift operation on the logarithmic base bit string from the logarithm operation unit according to the input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a second multiplication bit string; an exponent checking unit for checking whether or not the input exponent bit string Y is the ith power of a base 2 where i is an integer, and for, if so, furnishing a selection signal to direct selection of the second multiplication bit string; a multiplication bit string selection unit for receiving both the first multiplication bit string from the multiplier and the second multiplication bit string from the bit operation unit, for selecting and furnishing the second multiplication bit string when it receives the selection signal from the exponent checking unit, and for selecting and furnishing the first multiplication bit string otherwise; and an exponent operation unit for performing a base-2 exponential operation on the selected first or second multiplication bit string from the multiplication bit string selection unit, i.e., computing 2Z where Z is the selected first or second multiplication bit string, and for furnishing the computed base-2 exponential value as the power operation result XY.
Preferably, the exponent checking unit checks whether or not the input exponent bit string Y is xc2xd, and furnishes the selection signal to the multiplication bit string selection unit if so. The bit operation unit then shifts the logarithmic base bit string from the logarithm operation unit right for one bit position and furnishes the shifted logarithmic base bit string as the second multiplication bit string to the multiplication bit string selection unit.
Preferably, the exponent checking unit checks whether or not the input exponent bit string Y is xe2x88x921, and furnishes the selection signal to the multiplication bit string selection unit if so. The bit operation unit then inverts the logarithmic base bit string from the logarithm operation unit and furnishes the inverted logarithmic base bit string as the second multiplication bit string to the multiplication bit string selection unit.
Preferably, the exponent checking unit checks whether or not the input exponent bit string Y is xe2x88x92xc2xd, and furnishes the selection signal to the multiplication bit string selection unit if so. The bit operation unit then shifts the logarithmic base bit string from the logarithm operation unit right for one bit position and further inverts the shifted logarithmic base bit string, and furnishes the shifted and inverted logarithmic base bit string as the second multiplication bit string to the multiplication bit string selection unit.
In accordance with a preferred embodiment of the present invention, the input base bit string X is a bit string in a certain floating-point representation, and the logarithm operation unit includes an argument processing section for computing the logarithm of an argument of the input base bit string X using a base-2 logarithm operation table, a characteristic processing section for subtracting a predetermined characteristic offset value from a characteristic part of the input base bit string X and for furnishing a subtraction result, and a fixed-point bit string generating section for generating the logarithm of a fixed-point base bit string corresponding to the input floating-point bit string X based on the logarithm of the argument of the input base bit string X from the argument processing section and the subtraction result from the characteristic processing section. The logarithm operation unit can furnish the logarithm of the fixed-point base bit string from the fixed-point bit string generating section as the logarithmic base bit string.
The logarithm operation unit can further include a fixed value holding section for holding the base-2 logarithm of the Napierian number, a base checking section for checking whether or not the input base bit string X is the Napierian number, and for furnishing a fixed value selection signal to direct selection of the base-2 logarithm of the Napierian number if so, and a base output selection section for receiving both the logarithm of the fixed-point base bit string from the fixed-point bit string generating section and the base-2 logarithm of the Napierian number from the fixed value holding section, and for selecting and furnishing the base-2 logarithm of the Napierian number as the logarithmic base bit string when it receives the fixed value selection signal from the base checking section and for selecting and furnishing the logarithm of the fixed-point base bit string as the logarithmic base bit string otherwise.
In accordance with another preferred embodiment of the present invention, the input exponent bit string Y is a bit string in a certain floating-point representation, and the power operation device further includes an exponent processing unit for converting the input exponent bit string Y into an equivalent exponent bit string in a certain fixed-point representation defined by the multiplier.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.