Cadence has prototyped an IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC. With this milestone, SoC providers developing high-speed memory subsystems for high-end server, storage and enterprise applications can start developing DDR5 memory subsystems now with silicon-tested PHY and controller IP from Cadence. The Cadence test chip was fabricated in TSMC’s 7nm process and achieves a 4400 MT/sec data rate, 37.5 percent faster than the fastest commercial DDR4 memory at 3200MT/sec. (Photo: Business Wire)