#include "includes.h"
__global__ void dwt_per_X_O(float *d_ip, int rows, int cols, int cA_cols, int filt_len, int Halo_steps, float *d_cL, float *d_cH)
{
extern __shared__ float s_Data[];

//Offset to the left halo edge
const int baseX = (blockIdx.x * 2 * X_RESULT_STEPS - Halo_steps) * X_BLOCKDIM_X + threadIdx.x;
const int baseX1 = (blockIdx.x * X_RESULT_STEPS) * X_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * X_BLOCKDIM_Y + threadIdx.y;

if (baseY < rows) {

d_ip += baseY * cols + baseX;
d_cL += baseY * cA_cols + baseX1;
d_cH += baseY * cA_cols + baseX1;

//Loading data to shared memory

//Load Left Halo
#pragma unroll
for (int i = 0; i < Halo_steps; i++)
{
if (baseX + i * X_BLOCKDIM_X == -1) s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = d_ip[cols - 1];

else s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = (baseX + i * X_BLOCKDIM_X >= 0) ? d_ip[i * X_BLOCKDIM_X] : d_ip[i * X_BLOCKDIM_X + cols + 1];
}

// main data and Load right halo
#pragma unroll

for (int i = Halo_steps; i < Halo_steps + 2 * X_RESULT_STEPS + Halo_steps; i++)
{
if (baseX + i * X_BLOCKDIM_X == cols) s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = d_ip[i * X_BLOCKDIM_X - 1];

else s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = ((baseX + i * X_BLOCKDIM_X) < cols) ? d_ip[i * X_BLOCKDIM_X] : d_ip[i * X_BLOCKDIM_X - cols - 1];
}

//Compute and store results
__syncthreads();


#pragma unroll

for (int i = 0; i < X_RESULT_STEPS; i++)
{
if ((baseX1 + i * X_BLOCKDIM_X < cA_cols))
{
float sum_cL = 0, sum_cH = 0;

int l2 = filt_len / 2;

for (int l = 0; l < filt_len; ++l)
{
sum_cL += c_lpd[l] * s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x * 2 + Halo_steps*X_BLOCKDIM_X + 2 * i * X_BLOCKDIM_X + l2 - l]; //l2-l is to select the right center pixels with odd and even sized filters
sum_cH += c_hpd[l] * s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x * 2 + Halo_steps*X_BLOCKDIM_X + 2 * i * X_BLOCKDIM_X + l2 - l];
}
d_cL[i * X_BLOCKDIM_X] = sum_cL;
d_cH[i * X_BLOCKDIM_X] = sum_cH;
}
}
}
}
	.file	"tmpxft_00331f56_00000000-6_dwt_per_X_O.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z40__device_stub__Z11dwt_per_X_OPfiiiiiS_S_PfiiiiiS_S_
	.type	_Z40__device_stub__Z11dwt_per_X_OPfiiiiiS_S_PfiiiiiS_S_, @function
_Z40__device_stub__Z11dwt_per_X_OPfiiiiiS_S_PfiiiiiS_S_:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	216(%rsp), %rax
	movl	%edx, 32(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movl	%r9d, 20(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11dwt_per_X_OPfiiiiiS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z40__device_stub__Z11dwt_per_X_OPfiiiiiS_S_PfiiiiiS_S_, .-_Z40__device_stub__Z11dwt_per_X_OPfiiiiiS_S_PfiiiiiS_S_
	.globl	_Z11dwt_per_X_OPfiiiiiS_S_
	.type	_Z11dwt_per_X_OPfiiiiiS_S_, @function
_Z11dwt_per_X_OPfiiiiiS_S_:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z11dwt_per_X_OPfiiiiiS_S_PfiiiiiS_S_
	.cfi_endproc
.LFE2033:
	.size	_Z11dwt_per_X_OPfiiiiiS_S_, .-_Z11dwt_per_X_OPfiiiiiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z11dwt_per_X_OPfiiiiiS_S_"
.LC1:
	.string	"c_lpd"
.LC2:
	.string	"c_hpd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11dwt_per_X_OPfiiiiiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movl	$8, %r9d
	leaq	_ZL5c_lpd(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$8, %r9d
	leaq	_ZL5c_hpd(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL5c_hpd
	.comm	_ZL5c_hpd,8,8
	.local	_ZL5c_lpd
	.comm	_ZL5c_lpd,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void dwt_per_X_O(float *d_ip, int rows, int cols, int cA_cols, int filt_len, int Halo_steps, float *d_cL, float *d_cH)
{
extern __shared__ float s_Data[];

//Offset to the left halo edge
const int baseX = (blockIdx.x * 2 * X_RESULT_STEPS - Halo_steps) * X_BLOCKDIM_X + threadIdx.x;
const int baseX1 = (blockIdx.x * X_RESULT_STEPS) * X_BLOCKDIM_X + threadIdx.x;
const int baseY = blockIdx.y * X_BLOCKDIM_Y + threadIdx.y;

if (baseY < rows) {

d_ip += baseY * cols + baseX;
d_cL += baseY * cA_cols + baseX1;
d_cH += baseY * cA_cols + baseX1;

//Loading data to shared memory

//Load Left Halo
#pragma unroll
for (int i = 0; i < Halo_steps; i++)
{
if (baseX + i * X_BLOCKDIM_X == -1) s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = d_ip[cols - 1];

else s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = (baseX + i * X_BLOCKDIM_X >= 0) ? d_ip[i * X_BLOCKDIM_X] : d_ip[i * X_BLOCKDIM_X + cols + 1];
}

// main data and Load right halo
#pragma unroll

for (int i = Halo_steps; i < Halo_steps + 2 * X_RESULT_STEPS + Halo_steps; i++)
{
if (baseX + i * X_BLOCKDIM_X == cols) s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = d_ip[i * X_BLOCKDIM_X - 1];

else s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x + i * X_BLOCKDIM_X] = ((baseX + i * X_BLOCKDIM_X) < cols) ? d_ip[i * X_BLOCKDIM_X] : d_ip[i * X_BLOCKDIM_X - cols - 1];
}

//Compute and store results
__syncthreads();


#pragma unroll

for (int i = 0; i < X_RESULT_STEPS; i++)
{
if ((baseX1 + i * X_BLOCKDIM_X < cA_cols))
{
float sum_cL = 0, sum_cH = 0;

int l2 = filt_len / 2;

for (int l = 0; l < filt_len; ++l)
{
sum_cL += c_lpd[l] * s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x * 2 + Halo_steps*X_BLOCKDIM_X + 2 * i * X_BLOCKDIM_X + l2 - l]; //l2-l is to select the right center pixels with odd and even sized filters
sum_cH += c_hpd[l] * s_Data[(threadIdx.y*(2 * X_RESULT_STEPS + 2 * Halo_steps)*X_BLOCKDIM_X) + threadIdx.x * 2 + Halo_steps*X_BLOCKDIM_X + 2 * i * X_BLOCKDIM_X + l2 - l];
}
d_cL[i * X_BLOCKDIM_X] = sum_cL;
d_cH[i * X_BLOCKDIM_X] = sum_cH;
}
}
}
}
	.text
	.file	"dwt_per_X_O.hip"
	.globl	_Z26__device_stub__dwt_per_X_OPfiiiiiS_S_ # -- Begin function _Z26__device_stub__dwt_per_X_OPfiiiiiS_S_
	.type	_Z26__device_stub__dwt_per_X_OPfiiiiiS_S_,@function
_Z26__device_stub__dwt_per_X_OPfiiiiiS_S_: # @_Z26__device_stub__dwt_per_X_OPfiiiiiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11dwt_per_X_OPfiiiiiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__dwt_per_X_OPfiiiiiS_S_, .Lfunc_end0-_Z26__device_stub__dwt_per_X_OPfiiiiiS_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11dwt_per_X_OPfiiiiiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$c_lpd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$c_hpd, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$8, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	c_lpd,@object                   # @c_lpd
	.local	c_lpd
	.comm	c_lpd,8,8
	.type	c_hpd,@object                   # @c_hpd
	.local	c_hpd
	.comm	c_hpd,8,8
	.type	_Z11dwt_per_X_OPfiiiiiS_S_,@object # @_Z11dwt_per_X_OPfiiiiiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z11dwt_per_X_OPfiiiiiS_S_
	.p2align	3, 0x0
_Z11dwt_per_X_OPfiiiiiS_S_:
	.quad	_Z26__device_stub__dwt_per_X_OPfiiiiiS_S_
	.size	_Z11dwt_per_X_OPfiiiiiS_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11dwt_per_X_OPfiiiiiS_S_"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"c_lpd"
	.size	.L__unnamed_2, 6

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"c_hpd"
	.size	.L__unnamed_3, 6

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__dwt_per_X_OPfiiiiiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym c_lpd
	.addrsig_sym c_hpd
	.addrsig_sym _Z11dwt_per_X_OPfiiiiiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11dwt_per_X_OPfiiiiiS_S_ ; -- Begin function _Z11dwt_per_X_OPfiiiiiS_S_
	.globl	_Z11dwt_per_X_OPfiiiiiS_S_
	.p2align	8
	.type	_Z11dwt_per_X_OPfiiiiiS_S_,@function
_Z11dwt_per_X_OPfiiiiiS_S_:             ; @_Z11dwt_per_X_OPfiiiiiS_S_
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_bfe_u32 v11, v0, 10, 10
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v9, s15, 2, v11
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s4, v9
	s_cbranch_execz .LBB0_36
; %bb.1:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x18
	s_load_b64 s[8:9], s[0:1], 0x0
	v_and_b32_e32 v10, 0x3ff, v0
	s_lshl_b32 s3, s14, 7
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s4, s2, 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_sub_i32 s10, s3, s4
	s_cmp_gt_i32 s2, 0
	v_add_nc_u32_e32 v2, s10, v10
	v_mad_u64_u32 v[0:1], null, v9, s5, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_mov_b32 s9, 0
	s_cbranch_scc1 .LBB0_3
; %bb.2:                                ; %..preheader_crit_edge
	s_lshl_b32 s8, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s8, s8, 8
	s_branch .LBB0_4
.LBB0_3:
	s_mov_b32 s9, -1
                                        ; implicit-def: $sgpr8
.LBB0_4:                                ; %Flow254
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_9
; %bb.5:                                ; %.lr.ph
	s_lshl_b32 s8, s2, 1
	s_ashr_i32 s11, s5, 31
	s_add_i32 s8, s8, 8
	s_mov_b32 s10, s5
	v_mul_lo_u32 v3, v11, s8
	s_lshl_b64 s[10:11], s[10:11], 2
	v_lshlrev_b32_e32 v5, 2, v10
	v_add_co_u32 v4, vcc_lo, v0, s10
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v1, vcc_lo
	s_add_u32 s9, s10, 4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v7, 6, v3
	v_add_co_u32 v3, vcc_lo, v4, -4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, -1, v6, vcc_lo
	v_add3_u32 v12, v7, v5, 0
	v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
	s_addc_u32 s10, s11, 0
	s_mov_b32 s11, s2
.LBB0_6:                                ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v7, v3
	s_mov_b32 s12, exec_lo
	v_cmpx_ne_u32_e32 -1, v2
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	v_add_co_u32 v7, vcc_lo, v5, s9
	v_add_co_ci_u32_e32 v8, vcc_lo, s10, v6, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v8, v6, v8 :: v_dual_cndmask_b32 v7, v5, v7
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v5, vcc_lo, v5, 64
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	v_add_nc_u32_e32 v2, 16, v2
	s_add_i32 s11, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v12, v7
	v_add_nc_u32_e32 v12, 64, v12
	s_cbranch_scc0 .LBB0_6
.LBB0_9:                                ; %.preheader
	v_mul_lo_u32 v3, v11, s8
	s_cmp_gt_i32 s8, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 4, v3
	s_cbranch_scc1 .LBB0_11
; %bb.10:                               ; %.preheader.._crit_edge_crit_edge
	v_lshlrev_b32_e32 v5, 4, v3
	s_mov_b32 s9, 0
	s_branch .LBB0_12
.LBB0_11:
	s_mov_b32 s9, -1
                                        ; implicit-def: $vgpr5
.LBB0_12:                               ; %Flow251
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_16
; %bb.13:                               ; %.lr.ph103
	v_add3_u32 v3, v10, v2, s4
	v_add_nc_u32_e32 v4, s3, v10
	s_not_b32 s3, s5
	s_sub_i32 s2, s8, s2
	s_mov_b32 s8, s4
	v_lshl_add_u32 v3, v3, 2, 0
.LBB0_14:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_lt_i32_e32 vcc_lo, s5, v4
	s_add_i32 s2, s2, -1
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s5, v4
	v_add_nc_u32_e32 v4, 16, v4
	v_cndmask_b32_e64 v5, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, s8, v6
	s_add_i32 s8, s8, 16
	s_cmp_eq_u32 s2, 0
	v_mov_b32_e32 v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v5, vcc_lo, v0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v1, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v5
	v_add_nc_u32_e32 v3, 64, v3
	s_cbranch_scc0 .LBB0_14
; %bb.15:
	v_mov_b32_e32 v5, v2
.LBB0_16:                               ; %Flow252
	v_lshl_add_u32 v4, s14, 6, v10
	s_lshr_b32 s2, s7, 31
	s_load_b128 s[8:11], s[0:1], 0x20
	s_add_i32 s0, s7, s2
	v_lshlrev_b32_e32 v6, 1, v10
	v_mad_u64_u32 v[0:1], null, v9, s6, v[4:5]
	s_ashr_i32 s12, s0, 1
	s_cmp_gt_i32 s7, 0
	s_cselect_b32 s5, -1, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, c_lpd@rel32@lo+4
	s_addc_u32 s1, s1, c_lpd@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, c_hpd@rel32@lo+4
	s_addc_u32 s3, s3, c_hpd@rel32@hi+12
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_load_b64 s[2:3], s[2:3], 0x0
	s_add_i32 s4, s4, s12
	s_waitcnt lgkmcnt(0)
	v_add3_u32 v5, s4, v6, v5
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	v_cndmask_b32_e64 v6, 0, 1, s5
	s_barrier
	buffer_gl0_inv
	v_add_co_u32 v0, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	s_mov_b32 s10, exec_lo
	v_cmpx_gt_i32_e64 s6, v4
	s_cbranch_execz .LBB0_21
; %bb.17:
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_20
; %bb.18:                               ; %.lr.ph108.preheader
	v_lshl_add_u32 v9, v5, 2, 0
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	s_mov_b64 s[4:5], s[2:3]
	s_mov_b64 s[8:9], s[0:1]
	s_mov_b32 s11, s7
.LBB0_19:                               ; %.lr.ph108
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s12, s[8:9], 0x0
	ds_load_b32 v10, v9
	s_load_b32 s13, s[4:5], 0x0
	s_add_i32 s11, s11, -1
	s_add_u32 s8, s8, 4
	v_add_nc_u32_e32 v9, -4, v9
	s_addc_u32 s9, s9, 0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s11, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v8, s12, v10
	v_fmac_f32_e32 v7, s13, v10
	s_cbranch_scc0 .LBB0_19
.LBB0_20:                               ; %._crit_edge109
	global_store_b32 v[0:1], v8, off
	global_store_b32 v[2:3], v7, off
.LBB0_21:                               ; %Flow249
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v7, 16, v4
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v7
	s_cbranch_execz .LBB0_26
; %bb.22:
	v_cmp_ne_u32_e32 vcc_lo, 1, v6
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	s_cbranch_vccnz .LBB0_25
; %bb.23:                               ; %.lr.ph108.1
	v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v8, 2, v5
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[4:5], s[2:3]
	s_mov_b64 s[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v10, v8, 0, 0x80
	v_mov_b32_e32 v8, 0
	s_mov_b32 s11, s7
.LBB0_24:                               ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	global_load_b32 v11, v9, s[8:9]
	global_load_b32 v12, v9, s[4:5]
	ds_load_b32 v13, v10
	s_add_i32 s11, s11, -1
	s_add_u32 s8, s8, 4
	v_add_nc_u32_e32 v10, -4, v10
	s_addc_u32 s9, s9, 0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s11, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_fmac_f32 v8, v11, v13 :: v_dual_fmac_f32 v7, v13, v12
	s_cbranch_scc1 .LBB0_24
.LBB0_25:                               ; %._crit_edge109.1
	global_store_b32 v[0:1], v8, off offset:64
	global_store_b32 v[2:3], v7, off offset:64
.LBB0_26:                               ; %Flow246
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v7, 32, v4
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s6, v7
	s_cbranch_execz .LBB0_31
; %bb.27:
	v_cmp_ne_u32_e32 vcc_lo, 1, v6
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, 0
	s_cbranch_vccnz .LBB0_30
; %bb.28:                               ; %.lr.ph108.2
	v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v8, 2, v5
	v_mov_b32_e32 v9, 0
	s_mov_b64 s[4:5], s[2:3]
	s_mov_b64 s[8:9], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v10, v8, 0, 0x100
	v_mov_b32_e32 v8, 0
	s_mov_b32 s11, s7
.LBB0_29:                               ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	global_load_b32 v11, v9, s[8:9]
	global_load_b32 v12, v9, s[4:5]
	ds_load_b32 v13, v10
	s_add_i32 s11, s11, -1
	s_add_u32 s8, s8, 4
	v_add_nc_u32_e32 v10, -4, v10
	s_addc_u32 s9, s9, 0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s11, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_fmac_f32 v8, v11, v13 :: v_dual_fmac_f32 v7, v13, v12
	s_cbranch_scc1 .LBB0_29
.LBB0_30:                               ; %._crit_edge109.2
	global_store_b32 v[0:1], v8, off offset:128
	global_store_b32 v[2:3], v7, off offset:128
.LBB0_31:                               ; %Flow243
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v4, 48, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s6, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_36
; %bb.32:
	v_cmp_ne_u32_e32 vcc_lo, 1, v6
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v6, 0
	s_cbranch_vccnz .LBB0_35
; %bb.33:                               ; %.lr.ph108.3
	v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v6, 2, v5
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v7, v6, 0, 0x180
	v_mov_b32_e32 v6, 0
.LBB0_34:                               ; =>This Inner Loop Header: Depth=1
	s_clause 0x1
	global_load_b32 v8, v5, s[0:1]
	global_load_b32 v9, v5, s[2:3]
	ds_load_b32 v10, v7
	s_add_i32 s7, s7, -1
	s_add_u32 s0, s0, 4
	v_add_nc_u32_e32 v7, -4, v7
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_lg_u32 s7, 0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v6, v8, v10
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v10, v9
	s_cbranch_scc1 .LBB0_34
.LBB0_35:                               ; %._crit_edge109.3
	global_store_b32 v[0:1], v6, off offset:192
	global_store_b32 v[2:3], v4, off offset:192
.LBB0_36:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11dwt_per_X_OPfiiiiiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 48
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11dwt_per_X_OPfiiiiiS_S_, .Lfunc_end0-_Z11dwt_per_X_OPfiiiiiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1460
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	c_lpd                   ; @c_lpd
	.type	c_lpd,@object
	.section	.bss,"aw",@nobits
	.globl	c_lpd
	.p2align	3, 0x0
c_lpd:
	.quad	0
	.size	c_lpd, 8

	.protected	c_hpd                   ; @c_hpd
	.type	c_hpd,@object
	.globl	c_hpd
	.p2align	3, 0x0
c_hpd:
	.quad	0
	.size	c_hpd, 8

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym c_lpd
	.addrsig_sym c_hpd
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 48
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11dwt_per_X_OPfiiiiiS_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11dwt_per_X_OPfiiiiiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
