#include "includes.h"

//设备端代码
__global__ void cvlUnit(const char *imgR,const char *imgG,const char *imgB,const char *core, char *outR,char *outG,char *outB,int lenX,int lenY,int lenCore)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index=y*lenX+x;
if(x>=lenX||y>=lenY)return;
if(x-lenCore/2<0||x+lenCore/2>=lenX||y-lenCore/2<0||y+lenCore/2>=lenY){
outR[index]=imgR[index];
outG[index]=imgG[index];
outB[index]=imgB[index];
return ;
}


int i,j,tmpX,tmpY;
int sumR=0;
int sumG=0;
int sumB=0;
for(i=0;i<lenCore;i++){
for(j=0;j<lenCore;j++){
tmpX = x-lenCore/2+i;
tmpY = y-lenCore/2+j;
//			if(x==8&&y==8){printf("tmpX=%d,tmpY=%d:\n",tmpX,tmpY);}
sumR+=imgR[tmpY*lenX+tmpX]*core[j*lenCore+i];
//			if(x==8&&y==8){
//				printf("\tR:\t %d*%d,new=%d\n",imgR[tmpY*lenX+tmpX],core[j*lenCore+i],sumR);
//			}
sumG+=imgG[tmpY*lenX+tmpX]*core[j*lenCore+i];
//			if(x==8&&y==8){
//				printf("\tG:\t %d*%d,new=%d\n",imgG[tmpY*lenX+tmpX],core[j*lenCore+i],sumG);
//			}
sumB+=imgB[tmpY*lenX+tmpX]*core[j*lenCore+i];
//			if(x==8&&y==8){
//				printf("\tB:\t %d*%d,new=%d\n",imgB[tmpY*lenX+tmpX],core[j*lenCore+i],sumB);
//			}
}
}
outR[index]=(char)(sumR*1.0/(lenCore*lenCore));
outG[index]=(char)(sumG*1.0/(lenCore*lenCore));
outB[index]=(char)(sumB*1.0/(lenCore*lenCore));
return;
}
	.file	"tmpxft_0029f3fd_00000000-6_cvlUnit.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iiiPKcS0_S0_S0_PcS1_S1_iii
	.type	_Z47__device_stub__Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iiiPKcS0_S0_S0_PcS1_S1_iii, @function
_Z47__device_stub__Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iiiPKcS0_S0_S0_PcS1_S1_iii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iiiPKcS0_S0_S0_PcS1_S1_iii, .-_Z47__device_stub__Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iiiPKcS0_S0_S0_PcS1_S1_iii
	.globl	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.type	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii, @function
_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iiiPKcS0_S0_S0_PcS1_S1_iii
	.cfi_endproc
.LFE2033:
	.size	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii, .-_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

//设备端代码
__global__ void cvlUnit(const char *imgR,const char *imgG,const char *imgB,const char *core, char *outR,char *outG,char *outB,int lenX,int lenY,int lenCore)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int index=y*lenX+x;
if(x>=lenX||y>=lenY)return;
if(x-lenCore/2<0||x+lenCore/2>=lenX||y-lenCore/2<0||y+lenCore/2>=lenY){
outR[index]=imgR[index];
outG[index]=imgG[index];
outB[index]=imgB[index];
return ;
}


int i,j,tmpX,tmpY;
int sumR=0;
int sumG=0;
int sumB=0;
for(i=0;i<lenCore;i++){
for(j=0;j<lenCore;j++){
tmpX = x-lenCore/2+i;
tmpY = y-lenCore/2+j;
//			if(x==8&&y==8){printf("tmpX=%d,tmpY=%d:\n",tmpX,tmpY);}
sumR+=imgR[tmpY*lenX+tmpX]*core[j*lenCore+i];
//			if(x==8&&y==8){
//				printf("\tR:\t %d*%d,new=%d\n",imgR[tmpY*lenX+tmpX],core[j*lenCore+i],sumR);
//			}
sumG+=imgG[tmpY*lenX+tmpX]*core[j*lenCore+i];
//			if(x==8&&y==8){
//				printf("\tG:\t %d*%d,new=%d\n",imgG[tmpY*lenX+tmpX],core[j*lenCore+i],sumG);
//			}
sumB+=imgB[tmpY*lenX+tmpX]*core[j*lenCore+i];
//			if(x==8&&y==8){
//				printf("\tB:\t %d*%d,new=%d\n",imgB[tmpY*lenX+tmpX],core[j*lenCore+i],sumB);
//			}
}
}
outR[index]=(char)(sumR*1.0/(lenCore*lenCore));
outG[index]=(char)(sumG*1.0/(lenCore*lenCore));
outB[index]=(char)(sumB*1.0/(lenCore*lenCore));
return;
}
	.text
	.file	"cvlUnit.hip"
	.globl	_Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii # -- Begin function _Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.type	_Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii,@function
_Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii: # @_Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii, .Lfunc_end0-_Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii,@object # @_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.section	.rodata,"a",@progbits
	.globl	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.p2align	3, 0x0
_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii:
	.quad	_Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.size	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii ; -- Begin function _Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.globl	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
	.p2align	8
	.type	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii,@function
_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii:      ; @_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b128 s[20:23], s[0:1], 0x38
	v_and_b32_e32 v7, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s3, s14, s3
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	v_add_nc_u32_e32 v3, s3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_i32_e32 vcc_lo, s20, v3
	v_cmp_gt_i32_e64 s2, s21, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_14
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x0
	s_lshr_b32 s2, s22, 31
	s_load_b256 s[4:11], s[0:1], 0x20
	s_add_i32 s0, s22, s2
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s10, 0
	s_ashr_i32 s1, s0, 1
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v0, s1, v3
	v_add_nc_u32_e32 v1, s1, v3
	v_cmp_lt_i32_e32 vcc_lo, -1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s0, s20, v1
	v_mad_u64_u32 v[0:1], null, v2, s20, v[3:4]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, s0, -1
	s_and_saveexec_b32 s11, s0
; %bb.2:
	v_subrev_nc_u32_e32 v8, s1, v2
	v_add_nc_u32_e32 v1, s1, v2
	s_and_not1_b32 s2, s2, exec_lo
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, 0, v8
	v_cmp_le_i32_e64 s0, s21, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s0
; %bb.3:                                ; %Flow285
	s_or_b32 exec_lo, exec_lo, s11
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
                                        ; implicit-def: $vgpr0_vgpr1
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_u32 v2, vcc_lo, s12, v0
	s_and_not1_b32 s10, s10, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v1, vcc_lo
	global_load_u8 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v6, off
	global_load_u8 v6, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[2:3], v6, off
	global_load_u8 v2, v[4:5], off
.LBB0_5:                                ; %Flow286
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s2, s10
	s_cbranch_execz .LBB0_13
; %bb.6:                                ; %.preheader108
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_cmp_lt_i32 s22, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
	s_cbranch_scc1 .LBB0_12
; %bb.7:                                ; %.preheader.preheader
	v_mul_lo_u32 v1, s20, v8
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add3_u32 v3, v7, v1, s3
	v_mov_b32_e32 v1, 0
	s_mov_b32 s3, 0
	v_subrev_nc_u32_e32 v4, s1, v3
	v_mov_b32_e32 v3, 0
.LBB0_8:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v5, v4
	s_mov_b32 s10, s3
	s_mov_b32 s11, 0
.LBB0_9:                                ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v5
	v_add_co_u32 v10, s1, s12, v5
	v_mov_b32_e32 v12, s10
	v_add_co_u32 v6, vcc_lo, s14, v5
	v_add_co_u32 v8, s0, s16, v5
	v_add_nc_u32_e32 v5, s20, v5
	v_add_co_ci_u32_e64 v11, s1, s13, v9, s1
	v_add_co_ci_u32_e32 v7, vcc_lo, s15, v9, vcc_lo
	v_add_co_ci_u32_e64 v9, vcc_lo, s17, v9, s0
	global_load_i8 v12, v12, s[18:19]
	global_load_i8 v10, v[10:11], off
	global_load_i8 v6, v[6:7], off
	global_load_i8 v7, v[8:9], off
	s_add_i32 s11, s11, 1
	s_add_i32 s10, s10, s22
	s_cmp_lg_u32 s22, s11
	s_waitcnt vmcnt(2)
	v_mad_i32_i24 v3, v12, v10, v3
	s_waitcnt vmcnt(1)
	v_mad_i32_i24 v2, v6, v12, v2
	s_waitcnt vmcnt(0)
	v_mad_i32_i24 v1, v7, v12, v1
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_add_nc_u32_e32 v4, 1, v4
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s3, s22
	s_cbranch_scc1 .LBB0_8
; %bb.11:                               ; %._crit_edge119.loopexit
	v_cvt_f64_i32_e32 v[5:6], v3
	v_cvt_f64_i32_e32 v[3:4], v2
	v_cvt_f64_i32_e32 v[1:2], v1
.LBB0_12:                               ; %._crit_edge119
	s_mul_i32 s0, s22, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[7:8], s0
	v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[3:4]
	v_div_scale_f64 v[13:14], null, v[7:8], v[7:8], v[1:2]
	v_div_scale_f64 v[27:28], vcc_lo, v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[15:16], v[9:10]
	v_rcp_f64_e32 v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[19:20], v[13:14]
	v_fma_f64 v[21:22], -v[9:10], v[15:16], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[11:12], v[17:18], 1.0
	v_fma_f64 v[25:26], -v[13:14], v[19:20], 1.0
	v_fma_f64 v[15:16], v[15:16], v[21:22], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[17:18], v[23:24], v[17:18]
	v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], -v[9:10], v[15:16], 1.0
	v_fma_f64 v[23:24], -v[11:12], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], -v[13:14], v[19:20], 1.0
	v_fma_f64 v[15:16], v[15:16], v[21:22], v[15:16]
	v_div_scale_f64 v[21:22], s0, v[3:4], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[17:18], v[23:24], v[17:18]
	v_div_scale_f64 v[23:24], s1, v[1:2], v[7:8], v[1:2]
	v_fma_f64 v[19:20], v[19:20], v[25:26], v[19:20]
	v_mul_f64 v[25:26], v[27:28], v[15:16]
	v_mul_f64 v[29:30], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[31:32], v[23:24], v[19:20]
	v_fma_f64 v[9:10], -v[9:10], v[25:26], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], -v[11:12], v[29:30], v[21:22]
	v_fma_f64 v[13:14], -v[13:14], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[9:10], v[9:10], v[15:16], v[25:26]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[11:12], v[11:12], v[17:18], v[29:30]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[13:14], v[13:14], v[19:20], v[31:32]
	v_div_fixup_f64 v[5:6], v[9:10], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[3:4], v[11:12], v[7:8], v[3:4]
	v_div_fixup_f64 v[1:2], v[13:14], v[7:8], v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v7, v[5:6]
	v_cvt_i32_f64_e32 v8, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v2, v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
	global_store_b8 v[3:4], v7, off
	global_store_b8 v[5:6], v8, off
.LBB0_13:                               ; %Flow287
	s_or_b32 exec_lo, exec_lo, s2
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v2, off
.LBB0_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 33
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii, .Lfunc_end0-_Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1092
; NumSgprs: 26
; NumVgprs: 33
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 33
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z7cvlUnitPKcS0_S0_S0_PcS1_S1_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     33
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
