#include "includes.h"


__global__ void rgb2hsl_gpu_son( unsigned char * d_r, unsigned char * d_g, unsigned char * d_b, float * d_h , float * d_s , unsigned char * d_l , int size)
{
int x = threadIdx.x + blockDim.x*blockIdx.x;
if (x >= size) return;

float H,S,L;
float var_r = ( (float)d_r[x]/255 );//Convert RGB to [0,1]
float var_g = ( (float)d_g[x]/255 );
float var_b = ( (float)d_b[x]/255 );
float var_min = (var_r < var_g) ? var_r : var_g;
var_min = (var_min < var_b) ? var_min : var_b;   //min. value of RGB
float var_max = (var_r > var_g) ? var_r : var_g;
var_max = (var_max > var_b) ? var_max : var_b;   //max. value of RGB
float del_max = var_max - var_min;               //Delta RGB value

L = ( var_max + var_min ) / 2;
if ( del_max == 0 )//This is a gray, no chroma...
{
H = 0;
S = 0;
}
else                                    //Chromatic data...
{
if ( L < 0.5 )
S = del_max/(var_max+var_min);
else {
S = del_max/(2-var_max-var_min );

float del_r = (((var_max-var_r)/6)+(del_max/2))/del_max;
float del_g = (((var_max-var_g)/6)+(del_max/2))/del_max;
float del_b = (((var_max-var_b)/6)+(del_max/2))/del_max;
if( var_r == var_max ) H = del_b - del_g;
else {
if( var_g == var_max ) H = (1.0/3.0) + del_r - del_b;
else H = (2.0/3.0) + del_g - del_r;
}
}

if ( H < 0 ) H += 1;
if ( H > 1 ) H -= 1;
}
d_h[x] = H;
d_s[x] = S;
d_l[x] = (unsigned char)(L*255);
}
	.file	"tmpxft_002e6909_00000000-6_rgb2hsl_gpu_son.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_iPhS_S_PfS0_S_i
	.type	_Z47__device_stub__Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_iPhS_S_PfS0_S_i, @function
_Z47__device_stub__Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_iPhS_S_PfS0_S_i:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_iPhS_S_PfS0_S_i, .-_Z47__device_stub__Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_iPhS_S_PfS0_S_i
	.globl	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.type	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i, @function
_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_iPhS_S_PfS0_S_i
	.cfi_endproc
.LFE2033:
	.size	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i, .-_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"


__global__ void rgb2hsl_gpu_son( unsigned char * d_r, unsigned char * d_g, unsigned char * d_b, float * d_h , float * d_s , unsigned char * d_l , int size)
{
int x = threadIdx.x + blockDim.x*blockIdx.x;
if (x >= size) return;

float H,S,L;
float var_r = ( (float)d_r[x]/255 );//Convert RGB to [0,1]
float var_g = ( (float)d_g[x]/255 );
float var_b = ( (float)d_b[x]/255 );
float var_min = (var_r < var_g) ? var_r : var_g;
var_min = (var_min < var_b) ? var_min : var_b;   //min. value of RGB
float var_max = (var_r > var_g) ? var_r : var_g;
var_max = (var_max > var_b) ? var_max : var_b;   //max. value of RGB
float del_max = var_max - var_min;               //Delta RGB value

L = ( var_max + var_min ) / 2;
if ( del_max == 0 )//This is a gray, no chroma...
{
H = 0;
S = 0;
}
else                                    //Chromatic data...
{
if ( L < 0.5 )
S = del_max/(var_max+var_min);
else {
S = del_max/(2-var_max-var_min );

float del_r = (((var_max-var_r)/6)+(del_max/2))/del_max;
float del_g = (((var_max-var_g)/6)+(del_max/2))/del_max;
float del_b = (((var_max-var_b)/6)+(del_max/2))/del_max;
if( var_r == var_max ) H = del_b - del_g;
else {
if( var_g == var_max ) H = (1.0/3.0) + del_r - del_b;
else H = (2.0/3.0) + del_g - del_r;
}
}

if ( H < 0 ) H += 1;
if ( H > 1 ) H -= 1;
}
d_h[x] = H;
d_s[x] = S;
d_l[x] = (unsigned char)(L*255);
}
	.text
	.file	"rgb2hsl_gpu_son.hip"
	.globl	_Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i # -- Begin function _Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.type	_Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i,@function
_Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i: # @_Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i, .Lfunc_end0-_Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i,@object # @_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.p2align	3, 0x0
_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i:
	.quad	_Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.size	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i ; -- Begin function _Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.globl	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
	.p2align	8
	.type	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i,@function
_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i:      ; @_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b32 s3, s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_16
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
	v_add_co_u32 v7, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v2, vcc_lo
	global_load_u8 v0, v[3:4], off
	global_load_u8 v3, v[5:6], off
	global_load_u8 v4, v[7:8], off
	s_load_b128 s[4:7], s[0:1], 0x20
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(2)
	v_cvt_f32_ubyte0_e32 v0, v0
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v5, v3
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v4, v4
	v_div_scale_f32 v3, null, 0x437f0000, 0x437f0000, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v6, null, 0x437f0000, 0x437f0000, v5
	v_div_scale_f32 v7, null, 0x437f0000, 0x437f0000, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v8, v3
	v_rcp_f32_e32 v9, v6
	v_div_scale_f32 v11, vcc_lo, v0, 0x437f0000, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v10, v7
	v_div_scale_f32 v12, s2, v5, 0x437f0000, v5
	v_div_scale_f32 v16, s3, v4, 0x437f0000, v4
	v_fma_f32 v13, -v3, v8, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v6, v9, 1.0
	v_fma_f32 v15, -v7, v10, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, v13, v8 :: v_dual_fmac_f32 v9, v14, v9
	v_dual_mul_f32 v13, v11, v8 :: v_dual_mul_f32 v14, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v17, -v3, v13, v11
	v_fmac_f32_e32 v10, v15, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -v6, v14, v12
	v_fmac_f32_e32 v13, v17, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v15, v16, v10 :: v_dual_fmac_f32 v14, v18, v9
	v_fma_f32 v3, -v3, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, -v7, v15, v16
	v_fma_f32 v6, -v6, v14, v12
	v_mov_b32_e32 v11, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v3, v3, v8, v13
	v_fmac_f32_e32 v15, v19, v10
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v6, v6, v9, v14
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v7, -v7, v15, v16
	v_div_fixup_f32 v3, v3, 0x437f0000, v0
	v_mov_b32_e32 v9, 0
	v_div_fmas_f32 v8, v7, v10, v15
	v_div_fixup_f32 v7, v6, 0x437f0000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v10, v8, 0x437f0000, v4
	v_cmp_lt_f32_e32 vcc_lo, v3, v7
	v_cndmask_b32_e32 v0, v7, v3, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v3, v7
	v_cndmask_b32_e32 v5, v7, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, v0, v10
	v_cndmask_b32_e32 v4, v10, v0, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v5, v10
	v_cndmask_b32_e32 v8, v10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v6, v8, v4
	v_dual_sub_f32 v5, v8, v4 :: v_dual_mul_f32 v0, 0.5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_neq_f32_e32 0, v5
	s_cbranch_execz .LBB0_15
; %bb.2:
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr9
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 0.5, v0
	s_cbranch_execz .LBB0_12
; %bb.3:
	v_sub_f32_e32 v6, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v9, null, 0x40c00000, 0x40c00000, v6
	v_div_scale_f32 v13, vcc_lo, v6, 0x40c00000, v6
	v_rcp_f32_e32 v11, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v9, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v11
	v_mul_f32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v9, v12, v13
	v_fmac_f32_e32 v12, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v9, v12, v13
	v_div_fmas_f32 v9, v9, v11, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v9, v9, 0x40c00000, v6
	v_dual_sub_f32 v6, v8, v10 :: v_dual_fmac_f32 v9, 0.5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v11, null, 0x40c00000, 0x40c00000, v6
	v_div_scale_f32 v10, null, v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v13, v11
	v_div_scale_f32 v16, vcc_lo, v9, v5, v9
	v_rcp_f32_e32 v12, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v15, -v11, v13, 1.0
	v_fma_f32 v14, -v10, v12, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, v15, v13 :: v_dual_fmac_f32 v12, v14, v12
	v_div_scale_f32 v14, s0, v6, 0x40c00000, v6
	v_mul_f32_e32 v15, v16, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v14, v13
	v_fma_f32 v18, -v10, v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v11, v17, v14
	v_fmac_f32_e32 v15, v18, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v19, v13
	v_fma_f32 v10, -v10, v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, -v11, v17, v14
	v_div_fmas_f32 v10, v10, v12, v15
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v11, v13, v17
	v_div_fixup_f32 v12, v11, 0x40c00000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, 0.5, v5
	v_div_scale_f32 v6, null, v5, v5, v12
	v_div_scale_f32 v14, vcc_lo, v12, v5, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v6, v11, 1.0
	v_fmac_f32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v14, v11
	v_fma_f32 v15, -v6, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v15, v11
	v_fma_f32 v6, -v6, v13, v14
	v_sub_f32_e32 v14, 2.0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v13, v6, v11, v13
	v_sub_f32_e32 v6, v14, v4
	v_div_fixup_f32 v11, v10, v5, v9
                                        ; implicit-def: $vgpr9
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v10, v13, v5, v12
	v_cmpx_neq_f32_e32 v3, v8
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_9
; %bb.4:
	v_sub_f32_e32 v3, v8, v3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v4, null, 0x40c00000, 0x40c00000, v3
	v_div_scale_f32 v13, vcc_lo, v3, 0x40c00000, v3
	v_rcp_f32_e32 v9, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v4, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v12, v9
	v_mul_f32_e32 v12, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v4, v12, v13
	v_fmac_f32_e32 v12, v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v12, v13
	v_div_fmas_f32 v4, v4, v9, v12
	v_mul_f32_e32 v9, 0.5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v3, v4, 0x40c00000, v3
	v_add_f32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v4, null, v5, v5, v3
	v_rcp_f32_e32 v9, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v4, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v12, v9
	v_div_scale_f32 v12, vcc_lo, v3, v5, v3
	v_mul_f32_e32 v13, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v4, v13, v12
	v_fmac_f32_e32 v13, v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v13, v12
	v_div_fmas_f32 v4, v4, v9, v13
                                        ; implicit-def: $vgpr9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v3, v4, v5, v3
	v_cvt_f64_f32_e32 v[3:4], v3
	v_cmpx_neq_f32_e32 v7, v8
	s_xor_b32 s3, exec_lo, s3
; %bb.5:
	v_cvt_f64_f32_e32 v[7:8], v11
	s_mov_b32 s8, 0x55555555
	s_mov_b32 s9, 0x3fe55555
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_f64 v[7:8], v[7:8], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[7:8], -v[3:4]
	v_cvt_f32_f64_e32 v9, v[3:4]
                                        ; implicit-def: $vgpr3_vgpr4
; %bb.6:                                ; %Flow100
	s_and_not1_saveexec_b32 s3, s3
; %bb.7:
	s_mov_b32 s8, 0x55555555
	s_mov_b32 s9, 0x3fd55555
	v_cvt_f64_f32_e32 v[7:8], v10
	v_add_f64 v[3:4], v[3:4], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], -v[7:8]
	v_cvt_f32_f64_e32 v9, v[3:4]
; %bb.8:                                ; %Flow101
	s_or_b32 exec_lo, exec_lo, s3
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr11
.LBB0_9:                                ; %Flow102
	s_and_not1_saveexec_b32 s0, s0
; %bb.10:
	v_sub_f32_e32 v9, v10, v11
; %bb.11:                               ; %Flow103
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_12:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s2
	v_div_scale_f32 v3, null, v6, v6, v5
	v_div_scale_f32 v8, vcc_lo, v5, v6, v5
	v_cmp_gt_f32_e64 s0, 0, v9
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v7, v4
	v_mul_f32_e32 v7, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v3, v7, v8
	v_dual_fmac_f32 v7, v10, v4 :: v_dual_add_f32 v10, 1.0, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v3, v7, v8
	v_cndmask_b32_e64 v9, v9, v10, s0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v4, v7
	v_cmpx_lt_f32_e32 1.0, v9
; %bb.13:
	v_add_f32_e32 v9, -1.0, v9
; %bb.14:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fixup_f32 v11, v3, v6, v5
.LBB0_15:                               ; %Flow104
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_mul_f32_e32 v0, 0x437f0000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v7, v0
	v_add_co_u32 v5, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[5:6], v9, off
	global_store_b32 v[3:4], v11, off
	global_store_b8 v[0:1], v7, off
.LBB0_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i, .Lfunc_end0-_Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1608
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15rgb2hsl_gpu_sonPhS_S_PfS0_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
