// typedef struct {
//     unsigned long long int lo;
//     unsigned long long int hi;
//   } my_uint128;

//   my_uint128 add_uint128 (my_uint128 a, my_uint128 b)
//   {
//     my_uint128 res;
//     res.lo = a.lo + b.lo;
//     res.hi = a.hi + b.hi + (res.lo < a.lo);
//     return res;
//   }

// https://github.com/curtisseizert/CUDA-uint128
#include <stdint.h>
#include <iostream>

#define SLOTS_PER_BLOCK 1024

#define NUM_THREADS 256
#define NUM_BLOCKS 256

__constant__ uint64_t POWS[19] = {1ll, 10ll, 100ll, 1000ll, 10000ll, 100000ll, 1000000ll,
                                  10000000ll, 100000000ll, 1000000000ll, 10000000000ll,
                                  100000000000ll, 1000000000000ll, 10000000000000ll,
                                  100000000000000ll, 1000000000000000ll, 10000000000000000ll,
                                  100000000000000000ll, 1000000000000000000ll};


__global__ void isPolydivisible(uint64_t maxNum, uint64_t *results) {

    uint64_t start = blockIdx.x * blockDim.x + threadIdx.x;
    uint64_t stride = blockDim.x * gridDim.x;

    uint16_t numberFound = 0;
    uint64_t *threadResults = results + start * SLOTS_PER_BLOCK;

    for(uint64_t n = start; n < maxNum; n += stride) {
        bool polydivisible = true;
        uint16_t numDigits = 1;

        for(int i = 0; i < 19; ++i) {
            if(n >= POWS[i]) {
                numDigits = i + 1;
            }
        }

        __syncthreads();

        for(int i = 0; i < numDigits; ++i) {
            uint64_t num = n / POWS[i];
            if (num % (numDigits - i) != 0)
                polydivisible = false;
        }

        if(polydivisible)
            threadResults[numberFound++] = n;

        // Maybe sync threads?
    }
}


int main() {

    std::cout << "Enter the maximum number: " << std::flush;
    uint64_t maxNum = 0;
    std::cin >> maxNum;

    uint64_t *results;
    uint64_t arrLen = SLOTS_PER_BLOCK * NUM_BLOCKS * NUM_THREADS;
    cudaMallocManaged(&results, arrLen  * sizeof(uint64_t) );

    for(uint64_t i = 0; i < arrLen; ++i) {
        results[i] = 0;
    }

    cudaEvent_t start, stop;

    cudaEventCreate(&start);
    cudaEventCreate(&stop);

    cudaEventRecord(start);

    isPolydivisible<<<NUM_BLOCKS,NUM_THREADS>>>(maxNum, results);

    cudaEventRecord(stop);
    cudaEventSynchronize(stop);

    float millis = 0;
    cudaEventElapsedTime(&millis, start, stop);

    uint64_t count = 1;
    for(uint64_t i = 0; i < arrLen; ++i) {
        if(results[i] != 0) {
            std::cout << results[i] << "\n";
            ++count;
        }
    }

    std::cout << std::flush;

    printf("%0.3fs, %d numbers found\n", millis / 1000, count);
}

	.file	"tmpxft_002f58dd_00000000-6_PolydivisibleNumbersCUDA.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z15isPolydivisiblemPmmPm
	.type	_Z36__device_stub__Z15isPolydivisiblemPmmPm, @function
_Z36__device_stub__Z15isPolydivisiblemPmmPm:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15isPolydivisiblemPm(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z36__device_stub__Z15isPolydivisiblemPmmPm, .-_Z36__device_stub__Z15isPolydivisiblemPmmPm
	.globl	_Z15isPolydivisiblemPm
	.type	_Z15isPolydivisiblemPm, @function
_Z15isPolydivisiblemPm:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z15isPolydivisiblemPmmPm
	.cfi_endproc
.LFE3661:
	.size	_Z15isPolydivisiblemPm, .-_Z15isPolydivisiblemPm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter the maximum number: "
.LC2:
	.string	"\n"
.LC4:
	.string	"%0.3fs, %d numbers found\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC0(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	_ZSt4cout(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%r12, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$72, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZNSo5flushEv@PLT
	xorl	%eax, %eax
	movq	%rsp, %rsi
	leaq	_ZSt3cin(%rip), %rdi
	movq	%rax, (%rsp)
	call	_ZNSi10_M_extractImEERSiRT_@PLT
	movl	$1, %edx
	movl	$536870912, %esi
	leaq	8(%rsp), %rdi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %rdi
	xorl	%eax, %eax
	movl	$134217728, %ecx
	rep stosl
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$16777217, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 52(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 44(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z36__device_stub__Z15isPolydivisiblemPmmPm
.L9:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	movl	$1, %ebp
	leaq	.LC2(%rip), %r13
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	44(%rsp), %rdi
	movl	$0x00000000, 44(%rsp)
	call	cudaEventElapsedTime@PLT
.L11:
	movq	8(%rsp), %rax
	movq	(%rax,%rbx), %rsi
	testq	%rsi, %rsi
	je	.L10
	movq	%r12, %rdi
	incq	%rbp
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%r13, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L10:
	addq	$8, %rbx
	cmpq	$536870912, %rbx
	jne	.L11
	movq	%r12, %rdi
	call	_ZNSo5flushEv@PLT
	movq	%rbp, %rdx
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC4(%rip), %rsi
	movss	44(%rsp), %xmm0
	divss	.LC3(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$72, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z15isPolydivisiblemPm"
.LC6:
	.string	"POWS"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15isPolydivisiblemPm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movl	$152, %r9d
	leaq	_ZL4POWS(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL4POWS
	.comm	_ZL4POWS,152,32
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// typedef struct {
//     unsigned long long int lo;
//     unsigned long long int hi;
//   } my_uint128;

//   my_uint128 add_uint128 (my_uint128 a, my_uint128 b)
//   {
//     my_uint128 res;
//     res.lo = a.lo + b.lo;
//     res.hi = a.hi + b.hi + (res.lo < a.lo);
//     return res;
//   }

// https://github.com/curtisseizert/CUDA-uint128

#include <hip/hip_runtime.h>
#include <stdint.h>
#include <iostream>

#define SLOTS_PER_BLOCK 1024

#define NUM_THREADS 256
#define NUM_BLOCKS 256

__constant__ uint64_t POWS[19] = {1ll, 10ll, 100ll, 1000ll, 10000ll, 100000ll, 1000000ll,
                                  10000000ll, 100000000ll, 1000000000ll, 10000000000ll,
                                  100000000000ll, 1000000000000ll, 10000000000000ll,
                                  100000000000000ll, 1000000000000000ll, 10000000000000000ll,
                                  100000000000000000ll, 1000000000000000000ll};


__global__ void isPolydivisible(uint64_t maxNum, uint64_t *results) {

    uint64_t start = blockIdx.x * blockDim.x + threadIdx.x;
    uint64_t stride = blockDim.x * gridDim.x;

    uint16_t numberFound = 0;
    uint64_t *threadResults = results + start * SLOTS_PER_BLOCK;

    for(uint64_t n = start; n < maxNum; n += stride) {
        bool polydivisible = true;
        uint16_t numDigits = 1;

        for(int i = 0; i < 19; ++i) {
            if(n >= POWS[i]) {
                numDigits = i + 1;
            }
        }

        __syncthreads();

        for(int i = 0; i < numDigits; ++i) {
            uint64_t num = n / POWS[i];
            if (num % (numDigits - i) != 0)
                polydivisible = false;
        }

        if(polydivisible)
            threadResults[numberFound++] = n;

        // Maybe sync threads?
    }
}


int main() {

    std::cout << "Enter the maximum number: " << std::flush;
    uint64_t maxNum = 0;
    std::cin >> maxNum;

    uint64_t *results;
    uint64_t arrLen = SLOTS_PER_BLOCK * NUM_BLOCKS * NUM_THREADS;
    hipMallocManaged(&results, arrLen  * sizeof(uint64_t) );

    for(uint64_t i = 0; i < arrLen; ++i) {
        results[i] = 0;
    }

    hipEvent_t start, stop;

    hipEventCreate(&start);
    hipEventCreate(&stop);

    hipEventRecord(start);

    isPolydivisible<<<NUM_BLOCKS,NUM_THREADS>>>(maxNum, results);

    hipEventRecord(stop);
    hipEventSynchronize(stop);

    float millis = 0;
    hipEventElapsedTime(&millis, start, stop);

    uint64_t count = 1;
    for(uint64_t i = 0; i < arrLen; ++i) {
        if(results[i] != 0) {
            std::cout << results[i] << "\n";
            ++count;
        }
    }

    std::cout << std::flush;

    printf("%0.3fs, %d numbers found\n", millis / 1000, count);
}

	.text
	.file	"PolydivisibleNumbersCUDA.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub__isPolydivisiblemPm # -- Begin function _Z30__device_stub__isPolydivisiblemPm
	.type	_Z30__device_stub__isPolydivisiblemPm,@function
_Z30__device_stub__isPolydivisiblemPm:  # @_Z30__device_stub__isPolydivisiblemPm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15isPolydivisiblemPm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__isPolydivisiblemPm, .Lfunc_end0-_Z30__device_stub__isPolydivisiblemPm
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZNSo5flushEv
	leaq	32(%rsp), %rsi
	movq	$0, (%rsi)
	movl	$_ZSt3cin, %edi
	callq	_ZNSi10_M_extractImEERSiRT_
	leaq	16(%rsp), %rbx
	movl	$536870912, %esi                # imm = 0x20000000
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%rbx), %rdi
	movl	$536870912, %edx                # imm = 0x20000000
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	24(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967552, %rdi               # imm = 0x100000100
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z30__device_stub__isPolydivisiblemPm
.LBB1_2:
	movq	(%rsp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	12(%rsp), %rdi
	movl	$0, (%rdi)
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdx
	callq	hipEventElapsedTime
	movl	$1, %ebx
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movq	16(%rsp), %rax
	movq	(%rax,%r14,8), %rsi
	testq	%rsi, %rsi
	je	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertImEERSoT_
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%rbx
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	incq	%r14
	cmpq	$67108864, %r14                 # imm = 0x4000000
	jne	.LBB1_3
# %bb.6:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo5flushEv
	movss	12(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	divss	.LCPI1_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.2, %edi
	movq	%rbx, %rsi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15isPolydivisiblemPm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$POWS, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$152, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	POWS,@object                    # @POWS
	.local	POWS
	.comm	POWS,152,16
	.type	_Z15isPolydivisiblemPm,@object  # @_Z15isPolydivisiblemPm
	.section	.rodata,"a",@progbits
	.globl	_Z15isPolydivisiblemPm
	.p2align	3, 0x0
_Z15isPolydivisiblemPm:
	.quad	_Z30__device_stub__isPolydivisiblemPm
	.size	_Z15isPolydivisiblemPm, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Enter the maximum number: "
	.size	.L.str, 27

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%0.3fs, %d numbers found\n"
	.size	.L.str.2, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15isPolydivisiblemPm"
	.size	.L__unnamed_1, 23

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"POWS"
	.size	.L__unnamed_2, 5

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__isPolydivisiblemPm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym POWS
	.addrsig_sym _Z15isPolydivisiblemPm
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15isPolydivisiblemPm  ; -- Begin function _Z15isPolydivisiblemPm
	.globl	_Z15isPolydivisiblemPm
	.p2align	8
	.type	_Z15isPolydivisiblemPm,@function
_Z15isPolydivisiblemPm:                 ; @_Z15isPolydivisiblemPm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmpx_gt_u64_e64 s[4:5], v[1:2]
	s_cbranch_execz .LBB0_11
; %bb.1:                                ; %.preheader.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_lshlrev_b64 v[3:4], 13, v[1:2]
	v_mov_b32_e32 v0, v1
	v_mov_b32_e32 v1, v2
	s_mov_b32 s8, 0
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s9, s0, s2
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;     Child Loop BB0_6 Depth 2
	v_mov_b32_e32 v5, 1
	s_mov_b32 s2, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, POWS@rel32@lo+4
	s_addc_u32 s1, s1, POWS@rel32@hi+12
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b64 s[6:7], s[0:1], 0x0
	s_add_i32 s2, s2, 1
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s2, 19
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[0:1]
	v_cndmask_b32_e32 v5, s2, v5, vcc_lo
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
	s_mov_b32 s11, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_ne_u16_e32 0, v5
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v6, s8 :: v_dual_and_b32 v5, 0xffff, v5
	s_mov_b32 s13, -1
	s_mov_b32 s12, 0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, POWS@rel32@lo+4
	s_addc_u32 s3, s3, POWS@rel32@hi+12
                                        ; implicit-def: $sgpr14
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b64 s[6:7], s[2:3], 0x0
	v_cvt_f32_u32_e32 v7, v5
	v_cvt_f32_u32_e32 v8, v6
	v_sub_co_u32 v18, vcc_lo, 0, v5
	v_sub_co_ci_u32_e32 v19, vcc_lo, 0, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v9, s7
	v_fmac_f32_e32 v7, 0x4f800000, v8
	v_cvt_f32_u32_e32 v8, s6
	s_sub_u32 s0, 0, s6
	s_subb_u32 s1, 0, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x4f800000, v9
	v_rcp_f32_e32 v7, v7
	v_rcp_f32_e32 v8, v8
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v7, 0x5f7ffffc, v7 :: v_dual_mul_f32 v14, 0x5f7ffffc, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, 0x2f800000, v7 :: v_dual_mul_f32 v11, 0x2f800000, v14
	v_trunc_f32_e32 v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_trunc_f32_e32 v11, v11
	v_fmac_f32_e32 v7, 0xcf800000, v9
	v_cvt_u32_f32_e32 v20, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, 0xcf800000, v11
	v_cvt_u32_f32_e32 v21, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, v18, v20
	v_cvt_u32_f32_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, v19, v21
	v_mad_u64_u32 v[7:8], null, v18, v21, 0
	v_mul_hi_u32 v17, s0, v14
	v_mul_lo_u32 v23, s1, v14
	v_mul_lo_u32 v22, s0, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add3_u32 v15, v8, v9, v10
	v_mul_hi_u32 v16, v21, v7
	v_mad_u64_u32 v[8:9], null, v20, v7, 0
	v_cvt_u32_f32_e32 v7, v11
	v_mad_u64_u32 v[10:11], null, v21, v15, 0
	v_mad_u64_u32 v[12:13], null, v20, v15, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v15, s0, v7
	v_add_co_u32 v24, vcc_lo, v16, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v25, vcc_lo, 0, v11, vcc_lo
	v_add_nc_u32_e32 v10, v17, v15
	v_mul_hi_u32 v11, v14, v22
	v_mul_hi_u32 v15, v7, v22
	v_mul_lo_u32 v16, v7, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v23
	v_mul_lo_u32 v17, v14, v10
	v_mul_hi_u32 v22, v14, v10
	v_mul_hi_u32 v23, v7, v10
	v_mul_lo_u32 v10, v7, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, v11, v17
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v16
	v_add_co_ci_u32_e32 v11, vcc_lo, v17, v15, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v11, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v14, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v14, s0, v10
	v_mul_lo_u32 v15, s1, v10
	v_mul_lo_u32 v16, s0, v7
	v_mul_lo_u32 v11, s0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v16
	v_mul_hi_u32 v17, v7, v11
	v_mul_lo_u32 v22, v7, v11
	v_mul_hi_u32 v11, v10, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v15
	v_mul_lo_u32 v15, v10, v14
	v_mul_hi_u32 v16, v10, v14
	v_mul_hi_u32 v23, v7, v14
	v_mul_lo_u32 v14, v7, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, v11, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v22
	v_add_co_ci_u32_e32 v11, vcc_lo, v15, v17, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v11, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v22, v0, v15
	v_mad_u64_u32 v[10:11], null, v1, v15, 0
	v_mad_u64_u32 v[14:15], null, v0, v7, 0
	v_mad_u64_u32 v[16:17], null, v1, v7, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v22, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v7, v10
	v_add_co_ci_u32_e32 v7, vcc_lo, v14, v11, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v8, vcc_lo, v24, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, s0, v7, v16
	v_add_co_ci_u32_e32 v9, vcc_lo, v25, v9, vcc_lo
	v_add_co_ci_u32_e64 v15, s0, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v11, s7, v14
	v_mad_u64_u32 v[7:8], null, s6, v14, 0
	v_add_co_u32 v9, s0, v9, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v12, s6, v15
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, v14, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v21, vcc_lo, v21, v9
	v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
	v_add3_u32 v12, v8, v12, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[8:9], null, v18, v21, 0
	v_add_co_ci_u32_e32 v20, vcc_lo, v20, v10, vcc_lo
	v_mul_lo_u32 v13, v19, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v19, v1, v12
	v_sub_co_u32 v7, vcc_lo, v0, v7
	v_mul_lo_u32 v18, v18, v20
	v_mad_u64_u32 v[10:11], null, v20, v8, 0
	v_mul_hi_u32 v24, v21, v8
	v_subrev_co_ci_u32_e64 v8, s0, s7, v19, vcc_lo
	v_sub_co_ci_u32_e32 v12, vcc_lo, v1, v12, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s6, v7
	v_sub_co_u32 v19, s0, v7, s6
	v_add3_u32 v9, v9, v18, v13
	v_add_co_u32 v17, s1, v14, 2
	v_cndmask_b32_e64 v25, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v18, vcc_lo, 0, v8, s0
	v_cmp_le_u32_e32 vcc_lo, s6, v19
	v_mad_u64_u32 v[7:8], null, v21, v9, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u32_e64 s0, s7, v18
	v_add_co_ci_u32_e64 v22, s1, 0, v15, s1
	v_cndmask_b32_e64 v19, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s7, v12
	v_cndmask_b32_e64 v26, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s7, v12
	v_mad_u64_u32 v[12:13], null, v20, v9, 0
	v_cndmask_b32_e64 v9, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s7, v18
	v_cndmask_b32_e32 v18, v26, v25, vcc_lo
	v_add_co_u32 v7, vcc_lo, v24, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v19, s0
	v_add_co_u32 v7, vcc_lo, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v11, vcc_lo
	v_cmp_ne_u32_e64 s0, 0, v9
	v_cmp_ne_u32_e64 s1, 0, v18
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, v8, v12
	v_cndmask_b32_e64 v7, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v10, vcc_lo, v21, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v14, v7, s1
	v_cndmask_b32_e64 v7, v23, v22, s0
	v_mul_hi_u32 v16, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v15, v7, s1
	v_add_co_ci_u32_e32 v15, vcc_lo, v20, v9, vcc_lo
	v_mad_u64_u32 v[7:8], null, v14, v10, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, v13, v15, 0
	v_mad_u64_u32 v[11:12], null, v14, v15, 0
	v_add_co_u32 v9, vcc_lo, v16, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v7, vcc_lo, v9, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v10, v8, vcc_lo
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
	v_add_co_u32 v9, vcc_lo, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	v_mul_lo_u32 v11, v6, v9
	v_mad_u64_u32 v[7:8], null, v5, v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v5, v10
	v_sub_co_u32 v7, vcc_lo, v13, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v8, v8, v9, v11
	v_sub_nc_u32_e32 v9, v14, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v9, s0, v9, v6, vcc_lo
	v_sub_co_ci_u32_e32 v8, vcc_lo, v14, v8, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v7, v5
	v_sub_co_u32 v10, s0, v7, v5
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v12, vcc_lo, 0, v9, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_u32_e32 vcc_lo, v10, v5
	v_cmp_ge_u32_e64 s1, v12, v6
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_sub_co_ci_u32_e64 v9, vcc_lo, v9, v6, s0
	v_cmp_ge_u32_e64 s0, v8, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, 0, -1, s1
	v_cmp_eq_u32_e64 s1, v12, v6
	v_sub_co_u32 v14, vcc_lo, v10, v5
	v_cndmask_b32_e64 v16, 0, -1, s0
	v_cmp_eq_u32_e64 s0, v8, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v15, v13, s1
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_cndmask_b32_e64 v11, v16, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v13
	v_cmp_ne_u32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v9, v12, v9 :: v_dual_cndmask_b32 v10, v10, v14
	v_add_co_u32 v5, vcc_lo, v5, -1
	v_add_co_ci_u32_e32 v6, vcc_lo, -1, v6, vcc_lo
	v_cndmask_b32_e64 v8, v8, v9, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v7, v10, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e64 s0, 0, v[7:8]
	s_and_b32 s13, s0, s13
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_or_b32 s12, vcc_lo, s12
	s_and_not1_b32 s0, s14, exec_lo
	s_and_b32 s1, s13, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s14, s0, s1
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s0, s14, exec_lo
.LBB0_8:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_10
; %bb.9:                                ; %.critedge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v5, 0xffff, v2
	v_add_nc_u16 v2, v2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v5, 3, v5
	v_add_co_u32 v5, vcc_lo, v3, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
	global_store_b64 v[5:6], v[0:1], off
.LBB0_10:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v0, vcc_lo, v0, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[0:1]
	s_or_b32 s10, vcc_lo, s10
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_2
.LBB0_11:                               ; %._crit_edge40
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15isPolydivisiblemPm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15isPolydivisiblemPm, .Lfunc_end0-_Z15isPolydivisiblemPm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1908
; NumSgprs: 18
; NumVgprs: 27
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	POWS                    ; @POWS
	.type	POWS,@object
	.data
	.globl	POWS
	.p2align	4, 0x0
POWS:
	.quad	1                               ; 0x1
	.quad	10                              ; 0xa
	.quad	100                             ; 0x64
	.quad	1000                            ; 0x3e8
	.quad	10000                           ; 0x2710
	.quad	100000                          ; 0x186a0
	.quad	1000000                         ; 0xf4240
	.quad	10000000                        ; 0x989680
	.quad	100000000                       ; 0x5f5e100
	.quad	1000000000                      ; 0x3b9aca00
	.quad	10000000000                     ; 0x2540be400
	.quad	100000000000                    ; 0x174876e800
	.quad	1000000000000                   ; 0xe8d4a51000
	.quad	10000000000000                  ; 0x9184e72a000
	.quad	100000000000000                 ; 0x5af3107a4000
	.quad	1000000000000000                ; 0x38d7ea4c68000
	.quad	10000000000000000               ; 0x2386f26fc10000
	.quad	100000000000000000              ; 0x16345785d8a0000
	.quad	1000000000000000000             ; 0xde0b6b3a7640000
	.size	POWS, 152

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym POWS
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15isPolydivisiblemPm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15isPolydivisiblemPm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
