#include <stdio.h>
#include <math.h>
#include <cuda.h>
#include <iostream>
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>

__global__ void gpuMatSub(float* A, float* B, float* C, int Nrows, int Ncols) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < Ncols) && (ty < Nrows)) {
    tid = Ncols * ty + tx;
    C[tid] = A[tid] - B[tid];
  }
}

__global__ void gpuMatMul(float *A, float *B, float *C, int m, int n, int p) { 
  int row = blockIdx.y * blockDim.y + threadIdx.y; 
  int col = blockIdx.x * blockDim.x + threadIdx.x;
  float S = 0;
  if (col < p && row < m) {
    for(int i = 0; i < n; i++) {
      S += A[row * n + i] * B[i * p + col];
    }
    C[row * p + col] = S;
  }
}

__global__ void gpuMatTranspose(float *A, float *B, int Nrows, int Ncols)
{
  unsigned int tx, ty, pos, trans_pos;
  tx = blockIdx.x * blockDim.x + threadIdx.x;
  ty = blockIdx.y * blockDim.y + threadIdx.y;
  if (tx < Ncols && ty < Nrows) {
    pos = ty * Ncols + tx;
    trans_pos = tx * Nrows + ty;
    B[trans_pos] = A[pos];
  }
}

__global__ void gpuMatMulScalar(float *A, float *B, int Nrows, int Ncols, float lambda) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < Ncols) && (ty < Nrows)) {
    tid = Ncols * ty + tx;
    B[tid] = A[tid] * lambda;
  }
}

__global__ void gpuNorm2(float *A, float *norm, int N) {
  extern __shared__ float sdata[];
  unsigned int tid = threadIdx.x;
  unsigned int gid = tid + blockIdx.x * blockDim.x;

  if (gid < N) sdata[tid] = A[gid];
  else sdata[tid] = 0;
  __syncthreads();

  sdata[tid] = sdata[tid] * sdata[tid];
  __syncthreads();

  for (unsigned int stride = blockDim.x/2; stride > 0; stride = stride >> 1) {
    if (tid < stride) sdata[tid] = sdata[tid] + sdata[tid + stride];
    __syncthreads();
  }

  if (tid == 0) atomicAdd(norm, sdata[0]);
}

__global__ void gpuMeanVec(int *trainMat, int Ntrain, int dimension, float *mean) {
  int tid = threadIdx.x + blockIdx.x * blockDim.x;
  float tmp = 0;
  int DestIndex;
  for (int i = 0; i < Ntrain; i++) {
    DestIndex = i * dimension + tid;
    tmp = tmp + trainMat[DestIndex];
  }
  mean[tid] = tmp / Ntrain;
}

__global__ void gpuSubMean(int *trainMat, float *mean, int Ntrain, int dimension, float *X) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < dimension) && (ty < Ntrain)) {
    tid = dimension * ty + tx;
    X[tid] = trainMat[tid] - mean[tx];
  }
}

__global__ void gpuCovMat(float *A, float *B, int Nrows, int Ncols, float lambda) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < Ncols) && (ty < Nrows)) {
    tid = Ncols * ty + tx;
    B[tid] = A[tid] / lambda;
  }
}

__global__ void gpuNormalize(float *A, float *norm, float *B, int N) {
  extern __shared__ float sdata[];
  unsigned int tid = threadIdx.x;
  unsigned int gid = tid + blockIdx.x * blockDim.x;

  if (tid == 0) sdata[0] = norm[0];
  __syncthreads();

  if (gid < N) B[gid] = A[gid] / sdata[0];
}

__global__ void gpuEigVal(float *A, float *B, float *eigVal, int N) {
  extern __shared__ float sdata[];
  unsigned int tid = threadIdx.x;
  unsigned int gid = tid + blockIdx.x * blockDim.x;

  if (gid < N) sdata[tid] = A[gid] * B[gid];
  else sdata[tid] = 0;
  __syncthreads();

  for (unsigned int stride = blockDim.x/2; stride > 0; stride = stride >> 1) {
    if (tid < stride) sdata[tid] = sdata[tid] + sdata[tid+stride];
    __syncthreads();
  }
  if (tid == 0) atomicAdd(eigVal, sdata[0]);
}

float cpuNorm2(float *A, int Nrows, int Ncols) {
  float tmp = 0;
  float Norm;
  int DestIndex;
  for (int col = 0; col < Ncols; col++) {
    for (int row = 0; row < Nrows; row++) {
      DestIndex = row * Ncols + col;
      tmp = tmp + A[DestIndex] * A[DestIndex];
    }
  }
  Norm = sqrt(tmp);
  return Norm;
}

void cpuMatSub(float* A, float* B, int Nrows, int Ncols, float* C) {
  int col = 0;
  int row = 0;
  int DestIndex = 0;
  for (col = 0; col < Ncols; col++) {
    for (row = 0; row < Nrows; row++) {
      DestIndex = row * Ncols + col;
      C[DestIndex] = A[DestIndex] - B[DestIndex];
    }
  }
}

void identify(float *project_train_img, float *project_test_img, int Ntrain, int Ntest, int dimension, int *recognized_img) {
  int DestIndex;
  float *test;
  float *train;
  float *D;
  float distance = 0;
  float min;

  int buffer = dimension * sizeof(float);
  test = (float*)malloc(buffer);
  train = (float*)malloc(buffer);
  D = (float*)malloc(buffer);

  for (int i = 0; i < Ntest; i++) {
    min = 100000;
    for (int j = 0; j < dimension; j++) {
      DestIndex = i * dimension + j;
      test[j] = project_test_img[DestIndex];
    }

    for (int m = 0; m < Ntrain; m++) {
      for (int n = 0; n < dimension; n++) {
        DestIndex = m * dimension + n;
        train[n] = project_train_img[DestIndex];
      }
      cpuMatSub(train, test, 1, dimension, D);
      distance = cpuNorm2(D, 1, dimension);
      if (distance < min) {
        min = distance;
        recognized_img[i] = m + 1;
      }
    }
  }

  free(test);
  free(train);
  free(D);
}

int main() {
  FILE *fp_train;
  FILE *fp_test;
  FILE *fp_id;
  int *trainMat;
  int *testMat;
  int Ntrain = 163; // Number of training images
  int Ntest = 50;   // Number of test images
  int imgSize = 64; // Size of image
  int k = 50;       // Number of the principal components

  int dimension = imgSize * imgSize;  // The original dimension 4096
  int DestIndex;

  int trainMatBuffer = Ntrain * dimension * sizeof(int);
  int testMatBuffer = Ntest * dimension * sizeof(int);

  // Read training set
  trainMat = (int*)malloc(trainMatBuffer);
  fp_train = fopen("train_matrix.txt", "r");
  if (fp_train == NULL) {
    printf("Error open file\n");
    return 1;
  }
  for (int i = 0; i < Ntrain; i++) {
    for (int j = 0; j < dimension; j++) {
      DestIndex = i * dimension + j;
      fscanf(fp_train, "%d", &trainMat[DestIndex]);
    }
  }
  fclose(fp_train);

  // Read test set
  testMat = (int*)malloc(testMatBuffer);
  fp_test = fopen("test_matrix.txt", "r");
  if (fp_test == NULL) {
    printf("Error open file\n");
    return 1;
  }
  for (int i = 0; i < Ntest; i++) {
    for (int j = 0; j < dimension; j++) {
      DestIndex = i * dimension + j;
      fscanf(fp_test, "%d", &testMat[DestIndex]);
    }
  }
  fclose(fp_test);

  int *d_trainMat;
  int *d_testMat;
  float *d_mean;

  int imgBuffer = dimension * sizeof(float);

  cudaMalloc((void**)&d_trainMat, trainMatBuffer);
  cudaMalloc((void**)&d_testMat, testMatBuffer);
  cudaMalloc((void**)&d_mean, imgBuffer);

  // Copy the training and test matrices from Host to Device
  cudaMemcpy(d_trainMat, trainMat, trainMatBuffer, cudaMemcpyHostToDevice);
  cudaMemcpy(d_testMat, testMat, testMatBuffer, cudaMemcpyHostToDevice);

  // Calculate the mean vector of the training matrix
  gpuMeanVec<<<32, 128>>>(d_trainMat, Ntrain, dimension, d_mean);

  // Compute the difference between each image vector and the mean vector
  dim3 block1(128, 1);
  dim3 grid1(dimension/128, Ntrain);
  float *d_X;
  int Xbuffer = Ntrain * dimension * sizeof(float);
  cudaMalloc((void**)&d_X, Xbuffer);
  gpuSubMean<<<grid1, block1>>>(d_trainMat, d_mean, Ntrain, dimension, d_X);

  // Determine the covariance matrix
  int covMatBuffer = dimension * dimension * sizeof(float);
  float *d_Xt, *d_covMat;
  cudaMalloc((void**)&d_Xt, Xbuffer);
  cudaMalloc((void**)&d_covMat, covMatBuffer);
  gpuMatTranspose<<<grid1, block1>>>(d_X, d_Xt, Ntrain, dimension);
  dim3 block2(32, 16);
  dim3 grid2(dimension/32, dimension/16);
  gpuMatMul<<<grid2, block2>>>(d_Xt, d_X, d_covMat, dimension, Ntrain, dimension);

  // Find eigenvalues and eigenvectors of the covariance matrix
  float prev_lambda = 0;
  const float eps = 0.000001;

  float *Q, *normZ, *k_eig_vec;
  float *d_Q, *d_Z, *d_W, *d_normZ;

  int normBuffer = sizeof(float);
  int eigVecBuffer = k * imgBuffer;

  Q = (float*)malloc(imgBuffer);
  normZ = (float*)malloc(normBuffer);
  k_eig_vec = (float*)malloc(eigVecBuffer);

  cudaMalloc((void**)&d_Q, imgBuffer);
  cudaMalloc((void**)&d_Z, imgBuffer);
  cudaMalloc((void**)&d_W, covMatBuffer);
  cudaMalloc((void**)&d_normZ, normBuffer);

  int block3 = 32;
  int grid3 = dimension / block3;
  int sharedMemSize = block3 * sizeof(float);

  for (int i = 0; i < k; i++) {
    Q[0] = 1;
    for (int m = 1; m < dimension; m++) Q[m] = 0;
    cudaMemcpy(d_Q, Q, imgBuffer, cudaMemcpyHostToDevice);
    gpuMatMul<<<16, 256>>>(d_covMat, d_Q, d_Z, dimension, dimension, 1);

    // Power Method iteration
    for (int j = 0; j < 1000; j++) {
      normZ[0] = 0;
      cudaMemcpy(d_normZ, normZ, normBuffer, cudaMemcpyHostToDevice);
      gpuNorm2<<<grid3, block3, sharedMemSize>>>(d_Z, d_normZ, dimension);
      cudaThreadSynchronize();
      cudaMemcpy(normZ, d_normZ, normBuffer, cudaMemcpyDeviceToHost);
      normZ[0] = sqrt(normZ[0]);
      cudaMemcpy(d_normZ, normZ, normBuffer, cudaMemcpyHostToDevice);
      gpuNormalize<<<grid3, block3, sharedMemSize>>>(d_Z, d_normZ, d_Q, dimension);
      cudaThreadSynchronize();
      gpuMatMul<<<16, 256>>>(d_Q, d_covMat, d_Z, 1, dimension, dimension);
      cudaThreadSynchronize();
      normZ[0] = 0;
      cudaMemcpy(d_normZ, normZ, normBuffer, cudaMemcpyHostToDevice);
      gpuEigVal<<<grid3, block3, sharedMemSize>>>(d_Q, d_Z, d_normZ, dimension);
      cudaThreadSynchronize();
      cudaMemcpy(normZ, d_normZ, normBuffer, cudaMemcpyDeviceToHost);

      if (abs(prev_lambda-normZ[0]) < eps) {
        cudaMemcpy(Q, d_Q, imgBuffer, cudaMemcpyDeviceToHost);
        break;
      }
      prev_lambda = normZ[0];
    }

    // The new subspace created by k eigenvectors
    for (int p = 0; p < dimension; p++) {
      DestIndex = p * k + i;
      k_eig_vec[DestIndex] = Q[p];
    }

    // Calculate the new covariance matrix for the next eigenvalue and eigenvector
    gpuMatMul<<<grid2, block2>>>(d_Q, d_Q, d_W, dimension, 1, dimension);
    gpuMatMulScalar<<<grid2, block2>>>(d_W, d_W, dimension, dimension, normZ[0]);
    gpuMatSub<<<grid2, block2>>>(d_covMat, d_W, d_covMat, dimension, dimension);
  }

  // Project the training images in the new subspace
  float *d_kEigVec, *d_proj_train;
  int projTrainBuffer = Ntrain * k * sizeof(float);
  cudaMalloc((void**)&d_kEigVec, eigVecBuffer);
  cudaMalloc((void**)&d_proj_train, projTrainBuffer);
  cudaMemcpy(d_kEigVec, k_eig_vec, eigVecBuffer, cudaMemcpyHostToDevice);
  dim3 grid4((k+block2.x-1)/block2.x, (Ntrain+block2.y-1)/block2.y);
  gpuMatMul<<<grid4, block2>>>(d_X, d_kEigVec, d_proj_train, Ntrain, dimension, k);

  // Project the test images in the new subspace
  float *d_X1;
  cudaMalloc((void**)&d_X1, testMatBuffer);
  dim3 grid5(dimension/128, Ntest);
  gpuSubMean<<<grid5, block1>>>(d_testMat, d_mean, Ntest, dimension, d_X1);

  float *d_proj_test;
  int projTestBuffer = Ntest * k * sizeof(float);
  cudaMalloc((void**)&d_proj_test, projTestBuffer);
  dim3 grid6((k+block2.x-1)/block2.x, (Ntest+block2.y-1)/block2.y);
  gpuMatMul<<<grid6, block2>>>(d_X1, d_kEigVec, d_proj_test, Ntest, dimension, k);

  // Copy projected training and test matrices from Device to Host
  float *project_train_img, *project_test_img;
  project_train_img = (float*)malloc(projTrainBuffer);
  project_test_img = (float*)malloc(projTestBuffer);
  cudaMemcpy(project_train_img, d_proj_train, projTrainBuffer, cudaMemcpyDeviceToHost);
  cudaMemcpy(project_test_img, d_proj_test, projTestBuffer, cudaMemcpyDeviceToHost);

  cudaProfilerStop();

  // Choose the most similar images in the training set
  int *recognized_img;
  int recogBuffer = Ntest * sizeof(int);
  recognized_img = (int*)malloc(recogBuffer);
  identify(project_train_img, project_test_img, Ntrain, Ntest, k, recognized_img);

  fp_id = fopen("identify.txt", "wb");
  if (fp_id == NULL) {
    printf("Error open file\n");
    return 1;
  }
  fprintf(fp_id, "Test Image\t\tPrediction\n");
  for (int i = 0; i < Ntest; i++) {
    fprintf(fp_id, "%d \t\t\t\t %d\n", i + 1, recognized_img[i]);
  }
  fclose(fp_id);

  free(fp_train);
  free(fp_test);
  free(fp_id);
  free(trainMat);
  free(testMat);
  free(Q);
  free(normZ);
  free(k_eig_vec);
  free(project_train_img);
  free(project_test_img);
  free(recognized_img);

  cudaFree(d_trainMat);
  cudaFree(d_testMat);
  cudaFree(d_mean);
  cudaFree(d_X);
  cudaFree(d_covMat);
  cudaFree(d_Q);
  cudaFree(d_Z);
  cudaFree(d_W);
  cudaFree(d_normZ);
  cudaFree(d_kEigVec);
  cudaFree(d_proj_train);
  cudaFree(d_X1);
  cudaFree(d_proj_test);

  return 0;
}

	.file	"tmpxft_00367416_00000000-6_PCA.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3641:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3641:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z8cpuNorm2Pfii
	.type	_Z8cpuNorm2Pfii, @function
_Z8cpuNorm2Pfii:
.LFB3635:
	.cfi_startproc
	endbr64
	movslq	%edx, %rcx
	xorl	%eax, %eax
	xorps	%xmm1, %xmm1
	salq	$2, %rcx
.L3:
	cmpl	%edx, %eax
	jge	.L8
	movq	%rdi, %r9
	xorl	%r8d, %r8d
.L5:
	cmpl	%esi, %r8d
	jge	.L9
	movss	(%r9), %xmm0
	incl	%r8d
	addq	%rcx, %r9
	mulss	%xmm0, %xmm0
	addss	%xmm0, %xmm1
	jmp	.L5
.L9:
	incl	%eax
	addq	$4, %rdi
	jmp	.L3
.L8:
	movaps	%xmm1, %xmm0
	jmp	sqrtf@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z8cpuNorm2Pfii, .-_Z8cpuNorm2Pfii
	.globl	_Z9cpuMatSubPfS_iiS_
	.type	_Z9cpuMatSubPfS_iiS_, @function
_Z9cpuMatSubPfS_iiS_:
.LFB3636:
	.cfi_startproc
	endbr64
	movslq	%ecx, %r9
	movq	%rsi, %r11
	movq	%rdi, %r10
	xorl	%esi, %esi
	salq	$2, %r9
.L11:
	cmpl	%esi, %ecx
	jle	.L10
	leaq	0(,%rsi,4), %rax
	xorl	%edi, %edi
.L14:
	cmpl	%edx, %edi
	jge	.L15
	movss	(%r10,%rax), %xmm0
	subss	(%r11,%rax), %xmm0
	incl	%edi
	movss	%xmm0, (%r8,%rax)
	addq	%r9, %rax
	jmp	.L14
.L15:
	incq	%rsi
	jmp	.L11
.L10:
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z9cpuMatSubPfS_iiS_, .-_Z9cpuMatSubPfS_iiS_
	.globl	_Z8identifyPfS_iiiPi
	.type	_Z8identifyPfS_iiiPi, @function
_Z8identifyPfS_iiiPi:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%r9, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edx, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leal	0(,%r8,4), %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%ebp, %rbp
	movl	%r8d, %ebx
	movq	%rbp, %rdi
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movl	%ecx, 24(%rsp)
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	%rbp, %rdi
	xorl	%ebp, %ebp
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	xorl	%r9d, %r9d
	movq	%rax, 16(%rsp)
.L17:
	cmpl	%r9d, 24(%rsp)
	jle	.L25
	movslq	%ebp, %rax
	leaq	(%r12,%rax,4), %rdx
	xorl	%eax, %eax
.L26:
	cmpl	%eax, %ebx
	jle	.L29
	movss	(%rdx,%rax,4), %xmm0
	movq	(%rsp), %rsi
	movss	%xmm0, (%rsi,%rax,4)
	incq	%rax
	jmp	.L26
.L29:
	movss	.LC1(%rip), %xmm1
	xorl	%r11d, %r11d
	xorl	%eax, %eax
.L19:
	cmpl	%r14d, %eax
	jge	.L23
	movslq	%r11d, %rdx
	leaq	0(%r13,%rdx,4), %rcx
	xorl	%edx, %edx
.L24:
	cmpl	%edx, %ebx
	jle	.L30
	movss	(%rcx,%rdx,4), %xmm0
	movq	8(%rsp), %rsi
	movss	%xmm0, (%rsi,%rdx,4)
	incq	%rdx
	jmp	.L24
.L30:
	movq	16(%rsp), %r8
	movq	(%rsp), %rsi
	movl	%ebx, %ecx
	movl	$1, %edx
	movq	8(%rsp), %rdi
	movq	%r9, 40(%rsp)
	movl	%r11d, 36(%rsp)
	movl	%eax, 32(%rsp)
	movss	%xmm1, 28(%rsp)
	call	_Z9cpuMatSubPfS_iiS_
	movq	16(%rsp), %rdi
	movl	%ebx, %edx
	movl	$1, %esi
	call	_Z8cpuNorm2Pfii
	movl	32(%rsp), %eax
	movss	28(%rsp), %xmm1
	movl	36(%rsp), %r11d
	movq	40(%rsp), %r9
	incl	%eax
	comiss	%xmm0, %xmm1
	jbe	.L21
	movl	%eax, (%r15,%r9,4)
	movaps	%xmm0, %xmm1
.L21:
	addl	%ebx, %r11d
	jmp	.L19
.L23:
	incq	%r9
	addl	%ebx, %ebp
	jmp	.L17
.L25:
	movq	(%rsp), %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE3637:
	.size	_Z8identifyPfS_iiiPi, .-_Z8identifyPfS_iiiPi
	.globl	_Z34__device_stub__Z9gpuMatSubPfS_S_iiPfS_S_ii
	.type	_Z34__device_stub__Z9gpuMatSubPfS_S_iiPfS_S_ii, @function
_Z34__device_stub__Z9gpuMatSubPfS_S_iiPfS_S_ii:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9gpuMatSubPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L31:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z34__device_stub__Z9gpuMatSubPfS_S_iiPfS_S_ii, .-_Z34__device_stub__Z9gpuMatSubPfS_S_iiPfS_S_ii
	.globl	_Z9gpuMatSubPfS_S_ii
	.type	_Z9gpuMatSubPfS_S_ii, @function
_Z9gpuMatSubPfS_S_ii:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z9gpuMatSubPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE3664:
	.size	_Z9gpuMatSubPfS_S_ii, .-_Z9gpuMatSubPfS_S_ii
	.globl	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
	.type	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii, @function
_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9gpuMatMulPfS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L36:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii, .-_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
	.globl	_Z9gpuMatMulPfS_S_iii
	.type	_Z9gpuMatMulPfS_S_iii, @function
_Z9gpuMatMulPfS_S_iii:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
	.cfi_endproc
.LFE3666:
	.size	_Z9gpuMatMulPfS_S_iii, .-_Z9gpuMatMulPfS_S_iii
	.globl	_Z39__device_stub__Z15gpuMatTransposePfS_iiPfS_ii
	.type	_Z39__device_stub__Z15gpuMatTransposePfS_iiPfS_ii, @function
_Z39__device_stub__Z15gpuMatTransposePfS_iiPfS_ii:
.LFB3667:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15gpuMatTransposePfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L41:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3667:
	.size	_Z39__device_stub__Z15gpuMatTransposePfS_iiPfS_ii, .-_Z39__device_stub__Z15gpuMatTransposePfS_iiPfS_ii
	.globl	_Z15gpuMatTransposePfS_ii
	.type	_Z15gpuMatTransposePfS_ii, @function
_Z15gpuMatTransposePfS_ii:
.LFB3668:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15gpuMatTransposePfS_iiPfS_ii
	.cfi_endproc
.LFE3668:
	.size	_Z15gpuMatTransposePfS_ii, .-_Z15gpuMatTransposePfS_ii
	.globl	_Z40__device_stub__Z15gpuMatMulScalarPfS_iifPfS_iif
	.type	_Z40__device_stub__Z15gpuMatMulScalarPfS_iifPfS_iif, @function
_Z40__device_stub__Z15gpuMatMulScalarPfS_iifPfS_iif:
.LFB3669:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15gpuMatMulScalarPfS_iif(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L46:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3669:
	.size	_Z40__device_stub__Z15gpuMatMulScalarPfS_iifPfS_iif, .-_Z40__device_stub__Z15gpuMatMulScalarPfS_iifPfS_iif
	.globl	_Z15gpuMatMulScalarPfS_iif
	.type	_Z15gpuMatMulScalarPfS_iif, @function
_Z15gpuMatMulScalarPfS_iif:
.LFB3670:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15gpuMatMulScalarPfS_iifPfS_iif
	.cfi_endproc
.LFE3670:
	.size	_Z15gpuMatMulScalarPfS_iif, .-_Z15gpuMatMulScalarPfS_iif
	.globl	_Z30__device_stub__Z8gpuNorm2PfS_iPfS_i
	.type	_Z30__device_stub__Z8gpuNorm2PfS_iPfS_i, @function
_Z30__device_stub__Z8gpuNorm2PfS_iPfS_i:
.LFB3671:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z8gpuNorm2PfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L51:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3671:
	.size	_Z30__device_stub__Z8gpuNorm2PfS_iPfS_i, .-_Z30__device_stub__Z8gpuNorm2PfS_iPfS_i
	.globl	_Z8gpuNorm2PfS_i
	.type	_Z8gpuNorm2PfS_i, @function
_Z8gpuNorm2PfS_i:
.LFB3672:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z8gpuNorm2PfS_iPfS_i
	.cfi_endproc
.LFE3672:
	.size	_Z8gpuNorm2PfS_i, .-_Z8gpuNorm2PfS_i
	.globl	_Z34__device_stub__Z10gpuMeanVecPiiiPfPiiiPf
	.type	_Z34__device_stub__Z10gpuMeanVecPiiiPfPiiiPf, @function
_Z34__device_stub__Z10gpuMeanVecPiiiPfPiiiPf:
.LFB3673:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10gpuMeanVecPiiiPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L56:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3673:
	.size	_Z34__device_stub__Z10gpuMeanVecPiiiPfPiiiPf, .-_Z34__device_stub__Z10gpuMeanVecPiiiPfPiiiPf
	.globl	_Z10gpuMeanVecPiiiPf
	.type	_Z10gpuMeanVecPiiiPf, @function
_Z10gpuMeanVecPiiiPf:
.LFB3674:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10gpuMeanVecPiiiPfPiiiPf
	.cfi_endproc
.LFE3674:
	.size	_Z10gpuMeanVecPiiiPf, .-_Z10gpuMeanVecPiiiPf
	.globl	_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_
	.type	_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_, @function
_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_:
.LFB3675:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10gpuSubMeanPiPfiiS0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L61:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L63
	call	__stack_chk_fail@PLT
.L63:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3675:
	.size	_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_, .-_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_
	.globl	_Z10gpuSubMeanPiPfiiS0_
	.type	_Z10gpuSubMeanPiPfiiS0_, @function
_Z10gpuSubMeanPiPfiiS0_:
.LFB3676:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_
	.cfi_endproc
.LFE3676:
	.size	_Z10gpuSubMeanPiPfiiS0_, .-_Z10gpuSubMeanPiPfiiS0_
	.globl	_Z33__device_stub__Z9gpuCovMatPfS_iifPfS_iif
	.type	_Z33__device_stub__Z9gpuCovMatPfS_iifPfS_iif, @function
_Z33__device_stub__Z9gpuCovMatPfS_iifPfS_iif:
.LFB3677:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9gpuCovMatPfS_iif(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L66:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L68
	call	__stack_chk_fail@PLT
.L68:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3677:
	.size	_Z33__device_stub__Z9gpuCovMatPfS_iifPfS_iif, .-_Z33__device_stub__Z9gpuCovMatPfS_iifPfS_iif
	.globl	_Z9gpuCovMatPfS_iif
	.type	_Z9gpuCovMatPfS_iif, @function
_Z9gpuCovMatPfS_iif:
.LFB3678:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9gpuCovMatPfS_iifPfS_iif
	.cfi_endproc
.LFE3678:
	.size	_Z9gpuCovMatPfS_iif, .-_Z9gpuCovMatPfS_iif
	.globl	_Z37__device_stub__Z12gpuNormalizePfS_S_iPfS_S_i
	.type	_Z37__device_stub__Z12gpuNormalizePfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12gpuNormalizePfS_S_iPfS_S_i:
.LFB3679:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L71
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12gpuNormalizePfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L71:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L73
	call	__stack_chk_fail@PLT
.L73:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3679:
	.size	_Z37__device_stub__Z12gpuNormalizePfS_S_iPfS_S_i, .-_Z37__device_stub__Z12gpuNormalizePfS_S_iPfS_S_i
	.globl	_Z12gpuNormalizePfS_S_i
	.type	_Z12gpuNormalizePfS_S_i, @function
_Z12gpuNormalizePfS_S_i:
.LFB3680:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12gpuNormalizePfS_S_iPfS_S_i
	.cfi_endproc
.LFE3680:
	.size	_Z12gpuNormalizePfS_S_i, .-_Z12gpuNormalizePfS_S_i
	.globl	_Z33__device_stub__Z9gpuEigValPfS_S_iPfS_S_i
	.type	_Z33__device_stub__Z9gpuEigValPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9gpuEigValPfS_S_iPfS_S_i:
.LFB3681:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L76
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9gpuEigValPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L76:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L78
	call	__stack_chk_fail@PLT
.L78:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3681:
	.size	_Z33__device_stub__Z9gpuEigValPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9gpuEigValPfS_S_iPfS_S_i
	.globl	_Z9gpuEigValPfS_S_i
	.type	_Z9gpuEigValPfS_S_i, @function
_Z9gpuEigValPfS_S_i:
.LFB3682:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9gpuEigValPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3682:
	.size	_Z9gpuEigValPfS_S_i, .-_Z9gpuEigValPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"r"
.LC3:
	.string	"train_matrix.txt"
.LC4:
	.string	"Error open file\n"
.LC5:
	.string	"%d"
.LC6:
	.string	"test_matrix.txt"
.LC10:
	.string	"wb"
.LC11:
	.string	"identify.txt"
.LC12:
	.string	"Test Image\t\tPrediction\n"
.LC13:
	.string	"%d \t\t\t\t %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$2670592, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	leaq	.LC2(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$280, %rsp
	.cfi_def_cfa_offset 336
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movq	%r12, %rsi
	leaq	.LC3(%rip), %rdi
	movq	%rax, 24(%rsp)
	call	fopen@PLT
	movq	%rax, 8(%rsp)
	testq	%rax, %rax
	je	.L82
	movq	24(%rsp), %r14
	xorl	%r15d, %r15d
	leaq	.LC5(%rip), %rbp
	jmp	.L83
.L82:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L81
.L85:
	movq	8(%rsp), %rdi
	movq	%r13, %rdx
	movq	%rbp, %rsi
	xorl	%eax, %eax
	addq	$4, %r13
	call	__isoc23_fscanf@PLT
	decl	%ebx
	jne	.L85
	addl	$4096, %r15d
	addq	$16384, %r14
	cmpl	$667648, %r15d
	je	.L86
.L83:
	movq	%r14, %r13
	movl	$4096, %ebx
	jmp	.L85
.L86:
	movq	8(%rsp), %rdi
	call	fclose@PLT
	movl	$819200, %edi
	call	malloc@PLT
	movq	%r12, %rsi
	leaq	.LC6(%rip), %rdi
	movq	%rax, 32(%rsp)
	call	fopen@PLT
	movq	%rax, 16(%rsp)
	testq	%rax, %rax
	je	.L82
	movq	32(%rsp), %r14
.L87:
	movq	%r14, %r13
	movl	$4096, %r12d
.L88:
	movq	16(%rsp), %rdi
	movq	%r13, %rdx
	movq	%rbp, %rsi
	xorl	%eax, %eax
	addq	$4, %r13
	call	__isoc23_fscanf@PLT
	decl	%r12d
	jne	.L88
	addl	$4096, %ebx
	addq	$16384, %r14
	cmpl	$204800, %ebx
	jne	.L87
	movq	16(%rsp), %rdi
	call	fclose@PLT
	leaq	64(%rsp), %rdi
	movl	$2670592, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$819200, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rsi
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movl	$2670592, %edx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movl	$819200, %edx
	call	cudaMemcpy@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$134217729, %edi
	salq	$7, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$5, %rdi
	movq	%rdx, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%rdi, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L90
	movq	80(%rsp), %rcx
	movq	64(%rsp), %rdi
	movl	$4096, %edx
	movl	$163, %esi
	call	_Z34__device_stub__Z10gpuMeanVecPiiiPfPiiiPf
.L90:
	movl	$33554433, %eax
	leaq	88(%rsp), %rdi
	movl	$2670592, %esi
	movl	$1, 188(%rsp)
	movl	$1, 200(%rsp)
	salq	$7, %rax
	movq	%rax, 180(%rsp)
	movabsq	$700079669280, %rax
	movq	%rax, 192(%rsp)
	call	cudaMalloc@PLT
	movl	188(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	180(%rsp), %rdx
	movq	192(%rsp), %rdi
	movl	200(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L91
	movq	88(%rsp), %r8
	movq	80(%rsp), %rsi
	movl	$4096, %ecx
	movl	$163, %edx
	movq	64(%rsp), %rdi
	call	_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_
.L91:
	leaq	96(%rsp), %rdi
	movl	$2670592, %esi
	call	cudaMalloc@PLT
	leaq	104(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	movl	188(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	180(%rsp), %rdx
	movq	192(%rsp), %rdi
	movl	200(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L92
	movq	96(%rsp), %rsi
	movq	88(%rsp), %rdi
	movl	$4096, %ecx
	movl	$163, %edx
	call	_Z39__device_stub__Z15gpuMatTransposePfS_iiPfS_ii
.L92:
	movl	$2147483649, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	salq	$5, %rdx
	movl	$1, %esi
	movabsq	$1099511627904, %rdi
	movl	$1, 224(%rsp)
	movq	%rdi, 216(%rsp)
	movq	%rdx, 204(%rsp)
	movl	$1, 212(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L93
	movq	104(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$4096, %r9d
	movl	$163, %r8d
	movq	96(%rsp), %rdi
	movl	$4096, %ecx
	call	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
.L93:
	movl	$16384, %edi
	xorl	%r13d, %r13d
	movabsq	$4294967552, %r15
	call	malloc@PLT
	movl	$4, %edi
	movq	%rax, %r14
	call	malloc@PLT
	movl	$819200, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	leaq	112(%rsp), %rdi
	movl	$16384, %esi
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	leaq	120(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	leaq	128(%rsp), %rdi
	movl	$67108864, %esi
	call	cudaMalloc@PLT
	leaq	136(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	$0x00000000, (%rsp)
.L107:
	leaq	4(%r14), %rdx
	xorl	%eax, %eax
	movl	$4095, %ecx
	movq	%r14, %rsi
	movq	%rdx, %rdi
	movl	$0x3f800000, (%r14)
	movl	$16384, %edx
	rep stosl
	movq	112(%rsp), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$268435457, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rax
	movq	%r15, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rax, %rdi
	movq	%r15, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%rax, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L94
	movq	120(%rsp), %rdx
	movq	112(%rsp), %rsi
	movl	$1, %r9d
	movl	$4096, %r8d
	movq	104(%rsp), %rdi
	movl	$4096, %ecx
	call	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
.L94:
	movss	(%rsp), %xmm2
	movl	$134217729, %ebp
	movl	$1000, 60(%rsp)
	movabsq	$4294967424, %r12
	salq	$5, %rbp
	movss	%xmm2, 48(%rsp)
.L102:
	movl	$0x00000000, (%rbx)
	movq	136(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movl	$128, %r8d
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbp, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%r12, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L95
	movq	136(%rsp), %rsi
	movq	120(%rsp), %rdi
	movl	$4096, %edx
	call	_Z30__device_stub__Z8gpuNorm2PfS_iPfS_i
.L95:
	call	cudaThreadSynchronize@PLT
	movq	136(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movss	(%rbx), %xmm0
	call	sqrtf@PLT
	movq	136(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4, %edx
	movss	%xmm0, (%rbx)
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movl	$128, %r8d
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbp, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%r12, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L96
	movq	112(%rsp), %rdx
	movq	120(%rsp), %rdi
	movl	$4096, %ecx
	movq	136(%rsp), %rsi
	call	_Z37__device_stub__Z12gpuNormalizePfS_S_iPfS_S_i
.L96:
	call	cudaThreadSynchronize@PLT
	movl	$268435457, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$4, %rax
	movq	%r15, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rax, %rdi
	movq	%r15, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%rax, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L97
	movq	120(%rsp), %rdx
	movq	104(%rsp), %rsi
	movl	$4096, %r9d
	movl	$4096, %r8d
	movq	112(%rsp), %rdi
	movl	$1, %ecx
	call	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
.L97:
	call	cudaThreadSynchronize@PLT
	movl	$0x00000000, (%rbx)
	movl	$1, %ecx
	movq	%rbx, %rsi
	movq	136(%rsp), %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movl	$128, %r8d
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbp, 252(%rsp)
	movl	$1, 260(%rsp)
	movq	%r12, 240(%rsp)
	movl	$1, 248(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L98
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdi
	movl	$4096, %ecx
	movq	136(%rsp), %rdx
	call	_Z33__device_stub__Z9gpuEigValPfS_S_iPfS_S_i
.L98:
	call	cudaThreadSynchronize@PLT
	movq	136(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movss	(%rbx), %xmm4
	movss	48(%rsp), %xmm0
	movss	.LC9(%rip), %xmm1
	subss	%xmm4, %xmm0
	andps	.LC8(%rip), %xmm0
	movss	%xmm4, (%rsp)
	comiss	%xmm0, %xmm1
	jbe	.L129
	movq	112(%rsp), %rsi
	movl	$2, %ecx
	movl	$16384, %edx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	movss	48(%rsp), %xmm6
	movss	%xmm6, (%rsp)
	jmp	.L101
.L129:
	decl	60(%rsp)
	je	.L101
	movss	(%rsp), %xmm3
	movss	%xmm3, 48(%rsp)
	jmp	.L102
.L101:
	movq	40(%rsp), %rax
	leaq	(%rax,%r13,4), %rdx
	xorl	%eax, %eax
.L103:
	movss	(%r14,%rax,4), %xmm0
	incq	%rax
	addq	$200, %rdx
	movss	%xmm0, -200(%rdx)
	cmpq	$4096, %rax
	jne	.L103
	movl	212(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	204(%rsp), %rdx
	movq	216(%rsp), %rdi
	movl	224(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L104
	movq	112(%rsp), %rdi
	movq	128(%rsp), %rdx
	movl	$4096, %ecx
	movl	$4096, %r9d
	movl	$1, %r8d
	movq	%rdi, %rsi
	call	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
.L104:
	movl	212(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	204(%rsp), %rdx
	movq	216(%rsp), %rdi
	movl	224(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L105
	movss	(%rbx), %xmm0
	movl	$4096, %ecx
	movl	$4096, %edx
	movq	128(%rsp), %rdi
	movq	%rdi, %rsi
	call	_Z40__device_stub__Z15gpuMatMulScalarPfS_iifPfS_iif
.L105:
	movl	212(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	204(%rsp), %rdx
	movq	216(%rsp), %rdi
	movl	224(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L106
	movq	104(%rsp), %rdi
	movl	$4096, %r8d
	movl	$4096, %ecx
	movq	128(%rsp), %rsi
	movq	%rdi, %rdx
	call	_Z34__device_stub__Z9gpuMatSubPfS_S_iiPfS_S_ii
.L106:
	incq	%r13
	cmpq	$50, %r13
	jne	.L107
	leaq	144(%rsp), %rdi
	movl	$819200, %esi
	call	cudaMalloc@PLT
	leaq	152(%rsp), %rdi
	movl	$32600, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	movl	$819200, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	212(%rsp), %ecx
	movq	204(%rsp), %rdx
	movabsq	$47244640258, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L108
	movq	88(%rsp), %rdi
	movq	152(%rsp), %rdx
	movl	$50, %r9d
	movl	$4096, %r8d
	movq	144(%rsp), %rsi
	movl	$163, %ecx
	call	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
.L108:
	leaq	160(%rsp), %rdi
	movl	$819200, %esi
	call	cudaMalloc@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	188(%rsp), %ecx
	movq	180(%rsp), %rdx
	movabsq	$214748364832, %rdi
	movl	$1, 248(%rsp)
	movq	%rdi, 240(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L109
	movq	80(%rsp), %rsi
	movq	72(%rsp), %rdi
	movl	$4096, %ecx
	movl	$50, %edx
	movq	160(%rsp), %r8
	call	_Z37__device_stub__Z10gpuSubMeanPiPfiiS0_PiPfiiS0_
.L109:
	leaq	168(%rsp), %rdi
	movl	$10000, %esi
	call	cudaMalloc@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	212(%rsp), %ecx
	movq	204(%rsp), %rdx
	movabsq	$17179869186, %rdi
	movl	$1, 260(%rsp)
	movq	%rdi, 252(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L110
	movq	168(%rsp), %rdx
	movq	144(%rsp), %rsi
	movl	$50, %r9d
	movl	$4096, %r8d
	movq	160(%rsp), %rdi
	movl	$50, %ecx
	call	_Z35__device_stub__Z9gpuMatMulPfS_S_iiiPfS_S_iii
.L110:
	movl	$32600, %edi
	call	malloc@PLT
	movl	$10000, %edi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movq	152(%rsp), %rsi
	movl	$32600, %edx
	movq	%rax, 48(%rsp)
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	movl	$2, %ecx
	movq	168(%rsp), %rsi
	movl	$10000, %edx
	call	cudaMemcpy@PLT
	call	cudaProfilerStop@PLT
	movl	$200, %edi
	call	malloc@PLT
	movq	48(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$50, %r8d
	movq	%rax, %r9
	movl	$50, %ecx
	movl	$163, %edx
	movq	%rax, %r12
	call	_Z8identifyPfS_iiiPi
	leaq	.LC10(%rip), %rsi
	leaq	.LC11(%rip), %rdi
	call	fopen@PLT
	movq	%rax, %rbp
	testq	%rax, %rax
	je	.L82
	movq	%rax, %rdi
	leaq	.LC12(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	$1, %r13d
	leaq	.LC13(%rip), %r15
.L111:
	movl	-4(%r12,%r13,4), %r8d
	movl	%r13d, %ecx
	movq	%r15, %rdx
	movl	$2, %esi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	incq	%r13
	call	__fprintf_chk@PLT
	cmpq	$51, %r13
	jne	.L111
	movq	%rbp, %rdi
	call	fclose@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	32(%rsp), %rdi
	call	free@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	40(%rsp), %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	48(%rsp), %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	160(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rdi
	call	cudaFree@PLT
	xorl	%eax, %eax
.L81:
	movq	264(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L112
	call	__stack_chk_fail@PLT
.L112:
	addq	$280, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3638:
	.size	main, .-main
	.section	.rodata.str1.1
.LC14:
	.string	"_Z9gpuEigValPfS_S_i"
.LC15:
	.string	"_Z12gpuNormalizePfS_S_i"
.LC16:
	.string	"_Z9gpuCovMatPfS_iif"
.LC17:
	.string	"_Z10gpuSubMeanPiPfiiS0_"
.LC18:
	.string	"_Z10gpuMeanVecPiiiPf"
.LC19:
	.string	"_Z8gpuNorm2PfS_i"
.LC20:
	.string	"_Z15gpuMatMulScalarPfS_iif"
.LC21:
	.string	"_Z15gpuMatTransposePfS_ii"
.LC22:
	.string	"_Z9gpuMatMulPfS_S_iii"
.LC23:
	.string	"_Z9gpuMatSubPfS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3684:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9gpuEigValPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z12gpuNormalizePfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9gpuCovMatPfS_iif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10gpuSubMeanPiPfiiS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10gpuMeanVecPiiiPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8gpuNorm2PfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15gpuMatMulScalarPfS_iif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15gpuMatTransposePfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC22(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z9gpuMatMulPfS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9gpuMatSubPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3684:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1203982336
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC8:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4
	.align 4
.LC9:
	.long	897988541
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <iostream>

#include <hip/hip_runtime_api.h>

__global__ void gpuMatSub(float* A, float* B, float* C, int Nrows, int Ncols) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < Ncols) && (ty < Nrows)) {
    tid = Ncols * ty + tx;
    C[tid] = A[tid] - B[tid];
  }
}

__global__ void gpuMatMul(float *A, float *B, float *C, int m, int n, int p) { 
  int row = blockIdx.y * blockDim.y + threadIdx.y; 
  int col = blockIdx.x * blockDim.x + threadIdx.x;
  float S = 0;
  if (col < p && row < m) {
    for(int i = 0; i < n; i++) {
      S += A[row * n + i] * B[i * p + col];
    }
    C[row * p + col] = S;
  }
}

__global__ void gpuMatTranspose(float *A, float *B, int Nrows, int Ncols)
{
  unsigned int tx, ty, pos, trans_pos;
  tx = blockIdx.x * blockDim.x + threadIdx.x;
  ty = blockIdx.y * blockDim.y + threadIdx.y;
  if (tx < Ncols && ty < Nrows) {
    pos = ty * Ncols + tx;
    trans_pos = tx * Nrows + ty;
    B[trans_pos] = A[pos];
  }
}

__global__ void gpuMatMulScalar(float *A, float *B, int Nrows, int Ncols, float lambda) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < Ncols) && (ty < Nrows)) {
    tid = Ncols * ty + tx;
    B[tid] = A[tid] * lambda;
  }
}

__global__ void gpuNorm2(float *A, float *norm, int N) {
  extern __shared__ float sdata[];
  unsigned int tid = threadIdx.x;
  unsigned int gid = tid + blockIdx.x * blockDim.x;

  if (gid < N) sdata[tid] = A[gid];
  else sdata[tid] = 0;
  __syncthreads();

  sdata[tid] = sdata[tid] * sdata[tid];
  __syncthreads();

  for (unsigned int stride = blockDim.x/2; stride > 0; stride = stride >> 1) {
    if (tid < stride) sdata[tid] = sdata[tid] + sdata[tid + stride];
    __syncthreads();
  }

  if (tid == 0) atomicAdd(norm, sdata[0]);
}

__global__ void gpuMeanVec(int *trainMat, int Ntrain, int dimension, float *mean) {
  int tid = threadIdx.x + blockIdx.x * blockDim.x;
  float tmp = 0;
  int DestIndex;
  for (int i = 0; i < Ntrain; i++) {
    DestIndex = i * dimension + tid;
    tmp = tmp + trainMat[DestIndex];
  }
  mean[tid] = tmp / Ntrain;
}

__global__ void gpuSubMean(int *trainMat, float *mean, int Ntrain, int dimension, float *X) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < dimension) && (ty < Ntrain)) {
    tid = dimension * ty + tx;
    X[tid] = trainMat[tid] - mean[tx];
  }
}

__global__ void gpuCovMat(float *A, float *B, int Nrows, int Ncols, float lambda) {
  int tid, tx, ty;
  tx = threadIdx.x + blockIdx.x * blockDim.x;
  ty = threadIdx.y + blockIdx.y * blockDim.y;
  if ((tx < Ncols) && (ty < Nrows)) {
    tid = Ncols * ty + tx;
    B[tid] = A[tid] / lambda;
  }
}

__global__ void gpuNormalize(float *A, float *norm, float *B, int N) {
  extern __shared__ float sdata[];
  unsigned int tid = threadIdx.x;
  unsigned int gid = tid + blockIdx.x * blockDim.x;

  if (tid == 0) sdata[0] = norm[0];
  __syncthreads();

  if (gid < N) B[gid] = A[gid] / sdata[0];
}

__global__ void gpuEigVal(float *A, float *B, float *eigVal, int N) {
  extern __shared__ float sdata[];
  unsigned int tid = threadIdx.x;
  unsigned int gid = tid + blockIdx.x * blockDim.x;

  if (gid < N) sdata[tid] = A[gid] * B[gid];
  else sdata[tid] = 0;
  __syncthreads();

  for (unsigned int stride = blockDim.x/2; stride > 0; stride = stride >> 1) {
    if (tid < stride) sdata[tid] = sdata[tid] + sdata[tid+stride];
    __syncthreads();
  }
  if (tid == 0) atomicAdd(eigVal, sdata[0]);
}

float cpuNorm2(float *A, int Nrows, int Ncols) {
  float tmp = 0;
  float Norm;
  int DestIndex;
  for (int col = 0; col < Ncols; col++) {
    for (int row = 0; row < Nrows; row++) {
      DestIndex = row * Ncols + col;
      tmp = tmp + A[DestIndex] * A[DestIndex];
    }
  }
  Norm = sqrt(tmp);
  return Norm;
}

void cpuMatSub(float* A, float* B, int Nrows, int Ncols, float* C) {
  int col = 0;
  int row = 0;
  int DestIndex = 0;
  for (col = 0; col < Ncols; col++) {
    for (row = 0; row < Nrows; row++) {
      DestIndex = row * Ncols + col;
      C[DestIndex] = A[DestIndex] - B[DestIndex];
    }
  }
}

void identify(float *project_train_img, float *project_test_img, int Ntrain, int Ntest, int dimension, int *recognized_img) {
  int DestIndex;
  float *test;
  float *train;
  float *D;
  float distance = 0;
  float min;

  int buffer = dimension * sizeof(float);
  test = (float*)malloc(buffer);
  train = (float*)malloc(buffer);
  D = (float*)malloc(buffer);

  for (int i = 0; i < Ntest; i++) {
    min = 100000;
    for (int j = 0; j < dimension; j++) {
      DestIndex = i * dimension + j;
      test[j] = project_test_img[DestIndex];
    }

    for (int m = 0; m < Ntrain; m++) {
      for (int n = 0; n < dimension; n++) {
        DestIndex = m * dimension + n;
        train[n] = project_train_img[DestIndex];
      }
      cpuMatSub(train, test, 1, dimension, D);
      distance = cpuNorm2(D, 1, dimension);
      if (distance < min) {
        min = distance;
        recognized_img[i] = m + 1;
      }
    }
  }

  free(test);
  free(train);
  free(D);
}

int main() {
  FILE *fp_train;
  FILE *fp_test;
  FILE *fp_id;
  int *trainMat;
  int *testMat;
  int Ntrain = 163; // Number of training images
  int Ntest = 50;   // Number of test images
  int imgSize = 64; // Size of image
  int k = 50;       // Number of the principal components

  int dimension = imgSize * imgSize;  // The original dimension 4096
  int DestIndex;

  int trainMatBuffer = Ntrain * dimension * sizeof(int);
  int testMatBuffer = Ntest * dimension * sizeof(int);

  // Read training set
  trainMat = (int*)malloc(trainMatBuffer);
  fp_train = fopen("train_matrix.txt", "r");
  if (fp_train == NULL) {
    printf("Error open file\n");
    return 1;
  }
  for (int i = 0; i < Ntrain; i++) {
    for (int j = 0; j < dimension; j++) {
      DestIndex = i * dimension + j;
      fscanf(fp_train, "%d", &trainMat[DestIndex]);
    }
  }
  fclose(fp_train);

  // Read test set
  testMat = (int*)malloc(testMatBuffer);
  fp_test = fopen("test_matrix.txt", "r");
  if (fp_test == NULL) {
    printf("Error open file\n");
    return 1;
  }
  for (int i = 0; i < Ntest; i++) {
    for (int j = 0; j < dimension; j++) {
      DestIndex = i * dimension + j;
      fscanf(fp_test, "%d", &testMat[DestIndex]);
    }
  }
  fclose(fp_test);

  int *d_trainMat;
  int *d_testMat;
  float *d_mean;

  int imgBuffer = dimension * sizeof(float);

  hipMalloc((void**)&d_trainMat, trainMatBuffer);
  hipMalloc((void**)&d_testMat, testMatBuffer);
  hipMalloc((void**)&d_mean, imgBuffer);

  // Copy the training and test matrices from Host to Device
  hipMemcpy(d_trainMat, trainMat, trainMatBuffer, hipMemcpyHostToDevice);
  hipMemcpy(d_testMat, testMat, testMatBuffer, hipMemcpyHostToDevice);

  // Calculate the mean vector of the training matrix
  gpuMeanVec<<<32, 128>>>(d_trainMat, Ntrain, dimension, d_mean);

  // Compute the difference between each image vector and the mean vector
  dim3 block1(128, 1);
  dim3 grid1(dimension/128, Ntrain);
  float *d_X;
  int Xbuffer = Ntrain * dimension * sizeof(float);
  hipMalloc((void**)&d_X, Xbuffer);
  gpuSubMean<<<grid1, block1>>>(d_trainMat, d_mean, Ntrain, dimension, d_X);

  // Determine the covariance matrix
  int covMatBuffer = dimension * dimension * sizeof(float);
  float *d_Xt, *d_covMat;
  hipMalloc((void**)&d_Xt, Xbuffer);
  hipMalloc((void**)&d_covMat, covMatBuffer);
  gpuMatTranspose<<<grid1, block1>>>(d_X, d_Xt, Ntrain, dimension);
  dim3 block2(32, 16);
  dim3 grid2(dimension/32, dimension/16);
  gpuMatMul<<<grid2, block2>>>(d_Xt, d_X, d_covMat, dimension, Ntrain, dimension);

  // Find eigenvalues and eigenvectors of the covariance matrix
  float prev_lambda = 0;
  const float eps = 0.000001;

  float *Q, *normZ, *k_eig_vec;
  float *d_Q, *d_Z, *d_W, *d_normZ;

  int normBuffer = sizeof(float);
  int eigVecBuffer = k * imgBuffer;

  Q = (float*)malloc(imgBuffer);
  normZ = (float*)malloc(normBuffer);
  k_eig_vec = (float*)malloc(eigVecBuffer);

  hipMalloc((void**)&d_Q, imgBuffer);
  hipMalloc((void**)&d_Z, imgBuffer);
  hipMalloc((void**)&d_W, covMatBuffer);
  hipMalloc((void**)&d_normZ, normBuffer);

  int block3 = 32;
  int grid3 = dimension / block3;
  int sharedMemSize = block3 * sizeof(float);

  for (int i = 0; i < k; i++) {
    Q[0] = 1;
    for (int m = 1; m < dimension; m++) Q[m] = 0;
    hipMemcpy(d_Q, Q, imgBuffer, hipMemcpyHostToDevice);
    gpuMatMul<<<16, 256>>>(d_covMat, d_Q, d_Z, dimension, dimension, 1);

    // Power Method iteration
    for (int j = 0; j < 1000; j++) {
      normZ[0] = 0;
      hipMemcpy(d_normZ, normZ, normBuffer, hipMemcpyHostToDevice);
      gpuNorm2<<<grid3, block3, sharedMemSize>>>(d_Z, d_normZ, dimension);
      hipDeviceSynchronize();
      hipMemcpy(normZ, d_normZ, normBuffer, hipMemcpyDeviceToHost);
      normZ[0] = sqrt(normZ[0]);
      hipMemcpy(d_normZ, normZ, normBuffer, hipMemcpyHostToDevice);
      gpuNormalize<<<grid3, block3, sharedMemSize>>>(d_Z, d_normZ, d_Q, dimension);
      hipDeviceSynchronize();
      gpuMatMul<<<16, 256>>>(d_Q, d_covMat, d_Z, 1, dimension, dimension);
      hipDeviceSynchronize();
      normZ[0] = 0;
      hipMemcpy(d_normZ, normZ, normBuffer, hipMemcpyHostToDevice);
      gpuEigVal<<<grid3, block3, sharedMemSize>>>(d_Q, d_Z, d_normZ, dimension);
      hipDeviceSynchronize();
      hipMemcpy(normZ, d_normZ, normBuffer, hipMemcpyDeviceToHost);

      if (abs(prev_lambda-normZ[0]) < eps) {
        hipMemcpy(Q, d_Q, imgBuffer, hipMemcpyDeviceToHost);
        break;
      }
      prev_lambda = normZ[0];
    }

    // The new subspace created by k eigenvectors
    for (int p = 0; p < dimension; p++) {
      DestIndex = p * k + i;
      k_eig_vec[DestIndex] = Q[p];
    }

    // Calculate the new covariance matrix for the next eigenvalue and eigenvector
    gpuMatMul<<<grid2, block2>>>(d_Q, d_Q, d_W, dimension, 1, dimension);
    gpuMatMulScalar<<<grid2, block2>>>(d_W, d_W, dimension, dimension, normZ[0]);
    gpuMatSub<<<grid2, block2>>>(d_covMat, d_W, d_covMat, dimension, dimension);
  }

  // Project the training images in the new subspace
  float *d_kEigVec, *d_proj_train;
  int projTrainBuffer = Ntrain * k * sizeof(float);
  hipMalloc((void**)&d_kEigVec, eigVecBuffer);
  hipMalloc((void**)&d_proj_train, projTrainBuffer);
  hipMemcpy(d_kEigVec, k_eig_vec, eigVecBuffer, hipMemcpyHostToDevice);
  dim3 grid4((k+block2.x-1)/block2.x, (Ntrain+block2.y-1)/block2.y);
  gpuMatMul<<<grid4, block2>>>(d_X, d_kEigVec, d_proj_train, Ntrain, dimension, k);

  // Project the test images in the new subspace
  float *d_X1;
  hipMalloc((void**)&d_X1, testMatBuffer);
  dim3 grid5(dimension/128, Ntest);
  gpuSubMean<<<grid5, block1>>>(d_testMat, d_mean, Ntest, dimension, d_X1);

  float *d_proj_test;
  int projTestBuffer = Ntest * k * sizeof(float);
  hipMalloc((void**)&d_proj_test, projTestBuffer);
  dim3 grid6((k+block2.x-1)/block2.x, (Ntest+block2.y-1)/block2.y);
  gpuMatMul<<<grid6, block2>>>(d_X1, d_kEigVec, d_proj_test, Ntest, dimension, k);

  // Copy projected training and test matrices from Device to Host
  float *project_train_img, *project_test_img;
  project_train_img = (float*)malloc(projTrainBuffer);
  project_test_img = (float*)malloc(projTestBuffer);
  hipMemcpy(project_train_img, d_proj_train, projTrainBuffer, hipMemcpyDeviceToHost);
  hipMemcpy(project_test_img, d_proj_test, projTestBuffer, hipMemcpyDeviceToHost);

  hipProfilerStop();

  // Choose the most similar images in the training set
  int *recognized_img;
  int recogBuffer = Ntest * sizeof(int);
  recognized_img = (int*)malloc(recogBuffer);
  identify(project_train_img, project_test_img, Ntrain, Ntest, k, recognized_img);

  fp_id = fopen("identify.txt", "wb");
  if (fp_id == NULL) {
    printf("Error open file\n");
    return 1;
  }
  fprintf(fp_id, "Test Image\t\tPrediction\n");
  for (int i = 0; i < Ntest; i++) {
    fprintf(fp_id, "%d \t\t\t\t %d\n", i + 1, recognized_img[i]);
  }
  fclose(fp_id);

  free(fp_train);
  free(fp_test);
  free(fp_id);
  free(trainMat);
  free(testMat);
  free(Q);
  free(normZ);
  free(k_eig_vec);
  free(project_train_img);
  free(project_test_img);
  free(recognized_img);

  hipFree(d_trainMat);
  hipFree(d_testMat);
  hipFree(d_mean);
  hipFree(d_X);
  hipFree(d_covMat);
  hipFree(d_Q);
  hipFree(d_Z);
  hipFree(d_W);
  hipFree(d_normZ);
  hipFree(d_kEigVec);
  hipFree(d_proj_train);
  hipFree(d_X1);
  hipFree(d_proj_test);

  return 0;
}

	.text
	.file	"PCA.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z24__device_stub__gpuMatSubPfS_S_ii # -- Begin function _Z24__device_stub__gpuMatSubPfS_S_ii
	.type	_Z24__device_stub__gpuMatSubPfS_S_ii,@function
_Z24__device_stub__gpuMatSubPfS_S_ii:   # @_Z24__device_stub__gpuMatSubPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9gpuMatSubPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__gpuMatSubPfS_S_ii, .Lfunc_end0-_Z24__device_stub__gpuMatSubPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__gpuMatMulPfS_S_iii # -- Begin function _Z24__device_stub__gpuMatMulPfS_S_iii
	.type	_Z24__device_stub__gpuMatMulPfS_S_iii,@function
_Z24__device_stub__gpuMatMulPfS_S_iii:  # @_Z24__device_stub__gpuMatMulPfS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9gpuMatMulPfS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__gpuMatMulPfS_S_iii, .Lfunc_end1-_Z24__device_stub__gpuMatMulPfS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__gpuMatTransposePfS_ii # -- Begin function _Z30__device_stub__gpuMatTransposePfS_ii
	.type	_Z30__device_stub__gpuMatTransposePfS_ii,@function
_Z30__device_stub__gpuMatTransposePfS_ii: # @_Z30__device_stub__gpuMatTransposePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15gpuMatTransposePfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z30__device_stub__gpuMatTransposePfS_ii, .Lfunc_end2-_Z30__device_stub__gpuMatTransposePfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__gpuMatMulScalarPfS_iif # -- Begin function _Z30__device_stub__gpuMatMulScalarPfS_iif
	.type	_Z30__device_stub__gpuMatMulScalarPfS_iif,@function
_Z30__device_stub__gpuMatMulScalarPfS_iif: # @_Z30__device_stub__gpuMatMulScalarPfS_iif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15gpuMatMulScalarPfS_iif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z30__device_stub__gpuMatMulScalarPfS_iif, .Lfunc_end3-_Z30__device_stub__gpuMatMulScalarPfS_iif
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__gpuNorm2PfS_i # -- Begin function _Z23__device_stub__gpuNorm2PfS_i
	.type	_Z23__device_stub__gpuNorm2PfS_i,@function
_Z23__device_stub__gpuNorm2PfS_i:       # @_Z23__device_stub__gpuNorm2PfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8gpuNorm2PfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z23__device_stub__gpuNorm2PfS_i, .Lfunc_end4-_Z23__device_stub__gpuNorm2PfS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpuMeanVecPiiiPf # -- Begin function _Z25__device_stub__gpuMeanVecPiiiPf
	.type	_Z25__device_stub__gpuMeanVecPiiiPf,@function
_Z25__device_stub__gpuMeanVecPiiiPf:    # @_Z25__device_stub__gpuMeanVecPiiiPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpuMeanVecPiiiPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z25__device_stub__gpuMeanVecPiiiPf, .Lfunc_end5-_Z25__device_stub__gpuMeanVecPiiiPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpuSubMeanPiPfiiS0_ # -- Begin function _Z25__device_stub__gpuSubMeanPiPfiiS0_
	.type	_Z25__device_stub__gpuSubMeanPiPfiiS0_,@function
_Z25__device_stub__gpuSubMeanPiPfiiS0_: # @_Z25__device_stub__gpuSubMeanPiPfiiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpuSubMeanPiPfiiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z25__device_stub__gpuSubMeanPiPfiiS0_, .Lfunc_end6-_Z25__device_stub__gpuSubMeanPiPfiiS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__gpuCovMatPfS_iif # -- Begin function _Z24__device_stub__gpuCovMatPfS_iif
	.type	_Z24__device_stub__gpuCovMatPfS_iif,@function
_Z24__device_stub__gpuCovMatPfS_iif:    # @_Z24__device_stub__gpuCovMatPfS_iif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9gpuCovMatPfS_iif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z24__device_stub__gpuCovMatPfS_iif, .Lfunc_end7-_Z24__device_stub__gpuCovMatPfS_iif
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__gpuNormalizePfS_S_i # -- Begin function _Z27__device_stub__gpuNormalizePfS_S_i
	.type	_Z27__device_stub__gpuNormalizePfS_S_i,@function
_Z27__device_stub__gpuNormalizePfS_S_i: # @_Z27__device_stub__gpuNormalizePfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12gpuNormalizePfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z27__device_stub__gpuNormalizePfS_S_i, .Lfunc_end8-_Z27__device_stub__gpuNormalizePfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__gpuEigValPfS_S_i # -- Begin function _Z24__device_stub__gpuEigValPfS_S_i
	.type	_Z24__device_stub__gpuEigValPfS_S_i,@function
_Z24__device_stub__gpuEigValPfS_S_i:    # @_Z24__device_stub__gpuEigValPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9gpuEigValPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z24__device_stub__gpuEigValPfS_S_i, .Lfunc_end9-_Z24__device_stub__gpuEigValPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z8cpuNorm2Pfii                 # -- Begin function _Z8cpuNorm2Pfii
	.type	_Z8cpuNorm2Pfii,@function
_Z8cpuNorm2Pfii:                        # @_Z8cpuNorm2Pfii
	.cfi_startproc
# %bb.0:
	xorps	%xmm1, %xmm1
	xorps	%xmm0, %xmm0
	testl	%edx, %edx
	jle	.LBB10_4
# %bb.1:                                # %.preheader.lr.ph
	movl	%edx, %eax
	movl	%esi, %ecx
	leaq	(,%rax,4), %rdx
	xorl	%r8d, %r8d
.LBB10_2:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB10_6 Depth 2
	movq	%rcx, %r9
	movq	%rdi, %r10
	testl	%esi, %esi
	jle	.LBB10_3
.LBB10_6:                               # %.lr.ph
                                        #   Parent Loop BB10_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r10), %xmm2                   # xmm2 = mem[0],zero,zero,zero
	mulss	%xmm2, %xmm2
	addss	%xmm2, %xmm0
	addq	%rdx, %r10
	decq	%r9
	jne	.LBB10_6
.LBB10_3:                               # %._crit_edge
                                        #   in Loop: Header=BB10_2 Depth=1
	incq	%r8
	addq	$4, %rdi
	cmpq	%rax, %r8
	jne	.LBB10_2
.LBB10_4:                               # %._crit_edge22
	ucomiss	%xmm1, %xmm0
	jb	sqrtf                           # TAILCALL
# %bb.5:                                # %._crit_edge22.split
	sqrtss	%xmm0, %xmm0
	retq
.Lfunc_end10:
	.size	_Z8cpuNorm2Pfii, .Lfunc_end10-_Z8cpuNorm2Pfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9cpuMatSubPfS_iiS_            # -- Begin function _Z9cpuMatSubPfS_iiS_
	.type	_Z9cpuMatSubPfS_iiS_,@function
_Z9cpuMatSubPfS_iiS_:                   # @_Z9cpuMatSubPfS_iiS_
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB11_7
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	%ecx, %eax
	movl	%edx, %ecx
	leaq	(,%rax,4), %r9
	xorl	%r10d, %r10d
.LBB11_2:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB11_4 Depth 2
	testl	%edx, %edx
	jle	.LBB11_5
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB11_2 Depth=1
	movq	%rcx, %r11
	xorl	%ebx, %ebx
.LBB11_4:                               # %.lr.ph
                                        #   Parent Loop BB11_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rdi,%rbx), %xmm0              # xmm0 = mem[0],zero,zero,zero
	subss	(%rsi,%rbx), %xmm0
	movss	%xmm0, (%r8,%rbx)
	addq	%r9, %rbx
	decq	%r11
	jne	.LBB11_4
.LBB11_5:                               # %._crit_edge
                                        #   in Loop: Header=BB11_2 Depth=1
	incq	%r10
	addq	$4, %r8
	addq	$4, %rsi
	addq	$4, %rdi
	cmpq	%rax, %r10
	jne	.LBB11_2
# %bb.6:
	popq	%rbx
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
.LBB11_7:                               # %._crit_edge18
	retq
.Lfunc_end11:
	.size	_Z9cpuMatSubPfS_iiS_, .Lfunc_end11-_Z9cpuMatSubPfS_iiS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z8identifyPfS_iiiPi
.LCPI12_0:
	.long	0x47c35000                      # float 1.0E+5
.LCPI12_1:
	.long	0x00000000                      # float 0
	.text
	.globl	_Z8identifyPfS_iiiPi
	.type	_Z8identifyPfS_iiiPi,@function
_Z8identifyPfS_iiiPi:                   # @_Z8identifyPfS_iiiPi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r9, 48(%rsp)                   # 8-byte Spill
	movl	%r8d, %r14d
	movl	%ecx, %ebp
	movl	%edx, 8(%rsp)                   # 4-byte Spill
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	movq	%rdi, 56(%rsp)                  # 8-byte Spill
	leal	(,%r14,4), %eax
	movslq	%eax, %rbx
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r13
	movq	%rbx, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%rbx, %rdi
	callq	malloc
	movl	%ebp, %ecx
	movq	%rax, %rbp
	testl	%ecx, %ecx
	jle	.LBB12_9
# %bb.1:                                # %.preheader59.lr.ph
	movl	%r14d, %r12d
	leaq	(,%r12,4), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movl	%ecx, %eax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	8(%rsp), %eax                   # 4-byte Reload
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
.LBB12_2:                               # %.preheader59
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB12_6 Depth 2
                                        #       Child Loop BB12_11 Depth 3
                                        #       Child Loop BB12_13 Depth 3
	testl	%r14d, %r14d
	jle	.LBB12_4
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB12_2 Depth=1
	movq	16(%rsp), %rax                  # 8-byte Reload
                                        # kill: def $eax killed $eax killed $rax def $rax
	imull	%r14d, %eax
	movq	32(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rsi
	movq	%r13, %rdi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	callq	memcpy@PLT
.LBB12_4:                               # %.preheader58
                                        #   in Loop: Header=BB12_2 Depth=1
	cmpl	$0, 8(%rsp)                     # 4-byte Folded Reload
	jle	.LBB12_8
# %bb.5:                                # %.preheader.lr.ph
                                        #   in Loop: Header=BB12_2 Depth=1
	xorl	%ebx, %ebx
	movss	.LCPI12_0(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
.LBB12_6:                               # %.preheader
                                        #   Parent Loop BB12_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB12_11 Depth 3
                                        #       Child Loop BB12_13 Depth 3
	testl	%r14d, %r14d
	jle	.LBB12_7
# %bb.10:                               # %.preheader.i.preheader
                                        #   in Loop: Header=BB12_6 Depth=2
	movl	%ebx, %eax
	imull	%r14d, %eax
	movq	56(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rsi
	movq	%r15, %rdi
	movq	24(%rsp), %rdx                  # 8-byte Reload
	callq	memcpy@PLT
	xorl	%eax, %eax
.LBB12_11:                              # %.preheader.i
                                        #   Parent Loop BB12_2 Depth=1
                                        #     Parent Loop BB12_6 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r15,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	subss	(%r13,%rax,4), %xmm0
	movss	%xmm0, (%rbp,%rax,4)
	incq	%rax
	cmpq	%rax, %r12
	jne	.LBB12_11
# %bb.12:                               # %.preheader.i52.preheader
                                        #   in Loop: Header=BB12_6 Depth=2
	xorps	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB12_13:                              # %.preheader.i52
                                        #   Parent Loop BB12_2 Depth=1
                                        #     Parent Loop BB12_6 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rbp,%rax,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	%xmm1, %xmm1
	addss	%xmm1, %xmm0
	incq	%rax
	cmpq	%rax, %r12
	jne	.LBB12_13
	jmp	.LBB12_14
.LBB12_7:                               #   in Loop: Header=BB12_6 Depth=2
	xorps	%xmm0, %xmm0
.LBB12_14:                              # %_Z8cpuNorm2Pfii.exit
                                        #   in Loop: Header=BB12_6 Depth=2
	ucomiss	.LCPI12_1(%rip), %xmm0
	jb	.LBB12_16
# %bb.15:                               #   in Loop: Header=BB12_6 Depth=2
	sqrtss	%xmm0, %xmm0
	jmp	.LBB12_17
.LBB12_16:                              # %call.sqrt
                                        #   in Loop: Header=BB12_6 Depth=2
	callq	sqrtf
.LBB12_17:                              # %_Z8cpuNorm2Pfii.exit.split
                                        #   in Loop: Header=BB12_6 Depth=2
	incq	%rbx
	movss	12(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	ucomiss	%xmm0, %xmm1
	jbe	.LBB12_19
# %bb.18:                               #   in Loop: Header=BB12_6 Depth=2
	movq	48(%rsp), %rax                  # 8-byte Reload
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movl	%ebx, (%rax,%rcx,4)
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
.LBB12_19:                              # %_Z8cpuNorm2Pfii.exit._crit_edge
                                        #   in Loop: Header=BB12_6 Depth=2
	cmpq	64(%rsp), %rbx                  # 8-byte Folded Reload
	jne	.LBB12_6
.LBB12_8:                               # %._crit_edge65
                                        #   in Loop: Header=BB12_2 Depth=1
	movq	16(%rsp), %rcx                  # 8-byte Reload
	incq	%rcx
	movq	%rcx, %rax
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	cmpq	40(%rsp), %rcx                  # 8-byte Folded Reload
	jne	.LBB12_2
.LBB12_9:                               # %._crit_edge67
	movq	%r13, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%rbp, %rdi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	free                            # TAILCALL
.Lfunc_end12:
	.size	_Z8identifyPfS_iiiPi, .Lfunc_end12-_Z8identifyPfS_iiiPi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI13_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI13_1:
	.long	0x358637bd                      # float 9.99999997E-7
.LCPI13_2:
	.long	0x00000000                      # float 0
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$2670592, %edi                  # imm = 0x28C000
	callq	malloc
	movq	%rax, %r13
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB13_56
# %bb.1:                                # %.preheader395.preheader
	movq	%rax, %r14
	movq	%r13, %rbx
	xorl	%r15d, %r15d
.LBB13_2:                               # %.preheader395
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_3 Depth 2
	xorl	%r12d, %r12d
.LBB13_3:                               #   Parent Loop BB13_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%rbx,%r12), %rdx
	movl	$.L.str.3, %esi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r12
	cmpq	$16384, %r12                    # imm = 0x4000
	jne	.LBB13_3
# %bb.4:                                #   in Loop: Header=BB13_2 Depth=1
	incq	%r15
	addq	$16384, %rbx                    # imm = 0x4000
	cmpq	$163, %r15
	jne	.LBB13_2
# %bb.5:
	movq	%r14, %rdi
	callq	fclose
	movl	$819200, %edi                   # imm = 0xC8000
	callq	malloc
	movq	%rax, %rbx
	movl	$.L.str.4, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB13_56
# %bb.6:                                # %.preheader.preheader
	movq	%rbx, 136(%rsp)                 # 8-byte Spill
	xorl	%r15d, %r15d
.LBB13_7:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_8 Depth 2
	xorl	%r12d, %r12d
.LBB13_8:                               #   Parent Loop BB13_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%rbx,%r12), %rdx
	movl	$.L.str.3, %esi
	movq	%rax, %rbp
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	%rbp, %rax
	addq	$4, %r12
	cmpq	$16384, %r12                    # imm = 0x4000
	jne	.LBB13_8
# %bb.9:                                #   in Loop: Header=BB13_7 Depth=1
	incq	%r15
	addq	$16384, %rbx                    # imm = 0x4000
	cmpq	$50, %r15
	jne	.LBB13_7
# %bb.10:
	movabsq	$4294967424, %r12               # imm = 0x100000080
	movq	%rax, %rdi
	callq	fclose
	leaq	128(%rsp), %rbx
	movl	$2670592, %esi                  # imm = 0x28C000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	160(%rsp), %r15
	movl	$819200, %esi                   # imm = 0xC8000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	72(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	$2670592, %edx                  # imm = 0x28C000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	movl	$819200, %edx                   # imm = 0xC8000
	movq	136(%rsp), %rsi                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	-96(%r12), %rbx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_12
# %bb.11:
	movq	128(%rsp), %rdi
	movq	72(%rsp), %rcx
	movl	$163, %esi
	movl	$4096, %edx                     # imm = 0x1000
	callq	_Z25__device_stub__gpuMeanVecPiiiPf
.LBB13_12:
	movabsq	$700079669280, %r15             # imm = 0xA300000020
	leaq	48(%rsp), %rdi
	movl	$2670592, %esi                  # imm = 0x28C000
	callq	hipMalloc
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_14
# %bb.13:
	movq	128(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	48(%rsp), %r8
	movl	$163, %edx
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z25__device_stub__gpuSubMeanPiPfiiS0_
.LBB13_14:
	leaq	152(%rsp), %rdi
	movl	$2670592, %esi                  # imm = 0x28C000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_16
# %bb.15:
	movq	48(%rsp), %rdi
	movq	152(%rsp), %rsi
	movl	$163, %edx
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z30__device_stub__gpuMatTransposePfS_ii
.LBB13_16:
	movq	%r13, 168(%rsp)                 # 8-byte Spill
	movabsq	$1099511627904, %rdi            # imm = 0x10000000080
	movabsq	$68719476768, %rdx              # imm = 0x1000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_18
# %bb.17:
	movq	152(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movl	$4096, %ecx                     # imm = 0x1000
	movl	$163, %r8d
	movl	$4096, %r9d                     # imm = 0x1000
	callq	_Z24__device_stub__gpuMatMulPfS_S_iii
.LBB13_18:
	movl	$16384, %edi                    # imm = 0x4000
	callq	malloc
	movq	%rax, %r13
	movl	$4, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$819200, %edi                   # imm = 0xC8000
	callq	malloc
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	leaq	16(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$16384, %esi                    # imm = 0x4000
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movl	$67108864, %esi                 # imm = 0x4000000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	movq	%r13, %rax
	addq	$4, %rax
	movq	%rax, 184(%rsp)                 # 8-byte Spill
	xorl	%r12d, %r12d
	movabsq	$4294967424, %rcx               # imm = 0x100000080
	leaq	-112(%rcx), %rax
	movq	%rax, 176(%rsp)                 # 8-byte Spill
	movq	%rcx, %rax
	leaq	128(%rcx), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	80(%rsp), %rax                  # 8-byte Reload
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	xorps	%xmm0, %xmm0
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	movq	%r13, 88(%rsp)                  # 8-byte Spill
.LBB13_19:                              # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_23 Depth 2
                                        #     Child Loop BB13_37 Depth 2
	movq	%r12, 192(%rsp)                 # 8-byte Spill
	movl	$1065353216, (%r13)             # imm = 0x3F800000
	movl	$16380, %edx                    # imm = 0x3FFC
	movq	184(%rsp), %rdi                 # 8-byte Reload
	xorl	%esi, %esi
	callq	memset@PLT
	movq	16(%rsp), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%r13, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	176(%rsp), %r12                 # 8-byte Reload
	movq	%r12, %rdi
	movl	$1, %esi
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_21
# %bb.20:                               #   in Loop: Header=BB13_19 Depth=1
	movq	40(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	$4096, %ecx                     # imm = 0x1000
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$1, %r9d
	callq	_Z24__device_stub__gpuMatMulPfS_S_iii
.LBB13_21:                              # %.preheader449
                                        #   in Loop: Header=BB13_19 Depth=1
	movl	$1000, %r13d                    # imm = 0x3E8
.LBB13_23:                              #   Parent Loop BB13_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$0, (%r15)
	movq	8(%rsp), %rdi
	movl	$4, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$128, %r8d
	movabsq	$4294967424, %rdi               # imm = 0x100000080
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_25
# %bb.24:                               #   in Loop: Header=BB13_23 Depth=2
	movq	32(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$4096, %edx                     # imm = 0x1000
	callq	_Z23__device_stub__gpuNorm2PfS_i
.LBB13_25:                              #   in Loop: Header=BB13_23 Depth=2
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%r15), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	ucomiss	.LCPI13_2(%rip), %xmm0
	jb	.LBB13_27
# %bb.26:                               #   in Loop: Header=BB13_23 Depth=2
	sqrtss	%xmm0, %xmm0
	jmp	.LBB13_28
.LBB13_27:                              # %call.sqrt
                                        #   in Loop: Header=BB13_23 Depth=2
	callq	sqrtf
.LBB13_28:                              # %.split
                                        #   in Loop: Header=BB13_23 Depth=2
	movss	%xmm0, (%r15)
	movq	8(%rsp), %rdi
	movl	$4, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$128, %r8d
	movabsq	$4294967424, %rdi               # imm = 0x100000080
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_30
# %bb.29:                               #   in Loop: Header=BB13_23 Depth=2
	movq	32(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z27__device_stub__gpuNormalizePfS_S_i
.LBB13_30:                              #   in Loop: Header=BB13_23 Depth=2
	callq	hipDeviceSynchronize
	movq	%r12, %rdi
	movl	$1, %esi
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_32
# %bb.31:                               #   in Loop: Header=BB13_23 Depth=2
	movq	16(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	$1, %ecx
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$4096, %r9d                     # imm = 0x1000
	callq	_Z24__device_stub__gpuMatMulPfS_S_iii
.LBB13_32:                              #   in Loop: Header=BB13_23 Depth=2
	callq	hipDeviceSynchronize
	movl	$0, (%r15)
	movq	8(%rsp), %rdi
	movl	$4, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$128, %r8d
	movabsq	$4294967424, %rdi               # imm = 0x100000080
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_34
# %bb.33:                               #   in Loop: Header=BB13_23 Depth=2
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z24__device_stub__gpuEigValPfS_S_i
.LBB13_34:                              #   in Loop: Header=BB13_23 Depth=2
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	(%r15), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	24(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm1
	subss	%xmm0, %xmm1
	andps	.LCPI13_0(%rip), %xmm1
	movss	.LCPI13_1(%rip), %xmm2          # xmm2 = mem[0],zero,zero,zero
	ucomiss	%xmm1, %xmm2
	ja	.LBB13_35
# %bb.22:                               #   in Loop: Header=BB13_23 Depth=2
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	decl	%r13d
	jne	.LBB13_23
	jmp	.LBB13_36
.LBB13_35:                              #   in Loop: Header=BB13_19 Depth=1
	movq	16(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movq	88(%rsp), %rdi                  # 8-byte Reload
	movl	$2, %ecx
	movss	%xmm3, 24(%rsp)                 # 4-byte Spill
	callq	hipMemcpy
	movss	24(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
.LBB13_36:                              # %.loopexit
                                        #   in Loop: Header=BB13_19 Depth=1
	movss	%xmm0, 24(%rsp)                 # 4-byte Spill
	movq	144(%rsp), %rax                 # 8-byte Reload
	xorl	%ecx, %ecx
	movq	88(%rsp), %r13                  # 8-byte Reload
.LBB13_37:                              #   Parent Loop BB13_19 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r13,%rcx,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rax)
	incq	%rcx
	addq	$200, %rax
	cmpq	$4096, %rcx                     # imm = 0x1000
	jne	.LBB13_37
# %bb.38:                               #   in Loop: Header=BB13_19 Depth=1
	movabsq	$1099511627904, %rdi            # imm = 0x10000000080
	movl	$1, %esi
	movabsq	$68719476768, %r12              # imm = 0x1000000020
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_40
# %bb.39:                               #   in Loop: Header=BB13_19 Depth=1
	movq	16(%rsp), %rdi
	movq	64(%rsp), %rdx
	movq	%rdi, %rsi
	movl	$4096, %ecx                     # imm = 0x1000
	movl	$1, %r8d
	movl	$4096, %r9d                     # imm = 0x1000
	callq	_Z24__device_stub__gpuMatMulPfS_S_iii
.LBB13_40:                              #   in Loop: Header=BB13_19 Depth=1
	movabsq	$1099511627904, %rdi            # imm = 0x10000000080
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_42
# %bb.41:                               #   in Loop: Header=BB13_19 Depth=1
	movq	64(%rsp), %rdi
	movss	(%r15), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movq	%rdi, %rsi
	movl	$4096, %edx                     # imm = 0x1000
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z30__device_stub__gpuMatMulScalarPfS_iif
.LBB13_42:                              #   in Loop: Header=BB13_19 Depth=1
	movabsq	$1099511627904, %rdi            # imm = 0x10000000080
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	192(%rsp), %r12                 # 8-byte Reload
	jne	.LBB13_44
# %bb.43:                               #   in Loop: Header=BB13_19 Depth=1
	movq	40(%rsp), %rdi
	movq	64(%rsp), %rsi
	movq	%rdi, %rdx
	movl	$4096, %ecx                     # imm = 0x1000
	movl	$4096, %r8d                     # imm = 0x1000
	callq	_Z24__device_stub__gpuMatSubPfS_S_ii
.LBB13_44:                              #   in Loop: Header=BB13_19 Depth=1
	incq	%r12
	addq	$4, 144(%rsp)                   # 8-byte Folded Spill
	cmpq	$50, %r12
	jne	.LBB13_19
# %bb.45:
	leaq	120(%rsp), %rbx
	movl	$819200, %esi                   # imm = 0xC8000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	112(%rsp), %rdi
	movl	$32600, %esi                    # imm = 0x7F58
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	$819200, %edx                   # imm = 0xC8000
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$47244640258, %rdi              # imm = 0xB00000002
	movl	$1, %esi
	movabsq	$68719476768, %rbx              # imm = 0x1000000020
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_47
# %bb.46:
	movq	48(%rsp), %rdi
	movq	120(%rsp), %rsi
	movq	112(%rsp), %rdx
	movl	$163, %ecx
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$50, %r9d
	callq	_Z24__device_stub__gpuMatMulPfS_S_iii
.LBB13_47:
	leaq	104(%rsp), %rdi
	movl	$819200, %esi                   # imm = 0xC8000
	callq	hipMalloc
	movabsq	$214748364832, %rdi             # imm = 0x3200000020
	movl	$1, %esi
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_49
# %bb.48:
	movq	160(%rsp), %rdi
	movq	72(%rsp), %rsi
	movq	104(%rsp), %r8
	movl	$50, %edx
	movl	$4096, %ecx                     # imm = 0x1000
	callq	_Z25__device_stub__gpuSubMeanPiPfiiS0_
.LBB13_49:
	leaq	96(%rsp), %rdi
	movl	$10000, %esi                    # imm = 0x2710
	callq	hipMalloc
	movabsq	$17179869186, %rdi              # imm = 0x400000002
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB13_51
# %bb.50:
	movq	104(%rsp), %rdi
	movq	120(%rsp), %rsi
	movq	96(%rsp), %rdx
	movl	$50, %ecx
	movl	$4096, %r8d                     # imm = 0x1000
	movl	$50, %r9d
	callq	_Z24__device_stub__gpuMatMulPfS_S_iii
.LBB13_51:
	movl	$32600, %edi                    # imm = 0x7F58
	callq	malloc
	movq	%rax, %r12
	movl	$10000, %edi                    # imm = 0x2710
	callq	malloc
	movq	%rax, %rbx
	movq	112(%rsp), %rsi
	movl	$32600, %edx                    # imm = 0x7F58
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	96(%rsp), %rsi
	movl	$10000, %edx                    # imm = 0x2710
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipProfilerStop
	movl	$200, %edi
	callq	malloc
	movq	%rax, %r13
	movq	%r12, %rdi
	movq	%rbx, 24(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movl	$163, %edx
	movl	$50, %ecx
	movl	$50, %r8d
	movq	%rax, %r9
	callq	_Z8identifyPfS_iiiPi
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB13_56
# %bb.52:
	movq	%rax, %rbx
	movq	%r12, 56(%rsp)                  # 8-byte Spill
	movl	$.L.str.7, %edi
	movl	$23, %esi
	movl	$1, %edx
	movq	%rax, %rcx
	callq	fwrite@PLT
	xorl	%r12d, %r12d
.LBB13_53:                              # =>This Inner Loop Header: Depth=1
	movl	(%r13,%r12,4), %ecx
	incq	%r12
	movl	$.L.str.8, %esi
	movq	%rbx, %rdi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	fprintf
	cmpq	$50, %r12
	jne	.LBB13_53
# %bb.54:
	movq	%rbx, %rdi
	callq	fclose
	movq	%r14, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	movq	168(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	136(%rsp), %rdi                 # 8-byte Reload
	callq	free
	movq	88(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	80(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	56(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	24(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r13, %rdi
	callq	free
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	160(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	120(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	movq	96(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	jmp	.LBB13_55
.LBB13_56:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$1, %eax
.LBB13_55:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	main, .Lfunc_end13-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB14_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB14_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9gpuMatSubPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9gpuMatMulPfS_S_iii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15gpuMatTransposePfS_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15gpuMatMulScalarPfS_iif, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8gpuNorm2PfS_i, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpuMeanVecPiiiPf, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpuSubMeanPiPfiiS0_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9gpuCovMatPfS_iif, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12gpuNormalizePfS_S_i, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9gpuEigValPfS_S_i, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end14:
	.size	__hip_module_ctor, .Lfunc_end14-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB15_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB15_2:
	retq
.Lfunc_end15:
	.size	__hip_module_dtor, .Lfunc_end15-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9gpuMatSubPfS_S_ii,@object    # @_Z9gpuMatSubPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z9gpuMatSubPfS_S_ii
	.p2align	3, 0x0
_Z9gpuMatSubPfS_S_ii:
	.quad	_Z24__device_stub__gpuMatSubPfS_S_ii
	.size	_Z9gpuMatSubPfS_S_ii, 8

	.type	_Z9gpuMatMulPfS_S_iii,@object   # @_Z9gpuMatMulPfS_S_iii
	.globl	_Z9gpuMatMulPfS_S_iii
	.p2align	3, 0x0
_Z9gpuMatMulPfS_S_iii:
	.quad	_Z24__device_stub__gpuMatMulPfS_S_iii
	.size	_Z9gpuMatMulPfS_S_iii, 8

	.type	_Z15gpuMatTransposePfS_ii,@object # @_Z15gpuMatTransposePfS_ii
	.globl	_Z15gpuMatTransposePfS_ii
	.p2align	3, 0x0
_Z15gpuMatTransposePfS_ii:
	.quad	_Z30__device_stub__gpuMatTransposePfS_ii
	.size	_Z15gpuMatTransposePfS_ii, 8

	.type	_Z15gpuMatMulScalarPfS_iif,@object # @_Z15gpuMatMulScalarPfS_iif
	.globl	_Z15gpuMatMulScalarPfS_iif
	.p2align	3, 0x0
_Z15gpuMatMulScalarPfS_iif:
	.quad	_Z30__device_stub__gpuMatMulScalarPfS_iif
	.size	_Z15gpuMatMulScalarPfS_iif, 8

	.type	_Z8gpuNorm2PfS_i,@object        # @_Z8gpuNorm2PfS_i
	.globl	_Z8gpuNorm2PfS_i
	.p2align	3, 0x0
_Z8gpuNorm2PfS_i:
	.quad	_Z23__device_stub__gpuNorm2PfS_i
	.size	_Z8gpuNorm2PfS_i, 8

	.type	_Z10gpuMeanVecPiiiPf,@object    # @_Z10gpuMeanVecPiiiPf
	.globl	_Z10gpuMeanVecPiiiPf
	.p2align	3, 0x0
_Z10gpuMeanVecPiiiPf:
	.quad	_Z25__device_stub__gpuMeanVecPiiiPf
	.size	_Z10gpuMeanVecPiiiPf, 8

	.type	_Z10gpuSubMeanPiPfiiS0_,@object # @_Z10gpuSubMeanPiPfiiS0_
	.globl	_Z10gpuSubMeanPiPfiiS0_
	.p2align	3, 0x0
_Z10gpuSubMeanPiPfiiS0_:
	.quad	_Z25__device_stub__gpuSubMeanPiPfiiS0_
	.size	_Z10gpuSubMeanPiPfiiS0_, 8

	.type	_Z9gpuCovMatPfS_iif,@object     # @_Z9gpuCovMatPfS_iif
	.globl	_Z9gpuCovMatPfS_iif
	.p2align	3, 0x0
_Z9gpuCovMatPfS_iif:
	.quad	_Z24__device_stub__gpuCovMatPfS_iif
	.size	_Z9gpuCovMatPfS_iif, 8

	.type	_Z12gpuNormalizePfS_S_i,@object # @_Z12gpuNormalizePfS_S_i
	.globl	_Z12gpuNormalizePfS_S_i
	.p2align	3, 0x0
_Z12gpuNormalizePfS_S_i:
	.quad	_Z27__device_stub__gpuNormalizePfS_S_i
	.size	_Z12gpuNormalizePfS_S_i, 8

	.type	_Z9gpuEigValPfS_S_i,@object     # @_Z9gpuEigValPfS_S_i
	.globl	_Z9gpuEigValPfS_S_i
	.p2align	3, 0x0
_Z9gpuEigValPfS_S_i:
	.quad	_Z24__device_stub__gpuEigValPfS_S_i
	.size	_Z9gpuEigValPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"train_matrix.txt"
	.size	.L.str, 17

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"test_matrix.txt"
	.size	.L.str.4, 16

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"identify.txt"
	.size	.L.str.5, 13

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"wb"
	.size	.L.str.6, 3

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Test Image\t\tPrediction\n"
	.size	.L.str.7, 24

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"%d \t\t\t\t %d\n"
	.size	.L.str.8, 12

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9gpuMatSubPfS_S_ii"
	.size	.L__unnamed_1, 21

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9gpuMatMulPfS_S_iii"
	.size	.L__unnamed_2, 22

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z15gpuMatTransposePfS_ii"
	.size	.L__unnamed_3, 26

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z15gpuMatMulScalarPfS_iif"
	.size	.L__unnamed_4, 27

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z8gpuNorm2PfS_i"
	.size	.L__unnamed_5, 17

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z10gpuMeanVecPiiiPf"
	.size	.L__unnamed_6, 21

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z10gpuSubMeanPiPfiiS0_"
	.size	.L__unnamed_7, 24

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z9gpuCovMatPfS_iif"
	.size	.L__unnamed_8, 20

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z12gpuNormalizePfS_S_i"
	.size	.L__unnamed_9, 24

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z9gpuEigValPfS_S_i"
	.size	.L__unnamed_10, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr.2,@object                 # @str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr.2:
	.asciz	"Error open file"
	.size	.Lstr.2, 16

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__gpuMatSubPfS_S_ii
	.addrsig_sym _Z24__device_stub__gpuMatMulPfS_S_iii
	.addrsig_sym _Z30__device_stub__gpuMatTransposePfS_ii
	.addrsig_sym _Z30__device_stub__gpuMatMulScalarPfS_iif
	.addrsig_sym _Z23__device_stub__gpuNorm2PfS_i
	.addrsig_sym _Z25__device_stub__gpuMeanVecPiiiPf
	.addrsig_sym _Z25__device_stub__gpuSubMeanPiPfiiS0_
	.addrsig_sym _Z24__device_stub__gpuCovMatPfS_iif
	.addrsig_sym _Z27__device_stub__gpuNormalizePfS_S_i
	.addrsig_sym _Z24__device_stub__gpuEigValPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9gpuMatSubPfS_S_ii
	.addrsig_sym _Z9gpuMatMulPfS_S_iii
	.addrsig_sym _Z15gpuMatTransposePfS_ii
	.addrsig_sym _Z15gpuMatMulScalarPfS_iif
	.addrsig_sym _Z8gpuNorm2PfS_i
	.addrsig_sym _Z10gpuMeanVecPiiiPf
	.addrsig_sym _Z10gpuSubMeanPiPfiiS0_
	.addrsig_sym _Z9gpuCovMatPfS_iif
	.addrsig_sym _Z12gpuNormalizePfS_S_i
	.addrsig_sym _Z9gpuEigValPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9gpuMatSubPfS_S_ii    ; -- Begin function _Z9gpuMatSubPfS_S_ii
	.globl	_Z9gpuMatSubPfS_S_ii
	.p2align	8
	.type	_Z9gpuMatSubPfS_S_ii,@function
_Z9gpuMatSubPfS_S_ii:                   ; @_Z9gpuMatSubPfS_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_cmp_gt_i32_e64 s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9gpuMatSubPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9gpuMatSubPfS_S_ii, .Lfunc_end0-_Z9gpuMatSubPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 232
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9gpuMatMulPfS_S_iii   ; -- Begin function _Z9gpuMatMulPfS_S_iii
	.globl	_Z9gpuMatMulPfS_S_iii
	.p2align	8
	.type	_Z9gpuMatMulPfS_S_iii,@function
_Z9gpuMatMulPfS_S_iii:                  ; @_Z9gpuMatMulPfS_S_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x18
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s6, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB1_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v1, s5
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s5, s5, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s5, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc0 .LBB1_3
	s_branch .LBB1_5
.LBB1_4:
	v_mov_b32_e32 v6, 0
.LBB1_5:                                ; %Flow54
	v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9gpuMatMulPfS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9gpuMatMulPfS_S_iii, .Lfunc_end1-_Z9gpuMatMulPfS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15gpuMatTransposePfS_ii ; -- Begin function _Z15gpuMatTransposePfS_ii
	.globl	_Z15gpuMatTransposePfS_ii
	.p2align	8
	.type	_Z15gpuMatTransposePfS_ii,@function
_Z15gpuMatTransposePfS_ii:              ; @_Z15gpuMatTransposePfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u32_e32 vcc_lo, s5, v0
	v_cmp_gt_u32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v0, s4, v[1:2]
	v_mov_b32_e32 v5, v3
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15gpuMatTransposePfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z15gpuMatTransposePfS_ii, .Lfunc_end2-_Z15gpuMatTransposePfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z15gpuMatMulScalarPfS_iif ; -- Begin function _Z15gpuMatMulScalarPfS_iif
	.globl	_Z15gpuMatMulScalarPfS_iif
	.p2align	8
	.type	_Z15gpuMatMulScalarPfS_iif,@function
_Z15gpuMatMulScalarPfS_iif:             ; @_Z15gpuMatMulScalarPfS_iif
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, s6, v2
	global_store_b32 v[0:1], v2, off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15gpuMatMulScalarPfS_iif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z15gpuMatMulScalarPfS_iif, .Lfunc_end3-_Z15gpuMatMulScalarPfS_iif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 204
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8gpuNorm2PfS_i        ; -- Begin function _Z8gpuNorm2PfS_i
	.globl	_Z8gpuNorm2PfS_i
	.p2align	8
	.type	_Z8gpuNorm2PfS_i,@function
_Z8gpuNorm2PfS_i:                       ; @_Z8gpuNorm2PfS_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x24
	s_load_b32 s5, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s5, v1
	s_and_saveexec_b32 s5, vcc_lo
	s_cbranch_execz .LBB4_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_load_b32 v2, v[1:2], off
.LBB4_2:
	s_or_b32 exec_lo, exec_lo, s5
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s4, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v2, v1
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v2, v2, v2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB4_3:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB4_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB4_3 Depth=1
	s_lshr_b32 s0, s4, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB4_6
; %bb.5:                                ;   in Loop: Header=BB4_3 Depth=1
	v_lshl_add_u32 v2, s0, 2, v1
	ds_load_b32 v3, v1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB4_6:                                ;   in Loop: Header=BB4_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s4, 4
	s_mov_b32 s4, s0
	s_branch .LBB4_3
.LBB4_7:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_11
; %bb.8:
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s0, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s1, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s1
	s_cbranch_execz .LBB4_11
; %bb.9:
	s_bcnt1_i32_b32 s0, s0
	s_load_b32 s1, s[2:3], 0x0
	v_cvt_f32_ubyte0_e32 v1, s0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s0, 0
	ds_load_b32 v0, v2
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v3, v0, v1
	v_mov_b32_e32 v1, s1
.LBB4_10:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v3
	global_atomic_cmpswap_b32 v0, v2, v[0:1], s[2:3] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB4_10
.LBB4_11:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8gpuNorm2PfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z8gpuNorm2PfS_i, .Lfunc_end4-_Z8gpuNorm2PfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 420
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10gpuMeanVecPiiiPf    ; -- Begin function _Z10gpuMeanVecPiiiPf
	.globl	_Z10gpuMeanVecPiiiPf
	.p2align	8
	.type	_Z10gpuMeanVecPiiiPf,@function
_Z10gpuMeanVecPiiiPf:                   ; @_Z10gpuMeanVecPiiiPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_cmp_lt_i32 s2, 1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_cbranch_scc1 .LBB5_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[4:5], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v2, v1
	s_mov_b32 s6, s2
.LBB5_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_i32 s6, s6, -1
	s_cmp_eq_u32 s6, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_nc_u32_e32 v2, s3, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v3, v3
	v_add_f32_e32 v0, v0, v3
	s_cbranch_scc0 .LBB5_2
	s_branch .LBB5_4
.LBB5_3:
	v_mov_b32_e32 v0, 0
.LBB5_4:                                ; %Flow29
	v_cvt_f32_i32_e32 v3, s2
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v3, v3, v0
	v_div_scale_f32 v6, vcc_lo, v0, v3, v0
	v_rcp_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v2, v5, v6
	v_fmac_f32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v2, v5, v6
	v_ashrrev_i32_e32 v2, 31, v1
	v_div_fmas_f32 v4, v6, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_div_fixup_f32 v3, v4, v3, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpuMeanVecPiiiPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z10gpuMeanVecPiiiPf, .Lfunc_end5-_Z10gpuMeanVecPiiiPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10gpuSubMeanPiPfiiS0_ ; -- Begin function _Z10gpuSubMeanPiPfiiS0_
	.globl	_Z10gpuSubMeanPiPfiiS0_
	.p2align	8
	.type	_Z10gpuSubMeanPiPfiiS0_,@function
_Z10gpuSubMeanPiPfiiS0_:                ; @_Z10gpuSubMeanPiPfiiS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_cmp_gt_i32_e64 s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(1)
	v_cvt_f32_i32_e32 v1, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v4, v1, v0
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpuSubMeanPiPfiiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z10gpuSubMeanPiPfiiS0_, .Lfunc_end6-_Z10gpuSubMeanPiPfiiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9gpuCovMatPfS_iif     ; -- Begin function _Z9gpuCovMatPfS_iif
	.globl	_Z9gpuCovMatPfS_iif
	.p2align	8
	.type	_Z9gpuCovMatPfS_iif,@function
_Z9gpuCovMatPfS_iif:                    ; @_Z9gpuCovMatPfS_iif
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	v_cmp_gt_i32_e64 s2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s5, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v3, null, s6, s6, v2
	v_div_scale_f32 v6, vcc_lo, v2, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v4
	v_fma_f32 v7, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v4
	v_fma_f32 v3, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v3, v3, v4, v5
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_div_fixup_f32 v2, v3, s6, v2
	global_store_b32 v[0:1], v2, off
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9gpuCovMatPfS_iif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z9gpuCovMatPfS_iif, .Lfunc_end7-_Z9gpuCovMatPfS_iif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 292
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12gpuNormalizePfS_S_i ; -- Begin function _Z12gpuNormalizePfS_S_i
	.globl	_Z12gpuNormalizePfS_S_i
	.p2align	8
	.type	_Z12gpuNormalizePfS_S_i,@function
_Z12gpuNormalizePfS_S_i:                ; @_Z12gpuNormalizePfS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s8, s[0:1], 0x2c
	s_mov_b32 s9, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB8_2
; %bb.1:
	s_waitcnt lgkmcnt(0)
	s_load_b32 s6, s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s6
	ds_store_b32 v1, v2
.LBB8_2:
	s_or_b32 exec_lo, exec_lo, s9
	s_load_b32 s0, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, 0xffff, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_u32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB8_4
; %bb.3:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	ds_load_b32 v2, v2
	v_add_co_u32 v3, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f32 v4, null, v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	v_div_scale_f32 v6, vcc_lo, v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, v6, v5
	v_fma_f32 v8, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v5
	v_fma_f32 v4, -v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v4, v4, v5, v7
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	v_div_fixup_f32 v2, v4, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB8_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12gpuNormalizePfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z12gpuNormalizePfS_S_i, .Lfunc_end8-_Z12gpuNormalizePfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9gpuEigValPfS_S_i     ; -- Begin function _Z9gpuEigValPfS_S_i
	.globl	_Z9gpuEigValPfS_S_i
	.p2align	8
	.type	_Z9gpuEigValPfS_S_i,@function
_Z9gpuEigValPfS_S_i:                    ; @_Z9gpuEigValPfS_S_i
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmp_gt_u32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB9_2
; %bb.1:
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v3, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v3, v1
.LBB9_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_lshl_add_u32 v1, v0, 2, 0
	s_cmp_lt_u32 s2, 2
	ds_store_b32 v1, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB9_3:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB9_7
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB9_3 Depth=1
	s_lshr_b32 s3, s2, 1
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s3, v0
	s_cbranch_execz .LBB9_6
; %bb.5:                                ;   in Loop: Header=BB9_3 Depth=1
	v_lshl_add_u32 v2, s3, 2, v1
	ds_load_b32 v3, v1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v3, v2
	ds_store_b32 v1, v2
.LBB9_6:                                ;   in Loop: Header=BB9_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s2, 4
	s_mov_b32 s2, s3
	s_branch .LBB9_3
.LBB9_7:                                ; %._crit_edge
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB9_11
; %bb.8:
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mbcnt_lo_u32_b32 v0, s2, 0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_and_b32 s3, exec_lo, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 exec_lo, s3
	s_cbranch_execz .LBB9_11
; %bb.9:
	s_bcnt1_i32_b32 s2, s2
	s_load_b32 s3, s[0:1], 0x0
	v_cvt_f32_ubyte0_e32 v1, s2
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, 0
	ds_load_b32 v0, v2
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v3, v0, v1
	v_mov_b32_e32 v1, s3
.LBB9_10:                               ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v0, v1, v3
	global_atomic_cmpswap_b32 v0, v2, v[0:1], s[0:1] glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v0, v1
	v_mov_b32_e32 v1, v0
	s_or_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB9_10
.LBB9_11:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9gpuEigValPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z9gpuEigValPfS_S_i, .Lfunc_end9-_Z9gpuEigValPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 412
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
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        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12gpuNormalizePfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12gpuNormalizePfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
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        .value_kind:     by_value
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        .value_kind:     hidden_dynamic_lds_size
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    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9gpuEigValPfS_S_i
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    .sgpr_spill_count: 0
    .symbol:         _Z9gpuEigValPfS_S_i.kd
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    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
