#include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>

// Definitions
#define NUM_PARTICLES 10000
#define GM (1.0/NUM_PARTICLES)
#define PI 3.14159265
#define BLOCK_SIZE 256

// Structs
typedef struct { double x, y, z; } vector3;
typedef struct { vector3 *p, *v; } particles_t;

// Headers
double unirandom();
void new_particle(vector3 *p, vector3 *v);
__global__ void integrate_position(vector3 *p, vector3 *v, double dt);
__global__ void leapint(vector3 *p, vector3 *v, double dt);
__global__ void print_position(vector3 *p);

// Main function
int main(const int argc, const char** argv) {
  int num_blocks = (NUM_PARTICLES + BLOCK_SIZE - 1) / BLOCK_SIZE;
  double dt = 0.1;
  int nstep = 120;
  int nout = 1;

  int num_bytes = 2 * NUM_PARTICLES * sizeof(vector3);
  double *host_memory = (double *) malloc(num_bytes);
  double *device_memory;
  cudaMalloc(&device_memory, num_bytes);

  // Assign host memory
  particles_t host_particles;
  host_particles.p = (vector3*) host_memory;
  host_particles.v = ((vector3*) host_memory) + NUM_PARTICLES;
  // Assign device memory
  particles_t device_particles;
  device_particles.p = (vector3*) device_memory;
  device_particles.v = ((vector3*) device_memory) + NUM_PARTICLES;

  // Initialize bodies
  srand(time(0));
  for (int i = 0; i < NUM_PARTICLES; i++) {
    new_particle(&host_particles.p[i], &host_particles.v[i]);
  }

  // Needed to print in paralel
  cudaDeviceSetLimit(cudaLimitPrintfFifoSize, NUM_PARTICLES * 400);
  // Copy host to device
  cudaMemcpy(device_memory, host_memory, num_bytes, cudaMemcpyHostToDevice);

  // Loop leapfrog
  for (int i = 0; i < nstep; i++) {
    if (i % nout == 0) {
      print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
      cudaDeviceSynchronize();
    }

    leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
    cudaDeviceSynchronize();
    integrate_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
    cudaDeviceSynchronize();
    leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
    cudaDeviceSynchronize();
  }
  if (nstep % nout == 0) {
    print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
    cudaDeviceSynchronize();
  }

  free(host_memory);
  cudaFree(device_memory);
}

double unirandom() {
  return ((double) rand())/RAND_MAX;
}

void new_particle(vector3 *p, vector3 *v) {
  double X1 = unirandom();
  double r = pow(pow(X1, -2.0/3) - 1, -0.5);
  double X2 = unirandom();
  double X3 = unirandom();
  p->z = (1 - 2 * X2) * r;
  p->x = sqrt((r * r - p->z * p->z)) * cos(2 * PI * X3);
  p->y = sqrt((r * r - p->z * p->z)) * sin(2 * PI * X3);

  #ifdef STABLE
    double V_e = sqrt(2) * pow((1 + r * r), -0.25);
    double X4 = unirandom();
    double X5 = unirandom();
    while ((0.1 * X5) >= (X4 * X4 * pow((1 - X4 * X4), 3.5))) {
      X4 = unirandom();
      X5 = unirandom();
    }
    double V = X4 * V_e;
    double X6 = unirandom();
    double X7 = unirandom();
    v->z = (1 - 2 * X6) * V;
    v->x = sqrt((V * V - v->z * v->z)) * cos(2 * PI * X7);
    v->y = sqrt((V * V - v->z * v->z)) * sin(2 * PI * X7);
  #else
    (*v) = (vector3) {0.0, 0.0, 0.0};
  #endif
}

// Integrate position
__global__ void integrate_position(vector3 *p, vector3 *v, double dt) {
  unsigned long i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < NUM_PARTICLES) {
    p[i] = (vector3) {p[i].x + v[i].x * dt, p[i].y + v[i].y * dt, p[i].z + v[i].z * dt};
  }
}

// Leapfrog integrator
__global__ void leapint(vector3 *p, vector3 *v, double dt) {
  int i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < NUM_PARTICLES) {
    double ax = 0.0;
    double ay = 0.0;
    double az = 0.0;

    for (int j = 0; j < NUM_PARTICLES; j++) {
      if(i == j) {
        continue;
      }
      double dx = p[j].x - p[i].x;
      double dy = p[j].y - p[i].y;
      double dz = p[j].z - p[i].z;
      double accel = pow(rsqrt(dx * dx + dy * dy + dz * dz), 3);
      ax += dx * accel;
      ay += dy * accel;
      az += dz * accel;
    }

    v[i] = (vector3) {v[i].x + 0.5 * GM * dt * ax, v[i].y + 0.5 * GM * dt * ay, v[i].z + 0.5 * GM * dt * az};
  }
}

// Print positions
__global__ void print_position(vector3 *p) {
  int i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < NUM_PARTICLES) {
    printf("%d,%.6lf,%.6lf,%.6lf\n", i, p[i].x, p[i].y, p[i].z);
  }
}

	.file	"tmpxft_002980c4_00000000-6_plummer.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z9unirandomv
	.type	_Z9unirandomv, @function
_Z9unirandomv:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	rand@PLT
	cvtsi2sdl	%eax, %xmm0
	divsd	.LC0(%rip), %xmm0
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z9unirandomv, .-_Z9unirandomv
	.globl	_Z12new_particleP7vector3S0_
	.type	_Z12new_particleP7vector3S0_, @function
_Z12new_particleP7vector3S0_:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	call	_Z9unirandomv
	movsd	.LC1(%rip), %xmm1
	call	pow@PLT
	subsd	.LC3(%rip), %xmm0
	movsd	.LC2(%rip), %xmm1
	call	pow@PLT
	movsd	%xmm0, 24(%rsp)
	call	_Z9unirandomv
	movsd	%xmm0, 16(%rsp)
	call	_Z9unirandomv
	movsd	16(%rsp), %xmm1
	movsd	24(%rsp), %xmm2
	movsd	%xmm0, 8(%rsp)
	addsd	%xmm1, %xmm1
	movaps	%xmm1, %xmm0
	movsd	.LC3(%rip), %xmm1
	subsd	%xmm0, %xmm1
	mulsd	%xmm2, %xmm1
	mulsd	%xmm2, %xmm2
	movsd	%xmm1, 16(%rbx)
	mulsd	%xmm1, %xmm1
	subsd	%xmm1, %xmm2
	movaps	%xmm2, %xmm0
	movq	%xmm2, %r14
	call	sqrt@PLT
	movsd	8(%rsp), %xmm3
	leaq	40(%rsp), %rdi
	mulsd	.LC4(%rip), %xmm3
	movsd	%xmm0, 16(%rsp)
	leaq	32(%rsp), %rsi
	movaps	%xmm3, %xmm0
	call	sincos@PLT
	movsd	16(%rsp), %xmm1
	mulsd	32(%rsp), %xmm1
	movq	%r14, %xmm0
	movsd	40(%rsp), %xmm4
	movsd	%xmm4, 8(%rsp)
	movsd	%xmm1, (%rbx)
	call	sqrt@PLT
	mulsd	8(%rsp), %xmm0
	movsd	%xmm0, 8(%rbx)
	movq	$0x000000000, 0(%rbp)
	movq	$0x000000000, 8(%rbp)
	movq	$0x000000000, 16(%rbp)
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z12new_particleP7vector3S0_, .-_Z12new_particleP7vector3S0_
	.globl	_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
	.type	_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d, @function
_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	48(%rsp), %rdi
	leaq	60(%rsp), %rsi
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18integrate_positionP7vector3S0_d(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L6:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d, .-_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
	.globl	_Z18integrate_positionP7vector3S0_d
	.type	_Z18integrate_positionP7vector3S0_d, @function
_Z18integrate_positionP7vector3S0_d:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
	.cfi_endproc
.LFE2055:
	.size	_Z18integrate_positionP7vector3S0_d, .-_Z18integrate_positionP7vector3S0_d
	.globl	_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
	.type	_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d, @function
_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%rsi, 16(%rsp)
	leaq	48(%rsp), %rdi
	leaq	60(%rsp), %rsi
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7leapintP7vector3S0_d(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L12:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d, .-_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
	.globl	_Z7leapintP7vector3S0_d
	.type	_Z7leapintP7vector3S0_d, @function
_Z7leapintP7vector3S0_d:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
	.cfi_endproc
.LFE2057:
	.size	_Z7leapintP7vector3S0_d, .-_Z7leapintP7vector3S0_d
	.globl	_Z41__device_stub__Z14print_positionP7vector3P7vector3
	.type	_Z41__device_stub__Z14print_positionP7vector3P7vector3, @function
_Z41__device_stub__Z14print_positionP7vector3P7vector3:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z14print_positionP7vector3(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L17:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z41__device_stub__Z14print_positionP7vector3P7vector3, .-_Z41__device_stub__Z14print_positionP7vector3P7vector3
	.globl	_Z14print_positionP7vector3
	.type	_Z14print_positionP7vector3, @function
_Z14print_positionP7vector3:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z14print_positionP7vector3P7vector3
	.cfi_endproc
.LFE2059:
	.size	_Z14print_positionP7vector3, .-_Z14print_positionP7vector3
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$480000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$480000, %esi
	leaq	8(%rsp), %rdi
	movq	%rax, %r12
	call	cudaMalloc@PLT
	xorl	%edi, %edi
	movq	8(%rsp), %r13
	movq	%r12, %rbx
	call	time@PLT
	leaq	240000(%r12), %rbp
	movl	%eax, %edi
	leaq	240000(%r13), %r14
	call	srand@PLT
.L23:
	leaq	240000(%rbx), %rsi
	movq	%rbx, %rdi
	addq	$24, %rbx
	call	_Z12new_particleP7vector3S0_
	cmpq	%rbp, %rbx
	jne	.L23
	movl	$4000000, %esi
	movl	$1, %edi
	movl	$16777217, %ebx
	movl	$536870917, %ebp
	call	cudaDeviceSetLimit@PLT
	movq	8(%rsp), %rdi
	movq	%r12, %rsi
	salq	$8, %rbx
	movl	$1, %ecx
	movl	$480000, %edx
	movl	$120, %r15d
	salq	$3, %rbp
	call	cudaMemcpy@PLT
.L28:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rbp, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	%r13, %rdi
	call	_Z41__device_stub__Z14print_positionP7vector3P7vector3
.L24:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rbp, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movsd	.LC6(%rip), %xmm0
	movq	%r14, %rsi
	movq	%r13, %rdi
	call	_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
.L25:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rbp, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movsd	.LC6(%rip), %xmm0
	movq	%r14, %rsi
	movq	%r13, %rdi
	call	_Z49__device_stub__Z18integrate_positionP7vector3S0_dP7vector3S0_d
.L26:
	call	cudaDeviceSynchronize@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rbp, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movsd	.LC6(%rip), %xmm0
	movq	%r14, %rsi
	movq	%r13, %rdi
	call	_Z37__device_stub__Z7leapintP7vector3S0_dP7vector3S0_d
.L27:
	call	cudaDeviceSynchronize@PLT
	decl	%r15d
	jne	.L28
	movl	$16777217, %edx
	movl	$536870917, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	salq	$3, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 28(%rsp)
	movl	$1, 36(%rsp)
	movq	%rdi, 16(%rsp)
	movl	$1, 24(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	%r13, %rdi
	call	_Z41__device_stub__Z14print_positionP7vector3P7vector3
.L29:
	call	cudaDeviceSynchronize@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC7:
	.string	"_Z14print_positionP7vector3"
.LC8:
	.string	"_Z7leapintP7vector3S0_d"
.LC9:
	.string	"_Z18integrate_positionP7vector3S0_d"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14print_positionP7vector3(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7leapintP7vector3S0_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z18integrate_positionP7vector3S0_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	-4194304
	.long	1105199103
	.align 8
.LC1:
	.long	1431655765
	.long	-1075489451
	.align 8
.LC2:
	.long	0
	.long	-1075838976
	.align 8
.LC3:
	.long	0
	.long	1072693248
	.align 8
.LC4:
	.long	1405670641
	.long	1075388923
	.align 8
.LC6:
	.long	-1717986918
	.long	1069128089
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <time.h>

// Definitions
#define NUM_PARTICLES 10000
#define GM (1.0/NUM_PARTICLES)
#define PI 3.14159265
#define BLOCK_SIZE 256

// Structs
typedef struct { double x, y, z; } vector3;
typedef struct { vector3 *p, *v; } particles_t;

// Headers
double unirandom();
void new_particle(vector3 *p, vector3 *v);
__global__ void integrate_position(vector3 *p, vector3 *v, double dt);
__global__ void leapint(vector3 *p, vector3 *v, double dt);
__global__ void print_position(vector3 *p);

// Main function
int main(const int argc, const char** argv) {
  int num_blocks = (NUM_PARTICLES + BLOCK_SIZE - 1) / BLOCK_SIZE;
  double dt = 0.1;
  int nstep = 120;
  int nout = 1;

  int num_bytes = 2 * NUM_PARTICLES * sizeof(vector3);
  double *host_memory = (double *) malloc(num_bytes);
  double *device_memory;
  hipMalloc(&device_memory, num_bytes);

  // Assign host memory
  particles_t host_particles;
  host_particles.p = (vector3*) host_memory;
  host_particles.v = ((vector3*) host_memory) + NUM_PARTICLES;
  // Assign device memory
  particles_t device_particles;
  device_particles.p = (vector3*) device_memory;
  device_particles.v = ((vector3*) device_memory) + NUM_PARTICLES;

  // Initialize bodies
  srand(time(0));
  for (int i = 0; i < NUM_PARTICLES; i++) {
    new_particle(&host_particles.p[i], &host_particles.v[i]);
  }

  // Needed to print in paralel
  hipDeviceSetLimit(hipLimitPrintfFifoSize, NUM_PARTICLES * 400);
  // Copy host to device
  hipMemcpy(device_memory, host_memory, num_bytes, hipMemcpyHostToDevice);

  // Loop leapfrog
  for (int i = 0; i < nstep; i++) {
    if (i % nout == 0) {
      print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
      hipDeviceSynchronize();
    }

    leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
    hipDeviceSynchronize();
    integrate_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
    hipDeviceSynchronize();
    leapint<<<num_blocks, BLOCK_SIZE>>>(device_particles.p, device_particles.v, dt);
    hipDeviceSynchronize();
  }
  if (nstep % nout == 0) {
    print_position<<<num_blocks, BLOCK_SIZE>>>(device_particles.p);
    hipDeviceSynchronize();
  }

  free(host_memory);
  hipFree(device_memory);
}

double unirandom() {
  return ((double) rand())/RAND_MAX;
}

void new_particle(vector3 *p, vector3 *v) {
  double X1 = unirandom();
  double r = pow(pow(X1, -2.0/3) - 1, -0.5);
  double X2 = unirandom();
  double X3 = unirandom();
  p->z = (1 - 2 * X2) * r;
  p->x = sqrt((r * r - p->z * p->z)) * cos(2 * PI * X3);
  p->y = sqrt((r * r - p->z * p->z)) * sin(2 * PI * X3);

  #ifdef STABLE
    double V_e = sqrt(2) * pow((1 + r * r), -0.25);
    double X4 = unirandom();
    double X5 = unirandom();
    while ((0.1 * X5) >= (X4 * X4 * pow((1 - X4 * X4), 3.5))) {
      X4 = unirandom();
      X5 = unirandom();
    }
    double V = X4 * V_e;
    double X6 = unirandom();
    double X7 = unirandom();
    v->z = (1 - 2 * X6) * V;
    v->x = sqrt((V * V - v->z * v->z)) * cos(2 * PI * X7);
    v->y = sqrt((V * V - v->z * v->z)) * sin(2 * PI * X7);
  #else
    (*v) = (vector3) {0.0, 0.0, 0.0};
  #endif
}

// Integrate position
__global__ void integrate_position(vector3 *p, vector3 *v, double dt) {
  unsigned long i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < NUM_PARTICLES) {
    p[i] = (vector3) {p[i].x + v[i].x * dt, p[i].y + v[i].y * dt, p[i].z + v[i].z * dt};
  }
}

// Leapfrog integrator
__global__ void leapint(vector3 *p, vector3 *v, double dt) {
  int i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < NUM_PARTICLES) {
    double ax = 0.0;
    double ay = 0.0;
    double az = 0.0;

    for (int j = 0; j < NUM_PARTICLES; j++) {
      if(i == j) {
        continue;
      }
      double dx = p[j].x - p[i].x;
      double dy = p[j].y - p[i].y;
      double dz = p[j].z - p[i].z;
      double accel = pow(rsqrt(dx * dx + dy * dy + dz * dz), 3);
      ax += dx * accel;
      ay += dy * accel;
      az += dz * accel;
    }

    v[i] = (vector3) {v[i].x + 0.5 * GM * dt * ax, v[i].y + 0.5 * GM * dt * ay, v[i].z + 0.5 * GM * dt * az};
  }
}

// Print positions
__global__ void print_position(vector3 *p) {
  int i = blockDim.x * blockIdx.x + threadIdx.x;
  if (i < NUM_PARTICLES) {
    printf("%d,%.6lf,%.6lf,%.6lf\n", i, p[i].x, p[i].y, p[i].z);
  }
}

	.text
	.file	"plummer.hip"
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI0_0:
	.quad	0x3fb999999999999a              # double 0.10000000000000001
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$480000, %edi                   # imm = 0x75300
	callq	malloc
	movq	%rax, %rbx
	movq	%rsp, %r14
	movl	$480000, %esi                   # imm = 0x75300
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	240000(%rbx), %r15
	movq	(%r14), %r14
	xorl	%r12d, %r12d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	leaq	(%rbx,%r12), %rdi
	leaq	(%r15,%r12), %rsi
	callq	_Z12new_particleP7vector3S0_
	addq	$24, %r12
	cmpq	$240000, %r12                   # imm = 0x3A980
	jne	.LBB0_1
# %bb.2:
	movabsq	$4294967336, %r15               # imm = 0x100000028
	leaq	240000(%r14), %r12
	movl	$4000000, %esi                  # imm = 0x3D0900
	movl	$1, %edi
	callq	hipDeviceSetLimit
	movq	(%rsp), %rdi
	movl	$480000, %edx                   # imm = 0x75300
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$120, %ebp
	leaq	216(%r15), %r13
.LBB0_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_5
# %bb.4:                                #   in Loop: Header=BB0_3 Depth=1
	movq	%r14, %rdi
	callq	_Z29__device_stub__print_positionP7vector3
.LBB0_5:                                #   in Loop: Header=BB0_3 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_7
# %bb.6:                                #   in Loop: Header=BB0_3 Depth=1
	movq	%r14, %rdi
	movq	%r12, %rsi
	movsd	.LCPI0_0(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	_Z22__device_stub__leapintP7vector3S0_d
.LBB0_7:                                #   in Loop: Header=BB0_3 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_9
# %bb.8:                                #   in Loop: Header=BB0_3 Depth=1
	movq	%r14, %rdi
	movq	%r12, %rsi
	movsd	.LCPI0_0(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	_Z33__device_stub__integrate_positionP7vector3S0_d
.LBB0_9:                                #   in Loop: Header=BB0_3 Depth=1
	callq	hipDeviceSynchronize
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_11
# %bb.10:                               #   in Loop: Header=BB0_3 Depth=1
	movq	%r14, %rdi
	movq	%r12, %rsi
	movsd	.LCPI0_0(%rip), %xmm0           # xmm0 = mem[0],zero
	callq	_Z22__device_stub__leapintP7vector3S0_d
.LBB0_11:                               #   in Loop: Header=BB0_3 Depth=1
	callq	hipDeviceSynchronize
	decl	%ebp
	jne	.LBB0_3
# %bb.12:
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_14
# %bb.13:
	movq	%r14, %rdi
	callq	_Z29__device_stub__print_positionP7vector3
.LBB0_14:
	callq	hipDeviceSynchronize
	movq	%rbx, %rdi
	callq	free
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z12new_particleP7vector3S0_
.LCPI1_0:
	.quad	0x41dfffffffc00000              # double 2147483647
.LCPI1_1:
	.quad	0xbfe5555555555555              # double -0.66666666666666663
.LCPI1_2:
	.quad	0xbff0000000000000              # double -1
.LCPI1_3:
	.quad	0xbfe0000000000000              # double -0.5
.LCPI1_4:
	.quad	0x3ff0000000000000              # double 1
.LCPI1_5:
	.quad	0x401921fb53c8d4f1              # double 6.2831853000000004
.LCPI1_6:
	.quad	0x0000000000000000              # double 0
	.text
	.globl	_Z12new_particleP7vector3S0_
	.type	_Z12new_particleP7vector3S0_,@function
_Z12new_particleP7vector3S0_:           # @_Z12new_particleP7vector3S0_
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	callq	rand
	cvtsi2sd	%eax, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movsd	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero
	callq	pow
	addsd	.LCPI1_2(%rip), %xmm0
	movsd	.LCPI1_3(%rip), %xmm1           # xmm1 = mem[0],zero
	callq	pow
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	callq	rand
	cvtsi2sd	%eax, %xmm2
	divsd	.LCPI1_0(%rip), %xmm2
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	addsd	%xmm0, %xmm0
	movsd	.LCPI1_4(%rip), %xmm1           # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	movsd	(%rsp), %xmm0                   # 8-byte Reload
                                        # xmm0 = mem[0],zero
	mulsd	%xmm0, %xmm1
	movsd	%xmm1, 16(%r14)
	mulsd	%xmm0, %xmm0
	mulsd	%xmm1, %xmm1
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	subsd	%xmm1, %xmm0
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm1, %xmm0
	jb	.LBB1_2
# %bb.1:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB1_3
.LBB1_2:                                # %call.sqrt
	movsd	%xmm2, 8(%rsp)                  # 8-byte Spill
	callq	sqrt
	movsd	8(%rsp), %xmm2                  # 8-byte Reload
                                        # xmm2 = mem[0],zero
.LBB1_3:                                # %.split
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	mulsd	.LCPI1_5(%rip), %xmm2
	movsd	%xmm2, 8(%rsp)                  # 8-byte Spill
	movapd	%xmm2, %xmm0
	callq	cos
	mulsd	16(%rsp), %xmm0                 # 8-byte Folded Reload
	movsd	%xmm0, (%r14)
	movsd	16(%r14), %xmm0                 # xmm0 = mem[0],zero
	mulsd	%xmm0, %xmm0
	movsd	(%rsp), %xmm1                   # 8-byte Reload
                                        # xmm1 = mem[0],zero
	subsd	%xmm0, %xmm1
	movapd	%xmm1, %xmm0
	ucomisd	.LCPI1_6(%rip), %xmm1
	jb	.LBB1_5
# %bb.4:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB1_6
.LBB1_5:                                # %call.sqrt17
	callq	sqrt
.LBB1_6:                                # %.split.split
	movsd	%xmm0, (%rsp)                   # 8-byte Spill
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	sin
	mulsd	(%rsp), %xmm0                   # 8-byte Folded Reload
	movsd	%xmm0, 8(%r14)
	xorpd	%xmm0, %xmm0
	movupd	%xmm0, (%rbx)
	movq	$0, 16(%rbx)
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z12new_particleP7vector3S0_, .Lfunc_end1-_Z12new_particleP7vector3S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__print_positionP7vector3 # -- Begin function _Z29__device_stub__print_positionP7vector3
	.type	_Z29__device_stub__print_positionP7vector3,@function
_Z29__device_stub__print_positionP7vector3: # @_Z29__device_stub__print_positionP7vector3
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14print_positionP7vector3, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z29__device_stub__print_positionP7vector3, .Lfunc_end2-_Z29__device_stub__print_positionP7vector3
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__leapintP7vector3S0_d # -- Begin function _Z22__device_stub__leapintP7vector3S0_d
	.type	_Z22__device_stub__leapintP7vector3S0_d,@function
_Z22__device_stub__leapintP7vector3S0_d: # @_Z22__device_stub__leapintP7vector3S0_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7leapintP7vector3S0_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z22__device_stub__leapintP7vector3S0_d, .Lfunc_end3-_Z22__device_stub__leapintP7vector3S0_d
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__integrate_positionP7vector3S0_d # -- Begin function _Z33__device_stub__integrate_positionP7vector3S0_d
	.type	_Z33__device_stub__integrate_positionP7vector3S0_d,@function
_Z33__device_stub__integrate_positionP7vector3S0_d: # @_Z33__device_stub__integrate_positionP7vector3S0_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18integrate_positionP7vector3S0_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z33__device_stub__integrate_positionP7vector3S0_d, .Lfunc_end4-_Z33__device_stub__integrate_positionP7vector3S0_d
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z9unirandomv
.LCPI5_0:
	.quad	0x41dfffffffc00000              # double 2147483647
	.text
	.globl	_Z9unirandomv
	.type	_Z9unirandomv,@function
_Z9unirandomv:                          # @_Z9unirandomv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	rand
	cvtsi2sd	%eax, %xmm0
	divsd	.LCPI5_0(%rip), %xmm0
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z9unirandomv, .Lfunc_end5-_Z9unirandomv
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18integrate_positionP7vector3S0_d, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7leapintP7vector3S0_d, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14print_positionP7vector3, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14print_positionP7vector3,@object # @_Z14print_positionP7vector3
	.section	.rodata,"a",@progbits
	.globl	_Z14print_positionP7vector3
	.p2align	3, 0x0
_Z14print_positionP7vector3:
	.quad	_Z29__device_stub__print_positionP7vector3
	.size	_Z14print_positionP7vector3, 8

	.type	_Z7leapintP7vector3S0_d,@object # @_Z7leapintP7vector3S0_d
	.globl	_Z7leapintP7vector3S0_d
	.p2align	3, 0x0
_Z7leapintP7vector3S0_d:
	.quad	_Z22__device_stub__leapintP7vector3S0_d
	.size	_Z7leapintP7vector3S0_d, 8

	.type	_Z18integrate_positionP7vector3S0_d,@object # @_Z18integrate_positionP7vector3S0_d
	.globl	_Z18integrate_positionP7vector3S0_d
	.p2align	3, 0x0
_Z18integrate_positionP7vector3S0_d:
	.quad	_Z33__device_stub__integrate_positionP7vector3S0_d
	.size	_Z18integrate_positionP7vector3S0_d, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18integrate_positionP7vector3S0_d"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7leapintP7vector3S0_d"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14print_positionP7vector3"
	.size	.L__unnamed_3, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__print_positionP7vector3
	.addrsig_sym _Z22__device_stub__leapintP7vector3S0_d
	.addrsig_sym _Z33__device_stub__integrate_positionP7vector3S0_d
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14print_positionP7vector3
	.addrsig_sym _Z7leapintP7vector3S0_d
	.addrsig_sym _Z18integrate_positionP7vector3S0_d
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18integrate_positionP7vector3S0_d ; -- Begin function _Z18integrate_positionP7vector3S0_d
	.globl	_Z18integrate_positionP7vector3S0_d
	.p2align	8
	.type	_Z18integrate_positionP7vector3S0_d,@function
_Z18integrate_positionP7vector3S0_d:    ; @_Z18integrate_positionP7vector3S0_d
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 0x2710, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[8:9], null, v1, 24, s[4:5]
	v_mad_u64_u32 v[10:11], null, v1, 24, s[6:7]
	global_load_b128 v[0:3], v[8:9], off
	global_load_b128 v[4:7], v[10:11], off
	global_load_b64 v[12:13], v[8:9], off offset:16
	global_load_b64 v[10:11], v[10:11], off offset:16
	s_waitcnt vmcnt(2)
	v_fma_f64 v[0:1], v[4:5], s[0:1], v[0:1]
	v_fma_f64 v[2:3], v[6:7], s[0:1], v[2:3]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[4:5], v[10:11], s[0:1], v[12:13]
	s_clause 0x1
	global_store_b128 v[8:9], v[0:3], off
	global_store_b64 v[8:9], v[4:5], off offset:16
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18integrate_positionP7vector3S0_d
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18integrate_positionP7vector3S0_d, .Lfunc_end0-_Z18integrate_positionP7vector3S0_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 184
; NumSgprs: 16
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7leapintP7vector3S0_d ; -- Begin function _Z7leapintP7vector3S0_d
	.globl	_Z7leapintP7vector3S0_d
	.p2align	8
	.type	_Z7leapintP7vector3S0_d,@function
_Z7leapintP7vector3S0_d:                ; @_Z7leapintP7vector3S0_d
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x2710, v1
	s_cbranch_execz .LBB1_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_mov_b32 s8, 0x55555555
	s_mov_b32 s10, 0x968915a9
	s_mov_b32 s12, 0x4222de17
	s_mov_b32 s14, 0x3abe935a
	v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	s_mov_b32 s16, 0x47e6c9c2
	s_mov_b32 s18, 0xcfa74449
	s_mov_b32 s20, 0x71bf3c30
	s_mov_b32 s22, 0x1c7792ce
	s_mov_b32 s24, 0x924920da
	s_mov_b32 s26, 0x9999999c
	s_mov_b32 s28, 0xfefa39ef
	s_mov_b32 s30, 0x3b39803f
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[4:5], null, v1, 24, s[4:5]
	s_add_u32 s4, s4, 8
	s_mov_b32 s34, 0xd5df274d
	s_mov_b32 s36, 0x652b82fe
	s_mov_b32 s38, 0xfca7ab0c
	s_mov_b32 s40, 0x6a5dcb37
	s_mov_b32 s42, 0x623fde64
	s_mov_b32 s44, 0x7c89e6b0
	s_mov_b32 s46, 0x14761f6e
	s_mov_b32 s48, 0x1852b7b0
	s_mov_b32 s50, 0x11122322
	s_mov_b32 s52, 0x555502a1
	s_mov_b32 s54, 0x55555511
	s_mov_b32 s56, 11
	s_mov_b32 s33, 0
	s_mov_b32 s9, 0x3fe55555
	s_mov_b32 s11, 0x3fba6564
	s_mov_b32 s13, 0x3fbdee67
	s_mov_b32 s15, 0x3fbe25e4
	s_mov_b32 s17, 0x3fc110ef
	s_mov_b32 s19, 0x3fc3b13b
	s_mov_b32 s21, 0x3fc745d1
	s_addc_u32 s5, s5, 0
	s_mov_b32 s23, 0x3fcc71c7
	s_mov_b32 s25, 0x3fd24924
	s_mov_b32 s27, 0x3fd99999
	s_mov_b32 s29, 0x3fe62e42
	s_mov_b32 s31, 0x3c7abc9e
	s_mov_b32 s35, 0x3c8543b0
	s_mov_b32 s37, 0x3ff71547
	s_mov_b32 s39, 0x3e928af3
	s_mov_b32 s41, 0x3e5ade15
	s_mov_b32 s43, 0x3ec71dee
	s_mov_b32 s45, 0x3efa0199
	s_mov_b32 s47, 0x3f2a01a0
	s_mov_b32 s49, 0x3f56c16c
	s_mov_b32 s51, 0x3f811111
	s_mov_b32 s53, 0x3fa55555
	s_mov_b32 s55, 0x3fc55555
	s_mov_b32 s57, 0x3fe00000
	s_mov_b32 s59, 0xbfe55555
	s_mov_b32 s61, 0xbfe62e42
	s_mov_b32 s63, 0xbc7abc9e
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s64, exec_lo
	v_cmpx_ne_u32_e64 s33, v1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_clause 0x1
	global_load_b128 v[10:13], v[4:5], off
	global_load_b64 v[14:15], v[4:5], off offset:16
	s_add_u32 s0, s4, -8
	s_addc_u32 s1, s5, -1
	s_clause 0x1
	s_load_b128 s[68:71], s[0:1], 0x0
	s_load_b64 s[0:1], s[4:5], 0x8
	s_mov_b32 s58, s8
	s_mov_b32 s60, s28
	s_mov_b32 s62, s30
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_add_f64 v[12:13], s[70:71], -v[12:13]
	v_add_f64 v[10:11], s[68:69], -v[10:11]
	s_waitcnt vmcnt(0)
	v_add_f64 v[14:15], s[0:1], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[12:13], v[12:13]
	v_fma_f64 v[16:17], v[10:11], v[10:11], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[14:15], v[14:15], v[16:17]
	v_rsq_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[16:17], v[18:19], -v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[18:19], 0x180
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[16:17], v[18:19], 1.0
	v_mul_f64 v[20:21], v[18:19], v[16:17]
	v_fma_f64 v[16:17], 0x3fd80000, v[16:17], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[18:19]
	v_dual_cndmask_b32 v17, v19, v17 :: v_dual_cndmask_b32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[18:19], |v[16:17]|
	v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[18:19]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[18:19], v[18:19], v0
	v_frexp_exp_i32_f64_e32 v0, v[16:17]
	v_add_f64 v[20:21], v[18:19], 1.0
	v_add_f64 v[26:27], v[18:19], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_rcp_f64_e32 v[22:23], v[20:21]
	v_add_f64 v[28:29], v[20:21], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[28:29]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[22:23], v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], -v[20:21], v[22:23], 1.0
	v_fma_f64 v[22:23], v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[24:25], v[26:27], v[22:23]
	v_mul_f64 v[30:31], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[24:25], v[20:21], -v[30:31]
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[30:31], v[18:19]
	v_add_f64 v[28:29], v[26:27], -v[20:21]
	v_add_f64 v[30:31], v[20:21], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[26:27], -v[28:29]
	v_add_f64 v[18:19], v[30:31], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[26:27], -v[20:21]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[28:29], v[18:19]
	v_mul_f64 v[18:19], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[24:25], v[18:19]
	v_add_f64 v[22:23], v[20:21], -v[24:25]
	v_mul_f64 v[24:25], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	v_fma_f64 v[22:23], v[20:21], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[18:19], v[18:19]
	v_fma_f64 v[22:23], v[20:21], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_fma_f64 v[28:29], v[26:27], s[12:13], s[10:11]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	v_mul_f64 v[34:35], v[20:21], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[14:15]
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[16:17]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[20:21]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[24:25]
	v_fma_f64 v[28:29], v[26:27], v[28:29], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[26:27], v[28:29]
	v_fma_f64 v[24:25], v[26:27], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[22:23], v[28:29], v[24:25]
	v_add_f64 v[28:29], v[30:31], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[28:29], s[8:9]
	v_add_f64 v[30:31], v[28:29], -v[30:31]
	v_add_f64 v[36:37], v[32:33], s[58:59]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], -v[30:31]
	v_fma_f64 v[30:31], v[26:27], v[20:21], -v[34:35]
	v_add_f64 v[28:29], v[28:29], -v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], s[34:35]
	v_fma_f64 v[26:27], v[26:27], v[18:19], v[30:31]
	v_ldexp_f64 v[18:19], v[18:19], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_fma_f64 v[22:23], v[22:23], v[20:21], v[26:27]
	v_ldexp_f64 v[20:21], v[20:21], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[32:33], v[24:25]
	v_add_f64 v[28:29], v[34:35], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[32:33], -v[26:27]
	v_mul_f64 v[32:33], v[28:29], v[26:27]
	v_add_f64 v[34:35], v[28:29], -v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], v[30:31]
	v_fma_f64 v[30:31], v[28:29], v[26:27], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], -v[34:35]
	v_fma_f64 v[24:25], v[28:29], v[24:25], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[22:23], v[26:27], v[24:25]
	v_cvt_f64_i32_e32 v[26:27], v0
	v_add_f64 v[24:25], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[20:21], v[24:25]
	v_add_f64 v[30:31], v[24:25], -v[32:33]
	v_mul_f64 v[32:33], v[26:27], s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[28:29], -v[20:21]
	v_add_f64 v[22:23], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[26:27], s[28:29], -v[32:33]
	v_add_f64 v[20:21], v[24:25], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[18:19], v[22:23]
	v_fma_f64 v[22:23], v[26:27], s[30:31], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[32:33], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], v[18:19]
	v_add_f64 v[32:33], v[20:21], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[20:21], v[24:25]
	v_add_f64 v[28:29], v[24:25], -v[28:29]
	v_add_f64 v[22:23], v[22:23], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[26:27], -v[20:21]
	v_add_f64 v[18:19], v[18:19], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[26:27], -v[30:31]
	v_add_f64 v[24:25], v[24:25], -v[30:31]
	v_add_f64 v[28:29], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[34:35]
	v_add_f64 v[20:21], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[28:29], -v[22:23]
	v_add_f64 v[20:21], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[28:29], -v[24:25]
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_add_f64 v[30:31], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], -v[28:29]
	v_add_f64 v[24:25], v[30:31], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[22:23]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[30:31], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[20:21], -v[30:31]
	v_mul_f64 v[24:25], 0x40080000, v[20:21]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], 0x40080000, v[20:21], -v[24:25]
	v_cmp_class_f64_e64 vcc_lo, v[24:25], 0x204
	v_fma_f64 v[18:19], 0x40080000, v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[24:25], v[18:19]
	v_dual_cndmask_b32 v23, v21, v25 :: v_dual_cndmask_b32 v22, v20, v24
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[26:27], v[22:23], s[36:37]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[22:23]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[22:23]
	v_add_f64 v[18:19], v[18:19], -v[20:21]
	v_rndne_f64_e32 v[26:27], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[26:27], s[60:61], v[22:23]
	v_cvt_i32_f64_e32 v0, v[26:27]
	v_fma_f64 v[28:29], v[26:27], s[62:63], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[28:29], s[40:41], s[38:39]
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[44:45]
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[48:49]
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[52:53]
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[28:29], v[30:31], s[56:57]
	v_fma_f64 v[30:31], v[28:29], v[30:31], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], v[30:31], 1.0
	v_ldexp_f64 v[24:25], v[26:27], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, 0x7ff00000, v25, s0
	v_cndmask_b32_e32 v20, 0, v24, vcc_lo
	v_cmp_eq_f64_e64 s0, 0, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, 0, v0, s1
	v_cmp_class_f64_e64 s1, v[16:17], 0x204
	v_fma_f64 v[18:19], v[20:21], v[18:19], v[20:21]
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	v_cndmask_b32_e64 v0, 0x7ff00000, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v0, 0x7fffffff, v0, v17
	v_cndmask_b32_e32 v16, v18, v20, vcc_lo
	v_cndmask_b32_e32 v18, v19, v21, vcc_lo
	s_or_b32 vcc_lo, s0, s1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v16, v16, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v17, 0x7fffffff, v18, v17
	v_cndmask_b32_e32 v17, v17, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[10:11], v[16:17], v[2:3]
	v_fma_f64 v[8:9], v[12:13], v[16:17], v[8:9]
	v_fma_f64 v[6:7], v[14:15], v[16:17], v[6:7]
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s64
	s_add_i32 s33, s33, 1
	s_add_u32 s4, s4, 24
	s_addc_u32 s5, s5, 0
	s_cmpk_eq_i32 s33, 0x2710
	s_cbranch_scc0 .LBB1_2
; %bb.5:
	v_mad_i64_i32 v[4:5], null, v1, 24, s[6:7]
	s_mov_b32 s0, 0xeb1c432d
	s_mov_b32 s1, 0x3f0a36e2
	s_clause 0x1
	global_load_b128 v[10:13], v[4:5], off
	global_load_b64 v[14:15], v[4:5], off offset:16
	v_mul_f64 v[16:17], s[2:3], s[0:1]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[16:17], v[2:3], v[10:11]
	v_fma_f64 v[2:3], v[16:17], v[8:9], v[12:13]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[16:17], v[6:7], v[14:15]
	s_clause 0x1
	global_store_b128 v[4:5], v[0:3], off
	global_store_b64 v[4:5], v[6:7], off offset:16
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7leapintP7vector3S0_d
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 72
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7leapintP7vector3S0_d, .Lfunc_end1-_Z7leapintP7vector3S0_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2412
; NumSgprs: 74
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 74
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14print_positionP7vector3 ; -- Begin function _Z14print_positionP7vector3
	.globl	_Z14print_positionP7vector3
	.p2align	8
	.type	_Z14print_positionP7vector3,@function
_Z14print_positionP7vector3:            ; @_Z14print_positionP7vector3
; %bb.0:
	s_load_b32 s4, s[0:1], 0x14
	s_add_u32 s2, s0, 8
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e32 0x2710, v1
	s_cbranch_execz .LBB2_252
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mbcnt_lo_u32_b32 v36, -1, 0
	v_mov_b32_e32 v14, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v12, v36
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[4:5], null, v1, 24, s[0:1]
	s_clause 0x1
	global_load_b64 v[2:3], v[4:5], off offset:16
	global_load_b128 v[4:7], v[4:5], off
	s_load_b64 s[2:3], s[2:3], 0x50
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v12
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_7
; %bb.2:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[10:11], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	global_load_b64 v[13:14], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, v9, v11
	v_and_b32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v9, 24
	v_mul_hi_u32 v15, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v15, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v13, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v14, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[14:15], v0, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[14:15], v[10:11]
	s_cbranch_execz .LBB2_6
; %bb.3:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s5, 0
.LBB2_4:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	global_load_b64 v[16:17], v0, s[2:3]
	v_dual_mov_b32 v10, v14 :: v_dual_mov_b32 v11, v15
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[13:14], null, v8, 24, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, v14 :: v_dual_and_b32 v9, v9, v11
	v_mad_u64_u32 v[14:15], null, v9, 24, v[8:9]
	global_load_b64 v[8:9], v[13:14], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[14:15], v0, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_4
; %bb.5:                                ; %Flow471
	s_or_b32 exec_lo, exec_lo, s5
.LBB2_6:                                ; %Flow473
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_7:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v13, 0
	v_readfirstlane_b32 s4, v14
	v_readfirstlane_b32 s5, v15
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[16:17], v13, s[2:3] offset:40
	global_load_b128 v[8:11], v13, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v16
	v_readfirstlane_b32 s7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB2_9
; %bb.8:
	v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v15, v13
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v18, vcc_lo, v8, s9
	v_add_co_ci_u32_e32 v19, vcc_lo, s10, v9, vcc_lo
	v_dual_mov_b32 v16, 2 :: v_dual_mov_b32 v17, 1
	global_store_b128 v[18:19], v[14:17], off offset:8
.LBB2_9:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[14:15], 6, v[12:13]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v11, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v0, v14
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_add_co_ci_u32_e32 v17, vcc_lo, v10, v15, vcc_lo
	v_dual_mov_b32 v12, 33 :: v_dual_mov_b32 v15, v13
	v_dual_mov_b32 v14, v13 :: v_dual_mov_b32 v21, s15
	v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v19, s13
	v_mov_b32_e32 v18, s12
	s_clause 0x3
	global_store_b128 v[16:17], v[12:15], off
	global_store_b128 v[16:17], v[18:21], off offset:16
	global_store_b128 v[16:17], v[18:21], off offset:32
	global_store_b128 v[16:17], v[18:21], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB2_17
; %bb.10:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s7, exec_lo
	s_clause 0x1
	global_load_b64 v[20:21], v0, s[2:3] offset:32 glc
	global_load_b64 v[10:11], v0, s[2:3] offset:40
	v_dual_mov_b32 v19, s5 :: v_dual_mov_b32 v18, s4
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, s5, v11
	v_and_b32_e32 v10, s4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v11, v11, 24
	v_mul_hi_u32 v12, v10, 24
	v_mul_lo_u32 v10, v10, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v12, v11
	v_add_co_u32 v14, vcc_lo, v8, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, v9, v11, vcc_lo
	global_store_b64 v[14:15], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v0, v[18:21], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[20:21]
	s_cbranch_execz .LBB2_13
; %bb.11:                               ; %.preheader1.i.i.i.preheader
	s_mov_b32 s10, 0
.LBB2_12:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
	s_sleep 1
	global_store_b64 v[14:15], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v0, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_12
.LBB2_13:                               ; %Flow469
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v13, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v0, s10, 0
	global_load_b64 v[10:11], v13, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_15
; %bb.14:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v12, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[10:11], v[12:13], off offset:8
.LBB2_15:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[10:11], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB2_17
; %bb.16:
	global_load_b32 v10, v[10:11], off offset:24
	v_mov_b32_e32 v11, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v10
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[10:11], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_17:                               ; %Flow470
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v8, s9
	v_add_co_ci_u32_e32 v9, vcc_lo, s8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB2_18:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_20
; %bb.19:                               ;   in Loop: Header=BB2_18 Depth=1
	global_load_b32 v0, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB2_20:                               ;   in Loop: Header=BB2_18 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_22
; %bb.21:                               ;   in Loop: Header=BB2_18 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_23
.LBB2_22:                               ;   in Loop: Header=BB2_18 Depth=1
	s_mov_b32 s1, -1
.LBB2_23:                               ; %Flow464
                                        ;   in Loop: Header=BB2_18 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_18
; %bb.24:
	global_load_b64 v[8:9], v[16:17], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_28
; %bb.25:
	v_mov_b32_e32 v0, 0
	s_clause 0x2
	global_load_b64 v[12:13], v0, s[2:3] offset:40
	global_load_b64 v[16:17], v0, s[2:3] offset:24 glc
	global_load_b64 v[14:15], v0, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v18, vcc_lo, v12, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v18, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_dual_cndmask_b32 v11, v11, v19 :: v_dual_cndmask_b32 v10, v10, v18
	v_and_b32_e32 v13, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v12, v10, v12
	v_mul_lo_u32 v13, v13, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v18, v12, 24
	v_mul_lo_u32 v12, v12, 24
	v_add_nc_u32_e32 v13, v18, v13
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v14, v12
	v_mov_b32_e32 v12, v16
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v13, vcc_lo
	v_mov_b32_e32 v13, v17
	global_store_b64 v[14:15], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v0, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_28
; %bb.26:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB2_27:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[14:15], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v0, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[12:13]
	v_dual_mov_b32 v12, v16 :: v_dual_mov_b32 v13, v17
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_27
.LBB2_28:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, .str@rel32@lo+4
	s_addc_u32 s5, s5, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[4:5], 0
	s_cbranch_scc0 .LBB2_114
; %bb.29:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v11, v9 :: v_dual_and_b32 v0, 2, v8
	v_dual_mov_b32 v38, 0 :: v_dual_mov_b32 v15, 1
	v_and_b32_e32 v10, -3, v8
	v_mov_b32_e32 v14, 2
	s_mov_b64 s[6:7], 22
.LBB2_30:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_33 Depth 2
                                        ;     Child Loop BB2_40 Depth 2
                                        ;     Child Loop BB2_48 Depth 2
                                        ;     Child Loop BB2_56 Depth 2
                                        ;     Child Loop BB2_64 Depth 2
                                        ;     Child Loop BB2_72 Depth 2
                                        ;     Child Loop BB2_80 Depth 2
                                        ;     Child Loop BB2_88 Depth 2
                                        ;     Child Loop BB2_96 Depth 2
                                        ;     Child Loop BB2_102 Depth 2
                                        ;     Child Loop BB2_111 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[6:7], 56
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $sgpr15
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s8, s6, 56
	s_cselect_b32 s9, s7, 0
	s_cmp_gt_u32 s8, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB2_35
; %bb.31:                               ;   in Loop: Header=BB2_30 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB2_34
; %bb.32:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_lshl_b64 s[0:1], s[8:9], 3
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[4:5]
.LBB2_33:                               ; %.preheader31.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v12, v38, s[12:13]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v37, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], s10, v[37:38]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s0, s10
	v_or_b32_e32 v18, v12, v18
	v_or_b32_e32 v19, v13, v19
	s_cbranch_scc1 .LBB2_33
.LBB2_34:                               ; %Flow440
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s15, 0
.LBB2_35:                               ; %Flow442
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[4:5]
	s_cbranch_vccnz .LBB2_37
; %bb.36:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[18:19], v38, s[4:5]
	s_add_i32 s15, s8, -8
	s_add_u32 s0, s4, 8
	s_addc_u32 s1, s5, 0
.LBB2_37:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB2_42
; %bb.38:                               ;   in Loop: Header=BB2_30 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB2_41
; %bb.39:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB2_40:                               ; %.preheader29.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v12, v38, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v37, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], s10, v[37:38]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v20, v12, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v13, v21
	s_cbranch_scc1 .LBB2_40
.LBB2_41:                               ; %Flow435
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB2_43
.LBB2_42:                               ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr14
.LBB2_43:                               ; %Flow437
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB2_45
; %bb.44:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[20:21], v38, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_45:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB2_50
; %bb.46:                               ;   in Loop: Header=BB2_30 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB2_49
; %bb.47:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB2_48:                               ; %.preheader27.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v12, v38, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v37, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], s10, v[37:38]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v22, v12, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v23, v13, v23
	s_cbranch_scc1 .LBB2_48
.LBB2_49:                               ; %Flow430
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB2_51
.LBB2_50:                               ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB2_51:                               ; %Flow432
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB2_53
; %bb.52:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[22:23], v38, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_53:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB2_58
; %bb.54:                               ;   in Loop: Header=BB2_30 Depth=1
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB2_57
; %bb.55:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB2_56:                               ; %.preheader25.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v12, v38, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v37, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], s10, v[37:38]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v24, v12, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v25, v13, v25
	s_cbranch_scc1 .LBB2_56
.LBB2_57:                               ; %Flow425
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB2_59
.LBB2_58:                               ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $sgpr14
.LBB2_59:                               ; %Flow427
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB2_61
; %bb.60:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[24:25], v38, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_61:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB2_66
; %bb.62:                               ;   in Loop: Header=BB2_30 Depth=1
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB2_65
; %bb.63:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB2_64:                               ; %.preheader23.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v12, v38, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v37, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], s10, v[37:38]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s14, s12
	v_or_b32_e32 v26, v12, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v27, v13, v27
	s_cbranch_scc1 .LBB2_64
.LBB2_65:                               ; %Flow420
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s15, 0
	s_branch .LBB2_67
.LBB2_66:                               ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $sgpr15
.LBB2_67:                               ; %Flow422
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB2_69
; %bb.68:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[26:27], v38, s[0:1]
	s_add_i32 s15, s14, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_69:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_cmp_gt_u32 s15, 7
	s_cbranch_scc1 .LBB2_74
; %bb.70:                               ;   in Loop: Header=BB2_30 Depth=1
	v_mov_b32_e32 v28, 0
	v_mov_b32_e32 v29, 0
	s_cmp_eq_u32 s15, 0
	s_cbranch_scc1 .LBB2_73
; %bb.71:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], 0
.LBB2_72:                               ; %.preheader21.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s16, s0, s12
	s_addc_u32 s17, s1, s13
	s_add_u32 s12, s12, 1
	global_load_u8 v12, v38, s[16:17]
	s_addc_u32 s13, s13, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v37, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], s10, v[37:38]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u32 s15, s12
	v_or_b32_e32 v28, v12, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v29, v13, v29
	s_cbranch_scc1 .LBB2_72
.LBB2_73:                               ; %Flow415
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, 0
	s_mov_b32 s14, 0
	s_branch .LBB2_75
.LBB2_74:                               ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, -1
                                        ; implicit-def: $vgpr28_vgpr29
                                        ; implicit-def: $sgpr14
.LBB2_75:                               ; %Flow417
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB2_77
; %bb.76:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[28:29], v38, s[0:1]
	s_add_i32 s14, s15, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB2_77:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB2_82
; %bb.78:                               ;   in Loop: Header=BB2_30 Depth=1
	v_mov_b32_e32 v30, 0
	v_mov_b32_e32 v31, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB2_81
; %bb.79:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b64 s[10:11], 0
	s_mov_b64 s[12:13], s[0:1]
.LBB2_80:                               ; %.preheader.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v12, v38, s[12:13]
	s_add_i32 s14, s14, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v37, 0xffff, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[12:13], s10, v[37:38]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s14, 0
	v_or_b32_e32 v30, v12, v30
	v_or_b32_e32 v31, v13, v31
	s_cbranch_scc1 .LBB2_80
.LBB2_81:                               ; %Flow410
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, 0
	s_branch .LBB2_83
.LBB2_82:                               ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s10, -1
.LBB2_83:                               ; %Flow412
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccnz .LBB2_85
; %bb.84:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[30:31], v38, s[0:1]
.LBB2_85:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v37, v36 :: v_dual_mov_b32 v12, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v37
	v_mov_b32_e32 v13, 0
	v_cmp_eq_u32_e64 s0, s0, v37
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_91
; %bb.86:                               ;   in Loop: Header=BB2_30 Depth=1
	global_load_b64 v[34:35], v38, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[12:13], v38, s[2:3] offset:40
	global_load_b64 v[16:17], v38, s[2:3]
	s_mov_b32 s10, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v13, v13, v35
	v_and_b32_e32 v12, v12, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v13, v13, 24
	v_mul_hi_u32 v32, v12, 24
	v_mul_lo_u32 v12, v12, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, v32, v13
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v16, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, v17, v13, vcc_lo
	global_load_b64 v[32:33], v[12:13], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[12:13], v38, v[32:35], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[12:13], v[34:35]
	s_cbranch_execz .LBB2_90
; %bb.87:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s11, 0
.LBB2_88:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[16:17], v38, s[2:3] offset:40
	global_load_b64 v[32:33], v38, s[2:3]
	v_dual_mov_b32 v35, v13 :: v_dual_mov_b32 v34, v12
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v16, v16, v34
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[12:13], null, v16, 24, v[32:33]
	v_and_b32_e32 v32, v17, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, v32, 24, v[13:14]
	v_mov_b32_e32 v13, v16
	global_load_b64 v[32:33], v[12:13], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[12:13], v38, v[32:35], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[34:35]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB2_88
; %bb.89:                               ; %Flow405
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
.LBB2_90:                               ; %Flow407
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
.LBB2_91:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[16:17], v38, s[2:3] offset:40
	global_load_b128 v[32:35], v38, s[2:3]
	v_readfirstlane_b32 s10, v12
	v_readfirstlane_b32 s11, v13
	s_mov_b32 s16, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s12, v16
	v_readfirstlane_b32 s13, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[10:11], s[12:13]
	s_mul_i32 s1, s13, 24
	s_mul_hi_u32 s14, s12, 24
	s_mul_i32 s15, s12, 24
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB2_93
; %bb.92:                               ;   in Loop: Header=BB2_30 Depth=1
	v_dual_mov_b32 v12, s16 :: v_dual_mov_b32 v13, v38
	s_add_i32 s16, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v16, vcc_lo, v32, s15
	v_add_co_ci_u32_e32 v17, vcc_lo, s16, v33, vcc_lo
	global_store_b128 v[16:17], v[12:15], off offset:8
.LBB2_93:                               ;   in Loop: Header=BB2_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
	v_or_b32_e32 v12, 0, v11
	v_or_b32_e32 v13, v10, v0
	s_lshl_b64 s[12:13], s[12:13], 12
	s_lshl_b32 s16, s8, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s16, s16, 28
	v_dual_cndmask_b32 v17, v12, v11 :: v_dual_cndmask_b32 v12, v13, v10
	v_lshlrev_b64 v[10:11], 6, v[37:38]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v34, s12
	v_add_co_ci_u32_e32 v35, vcc_lo, s13, v35, vcc_lo
	s_and_b32 s16, s16, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v34, vcc_lo, v13, v10
	v_and_or_b32 v16, 0xffffff1f, v12, s16
	v_add_co_ci_u32_e32 v35, vcc_lo, v35, v11, vcc_lo
	s_clause 0x3
	global_store_b128 v[34:35], v[16:19], off
	global_store_b128 v[34:35], v[20:23], off offset:16
	global_store_b128 v[34:35], v[24:27], off offset:32
	global_store_b128 v[34:35], v[28:31], off offset:48
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB2_101
; %bb.94:                               ;   in Loop: Header=BB2_30 Depth=1
	s_clause 0x1
	global_load_b64 v[20:21], v38, s[2:3] offset:32 glc
	global_load_b64 v[10:11], v38, s[2:3] offset:40
	v_dual_mov_b32 v18, s10 :: v_dual_mov_b32 v19, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s16, v10
	v_readfirstlane_b32 s17, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[16:17], s[16:17], s[10:11]
	s_mul_i32 s13, s17, 24
	s_mul_hi_u32 s17, s16, 24
	s_mul_i32 s16, s16, 24
	s_add_i32 s17, s17, s13
	v_add_co_u32 v16, vcc_lo, v32, s16
	v_add_co_ci_u32_e32 v17, vcc_lo, s17, v33, vcc_lo
	s_mov_b32 s13, exec_lo
	global_store_b64 v[16:17], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v38, v[18:21], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[20:21]
	s_cbranch_execz .LBB2_97
; %bb.95:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s16, 0
.LBB2_96:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
	s_sleep 1
	global_store_b64 v[16:17], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v38, v[10:13], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB2_96
.LBB2_97:                               ; %Flow403
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b64 v[10:11], v38, s[2:3] offset:16
	s_mov_b32 s16, exec_lo
	s_mov_b32 s13, exec_lo
	v_mbcnt_lo_u32_b32 v12, s16, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v12
	s_cbranch_execz .LBB2_99
; %bb.98:                               ;   in Loop: Header=BB2_30 Depth=1
	s_bcnt1_i32_b32 s16, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v37, s16
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[10:11], v[37:38], off offset:8
.LBB2_99:                               ;   in Loop: Header=BB2_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[10:11], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB2_101
; %bb.100:                              ;   in Loop: Header=BB2_30 Depth=1
	global_load_b32 v37, v[10:11], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v37
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[37:38], off
	s_and_b32 m0, s13, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_101:                              ; %Flow404
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_add_i32 s14, s14, s1
	v_add_co_u32 v10, vcc_lo, v32, s15
	v_add_co_ci_u32_e32 v11, vcc_lo, s14, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v10, 20
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
.LBB2_102:                              ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v12, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_104
; %bb.103:                              ;   in Loop: Header=BB2_102 Depth=2
	global_load_b32 v12, v[10:11], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v12, 1, v12
.LBB2_104:                              ;   in Loop: Header=BB2_102 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v12
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_106
; %bb.105:                              ;   in Loop: Header=BB2_102 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_107
.LBB2_106:                              ;   in Loop: Header=BB2_102 Depth=2
	s_mov_b32 s1, -1
.LBB2_107:                              ; %Flow398
                                        ;   in Loop: Header=BB2_102 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_102
; %bb.108:                              ;   in Loop: Header=BB2_30 Depth=1
	global_load_b128 v[10:13], v[34:35], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_112
; %bb.109:                              ;   in Loop: Header=BB2_30 Depth=1
	s_clause 0x2
	global_load_b64 v[12:13], v38, s[2:3] offset:40
	global_load_b64 v[20:21], v38, s[2:3] offset:24 glc
	global_load_b64 v[18:19], v38, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v22, vcc_lo, v12, 1
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v22, s10
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[16:17]
	v_dual_cndmask_b32 v17, v17, v23 :: v_dual_cndmask_b32 v16, v16, v22
	v_and_b32_e32 v13, v17, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v12, v16, v12
	v_mul_hi_u32 v22, v12, 24
	v_mul_lo_u32 v12, v12, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, vcc_lo, v18, v12
	v_mov_b32_e32 v18, v20
	v_mul_lo_u32 v13, v13, 24
	v_add_nc_u32_e32 v13, v22, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, v19, v13, vcc_lo
	v_mov_b32_e32 v19, v21
	global_store_b64 v[12:13], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v38, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[18:19], v[20:21]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_112
; %bb.110:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_mov_b32 s0, 0
.LBB2_111:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB2_30 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[12:13], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[20:21], v38, v[16:19], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[18:19]
	v_dual_mov_b32 v18, v20 :: v_dual_mov_b32 v19, v21
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_111
.LBB2_112:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB2_30 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s6, s6, s8
	s_subb_u32 s7, s7, s9
	s_add_u32 s4, s4, s8
	s_addc_u32 s5, s5, s9
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc1 .LBB2_30
; %bb.113:                              ; %Flow443
	s_mov_b32 s0, 0
	s_branch .LBB2_115
.LBB2_114:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr10_vgpr11
.LBB2_115:                              ; %Flow458
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB2_144
; %bb.116:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v10, v36
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v10
	v_cmp_eq_u32_e64 s0, s0, v10
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_122
; %bb.117:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[13:14], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[11:12], v0, s[2:3] offset:40
	global_load_b64 v[15:16], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v11, v11, v13
	v_and_b32_e32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v11, 24
	v_mul_lo_u32 v12, v12, 24
	v_mul_lo_u32 v11, v11, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v17, v12
	s_waitcnt vmcnt(0)
	v_add_co_u32 v11, vcc_lo, v15, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v12, vcc_lo, v16, v12, vcc_lo
	global_load_b64 v[11:12], v[11:12], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[16:17], v0, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[16:17], v[13:14]
	s_cbranch_execz .LBB2_121
; %bb.118:                              ; %.preheader3.i.i.i13.preheader
	s_mov_b32 s5, 0
.LBB2_119:                              ; %.preheader3.i.i.i13
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v0, s[2:3] offset:40
	global_load_b64 v[18:19], v0, s[2:3]
	v_dual_mov_b32 v13, v16 :: v_dual_mov_b32 v14, v17
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, v11, v13
	v_and_b32_e32 v12, v12, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v11, 24, v[18:19]
	v_mov_b32_e32 v11, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, v12, 24, v[11:12]
	global_load_b64 v[11:12], v[15:16], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[16:17], v0, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[13:14]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_119
; %bb.120:                              ; %Flow455
	s_or_b32 exec_lo, exec_lo, s5
.LBB2_121:                              ; %Flow457
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_122:                              ; %.loopexit4.i.i.i8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v11, 0
	v_readfirstlane_b32 s4, v16
	v_readfirstlane_b32 s5, v17
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[18:19], v11, s[2:3] offset:40
	global_load_b128 v[12:15], v11, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v18
	v_readfirstlane_b32 s7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB2_124
; %bb.123:
	v_dual_mov_b32 v16, s10 :: v_dual_mov_b32 v17, v11
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v20, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v21, vcc_lo, s10, v13, vcc_lo
	v_dual_mov_b32 v18, 2 :: v_dual_mov_b32 v19, 1
	global_store_b128 v[20:21], v[16:19], off offset:8
.LBB2_124:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[16:17], 6, v[10:11]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v14, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v15, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v0, v16
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v8, 0xffffff1f, v8, 32
	v_add_co_ci_u32_e32 v15, vcc_lo, v10, v17, vcc_lo
	v_dual_mov_b32 v10, v11 :: v_dual_mov_b32 v19, s15
	v_dual_mov_b32 v18, s14 :: v_dual_mov_b32 v17, s13
	v_mov_b32_e32 v16, s12
	s_clause 0x3
	global_store_b128 v[14:15], v[8:11], off
	global_store_b128 v[14:15], v[16:19], off offset:16
	global_store_b128 v[14:15], v[16:19], off offset:32
	global_store_b128 v[14:15], v[16:19], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB2_132
; %bb.125:
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v19, s5
	v_mov_b32_e32 v18, s4
	s_clause 0x1
	global_load_b64 v[20:21], v0, s[2:3] offset:32 glc
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v8
	v_readfirstlane_b32 s11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v16, vcc_lo, v12, s10
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v13, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[16:17], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v0, v[18:21], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[10:11], v[20:21]
	s_cbranch_execz .LBB2_128
; %bb.126:                              ; %.preheader1.i.i.i11.preheader
	s_mov_b32 s10, 0
.LBB2_127:                              ; %.preheader1.i.i.i11
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v9, s5
	s_sleep 1
	global_store_b64 v[16:17], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v0, v[8:11], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_127
.LBB2_128:                              ; %Flow453
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v11, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v0, s10, 0
	global_load_b64 v[8:9], v11, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_130
; %bb.129:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v10, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[10:11], off offset:8
.LBB2_130:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB2_132
; %bb.131:
	global_load_b32 v8, v[8:9], off offset:24
	v_mov_b32_e32 v9, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v8
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[8:9], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_132:                              ; %Flow454
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v9, vcc_lo, s8, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB2_133:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v0, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_135
; %bb.134:                              ;   in Loop: Header=BB2_133 Depth=1
	global_load_b32 v0, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v0, 1, v0
.LBB2_135:                              ;   in Loop: Header=BB2_133 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v0
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_137
; %bb.136:                              ;   in Loop: Header=BB2_133 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_138
.LBB2_137:                              ;   in Loop: Header=BB2_133 Depth=1
	s_mov_b32 s1, -1
.LBB2_138:                              ; %Flow448
                                        ;   in Loop: Header=BB2_133 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_133
; %bb.139:
	global_load_b128 v[10:13], v[14:15], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_143
; %bb.140:
	v_mov_b32_e32 v0, 0
	s_clause 0x2
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	global_load_b64 v[16:17], v0, s[2:3] offset:24 glc
	global_load_b64 v[14:15], v0, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v18, vcc_lo, v8, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v18, s4
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v19 :: v_dual_cndmask_b32 v12, v12, v18
	v_and_b32_e32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v8, v12, v8
	v_mul_lo_u32 v9, v9, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v18, v8, 24
	v_mul_lo_u32 v8, v8, 24
	v_add_nc_u32_e32 v9, v18, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v14, v8
	v_mov_b32_e32 v14, v16
	v_add_co_ci_u32_e32 v9, vcc_lo, v15, v9, vcc_lo
	v_mov_b32_e32 v15, v17
	global_store_b64 v[8:9], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v0, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_143
; %bb.141:                              ; %.preheader.i.i.i10.preheader
	s_mov_b32 s0, 0
.LBB2_142:                              ; %.preheader.i.i.i10
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[8:9], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v0, v[12:15], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[14:15]
	v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_142
.LBB2_143:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_144:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v12, v36
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v12
	v_cmp_eq_u32_e64 s0, s0, v12
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_150
; %bb.145:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[15:16], v0, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v0, s[2:3] offset:40
	global_load_b64 v[13:14], v0, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v9, v9, v16
	v_and_b32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v9, 24
	v_mul_hi_u32 v17, v8, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v17, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v13, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v14, v9, vcc_lo
	global_load_b64 v[13:14], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[15:16]
	s_cbranch_execz .LBB2_149
; %bb.146:                              ; %.preheader3.i.i.i20.preheader
	s_mov_b32 s5, 0
.LBB2_147:                              ; %.preheader3.i.i.i20
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[13:14], v0, s[2:3] offset:40
	global_load_b64 v[17:18], v0, s[2:3]
	v_dual_mov_b32 v16, v9 :: v_dual_mov_b32 v15, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v13, v13, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[8:9], null, v13, 24, v[17:18]
	v_and_b32_e32 v17, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, v17, 24, v[9:10]
	v_mov_b32_e32 v9, v13
	global_load_b64 v[13:14], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v0, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[15:16]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_147
; %bb.148:                              ; %Flow391
	s_or_b32 exec_lo, exec_lo, s5
.LBB2_149:                              ; %Flow393
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_150:                              ; %.loopexit4.i.i.i14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v13, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[18:19], v13, s[2:3] offset:40
	global_load_b128 v[14:17], v13, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v18
	v_readfirstlane_b32 s7, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB2_152
; %bb.151:
	v_dual_mov_b32 v18, s10 :: v_dual_mov_b32 v19, v13
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v14, s9
	v_add_co_ci_u32_e32 v9, vcc_lo, s10, v15, vcc_lo
	v_dual_mov_b32 v20, 2 :: v_dual_mov_b32 v21, 1
	global_store_b128 v[8:9], v[18:21], off offset:8
.LBB2_152:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[8:9], 6, v[12:13]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v16, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v17, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v0, v8
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v10, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v17, vcc_lo, v12, v9, vcc_lo
	v_dual_mov_b32 v12, v1 :: v_dual_mov_b32 v21, s15
	v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v19, s13
	v_mov_b32_e32 v18, s12
	s_clause 0x3
	global_store_b128 v[16:17], v[10:13], off
	global_store_b128 v[16:17], v[18:21], off offset:16
	global_store_b128 v[16:17], v[18:21], off offset:32
	global_store_b128 v[16:17], v[18:21], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB2_160
; %bb.153:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v19, s5
	v_mov_b32_e32 v18, s4
	s_clause 0x1
	global_load_b64 v[20:21], v12, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v12, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v0, vcc_lo, v14, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v15, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[0:1], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v12, v[18:21], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[10:11], v[20:21]
	s_cbranch_execz .LBB2_156
; %bb.154:                              ; %.preheader1.i.i.i18.preheader
	s_mov_b32 s10, 0
.LBB2_155:                              ; %.preheader1.i.i.i18
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v9, s5
	s_sleep 1
	global_store_b64 v[0:1], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v12, v[8:11], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_155
.LBB2_156:                              ; %Flow389
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v9, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v8, s10, 0
	global_load_b64 v[0:1], v9, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB2_158
; %bb.157:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[8:9], off offset:8
.LBB2_158:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB2_160
; %bb.159:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_160:                              ; %Flow390
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v14, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_161:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v8, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_163
; %bb.162:                              ;   in Loop: Header=BB2_161 Depth=1
	global_load_b32 v8, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v8, 1, v8
.LBB2_163:                              ;   in Loop: Header=BB2_161 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v8
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_165
; %bb.164:                              ;   in Loop: Header=BB2_161 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_166
.LBB2_165:                              ;   in Loop: Header=BB2_161 Depth=1
	s_mov_b32 s1, -1
.LBB2_166:                              ; %Flow384
                                        ;   in Loop: Header=BB2_161 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_161
; %bb.167:
	global_load_b64 v[8:9], v[16:17], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_171
; %bb.168:
	v_mov_b32_e32 v14, 0
	s_clause 0x2
	global_load_b64 v[0:1], v14, s[2:3] offset:40
	global_load_b64 v[15:16], v14, s[2:3] offset:24 glc
	global_load_b64 v[12:13], v14, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v17, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v17, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
	v_and_b32_e32 v1, v11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v10, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v17, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v17, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v12, v0
	v_mov_b32_e32 v12, v15
	v_add_co_ci_u32_e32 v1, vcc_lo, v13, v1, vcc_lo
	v_mov_b32_e32 v13, v16
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v14, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_171
; %bb.169:                              ; %.preheader.i.i.i17.preheader
	s_mov_b32 s0, 0
.LBB2_170:                              ; %.preheader.i.i.i17
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v14, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[12:13]
	v_dual_mov_b32 v12, v15 :: v_dual_mov_b32 v13, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_170
.LBB2_171:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v0, v36
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_177
; %bb.172:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[12:13], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[10:11], v1, s[2:3] offset:40
	global_load_b64 v[14:15], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v10, v10, v12
	v_and_b32_e32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v16, v10, 24
	v_mul_lo_u32 v11, v11, 24
	v_mul_lo_u32 v10, v10, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v16, v11
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v14, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, v15, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[10:11], v1, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[10:11], v[12:13]
	s_cbranch_execz .LBB2_176
; %bb.173:                              ; %.preheader3.i.i.i27.preheader
	s_mov_b32 s5, 0
.LBB2_174:                              ; %.preheader3.i.i.i27
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[14:15], v1, s[2:3] offset:40
	global_load_b64 v[16:17], v1, s[2:3]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v14, v14, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[16:17]
	v_and_b32_e32 v16, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, v16, 24, v[11:12]
	v_mov_b32_e32 v11, v14
	global_load_b64 v[10:11], v[10:11], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[10:11], v1, v[10:13], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_174
; %bb.175:                              ; %Flow377
	s_or_b32 exec_lo, exec_lo, s5
.LBB2_176:                              ; %Flow379
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_177:                              ; %.loopexit4.i.i.i21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	v_readfirstlane_b32 s4, v10
	v_readfirstlane_b32 s5, v11
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[16:17], v1, s[2:3] offset:40
	global_load_b128 v[12:15], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v16
	v_readfirstlane_b32 s7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB2_179
; %bb.178:
	v_dual_mov_b32 v16, s10 :: v_dual_mov_b32 v17, v1
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v11, vcc_lo, s10, v13, vcc_lo
	v_dual_mov_b32 v18, 2 :: v_dual_mov_b32 v19, 1
	global_store_b128 v[10:11], v[16:19], off offset:8
.LBB2_179:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v14, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v15, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, v0
	s_mov_b32 s15, s12
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	v_and_or_b32 v8, 0xffffff1f, v8, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	v_dual_mov_b32 v10, v4 :: v_dual_mov_b32 v11, v5
	v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
	v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
	s_clause 0x3
	global_store_b128 v[0:1], v[8:11], off
	global_store_b128 v[0:1], v[14:17], off offset:16
	global_store_b128 v[0:1], v[14:17], off offset:32
	global_store_b128 v[0:1], v[14:17], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB2_187
; %bb.180:
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v15, s4
	v_mov_b32_e32 v16, s5
	s_clause 0x1
	global_load_b64 v[17:18], v14, s[2:3] offset:32 glc
	global_load_b64 v[4:5], v14, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v4, vcc_lo, v12, s10
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v13, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[4:5], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v14, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[10:11], v[17:18]
	s_cbranch_execz .LBB2_183
; %bb.181:                              ; %.preheader1.i.i.i25.preheader
	s_mov_b32 s10, 0
.LBB2_182:                              ; %.preheader1.i.i.i25
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v8, s4 :: v_dual_mov_b32 v9, s5
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v14, v[8:11], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_182
.LBB2_183:                              ; %Flow375
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v9, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v8, s10, 0
	global_load_b64 v[4:5], v9, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB2_185
; %bb.184:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[8:9], off offset:8
.LBB2_185:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB2_187
; %bb.186:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[4:5], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_187:                              ; %Flow376
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v4, vcc_lo, v12, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB2_188:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v8, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_190
; %bb.189:                              ;   in Loop: Header=BB2_188 Depth=1
	global_load_b32 v8, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v8, 1, v8
.LBB2_190:                              ;   in Loop: Header=BB2_188 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v8
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_192
; %bb.191:                              ;   in Loop: Header=BB2_188 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_193
.LBB2_192:                              ;   in Loop: Header=BB2_188 Depth=1
	s_mov_b32 s1, -1
.LBB2_193:                              ; %Flow370
                                        ;   in Loop: Header=BB2_188 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_188
; %bb.194:
	global_load_b64 v[4:5], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_198
; %bb.195:
	v_mov_b32_e32 v12, 0
	s_clause 0x2
	global_load_b64 v[0:1], v12, s[2:3] offset:40
	global_load_b64 v[13:14], v12, s[2:3] offset:24 glc
	global_load_b64 v[10:11], v12, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v15, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v15, s4
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v16 :: v_dual_cndmask_b32 v8, v8, v15
	v_and_b32_e32 v1, v9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v8, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v15, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v15, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v10, v0
	v_mov_b32_e32 v10, v13
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	v_mov_b32_e32 v11, v14
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v12, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[13:14]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_198
; %bb.196:                              ; %.preheader.i.i.i24.preheader
	s_mov_b32 s0, 0
.LBB2_197:                              ; %.preheader.i.i.i24
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v12, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[10:11]
	v_dual_mov_b32 v10, v13 :: v_dual_mov_b32 v11, v14
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_197
.LBB2_198:                              ; %__ockl_printf_append_args.exit28
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v0, v36
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_204
; %bb.199:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[10:11], v1, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[8:9], v1, s[2:3] offset:40
	global_load_b64 v[12:13], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v10
	v_and_b32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v14, v8, 24
	v_mul_lo_u32 v9, v9, 24
	v_mul_lo_u32 v8, v8, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v14, v9
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v12, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[12:13], v1, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[12:13], v[10:11]
	s_cbranch_execz .LBB2_203
; %bb.200:                              ; %.preheader3.i.i.i35.preheader
	s_mov_b32 s5, 0
.LBB2_201:                              ; %.preheader3.i.i.i35
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v1, s[2:3] offset:40
	global_load_b64 v[14:15], v1, s[2:3]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v8, v8, v10
	v_and_b32_e32 v9, v9, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v8, 24, v[14:15]
	v_mov_b32_e32 v8, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, v9, 24, v[8:9]
	global_load_b64 v[8:9], v[12:13], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[12:13], v1, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_201
; %bb.202:                              ; %Flow363
	s_or_b32 exec_lo, exec_lo, s5
.LBB2_203:                              ; %Flow365
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_204:                              ; %.loopexit4.i.i.i29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	v_readfirstlane_b32 s4, v12
	v_readfirstlane_b32 s5, v13
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[14:15], v1, s[2:3] offset:40
	global_load_b128 v[8:11], v1, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v14
	v_readfirstlane_b32 s7, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB2_206
; %bb.205:
	v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, v1
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v16, vcc_lo, v8, s9
	v_add_co_ci_u32_e32 v17, vcc_lo, s10, v9, vcc_lo
	v_dual_mov_b32 v14, 2 :: v_dual_mov_b32 v15, 1
	global_store_b128 v[16:17], v[12:15], off offset:8
.LBB2_206:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v10, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v10, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v4, 0xffffff1f, v4, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v11, v1, vcc_lo
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v13, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[4:7], off
	global_store_b128 v[0:1], v[10:13], off offset:16
	global_store_b128 v[0:1], v[10:13], off offset:32
	global_store_b128 v[0:1], v[10:13], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB2_214
; %bb.207:
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v13, s4
	v_mov_b32_e32 v14, s5
	s_clause 0x1
	global_load_b64 v[15:16], v12, s[2:3] offset:32 glc
	global_load_b64 v[4:5], v12, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v4
	v_readfirstlane_b32 s11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v10, vcc_lo, v8, s10
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v9, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[10:11], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v12, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[6:7], v[15:16]
	s_cbranch_execz .LBB2_210
; %bb.208:                              ; %.preheader1.i.i.i33.preheader
	s_mov_b32 s10, 0
.LBB2_209:                              ; %.preheader1.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
	s_sleep 1
	global_store_b64 v[10:11], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v12, v[4:7], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_209
.LBB2_210:                              ; %Flow361
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v7, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v6, s10, 0
	global_load_b64 v[4:5], v7, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v6
	s_cbranch_execz .LBB2_212
; %bb.211:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v6, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[6:7], off offset:8
.LBB2_212:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[6:7], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[6:7]
	s_cbranch_vccnz .LBB2_214
; %bb.213:
	global_load_b32 v4, v[4:5], off offset:24
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v4
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[6:7], v[4:5], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_214:                              ; %Flow362
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v4, vcc_lo, v8, s9
	v_add_co_ci_u32_e32 v5, vcc_lo, s8, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB2_215:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v6, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_217
; %bb.216:                              ;   in Loop: Header=BB2_215 Depth=1
	global_load_b32 v6, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v6, 1, v6
.LBB2_217:                              ;   in Loop: Header=BB2_215 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v6
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_219
; %bb.218:                              ;   in Loop: Header=BB2_215 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_220
.LBB2_219:                              ;   in Loop: Header=BB2_215 Depth=1
	s_mov_b32 s1, -1
.LBB2_220:                              ; %Flow356
                                        ;   in Loop: Header=BB2_215 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_215
; %bb.221:
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_225
; %bb.222:
	v_mov_b32_e32 v10, 0
	s_clause 0x2
	global_load_b64 v[6:7], v10, s[2:3] offset:40
	global_load_b64 v[11:12], v10, s[2:3] offset:24 glc
	global_load_b64 v[8:9], v10, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v13, vcc_lo, v6, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v13, s4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v14 :: v_dual_cndmask_b32 v4, v4, v13
	v_and_b32_e32 v7, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v6, v4, v6
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v6, 24
	v_mul_lo_u32 v6, v6, 24
	v_add_nc_u32_e32 v7, v13, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, v8, v6
	v_mov_b32_e32 v6, v11
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v7, vcc_lo
	v_mov_b32_e32 v7, v12
	global_store_b64 v[8:9], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v10, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_225
; %bb.223:                              ; %.preheader.i.i.i32.preheader
	s_mov_b32 s0, 0
.LBB2_224:                              ; %.preheader.i.i.i32
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[8:9], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v10, v[4:7], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[6:7]
	v_dual_mov_b32 v6, v11 :: v_dual_mov_b32 v7, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_224
.LBB2_225:                              ; %__ockl_printf_append_args.exit36
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v36
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v36
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_231
; %bb.226:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s4, exec_lo
	global_load_b64 v[10:11], v4, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[2:3] offset:40
	global_load_b64 v[7:8], v4, s[2:3]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v10
	v_and_b32_e32 v6, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v5, 24
	v_mul_lo_u32 v6, v6, 24
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v9, v6
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v7, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, v8, v6, vcc_lo
	global_load_b64 v[8:9], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v4, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[10:11]
	s_cbranch_execz .LBB2_230
; %bb.227:                              ; %.preheader3.i.i.i43.preheader
	s_mov_b32 s5, 0
.LBB2_228:                              ; %.preheader3.i.i.i43
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[2:3] offset:40
	global_load_b64 v[12:13], v4, s[2:3]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v10
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v5, 24, v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v8 :: v_dual_and_b32 v6, v6, v11
	v_mad_u64_u32 v[8:9], null, v6, 24, v[5:6]
	global_load_b64 v[8:9], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v4, v[8:11], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	s_or_b32 s5, vcc_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s5
	s_cbranch_execnz .LBB2_228
; %bb.229:                              ; %Flow349
	s_or_b32 exec_lo, exec_lo, s5
.LBB2_230:                              ; %Flow351
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB2_231:                              ; %.loopexit4.i.i.i37
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v37, 0
	v_readfirstlane_b32 s4, v8
	v_readfirstlane_b32 s5, v9
	s_mov_b32 s10, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v37, s[2:3] offset:40
	global_load_b128 v[4:7], v37, s[2:3]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[4:5], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s8, s6, 24
	s_mul_i32 s9, s6, 24
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB2_233
; %bb.232:
	v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, v37
	s_add_i32 s10, s8, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v13, vcc_lo, s10, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB2_233:
	s_or_b32 exec_lo, exec_lo, s11
	s_lshl_b64 s[6:7], s[6:7], 12
	s_mov_b32 s12, 0
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v6, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
	v_lshlrev_b64 v[6:7], 6, v[36:37]
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v8, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, v9, v7, vcc_lo
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13
	v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, s15
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s6, s0
	s_cbranch_execz .LBB2_241
; %bb.234:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
	v_mov_b32_e32 v10, s5
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v8, s[2:3] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[4:5]
	s_mul_i32 s7, s11, 24
	s_mul_hi_u32 s11, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s11, s11, s7
	v_add_co_u32 v6, vcc_lo, v4, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v5, vcc_lo
	s_mov_b32 s7, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB2_237
; %bb.235:                              ; %.preheader1.i.i.i41.preheader
	s_mov_b32 s10, 0
.LBB2_236:                              ; %.preheader1.i.i.i41
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_236
.LBB2_237:                              ; %Flow347
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v3, 0
	s_mov_b32 s10, exec_lo
	s_mov_b32 s7, exec_lo
	v_mbcnt_lo_u32_b32 v2, s10, 0
	global_load_b64 v[0:1], v3, s[2:3] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB2_239
; %bb.238:
	s_bcnt1_i32_b32 s10, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s10
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB2_239:
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB2_241
; %bb.240:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s7, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s7, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB2_241:                              ; %Flow348
	s_or_b32 exec_lo, exec_lo, s6
	s_add_i32 s8, s8, s1
	v_add_co_u32 v0, vcc_lo, v4, s9
	v_add_co_ci_u32_e32 v1, vcc_lo, s8, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB2_242:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB2_244
; %bb.243:                              ;   in Loop: Header=BB2_242 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB2_244:                              ;   in Loop: Header=BB2_242 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB2_246
; %bb.245:                              ;   in Loop: Header=BB2_242 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB2_247
.LBB2_246:                              ;   in Loop: Header=BB2_242 Depth=1
	s_mov_b32 s1, -1
.LBB2_247:                              ; %Flow342
                                        ;   in Loop: Header=BB2_242 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB2_242
; %bb.248:
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB2_252
; %bb.249:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[4:5], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_252
; %bb.250:                              ; %.preheader.i.i.i40.preheader
	s_mov_b32 s0, 0
.LBB2_251:                              ; %.preheader.i.i.i40
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_251
.LBB2_252:                              ; %__ockl_printf_append_args.exit44
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14print_positionP7vector3
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z14print_positionP7vector3, .Lfunc_end2-_Z14print_positionP7vector3
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10824
; NumSgprs: 20
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d,%.6lf,%.6lf,%.6lf\n"
	.size	.str, 22

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18integrate_positionP7vector3S0_d
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z18integrate_positionP7vector3S0_d.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7leapintP7vector3S0_d
    .private_segment_fixed_size: 0
    .sgpr_count:     74
    .sgpr_spill_count: 0
    .symbol:         _Z7leapintP7vector3S0_d.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         88
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14print_positionP7vector3
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z14print_positionP7vector3.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
