#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){

	__shared__ int tmp[2][128];
	unsigned int myblock = blockIdx.x;
	unsigned int tid = threadIdx.x;

	while(myblock < size_tmp){

		tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
        __syncthreads();

        int iout = 0;
        for (int d = 0; d < block_d; ++d){   //depth d
        	iout ^= 1;
        	int *tmp_out = tmp[iout];
        	int *tmp_in = tmp[iout ^ 1];
        	int t1 = tid - (1 << d);    //tid - 2^d
        	if (t1 >= 0) {              //tid > 2^d
        		tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
            }
            else {
            	tmp_out[tid] = tmp_in[tid];
            }
            __syncthreads();
        }

        out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
        aux[myblock] = tmp[iout][127]; //last element of each block for next scan
        myblock+=128;
	}
}

__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){

	__shared__ int tmp[128];
	unsigned int myblock = blockIdx.x;
	unsigned int tid = threadIdx.x;

	while(myblock < size_tmp){

		tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
        __syncthreads();

        if(myblock > 0){
        	tmp[tid] += d_aux2[myblock-1];
        	__syncthreads();
        }

        d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
        myblock+=128;
	}
}

int main()
{
	int *in;
	int *out;
	int *out_2;
    int *h_out;
	int *aux;
	int *aux_2;
	int num_size = 32000000;
	int size_tmp = (num_size + 127) / 128;
	int block_d = 7;   //depth of block, log2(128) = 7
	cudaMallocHost((void **) &in, sizeof(int)*num_size);
	cudaMallocHost((void **) &out, sizeof(int)*num_size);
    cudaMallocHost((void **) &h_out, sizeof(int)*num_size);
	cudaMallocHost((void **) &out_2, sizeof(int)*num_size);
	cudaMallocHost((void **) &aux, sizeof(int)*size_tmp);  //for checking itermediate values
	cudaMallocHost((void **) &aux_2, sizeof(int)*size_tmp);  //for checking the update itermediate values

	for (int i = 0; i < num_size; i++) {
		in[i] = i;
		out[i] = 0;
    }

    for (int i = 0; i < size_tmp; i++) {
		aux[i] = 0;
    }

    int *d_in;
    int *d_out;
    int *d_aux;
    // int dszp = (num_size)*sizeof(int);
    int dszp_aux = (size_tmp)*sizeof(int);
    cudaMalloc((void **) &d_in, sizeof(int)*num_size);
    cudaMalloc((void **) &d_out, sizeof(int)*num_size);
    cudaMalloc((void **) &d_aux, sizeof(int)*size_tmp);
    // cudaMemset(d_out, 0, dszp);
    cudaMemset(d_aux, 0, dszp_aux);

// Phase1: scan original data per block and store last element of each block for later scan

    cudaMemcpy(d_in, in, sizeof(int)*num_size, cudaMemcpyHostToDevice);
    gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
    cudaMemcpy(out, d_out, sizeof(int)*num_size, cudaMemcpyDeviceToHost);
    cudaMemcpy(aux, d_aux, sizeof(int)*size_tmp, cudaMemcpyDeviceToHost);
    cudaThreadSynchronize();

// Phase2: scan the last element of each block to accumulate the sum of each block

    aux_2[0] = aux[0];
    for(int i = 1; i < size_tmp; i++){
        aux_2[i] = aux[i] + aux_2[i-1];
    }

    int *d_aux2;
    cudaMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
    cudaMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, cudaMemcpyHostToDevice);

// Phase3: scan the last element of each block to accumulate the sum of each block
    int *d_out2;
    cudaMalloc((void **) &d_out2, sizeof(int)*num_size);
    gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
    cudaMemcpy(out_2, d_out2, sizeof(int)*num_size, cudaMemcpyDeviceToHost);

// check the GPU results
    printf("First 200 elements of the scan results:\n");
    for (int i = 0; i < 200; i++){
    	printf("%d\t", out_2[i]);
    	if (i % 10 == 0) printf("\n");
    }
    printf("\n");

    // printf("last 100 elements of the scan results:\n");
    // for (int i = num_size-101; i < num_size-1; i++){
    //     printf("%d\t", out_2[i]);
    //     if (i % 10 == 0) printf("\n");
    // }
    // printf("\n");

// verify via comparasion with cpu version
    int psum = 0;
    for (int i = 0; i < num_size; i++){
        psum += in[i];
        if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
    }
    printf("successfully scan!\n");

    cudaFree(d_in);
    cudaFree(d_out);
    cudaFree(d_out2);
    cudaFree(d_aux);
    cudaFree(d_aux2);


    cudaFreeHost(in);
    cudaFreeHost(out);
    cudaFreeHost(out_2);
    cudaFreeHost(h_out);
    cudaFreeHost(aux);
    cudaFreeHost(aux_2);

    return 0;
}

	.file	"tmpxft_00320f15_00000000-6_scan.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
	.type	_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii, @function
_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z24gpu_scan_sharemem_phaseIPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii, .-_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
	.globl	_Z24gpu_scan_sharemem_phaseIPiS_S_ii
	.type	_Z24gpu_scan_sharemem_phaseIPiS_S_ii, @function
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE3661:
	.size	_Z24gpu_scan_sharemem_phaseIPiS_S_ii, .-_Z24gpu_scan_sharemem_phaseIPiS_S_ii
	.globl	_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
	.type	_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i, @function
_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i, .-_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
	.globl	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
	.type	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, @function
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
	.cfi_endproc
.LFE3663:
	.size	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, .-_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"First 200 elements of the scan results:\n"
.LC1:
	.string	"%d\t"
.LC2:
	.string	"\n"
.LC3:
	.string	"mismatch at %d, was: %d, should be: %d\n"
.LC4:
	.string	"successfully scan!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$128000000, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$136, %rsp
	.cfi_def_cfa_offset 160
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMallocHost@PLT
	leaq	16(%rsp), %rdi
	movl	$128000000, %esi
	call	cudaMallocHost@PLT
	leaq	32(%rsp), %rdi
	movl	$128000000, %esi
	call	cudaMallocHost@PLT
	leaq	24(%rsp), %rdi
	movl	$128000000, %esi
	call	cudaMallocHost@PLT
	leaq	40(%rsp), %rdi
	movl	$1000000, %esi
	call	cudaMallocHost@PLT
	leaq	48(%rsp), %rdi
	movl	$1000000, %esi
	call	cudaMallocHost@PLT
	movq	8(%rsp), %rcx
	movq	16(%rsp), %rdx
	xorl	%eax, %eax
.L14:
	xorl	%esi, %esi
	movl	%eax, (%rcx,%rax,4)
	movl	%esi, (%rdx,%rax,4)
	incq	%rax
	cmpq	$32000000, %rax
	jne	.L14
	movq	40(%rsp), %rdi
	xorl	%eax, %eax
	movl	$250000, %ecx
	movl	$128000000, %esi
	rep stosl
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$128000000, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$1000000, %esi
	call	cudaMalloc@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	movl	$1000000, %edx
	call	cudaMemset@PLT
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movl	$128000000, %edx
	call	cudaMemcpy@PLT
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 116(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 108(%rsp)
	movq	%rdi, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$250000, %ecx
	movl	$7, %r8d
	movq	56(%rsp), %rdi
	call	_Z50__device_stub__Z24gpu_scan_sharemem_phaseIPiS_S_iiPiS_S_ii
.L15:
	movq	64(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$128000000, %edx
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rsi
	movq	40(%rsp), %rdi
	movl	$1000000, %edx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	40(%rsp), %rsi
	movq	48(%rsp), %rdx
	movl	(%rsi), %eax
	movl	%eax, (%rdx)
	movl	$4, %eax
.L16:
	movl	-4(%rdx,%rax), %ecx
	addl	(%rsi,%rax), %ecx
	movl	%ecx, (%rdx,%rax)
	addq	$4, %rax
	cmpq	$1000000, %rax
	jne	.L16
	leaq	80(%rsp), %rdi
	movl	$1000000, %esi
	call	cudaMalloc@PLT
	movq	48(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	$1, %ecx
	movl	$1000000, %edx
	call	cudaMemcpy@PLT
	leaq	88(%rsp), %rdi
	movl	$128000000, %esi
	call	cudaMalloc@PLT
	movl	$33554433, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movl	$1, 116(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 108(%rsp)
	movq	%rdi, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	80(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$250000, %ecx
	movq	64(%rsp), %rdi
	call	_Z51__device_stub__Z26gpu_scan_sharemem_phaseIIIPiS_S_iPiS_S_i
.L17:
	movq	88(%rsp), %rsi
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	xorl	%ebx, %ebx
	movl	$128000000, %edx
	leaq	.LC1(%rip), %rbp
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L19:
	movq	24(%rsp), %rax
	movq	%rbp, %rsi
	movl	$2, %edi
	movl	(%rax,%rbx,4), %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%ebx, %eax
	movl	$10, %ecx
	cltd
	idivl	%ecx
	testl	%edx, %edx
	jne	.L18
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L18:
	incq	%rbx
	cmpq	$200, %rbx
	jne	.L19
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rax
	xorl	%edx, %edx
	xorl	%r8d, %r8d
	movq	24(%rsp), %rsi
.L22:
	movl	(%rsi,%rdx,4), %ecx
	addl	(%rax,%rdx,4), %r8d
	cmpl	%r8d, %ecx
	je	.L20
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L13
.L20:
	incq	%rdx
	cmpq	$32000000, %rdx
	jne	.L22
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	16(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	24(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	32(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	48(%rsp), %rdi
	call	cudaFreeHost@PLT
	xorl	%eax, %eax
.L13:
	movq	120(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$136, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z26gpu_scan_sharemem_phaseIIIPiS_S_i"
.LC6:
	.string	"_Z24gpu_scan_sharemem_phaseIPiS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z24gpu_scan_sharemem_phaseIPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>

__global__ void gpu_scan_sharemem_phaseI(int *in, int *out, int *aux, int size_tmp, int block_d){

	__shared__ int tmp[2][128];
	unsigned int myblock = blockIdx.x;
	unsigned int tid = threadIdx.x;

	while(myblock < size_tmp){

		tmp[0][tid] = in[myblock*blockDim.x+threadIdx.x];
        __syncthreads();

        int iout = 0;
        for (int d = 0; d < block_d; ++d){   //depth d
        	iout ^= 1;
        	int *tmp_out = tmp[iout];
        	int *tmp_in = tmp[iout ^ 1];
        	int t1 = tid - (1 << d);    //tid - 2^d
        	if (t1 >= 0) {              //tid > 2^d
        		tmp_out[tid] = tmp_in[tid] + tmp_in[t1];
            }
            else {
            	tmp_out[tid] = tmp_in[tid];
            }
            __syncthreads();
        }

        out[myblock*blockDim.x+threadIdx.x] = tmp[iout][tid];
        aux[myblock] = tmp[iout][127]; //last element of each block for next scan
        myblock+=128;
	}
}

__global__ void gpu_scan_sharemem_phaseIII(int *d_out, int *d_out2, int *d_aux2, int size_tmp){

	__shared__ int tmp[128];
	unsigned int myblock = blockIdx.x;
	unsigned int tid = threadIdx.x;

	while(myblock < size_tmp){

		tmp[tid] = d_out[myblock*blockDim.x+threadIdx.x];
        __syncthreads();

        if(myblock > 0){
        	tmp[tid] += d_aux2[myblock-1];
        	__syncthreads();
        }

        d_out2[myblock*blockDim.x+threadIdx.x] = tmp[tid];
        myblock+=128;
	}
}

int main()
{
	int *in;
	int *out;
	int *out_2;
    int *h_out;
	int *aux;
	int *aux_2;
	int num_size = 32000000;
	int size_tmp = (num_size + 127) / 128;
	int block_d = 7;   //depth of block, log2(128) = 7
	hipHostMalloc((void **) &in, sizeof(int)*num_size, hipHostMallocDefault);
	hipHostMalloc((void **) &out, sizeof(int)*num_size, hipHostMallocDefault);
    hipHostMalloc((void **) &h_out, sizeof(int)*num_size, hipHostMallocDefault);
	hipHostMalloc((void **) &out_2, sizeof(int)*num_size, hipHostMallocDefault);
	hipHostMalloc((void **) &aux, sizeof(int)*size_tmp, hipHostMallocDefault);  //for checking itermediate values
	hipHostMalloc((void **) &aux_2, sizeof(int)*size_tmp, hipHostMallocDefault);  //for checking the update itermediate values

	for (int i = 0; i < num_size; i++) {
		in[i] = i;
		out[i] = 0;
    }

    for (int i = 0; i < size_tmp; i++) {
		aux[i] = 0;
    }

    int *d_in;
    int *d_out;
    int *d_aux;
    // int dszp = (num_size)*sizeof(int);
    int dszp_aux = (size_tmp)*sizeof(int);
    hipMalloc((void **) &d_in, sizeof(int)*num_size);
    hipMalloc((void **) &d_out, sizeof(int)*num_size);
    hipMalloc((void **) &d_aux, sizeof(int)*size_tmp);
    // cudaMemset(d_out, 0, dszp);
    hipMemset(d_aux, 0, dszp_aux);

// Phase1: scan original data per block and store last element of each block for later scan

    hipMemcpy(d_in, in, sizeof(int)*num_size, hipMemcpyHostToDevice);
    gpu_scan_sharemem_phaseI<<<128, 128>>>(d_in, d_out, d_aux, size_tmp, block_d);
    hipMemcpy(out, d_out, sizeof(int)*num_size, hipMemcpyDeviceToHost);
    hipMemcpy(aux, d_aux, sizeof(int)*size_tmp, hipMemcpyDeviceToHost);
    hipDeviceSynchronize();

// Phase2: scan the last element of each block to accumulate the sum of each block

    aux_2[0] = aux[0];
    for(int i = 1; i < size_tmp; i++){
        aux_2[i] = aux[i] + aux_2[i-1];
    }

    int *d_aux2;
    hipMalloc((void **) &d_aux2, sizeof(int)*size_tmp);
    hipMemcpy(d_aux2, aux_2, sizeof(int)*size_tmp, hipMemcpyHostToDevice);

// Phase3: scan the last element of each block to accumulate the sum of each block
    int *d_out2;
    hipMalloc((void **) &d_out2, sizeof(int)*num_size);
    gpu_scan_sharemem_phaseIII<<<128, 128>>>(d_out, d_out2, d_aux2, size_tmp);
    hipMemcpy(out_2, d_out2, sizeof(int)*num_size, hipMemcpyDeviceToHost);

// check the GPU results
    printf("First 200 elements of the scan results:\n");
    for (int i = 0; i < 200; i++){
    	printf("%d\t", out_2[i]);
    	if (i % 10 == 0) printf("\n");
    }
    printf("\n");

    // printf("last 100 elements of the scan results:\n");
    // for (int i = num_size-101; i < num_size-1; i++){
    //     printf("%d\t", out_2[i]);
    //     if (i % 10 == 0) printf("\n");
    // }
    // printf("\n");

// verify via comparasion with cpu version
    int psum = 0;
    for (int i = 0; i < num_size; i++){
        psum += in[i];
        if (psum != out_2[i]) {printf("mismatch at %d, was: %d, should be: %d\n", i, out_2[i], psum); return 1;}
    }
    printf("successfully scan!\n");

    hipFree(d_in);
    hipFree(d_out);
    hipFree(d_out2);
    hipFree(d_aux);
    hipFree(d_aux2);


    hipHostFree(in);
    hipHostFree(out);
    hipHostFree(out_2);
    hipHostFree(h_out);
    hipHostFree(aux);
    hipHostFree(aux_2);

    return 0;
}

	.text
	.file	"scan.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii # -- Begin function _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
	.type	_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii,@function
_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii: # @_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii, .Lfunc_end0-_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i # -- Begin function _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
	.type	_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i,@function
_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i: # @_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i, .Lfunc_end1-_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	48(%rsp), %rbx
	xorl	%r15d, %r15d
	movl	$128000000, %esi                # imm = 0x7A12000
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	72(%rsp), %r14
	movl	$128000000, %esi                # imm = 0x7A12000
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	80(%rsp), %rdi
	movl	$128000000, %esi                # imm = 0x7A12000
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	16(%rsp), %rdi
	movl	$128000000, %esi                # imm = 0x7A12000
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	8(%rsp), %rdi
	movl	$1000000, %esi                  # imm = 0xF4240
	xorl	%edx, %edx
	callq	hipHostMalloc
	leaq	40(%rsp), %rdi
	movl	$1000000, %esi                  # imm = 0xF4240
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	(%rbx), %rax
	movq	(%r14), %rcx
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movl	%r15d, (%rax,%r15,4)
	movl	$0, (%rcx,%r15,4)
	incq	%r15
	cmpq	$32000000, %r15                 # imm = 0x1E84800
	jne	.LBB2_1
# %bb.2:                                # %.preheader
	movabsq	$4294967424, %rbx               # imm = 0x100000080
	movq	8(%rsp), %rdi
	movl	$1000000, %edx                  # imm = 0xF4240
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	64(%rsp), %r14
	movl	$128000000, %esi                # imm = 0x7A12000
	movq	%r14, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$128000000, %esi                # imm = 0x7A12000
	callq	hipMalloc
	leaq	32(%rsp), %r15
	movl	$1000000, %esi                  # imm = 0xF4240
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$1000000, %edx                  # imm = 0xF4240
	xorl	%esi, %esi
	callq	hipMemset
	movq	(%r14), %rdi
	movq	48(%rsp), %rsi
	movl	$128000000, %edx                # imm = 0x7A12000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	64(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	$250000, %ecx                   # imm = 0x3D090
	movl	$7, %r8d
	callq	_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
.LBB2_4:
	movq	72(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$128000000, %edx                # imm = 0x7A12000
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	$1000000, %edx                  # imm = 0xF4240
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rax
	movl	(%rax), %ecx
	movq	40(%rsp), %rdx
	movl	%ecx, (%rdx)
	movl	$1, %esi
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	addl	(%rax,%rsi,4), %ecx
	movl	%ecx, (%rdx,%rsi,4)
	incq	%rsi
	cmpq	$250000, %rsi                   # imm = 0x3D090
	jne	.LBB2_5
# %bb.6:
	leaq	56(%rsp), %r14
	movl	$1000000, %esi                  # imm = 0xF4240
	movq	%r14, %rdi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	40(%rsp), %rsi
	movl	$1000000, %edx                  # imm = 0xF4240
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rdi
	movl	$128000000, %esi                # imm = 0x7A12000
	callq	hipMalloc
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	56(%rsp), %rdx
	movl	$250000, %ecx                   # imm = 0x3D090
	callq	_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
.LBB2_8:
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$128000000, %edx                # imm = 0x7A12000
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
.LBB2_9:                                # =>This Inner Loop Header: Depth=1
	movzbl	%r14b, %eax
	imull	$205, %eax, %eax
	shrl	$10, %eax
	andl	$-2, %eax
	leal	(%rax,%rax,4), %ebp
	movq	16(%rsp), %rax
	movl	(%rax,%r14,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	addb	%bl, %bpl
	jne	.LBB2_11
# %bb.10:                               #   in Loop: Header=BB2_9 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
.LBB2_11:                               #   in Loop: Header=BB2_9 Depth=1
	incq	%r14
	decb	%bl
	cmpq	$200, %r14
	jne	.LBB2_9
# %bb.12:
	movl	$10, %edi
	callq	putchar@PLT
	movq	48(%rsp), %rax
	xorl	%esi, %esi
	movq	16(%rsp), %rdi
	xorl	%ecx, %ecx
.LBB2_13:                               # =>This Inner Loop Header: Depth=1
	addl	(%rax,%rsi,4), %ecx
	movl	(%rdi,%rsi,4), %edx
	cmpl	%edx, %ecx
	jne	.LBB2_17
# %bb.14:                               #   in Loop: Header=BB2_13 Depth=1
	incq	%rsi
	cmpq	$32000000, %rsi                 # imm = 0x1E84800
	jne	.LBB2_13
# %bb.15:
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipHostFree
	movq	72(%rsp), %rdi
	callq	hipHostFree
	movq	16(%rsp), %rdi
	callq	hipHostFree
	movq	80(%rsp), %rdi
	callq	hipHostFree
	movq	8(%rsp), %rdi
	callq	hipHostFree
	movq	40(%rsp), %rdi
	callq	hipHostFree
	xorl	%eax, %eax
	jmp	.LBB2_16
.LBB2_17:
	movl	$.L.str.3, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %eax
.LBB2_16:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24gpu_scan_sharemem_phaseIPiS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24gpu_scan_sharemem_phaseIPiS_S_ii,@object # @_Z24gpu_scan_sharemem_phaseIPiS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z24gpu_scan_sharemem_phaseIPiS_S_ii
	.p2align	3, 0x0
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:
	.quad	_Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
	.size	_Z24gpu_scan_sharemem_phaseIPiS_S_ii, 8

	.type	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i,@object # @_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
	.globl	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
	.p2align	3, 0x0
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:
	.quad	_Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
	.size	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d\t"
	.size	.L.str.1, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"mismatch at %d, was: %d, should be: %d\n"
	.size	.L.str.3, 40

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z24gpu_scan_sharemem_phaseIPiS_S_ii"
	.size	.L__unnamed_1, 37

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z26gpu_scan_sharemem_phaseIIIPiS_S_i"
	.size	.L__unnamed_2, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"First 200 elements of the scan results:"
	.size	.Lstr, 40

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"successfully scan!"
	.size	.Lstr.1, 19

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__gpu_scan_sharemem_phaseIPiS_S_ii
	.addrsig_sym _Z41__device_stub__gpu_scan_sharemem_phaseIIIPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24gpu_scan_sharemem_phaseIPiS_S_ii
	.addrsig_sym _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24gpu_scan_sharemem_phaseIPiS_S_ii ; -- Begin function _Z24gpu_scan_sharemem_phaseIPiS_S_ii
	.globl	_Z24gpu_scan_sharemem_phaseIPiS_S_ii
	.p2align	8
	.type	_Z24gpu_scan_sharemem_phaseIPiS_S_ii,@function
_Z24gpu_scan_sharemem_phaseIPiS_S_ii:   ; @_Z24gpu_scan_sharemem_phaseIPiS_S_ii
; %bb.0:
	s_load_b64 s[8:9], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s15, s8
	s_cbranch_scc1 .LBB0_8
; %bb.1:                                ; %.lr.ph41
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_lshlrev_b32_e32 v3, 2, v0
	v_not_b32_e32 v4, v0
	v_mov_b32_e32 v5, 0
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s3, 0xffff
	s_cmp_gt_i32 s9, 0
	s_mov_b32 s3, 0
	s_cselect_b32 s11, -1, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	v_mad_u64_u32 v[1:2], null, s2, s10, v[0:1]
	v_mov_b32_e32 v2, v5
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_add_co_u32 v6, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v2, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s11
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_7
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s13, 0
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_lshl_add_u32 v7, s12, 9, v3
	s_lshl_b32 s15, -1, s13
	s_mov_b32 s14, exec_lo
	ds_load_b32 v6, v7
	v_cmpx_gt_i32_e64 s15, v4
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_lshl_add_u32 v7, s15, 2, v7
	ds_load_b32 v7, v7
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v7, v6
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_xor_b32 s12, s12, 1
	s_add_i32 s13, s13, 1
	v_lshl_add_u32 v7, s12, 9, v3
	s_cmp_eq_u32 s9, s13
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v7, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_4
.LBB0_7:                                ; %Flow59
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_lshl_b32 s12, s12, 9
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_lshl_add_u32 v6, v0, 2, s12
	v_mov_b32_e32 v7, s12
	s_lshl_b64 s[12:13], s[2:3], 2
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	ds_load_b32 v6, v6
	ds_load_b32 v7, v7 offset:508
	s_add_u32 s12, s0, s12
	s_addc_u32 s13, s1, s13
	s_addk_i32 s2, 0x80
	s_waitcnt lgkmcnt(1)
	global_store_b32 v[1:2], v6, off
	s_waitcnt lgkmcnt(0)
	global_store_b32 v5, v7, s[12:13]
	s_cmp_ge_u32 s2, s8
	s_cbranch_scc0 .LBB0_2
.LBB0_8:                                ; %._crit_edge42
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24gpu_scan_sharemem_phaseIPiS_S_ii
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24gpu_scan_sharemem_phaseIPiS_S_ii, .Lfunc_end0-_Z24gpu_scan_sharemem_phaseIPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 404
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i ; -- Begin function _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
	.globl	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
	.p2align	8
	.type	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i,@function
_Z26gpu_scan_sharemem_phaseIIIPiS_S_i:  ; @_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
; %bb.0:
	s_load_b32 s8, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_u32 s15, s8
	s_cbranch_scc1 .LBB1_5
; %bb.1:                                ; %.lr.ph
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_lshlrev_b32_e32 v0, 2, v0
	v_mov_b32_e32 v2, 0
	s_lshl_b32 s9, s2, 7
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_cmp_eq_u32 s15, 0
	v_add_co_u32 v5, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v5
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s2, s15, -1
	ds_load_b32 v6, v0
	s_lshl_b64 s[10:11], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s10, s0, s10
	s_addc_u32 s11, s1, s11
	global_load_b32 v5, v2, s[10:11]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	ds_store_b32 v0, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	ds_load_b32 v5, v0
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_add_nc_u32_e32 v1, s9, v1
	s_addk_i32 s15, 0x80
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s15, s8
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[3:4], v5, off
	s_cbranch_scc1 .LBB1_2
.LBB1_5:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
		.amdhsa_group_segment_fixed_size 512
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z26gpu_scan_sharemem_phaseIIIPiS_S_i, .Lfunc_end1-_Z26gpu_scan_sharemem_phaseIIIPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 512 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
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        .size:           2
        .value_kind:     hidden_group_size_y
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        .size:           2
        .value_kind:     hidden_group_size_z
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        .value_kind:     hidden_remainder_z
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        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24gpu_scan_sharemem_phaseIPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z24gpu_scan_sharemem_phaseIPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
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        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
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        .size:           4
        .value_kind:     hidden_block_count_y
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        .size:           4
        .value_kind:     hidden_block_count_z
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        .value_kind:     hidden_group_size_y
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        .value_kind:     hidden_grid_dims
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    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26gpu_scan_sharemem_phaseIIIPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26gpu_scan_sharemem_phaseIIIPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
