
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
using namespace std;

#define N 8


void cpuMatMul(float A[N][N], float B[N][N], float out[N][N]);

__global__ void gpuMatMul(float *A, float *B, float *out, int W);

int main(){


    float A[N][N];
    float B[N][N];
    float C[N][N];
    
    float* pA;
    float* pB;
    float* pC;

    pA = (float*)malloc(sizeof(float) *N* N);
    pB = (float*)malloc(sizeof(float) *N* N);
    pC = (float*)malloc(sizeof(float) *N* N);


    float *dA, *dB, *dC;


    // Allocate memory
    //a = (float*)malloc(sizeof(float) * N);
    //b = (float*)malloc(sizeof(float) * N);
    //out = (float*)malloc(sizeof(float) * N);
    
    //initialize the arrays
    for (int k = 0;k < N; k++) {
        for (int m = 0; m < N;m++) {
            A[m][k] = 2*(float)m + 3*(float)k;
            pA[m*N + k] = A[m][k];
            B[m][k] = 3*(float)m + 4*(float)k;
            pB[m*N + k] = B[m][k];
        }
    }

    cpuMatMul(A, B, C);





    cudaMalloc((void**)&dA, sizeof(float) * N * N); //void** is a pointer to a pointer of unspecified type
    cudaMalloc((void**)&dB, sizeof(float) * N * N);
    cudaMalloc((void**)&dC, sizeof(float) * N * N);


    cudaMemcpy(dA, pA, sizeof(float) * N * N, cudaMemcpyHostToDevice);
    cudaMemcpy(dB, pB, sizeof(float) * N * N, cudaMemcpyHostToDevice);


    //using 2d indexing of threads and blocks
    dim3 threads(4, 4);
    dim3 blocks(2, 2);

    //We must have threads * blocks = (N,N)
    gpuMatMul <<<blocks, threads >>>(dA, dB, dC, N);
    cudaMemcpy(pC, dC, sizeof(float) * N * N, cudaMemcpyDeviceToHost);


    cout << endl;
    for (int m = 0; m < N;m++) {
        for (int n = 0; n < N;n++) {
            cout << C[m][n] << " ";
        }
        cout << endl;
    }
    cout << endl;

    for (int m = 0; m < N;m++) {
        for (int n = 0; n < N;n++) {
            cout << pC[m*N+n] << " ";
        }
        cout << endl;
    }
    cout << endl;

    //free memory
    cudaFree(dA);cudaFree(dB);cudaFree(dC);
    free(pA);free(pB);free(pC);
    return 0;
    }

void cpuMatMul(float A[N][N], float B[N][N], float out[N][N]) {
    float sum = 0.0;
    for (int i = 0; i < N; i++) {
        for (int j = 0;j < N; j++) {
            sum = 0.0;
            for (int k = 0; k < N;k++) {
                sum = sum + A[i][k] * B[k][j];
            }
            out[i][j] = sum;
        }
    }
}

__global__ void gpuMatMul(float *A, float *B, float *out, int W) {
    //element(x, y) can be addressed as : x * width + y
    //eg for a 4x4 matrix, m(1,1) = 5 = 1*4+1

    int col = blockIdx.y * blockDim.y + threadIdx.y;
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    float sum = 0.0;
    if (row < W && col < W) {
        //prevents us from going out of bound in case we launch more threads/blocks
        //than necessary
        for (int k = 0;k < W;k++) {
            //sum = sum + A[row][k] + B[k][col]
            sum += A[row * W + k] * B[k * W + col];
        }
        out[row*W+col] = sum;
    }
}
	.file	"tmpxft_002e5316_00000000-6_CudaMatrixMultiplication.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4294:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4294:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z9cpuMatMulPA8_fS0_S0_
	.type	_Z9cpuMatMulPA8_fS0_S0_, @function
_Z9cpuMatMulPA8_fS0_S0_:
.LFB3636:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L4:
	leaq	(%rdi,%rax), %r11
	xorl	%ecx, %ecx
	leaq	(%rdx,%rax), %r10
.L8:
	leaq	(%rsi,%rcx), %r9
	xorl	%r8d, %r8d
	xorps	%xmm0, %xmm0
.L5:
	movss	(%r11,%r8,4), %xmm1
	mulss	(%r9), %xmm1
	incq	%r8
	addq	$32, %r9
	addss	%xmm1, %xmm0
	cmpq	$8, %r8
	jne	.L5
	movss	%xmm0, (%r10,%rcx)
	addq	$4, %rcx
	cmpq	$32, %rcx
	jne	.L8
	addq	$32, %rax
	cmpq	$256, %rax
	jne	.L4
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z9cpuMatMulPA8_fS0_S0_, .-_Z9cpuMatMulPA8_fS0_S0_
	.globl	_Z33__device_stub__Z9gpuMatMulPfS_S_iPfS_S_i
	.type	_Z33__device_stub__Z9gpuMatMulPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9gpuMatMulPfS_S_iPfS_S_i:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9gpuMatMulPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L11:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z33__device_stub__Z9gpuMatMulPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9gpuMatMulPfS_S_iPfS_S_i
	.globl	_Z9gpuMatMulPfS_S_i
	.type	_Z9gpuMatMulPfS_S_i, @function
_Z9gpuMatMulPfS_S_i:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9gpuMatMulPfS_S_iPfS_S_i
	.cfi_endproc
.LFE3662:
	.size	_Z9gpuMatMulPfS_S_i, .-_Z9gpuMatMulPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	" "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$256, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$840, %rsp
	.cfi_def_cfa_offset 896
	movq	%fs:40, %rax
	movq	%rax, 824(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$256, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$256, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movss	.LC1(%rip), %xmm3
	movss	.LC2(%rip), %xmm4
	xorl	%edx, %edx
	movq	%rax, %rbp
.L17:
	cvtsi2ssl	%edx, %xmm0
	leaq	0(,%rdx,4), %rax
	xorl	%ecx, %ecx
	movaps	%xmm0, %xmm5
	movaps	%xmm0, %xmm1
	mulss	%xmm3, %xmm5
	mulss	%xmm4, %xmm1
.L18:
	cvtsi2ssl	%ecx, %xmm0
	incl	%ecx
	leaq	56(%rsp), %rdi
	leaq	312(%rsp), %rsi
	movaps	%xmm0, %xmm2
	addss	%xmm0, %xmm2
	mulss	%xmm3, %xmm0
	addss	%xmm5, %xmm2
	addss	%xmm1, %xmm0
	movss	%xmm2, 56(%rsp,%rax)
	movss	%xmm2, 0(%r13,%rax)
	movss	%xmm0, 312(%rsp,%rax)
	movss	%xmm0, (%r12,%rax)
	addq	$32, %rax
	cmpl	$8, %ecx
	jne	.L18
	incq	%rdx
	cmpq	$8, %rdx
	jne	.L17
	leaq	568(%rsp), %rbx
	movq	%rbx, %rdx
	call	_Z9cpuMatMulPA8_fS0_S0_
	leaq	8(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$17179869188, %rdx
	movl	$1, %esi
	movabsq	$8589934594, %rdi
	movl	$1, 40(%rsp)
	movq	%rdx, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$8, %ecx
	movq	8(%rsp), %rdi
	call	_Z33__device_stub__Z9gpuMatMulPfS_S_iPfS_S_i
.L20:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$256, %edx
	movq	%rbp, %rdi
	leaq	824(%rsp), %r15
	call	cudaMemcpy@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
.L21:
	xorl	%r14d, %r14d
.L22:
	leaq	_ZSt4cout(%rip), %rdi
	cvtss2sd	(%rbx,%r14,4), %xmm0
	incq	%r14
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$1, %edx
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$8, %r14
	jne	.L22
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	addq	$32, %rbx
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpq	%r15, %rbx
	jne	.L21
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	xorl	%ebx, %ebx
	call	_ZNSolsEPFRSoS_E.isra.0
.L24:
	movq	%rbx, %r15
	xorl	%r14d, %r14d
	salq	$5, %r15
	addq	%rbp, %r15
.L25:
	leaq	_ZSt4cout(%rip), %rdi
	cvtss2sd	(%r15,%r14,4), %xmm0
	incq	%r14
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$1, %edx
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$8, %r14
	jne	.L25
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	incq	%rbx
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpq	$8, %rbx
	jne	.L24
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	824(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$840, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z9gpuMatMulPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9gpuMatMulPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1077936128
	.align 4
.LC2:
	.long	1082130432
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"

#include <iostream>
using namespace std;

#define N 8


void cpuMatMul(float A[N][N], float B[N][N], float out[N][N]);

__global__ void gpuMatMul(float *A, float *B, float *out, int W);

int main(){


    float A[N][N];
    float B[N][N];
    float C[N][N];
    
    float* pA;
    float* pB;
    float* pC;

    pA = (float*)malloc(sizeof(float) *N* N);
    pB = (float*)malloc(sizeof(float) *N* N);
    pC = (float*)malloc(sizeof(float) *N* N);


    float *dA, *dB, *dC;


    // Allocate memory
    //a = (float*)malloc(sizeof(float) * N);
    //b = (float*)malloc(sizeof(float) * N);
    //out = (float*)malloc(sizeof(float) * N);
    
    //initialize the arrays
    for (int k = 0;k < N; k++) {
        for (int m = 0; m < N;m++) {
            A[m][k] = 2*(float)m + 3*(float)k;
            pA[m*N + k] = A[m][k];
            B[m][k] = 3*(float)m + 4*(float)k;
            pB[m*N + k] = B[m][k];
        }
    }

    cpuMatMul(A, B, C);





    hipMalloc((void**)&dA, sizeof(float) * N * N); //void** is a pointer to a pointer of unspecified type
    hipMalloc((void**)&dB, sizeof(float) * N * N);
    hipMalloc((void**)&dC, sizeof(float) * N * N);


    hipMemcpy(dA, pA, sizeof(float) * N * N, hipMemcpyHostToDevice);
    hipMemcpy(dB, pB, sizeof(float) * N * N, hipMemcpyHostToDevice);


    //using 2d indexing of threads and blocks
    dim3 threads(4, 4);
    dim3 blocks(2, 2);

    //We must have threads * blocks = (N,N)
    gpuMatMul <<<blocks, threads >>>(dA, dB, dC, N);
    hipMemcpy(pC, dC, sizeof(float) * N * N, hipMemcpyDeviceToHost);


    cout << endl;
    for (int m = 0; m < N;m++) {
        for (int n = 0; n < N;n++) {
            cout << C[m][n] << " ";
        }
        cout << endl;
    }
    cout << endl;

    for (int m = 0; m < N;m++) {
        for (int n = 0; n < N;n++) {
            cout << pC[m*N+n] << " ";
        }
        cout << endl;
    }
    cout << endl;

    //free memory
    hipFree(dA);hipFree(dB);hipFree(dC);
    free(pA);free(pB);free(pC);
    return 0;
    }

void cpuMatMul(float A[N][N], float B[N][N], float out[N][N]) {
    float sum = 0.0;
    for (int i = 0; i < N; i++) {
        for (int j = 0;j < N; j++) {
            sum = 0.0;
            for (int k = 0; k < N;k++) {
                sum = sum + A[i][k] * B[k][j];
            }
            out[i][j] = sum;
        }
    }
}

__global__ void gpuMatMul(float *A, float *B, float *out, int W) {
    //element(x, y) can be addressed as : x * width + y
    //eg for a 4x4 matrix, m(1,1) = 5 = 1*4+1

    int col = blockIdx.y * blockDim.y + threadIdx.y;
    int row = blockIdx.x * blockDim.x + threadIdx.x;
    float sum = 0.0;
    if (row < W && col < W) {
        //prevents us from going out of bound in case we launch more threads/blocks
        //than necessary
        for (int k = 0;k < W;k++) {
            //sum = sum + A[row][k] + B[k][col]
            sum += A[row * W + k] * B[k * W + col];
        }
        out[row*W+col] = sum;
    }
}
	.text
	.file	"CudaMatrixMultiplication.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI0_0:
	.long	0x40400000                      # float 3
.LCPI0_1:
	.long	0x40800000                      # float 4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$808, %rsp                      # imm = 0x328
	.cfi_def_cfa_offset 864
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, %rbx
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, %r14
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, (%rsp)                    # 8-byte Spill
	xorl	%eax, %eax
	movss	.LCPI0_0(%rip), %xmm0           # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI0_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorl	%ecx, %ecx
.LBB0_1:                                # %.preheader55
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_2 Depth 2
	xorps	%xmm2, %xmm2
	cvtsi2ss	%ecx, %xmm2
	movaps	%xmm2, %xmm3
	mulss	%xmm0, %xmm3
	mulss	%xmm1, %xmm2
	movq	%rax, %rdx
	xorl	%esi, %esi
.LBB0_2:                                #   Parent Loop BB0_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm4, %xmm4
	cvtsi2ss	%esi, %xmm4
	movaps	%xmm4, %xmm5
	addss	%xmm4, %xmm5
	addss	%xmm3, %xmm5
	movss	%xmm5, 544(%rsp,%rdx)
	movss	%xmm5, (%rbx,%rdx)
	mulss	%xmm0, %xmm4
	addss	%xmm2, %xmm4
	movss	%xmm4, 288(%rsp,%rdx)
	movss	%xmm4, (%r14,%rdx)
	incq	%rsi
	addq	$32, %rdx
	cmpq	$8, %rsi
	jne	.LBB0_2
# %bb.3:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%rcx
	addq	$4, %rax
	cmpq	$8, %rcx
	jne	.LBB0_1
# %bb.4:                                # %.preheader19.i.preheader
	leaq	544(%rsp), %rax
	xorl	%ecx, %ecx
	leaq	288(%rsp), %rdx
.LBB0_5:                                # %.preheader19.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_6 Depth 2
                                        #       Child Loop BB0_7 Depth 3
	movq	%rcx, %rsi
	shlq	$5, %rsi
	addq	%rsp, %rsi
	addq	$32, %rsi
	movq	%rdx, %rdi
	xorl	%r8d, %r8d
.LBB0_6:                                # %.preheader.i
                                        #   Parent Loop BB0_5 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_7 Depth 3
	xorps	%xmm0, %xmm0
	xorl	%r9d, %r9d
.LBB0_7:                                #   Parent Loop BB0_5 Depth=1
                                        #     Parent Loop BB0_6 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rax,%r9), %xmm1               # xmm1 = mem[0],zero,zero,zero
	mulss	(%rdi,%r9,8), %xmm1
	addss	%xmm1, %xmm0
	addq	$4, %r9
	cmpq	$32, %r9
	jne	.LBB0_7
# %bb.8:                                #   in Loop: Header=BB0_6 Depth=2
	movss	%xmm0, (%rsi,%r8,4)
	incq	%r8
	addq	$4, %rdi
	cmpq	$8, %r8
	jne	.LBB0_6
# %bb.9:                                #   in Loop: Header=BB0_5 Depth=1
	incq	%rcx
	addq	$32, %rax
	cmpq	$8, %rcx
	jne	.LBB0_5
# %bb.10:                               # %_Z9cpuMatMulPA8_fS0_S0_.exit
	leaq	24(%rsp), %r12
	movl	$256, %esi                      # imm = 0x100
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %r13
	movl	$256, %esi                      # imm = 0x100
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$8589934594, %rdi               # imm = 0x200000002
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_12
# %bb.11:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$8, %ecx
	callq	_Z24__device_stub__gpuMatMulPfS_S_i
.LBB0_12:
	movq	8(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movq	(%rsp), %rdi                    # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %r12d
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	32(%rsp), %r13
	xorl	%ebp, %ebp
.LBB0_13:                               # %.preheader54
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_14 Depth 2
	xorl	%r15d, %r15d
.LBB0_14:                               #   Parent Loop BB0_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%r15,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	$8, %r15
	jne	.LBB0_14
# %bb.15:                               #   in Loop: Header=BB0_13 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%rbp
	addq	$32, %r13
	cmpq	$8, %rbp
	jne	.LBB0_13
# %bb.16:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %r12d
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%r13d, %r13d
	movq	(%rsp), %rbp                    # 8-byte Reload
.LBB0_17:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_18 Depth 2
	xorl	%r15d, %r15d
.LBB0_18:                               #   Parent Loop BB0_17 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbp,%r15,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	$8, %r15
	jne	.LBB0_18
# %bb.19:                               #   in Loop: Header=BB0_17 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incq	%r13
	addq	$32, %rbp
	cmpq	$8, %r13
	jne	.LBB0_17
# %bb.20:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	(%rsp), %rdi                    # 8-byte Reload
	callq	free
	xorl	%eax, %eax
	addq	$808, %rsp                      # imm = 0x328
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z9cpuMatMulPA8_fS0_S0_         # -- Begin function _Z9cpuMatMulPA8_fS0_S0_
	.type	_Z9cpuMatMulPA8_fS0_S0_,@function
_Z9cpuMatMulPA8_fS0_S0_:                # @_Z9cpuMatMulPA8_fS0_S0_
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
.LBB1_1:                                # %.preheader19
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
                                        #       Child Loop BB1_3 Depth 3
	movq	%rax, %rcx
	shlq	$5, %rcx
	addq	%rdx, %rcx
	movq	%rsi, %r8
	xorl	%r9d, %r9d
.LBB1_2:                                # %.preheader
                                        #   Parent Loop BB1_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_3 Depth 3
	xorps	%xmm0, %xmm0
	xorl	%r10d, %r10d
.LBB1_3:                                #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rdi,%r10), %xmm1              # xmm1 = mem[0],zero,zero,zero
	mulss	(%r8,%r10,8), %xmm1
	addss	%xmm1, %xmm0
	addq	$4, %r10
	cmpq	$32, %r10
	jne	.LBB1_3
# %bb.4:                                #   in Loop: Header=BB1_2 Depth=2
	movss	%xmm0, (%rcx,%r9,4)
	incq	%r9
	addq	$4, %r8
	cmpq	$8, %r9
	jne	.LBB1_2
# %bb.5:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rax
	addq	$32, %rdi
	cmpq	$8, %rax
	jne	.LBB1_1
# %bb.6:
	retq
.Lfunc_end1:
	.size	_Z9cpuMatMulPA8_fS0_S0_, .Lfunc_end1-_Z9cpuMatMulPA8_fS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__gpuMatMulPfS_S_i # -- Begin function _Z24__device_stub__gpuMatMulPfS_S_i
	.type	_Z24__device_stub__gpuMatMulPfS_S_i,@function
_Z24__device_stub__gpuMatMulPfS_S_i:    # @_Z24__device_stub__gpuMatMulPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9gpuMatMulPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__gpuMatMulPfS_S_i, .Lfunc_end2-_Z24__device_stub__gpuMatMulPfS_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9gpuMatMulPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9gpuMatMulPfS_S_i,@object     # @_Z9gpuMatMulPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z9gpuMatMulPfS_S_i
	.p2align	3, 0x0
_Z9gpuMatMulPfS_S_i:
	.quad	_Z24__device_stub__gpuMatMulPfS_S_i
	.size	_Z9gpuMatMulPfS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" "
	.size	.L.str, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9gpuMatMulPfS_S_i"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__gpuMatMulPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9gpuMatMulPfS_S_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9gpuMatMulPfS_S_i     ; -- Begin function _Z9gpuMatMulPfS_S_i
	.globl	_Z9gpuMatMulPfS_S_i
	.p2align	8
	.type	_Z9gpuMatMulPfS_S_i,@function
_Z9gpuMatMulPfS_S_i:                    ; @_Z9gpuMatMulPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_mov_b32 s3, exec_lo
	v_max_i32_e32 v2, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mul_lo_u32 v1, v1, s2
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v4, v0
	s_mov_b32 s3, s2
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s3, 0
	v_lshlrev_b64 v[7:8], 2, v[4:5]
	v_add_nc_u32_e32 v4, s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_load_b32 v5, v[2:3], off
	global_load_b32 v7, v[7:8], off
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v6, v5, v7
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v6, 0
.LBB0_5:                                ; %Flow46
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9gpuMatMulPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9gpuMatMulPfS_S_i, .Lfunc_end0-_Z9gpuMatMulPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9gpuMatMulPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9gpuMatMulPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
