#include "includes.h"
__global__ void kExtractPatches(float* images, float* patches, float* indices, float* width_offset, float* height_offset, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
const unsigned long idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned long numThreads = blockDim.x * gridDim.x;
const unsigned long total_pixels = patch_width * patch_height * num_colors * num_images;
unsigned long ind, pos;
unsigned long image_id, dest_row, dest_col, color, source_row, source_col;
for (unsigned long i = idx; i < total_pixels; i += numThreads) {
ind = i;
image_id = ind % num_images; ind /= num_images;
dest_col = ind % patch_width; ind /= patch_width;
dest_row = ind % patch_height; ind /= patch_height;
color = ind % num_colors;

source_row = int(height_offset[image_id]) + dest_row;
source_col = int(width_offset[image_id]) + dest_col;
pos = img_width * img_height * num_colors * (int)indices[image_id] + img_width * img_height * color + img_width * source_row + source_col;
patches[i] = images[pos];
}
}
	.file	"tmpxft_002b2d47_00000000-6_kExtractPatches.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
	.type	_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, @function
_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z15kExtractPatchesPfS_S_S_S_iiiiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii, .-_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
	.globl	_Z15kExtractPatchesPfS_S_S_S_iiiiii
	.type	_Z15kExtractPatchesPfS_S_S_S_iiiiii, @function
_Z15kExtractPatchesPfS_S_S_S_iiiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z15kExtractPatchesPfS_S_S_S_iiiiiiPfS_S_S_S_iiiiii
	.cfi_endproc
.LFE2033:
	.size	_Z15kExtractPatchesPfS_S_S_S_iiiiii, .-_Z15kExtractPatchesPfS_S_S_S_iiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15kExtractPatchesPfS_S_S_S_iiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15kExtractPatchesPfS_S_S_S_iiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kExtractPatches(float* images, float* patches, float* indices, float* width_offset, float* height_offset, int num_images, int img_width, int img_height, int patch_width, int patch_height, int num_colors) {
const unsigned long idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned long numThreads = blockDim.x * gridDim.x;
const unsigned long total_pixels = patch_width * patch_height * num_colors * num_images;
unsigned long ind, pos;
unsigned long image_id, dest_row, dest_col, color, source_row, source_col;
for (unsigned long i = idx; i < total_pixels; i += numThreads) {
ind = i;
image_id = ind % num_images; ind /= num_images;
dest_col = ind % patch_width; ind /= patch_width;
dest_row = ind % patch_height; ind /= patch_height;
color = ind % num_colors;

source_row = int(height_offset[image_id]) + dest_row;
source_col = int(width_offset[image_id]) + dest_col;
pos = img_width * img_height * num_colors * (int)indices[image_id] + img_width * img_height * color + img_width * source_row + source_col;
patches[i] = images[pos];
}
}
	.text
	.file	"kExtractPatches.hip"
	.globl	_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii # -- Begin function _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
	.type	_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii,@function
_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii: # @_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15kExtractPatchesPfS_S_S_S_iiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii, .Lfunc_end0-_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15kExtractPatchesPfS_S_S_S_iiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15kExtractPatchesPfS_S_S_S_iiiiii,@object # @_Z15kExtractPatchesPfS_S_S_S_iiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z15kExtractPatchesPfS_S_S_S_iiiiii
	.p2align	3, 0x0
_Z15kExtractPatchesPfS_S_S_S_iiiiii:
	.quad	_Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
	.size	_Z15kExtractPatchesPfS_S_S_S_iiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z15kExtractPatchesPfS_S_S_S_iiiiii"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__kExtractPatchesPfS_S_S_S_iiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15kExtractPatchesPfS_S_S_S_iiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15kExtractPatchesPfS_S_S_S_iiiiii ; -- Begin function _Z15kExtractPatchesPfS_S_S_S_iiiiii
	.globl	_Z15kExtractPatchesPfS_S_S_S_iiiiii
	.p2align	8
	.type	_Z15kExtractPatchesPfS_S_S_S_iiiiii,@function
_Z15kExtractPatchesPfS_S_S_S_iiiiii:    ; @_Z15kExtractPatchesPfS_S_S_S_iiiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x28
	s_load_b64 s[20:21], s[0:1], 0x38
	s_add_u32 s4, s0, 64
	s_addc_u32 s5, s1, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s14, s2, 0xffff
	s_mul_i32 s2, s19, s16
	v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
	s_mul_i32 s2, s2, s20
	v_mov_b32_e32 v2, 0
	s_mul_i32 s2, s2, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_u64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_mov_b32 s22, s16
	s_ashr_i32 s16, s16, 31
	v_cvt_f32_u32_e32 v0, s22
	v_cvt_f32_u32_e32 v3, s16
	s_ashr_i32 s23, s19, 31
	s_ashr_i32 s24, s20, 31
	v_cvt_f32_u32_e32 v4, s23
	v_cvt_f32_u32_e32 v5, s20
	v_fmac_f32_e32 v0, 0x4f800000, v3
	v_cvt_f32_u32_e32 v3, s19
	v_cvt_f32_u32_e32 v6, s24
	s_ashr_i32 s25, s21, 31
	s_mov_b32 s26, s21
	s_load_b32 s15, s[4:5], 0x0
	v_fmac_f32_e32 v3, 0x4f800000, v4
	v_rcp_f32_e32 v0, v0
	v_fmac_f32_e32 v5, 0x4f800000, v6
	v_cvt_f32_u32_e32 v4, s26
	v_cvt_f32_u32_e32 v6, s25
	v_rcp_f32_e32 v3, v3
	s_load_b256 s[4:11], s[0:1], 0x0
	v_rcp_f32_e32 v5, v5
	s_load_b64 s[12:13], s[0:1], 0x20
	v_fmac_f32_e32 v4, 0x4f800000, v6
	s_mul_i32 s18, s18, s17
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_mul_i32 s21, s18, s21
	s_ashr_i32 s27, s18, 31
	v_rcp_f32_e32 v4, v4
	v_mul_f32_e32 v7, 0x5f7ffffc, v3
	v_mul_f32_e32 v6, 0x2f800000, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, 0x5f7ffffc, v5
	s_ashr_i32 s28, s17, 31
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s14, s15, s14
	s_mov_b32 s15, 0
	v_trunc_f32_e32 v5, v6
	v_dual_mul_f32 v6, 0x2f800000, v7 :: v_dual_mul_f32 v9, 0x2f800000, v8
	v_mul_f32_e32 v10, 0x5f7ffffc, v4
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v11, v6
	v_trunc_f32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v6, 0x2f800000, v10
	v_fmac_f32_e32 v0, 0xcf800000, v5
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_fmac_f32_e32 v7, 0xcf800000, v11
	v_trunc_f32_e32 v12, v6
	v_fmac_f32_e32 v8, 0xcf800000, v9
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v10, 0xcf800000, v12
	v_cvt_u32_f32_e32 v5, v5
	v_cvt_u32_f32_e32 v6, v7
	v_cvt_u32_f32_e32 v7, v11
	v_cvt_u32_f32_e32 v8, v8
	v_cvt_u32_f32_e32 v9, v9
	v_cvt_u32_f32_e32 v10, v10
	v_cvt_u32_f32_e32 v11, v12
	s_lshl_b64 s[6:7], s[14:15], 2
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_sub_u32 s1, 0, s22
	s_subb_u32 s34, 0, s16
	v_mul_hi_u32 v12, s1, v0
	v_mul_lo_u32 v13, s1, v5
	s_sub_u32 s35, 0, s19
	s_subb_u32 s36, 0, s23
	v_mul_hi_u32 v16, s35, v6
	v_mul_lo_u32 v17, s35, v7
	s_sub_u32 s30, 0, s20
	v_mul_lo_u32 v15, s34, v0
	v_mul_hi_u32 v20, s30, v8
	v_mul_lo_u32 v21, s30, v9
	s_subb_u32 s33, 0, s24
	v_mul_lo_u32 v19, s36, v6
	s_sub_u32 s29, 0, s26
	v_add_nc_u32_e32 v12, v12, v13
	v_mul_lo_u32 v14, s1, v0
	v_mul_lo_u32 v23, s33, v8
	v_mul_hi_u32 v24, s29, v10
	v_mul_lo_u32 v25, s29, v11
	v_add_nc_u32_e32 v16, v16, v17
	v_mul_lo_u32 v18, s35, v6
	s_subb_u32 s31, 0, s25
	v_add_nc_u32_e32 v20, v20, v21
	v_add_nc_u32_e32 v12, v12, v15
	v_mul_lo_u32 v27, s31, v10
	v_mul_lo_u32 v22, s30, v8
	v_add_nc_u32_e32 v16, v16, v19
	v_mul_hi_u32 v13, v0, v14
	v_add_nc_u32_e32 v15, v24, v25
	v_add_nc_u32_e32 v19, v20, v23
	v_mul_lo_u32 v23, v0, v12
	v_mul_hi_u32 v20, v0, v12
	v_mul_hi_u32 v17, v6, v18
	v_mul_lo_u32 v32, v6, v16
	v_add_nc_u32_e32 v15, v15, v27
	v_mul_hi_u32 v27, v6, v16
	v_mul_hi_u32 v21, v8, v22
	v_mul_lo_u32 v35, v8, v19
	v_mul_hi_u32 v33, v7, v16
	v_mul_lo_u32 v34, v7, v16
	v_mul_hi_u32 v16, v8, v19
	v_add_co_u32 v13, vcc_lo, v13, v23
	v_mul_hi_u32 v28, v5, v14
	v_mul_lo_u32 v14, v5, v14
	v_mul_hi_u32 v36, v9, v19
	v_mul_lo_u32 v37, v9, v19
	v_mul_hi_u32 v19, v10, v15
	v_mul_lo_u32 v38, v10, v15
	v_mul_hi_u32 v39, v11, v15
	v_mul_lo_u32 v40, v11, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v20, vcc_lo
	v_add_co_u32 v20, vcc_lo, v17, v32
	v_mul_hi_u32 v31, v5, v12
	v_add_co_ci_u32_e32 v23, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v21, vcc_lo, v21, v35
	v_mul_lo_u32 v12, v5, v12
	v_add_co_ci_u32_e32 v27, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v13, vcc_lo, v13, v14
	v_add_co_ci_u32_e32 v13, vcc_lo, v15, v28, vcc_lo
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v31, vcc_lo
	v_mul_lo_u32 v26, s29, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, v13, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v14, vcc_lo
	v_mul_hi_u32 v29, v7, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, v0, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, v5, v13, vcc_lo
	v_mul_hi_u32 v24, v10, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v15, s1, v12
	v_mul_lo_u32 v16, s34, v12
	v_mul_lo_u32 v17, s1, v13
	v_mul_lo_u32 v14, s1, v12
	v_mul_lo_u32 v18, v7, v18
	v_mul_hi_u32 v30, v9, v22
	v_mul_lo_u32 v22, v9, v22
	v_add_co_u32 v24, s0, v24, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v32, s0, 0, v19, s0
	v_add_nc_u32_e32 v15, v15, v17
	v_mul_hi_u32 v19, v13, v14
	v_mul_lo_u32 v28, v13, v14
	v_mul_hi_u32 v14, v12, v14
	v_mul_hi_u32 v25, v11, v26
	v_add_nc_u32_e32 v15, v15, v16
	v_mul_lo_u32 v26, v11, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v16, v12, v15
	v_mul_hi_u32 v17, v12, v15
	v_mul_hi_u32 v31, v13, v15
	v_mul_lo_u32 v15, v13, v15
	v_add_co_u32 v14, vcc_lo, v14, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, v16, v19, vcc_lo
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v31, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v14, vcc_lo, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v19, vcc_lo, v13, v15, vcc_lo
	v_mul_hi_u32 v28, v1, v14
	v_mad_u64_u32 v[12:13], null, v2, v14, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, v1, v19, 0
	v_mad_u64_u32 v[16:17], null, v2, v19, 0
	v_add_co_u32 v14, vcc_lo, v28, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v12, vcc_lo, v14, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, v15, v13, vcc_lo
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v17, vcc_lo
	v_add_co_u32 v14, vcc_lo, v20, v18
	v_add_co_u32 v15, s0, v12, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v16, s0, 0, v13, s0
	v_add_co_ci_u32_e32 v14, vcc_lo, v23, v29, vcc_lo
	v_mul_lo_u32 v18, s16, v15
	v_mad_u64_u32 v[12:13], null, s22, v15, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v23, s22, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v19, vcc_lo, v15, 1
	v_add_co_u32 v14, s0, v14, v34
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v16, vcc_lo
	v_add_co_ci_u32_e64 v17, vcc_lo, 0, v17, s0
	v_add3_u32 v13, v13, v23, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v6, v14
	v_add_co_ci_u32_e32 v17, vcc_lo, v7, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v34, v2, v13
	v_sub_co_u32 v12, vcc_lo, v1, v12
	v_mul_hi_u32 v23, s35, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v33, s35, v17
	v_subrev_co_ci_u32_e64 v34, s0, s16, v34, vcc_lo
	v_sub_co_ci_u32_e32 v13, vcc_lo, v2, v13, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v12
	v_sub_co_u32 v41, s0, v12, s22
	v_add_nc_u32_e32 v23, v23, v33
	v_mul_lo_u32 v31, s36, v14
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v33, vcc_lo, 0, v34, s0
	v_cmp_le_u32_e32 vcc_lo, s22, v41
	v_mul_lo_u32 v18, s35, v14
	v_add_co_u32 v20, s1, v15, 2
	v_add_nc_u32_e32 v23, v23, v31
	v_cndmask_b32_e64 v34, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s16, v13
	v_cmp_le_u32_e64 s0, s16, v33
	v_add_co_ci_u32_e64 v28, s1, 0, v16, s1
	v_mul_hi_u32 v35, v17, v18
	v_cndmask_b32_e64 v31, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s16, v13
	v_cndmask_b32_e64 v13, 0, -1, s0
	v_mul_lo_u32 v38, v17, v18
	v_mul_hi_u32 v18, v14, v18
	v_mul_lo_u32 v41, v14, v23
	v_cndmask_b32_e32 v12, v31, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s16, v33
	v_mul_hi_u32 v31, v14, v23
	v_mul_hi_u32 v42, v17, v23
	v_mul_lo_u32 v23, v17, v23
	v_cmp_ne_u32_e64 s1, 0, v12
	v_cndmask_b32_e32 v13, v13, v34, vcc_lo
	v_add_co_u32 v18, vcc_lo, v18, v41
	v_add_co_ci_u32_e32 v31, vcc_lo, 0, v31, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s0, 0, v13
	v_add_co_u32 v12, vcc_lo, v18, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v29, v28, s0
	v_cndmask_b32_e64 v12, v19, v20, s0
	v_cndmask_b32_e64 v28, v16, v13, s1
	v_add_co_ci_u32_e32 v13, vcc_lo, v31, v35, vcc_lo
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v20, v15, v12, s1
	v_add_co_u32 v12, vcc_lo, v13, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v16, vcc_lo
	v_mul_lo_u32 v29, v28, s22
	v_add_co_u32 v16, vcc_lo, v14, v12
	v_mul_lo_u32 v23, v20, s16
	v_mad_u64_u32 v[12:13], null, v20, s22, 0
	v_add_co_ci_u32_e32 v31, vcc_lo, v17, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[14:15], null, v28, v16, 0
	v_mul_hi_u32 v33, v20, v16
	v_mad_u64_u32 v[16:17], null, v20, v31, 0
	v_add3_u32 v13, v13, v23, v29
	v_sub_co_u32 v12, vcc_lo, v1, v12
	v_mad_u64_u32 v[18:19], null, v28, v31, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v13, vcc_lo, v2, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, v33, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v16, v14
	v_add_co_ci_u32_e32 v23, vcc_lo, v17, v15, vcc_lo
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v17, vcc_lo, s11, v13, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v13, vcc_lo
	v_add_co_u32 v21, vcc_lo, v21, v22
	v_add_co_ci_u32_e32 v21, vcc_lo, v27, v30, vcc_lo
	v_add_co_u32 v18, s0, v23, v18
	global_load_b32 v23, v[14:15], off
	global_load_b32 v27, v[16:17], off
	global_load_b32 v29, v[12:13], off
	v_add_co_ci_u32_e64 v19, s0, 0, v19, s0
	v_mul_lo_u32 v14, s23, v18
	v_mad_u64_u32 v[12:13], null, s19, v18, 0
	v_add_co_u32 v16, s0, v21, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v21, s19, v19
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v36, vcc_lo
	v_add_co_u32 v15, vcc_lo, v18, 1
	v_add_co_ci_u32_e32 v31, vcc_lo, 0, v19, vcc_lo
	v_add_co_ci_u32_e64 v22, vcc_lo, 0, v22, s0
	v_add3_u32 v13, v13, v21, v14
	v_add_co_u32 v16, vcc_lo, v8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v22, vcc_lo, v9, v22, vcc_lo
	v_sub_nc_u32_e32 v35, v28, v13
	v_sub_co_u32 v12, vcc_lo, v20, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v21, s30, v16
	v_mul_lo_u32 v34, s30, v22
	s_delay_alu instid0(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v35, s0, s23, v35, vcc_lo
	v_sub_co_ci_u32_e32 v13, vcc_lo, v28, v13, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s19, v12
	v_sub_co_u32 v38, s0, v12, s19
	v_add_nc_u32_e32 v21, v21, v34
	v_mul_lo_u32 v33, s33, v16
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v34, vcc_lo, 0, v35, s0
	v_cmp_le_u32_e32 vcc_lo, s19, v38
	v_mul_lo_u32 v14, s30, v16
	v_add_co_u32 v17, s1, v18, 2
	v_add_nc_u32_e32 v21, v21, v33
	v_cndmask_b32_e64 v35, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s23, v13
	v_cmp_le_u32_e64 s0, s23, v34
	v_add_co_ci_u32_e64 v30, s1, 0, v19, s1
	v_mul_hi_u32 v36, v22, v14
	v_cndmask_b32_e64 v33, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s23, v13
	v_cndmask_b32_e64 v13, 0, -1, s0
	v_mul_lo_u32 v37, v22, v14
	v_mul_hi_u32 v14, v16, v14
	v_mul_lo_u32 v38, v16, v21
	v_cndmask_b32_e32 v12, v33, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s23, v34
	v_mul_hi_u32 v33, v16, v21
	v_mul_hi_u32 v41, v22, v21
	v_mul_lo_u32 v21, v22, v21
	v_cmp_ne_u32_e64 s1, 0, v12
	v_cndmask_b32_e32 v13, v13, v35, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v38
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s0, 0, v13
	v_add_co_u32 v12, vcc_lo, v14, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v31, v30, s0
	v_cndmask_b32_e64 v12, v15, v17, s0
	v_cndmask_b32_e64 v30, v19, v13, s1
	v_add_co_ci_u32_e32 v13, vcc_lo, v33, v36, vcc_lo
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v31, v18, v12, s1
	v_add_co_u32 v12, vcc_lo, v13, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	v_mul_lo_u32 v33, v30, s19
	v_add_co_u32 v16, vcc_lo, v16, v12
	v_mul_lo_u32 v21, v31, s23
	v_mad_u64_u32 v[12:13], null, v31, s19, 0
	v_add_co_ci_u32_e32 v22, vcc_lo, v22, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[14:15], null, v30, v16, 0
	v_mul_hi_u32 v34, v31, v16
	v_mad_u64_u32 v[16:17], null, v31, v22, 0
	v_add3_u32 v13, v13, v21, v33
	v_sub_co_u32 v12, vcc_lo, v20, v12
	v_mad_u64_u32 v[18:19], null, v30, v22, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_co_ci_u32_e32 v13, vcc_lo, v28, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, v34, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v14, vcc_lo, v16, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, v17, v15, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v16, vcc_lo, v24, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v17, s0, v14, v18
	v_add_co_ci_u32_e64 v18, s0, 0, v15, s0
	v_add_co_ci_u32_e32 v16, vcc_lo, v32, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v20, s24, v17
	v_mad_u64_u32 v[14:15], null, s20, v17, 0
	v_mul_lo_u32 v24, s20, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v39, vcc_lo
	v_add_co_u32 v21, vcc_lo, v17, 1
	v_add_co_u32 v16, s0, v16, v40
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e64 v19, vcc_lo, 0, v19, s0
	v_add3_u32 v15, v15, v24, v20
	v_add_co_u32 v16, vcc_lo, v10, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v19, vcc_lo, v11, v19, vcc_lo
	v_sub_nc_u32_e32 v33, v30, v15
	v_sub_co_u32 v14, vcc_lo, v31, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_hi_u32 v24, s29, v16
	v_mul_lo_u32 v32, s29, v19
	s_delay_alu instid0(VALU_DEP_4)
	v_subrev_co_ci_u32_e64 v33, s0, s24, v33, vcc_lo
	v_sub_co_ci_u32_e32 v15, vcc_lo, v30, v15, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v14
	v_sub_co_u32 v36, s0, v14, s20
	v_add_nc_u32_e32 v24, v24, v32
	v_mul_lo_u32 v28, s31, v16
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v32, vcc_lo, 0, v33, s0
	v_cmp_le_u32_e32 vcc_lo, s20, v36
	v_mul_lo_u32 v20, s29, v16
	v_add_co_u32 v22, s1, v17, 2
	v_add_nc_u32_e32 v24, v24, v28
	v_cndmask_b32_e64 v33, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s24, v15
	v_cmp_le_u32_e64 s0, s24, v32
	v_add_co_ci_u32_e64 v25, s1, 0, v18, s1
	v_mul_hi_u32 v34, v19, v20
	v_cndmask_b32_e64 v28, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s24, v15
	v_cndmask_b32_e64 v15, 0, -1, s0
	v_mul_lo_u32 v35, v19, v20
	v_mul_hi_u32 v20, v16, v20
	v_mul_lo_u32 v36, v16, v24
	v_cndmask_b32_e32 v14, v28, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s24, v32
	v_mul_hi_u32 v28, v16, v24
	v_mul_hi_u32 v37, v19, v24
	v_mul_lo_u32 v24, v19, v24
	v_cmp_ne_u32_e64 s1, 0, v14
	v_cndmask_b32_e32 v15, v15, v33, vcc_lo
	v_add_co_u32 v20, vcc_lo, v20, v36
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e64 s0, 0, v15
	v_add_co_u32 v14, vcc_lo, v20, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v21, v22, s0
	v_cndmask_b32_e64 v14, v26, v25, s0
	v_cndmask_b32_e64 v22, v17, v15, s1
	v_add_co_ci_u32_e32 v15, vcc_lo, v28, v34, vcc_lo
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, v18, v14, s1
	v_add_co_u32 v18, vcc_lo, v15, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	v_mul_lo_u32 v26, v22, s24
	v_add_co_u32 v18, vcc_lo, v16, v18
	v_mad_u64_u32 v[14:15], null, v22, s20, 0
	v_mul_lo_u32 v24, v25, s20
	v_add_co_ci_u32_e32 v28, vcc_lo, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, v25, v18, 0
	v_mul_hi_u32 v32, v22, v18
	v_mad_u64_u32 v[18:19], null, v22, v28, 0
	v_add3_u32 v15, v15, v26, v24
	v_sub_co_u32 v24, vcc_lo, v31, v14
	v_mad_u64_u32 v[20:21], null, v25, v28, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_co_ci_u32_e32 v26, vcc_lo, v30, v15, vcc_lo
	v_add_co_u32 v14, vcc_lo, v32, v18
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v14, vcc_lo, v14, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, v15, v17, vcc_lo
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v21, vcc_lo
	v_add_co_u32 v16, vcc_lo, v14, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v15, vcc_lo
	v_mul_lo_u32 v18, s25, v16
	v_mad_u64_u32 v[14:15], null, s26, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v16, s26, v17
	v_sub_co_u32 v14, vcc_lo, v22, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v16, v18
	v_sub_nc_u32_e32 v16, v25, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v16, s0, s25, v16, vcc_lo
	v_sub_co_ci_u32_e32 v15, vcc_lo, v25, v15, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s26, v14
	v_sub_co_u32 v17, s0, v14, s26
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v19, vcc_lo, 0, v16, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s26, v17
	v_cmp_le_u32_e64 s1, s25, v19
	v_cndmask_b32_e64 v20, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s25, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, 0, -1, s1
	v_cndmask_b32_e64 v21, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v16, vcc_lo, s25, v16, s0
	v_sub_co_u32 v22, vcc_lo, v17, s26
	v_cmp_eq_u32_e64 s0, s25, v15
	v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s25, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v18, v21, v18, s0
	v_cndmask_b32_e32 v20, v25, v20, vcc_lo
	v_cmp_ne_u32_e64 s0, 0, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v20
	v_dual_cndmask_b32 v16, v19, v16 :: v_dual_cndmask_b32 v17, v17, v22
	v_cndmask_b32_e64 v16, v15, v16, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v14, v17, s0
	v_mul_lo_u32 v16, v16, s18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v17, s27
	v_mad_u64_u32 v[14:15], null, v17, s18, 0
	v_add3_u32 v15, v15, v18, v16
	s_waitcnt vmcnt(0)
	v_cvt_i32_f32_e32 v16, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_mul_lo_u32 v16, s21, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v20, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v15, vcc_lo
	v_cvt_i32_f32_e32 v15, v23
	v_cvt_i32_f32_e32 v14, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v17, 31, v15
	v_add_co_u32 v22, vcc_lo, v24, v15
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v23, vcc_lo, v26, v17, vcc_lo
	v_mul_lo_u32 v24, v22, s28
	v_mad_u64_u32 v[18:19], null, v22, s17, 0
	v_ashrrev_i32_e32 v17, 31, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v22, v23, s17
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v19, v19, v24, v22
	v_add_co_u32 v20, vcc_lo, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v21, vcc_lo, v21, v17, vcc_lo
	v_lshlrev_b64 v[16:17], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v20, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, v21, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v16, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, v17, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v12, v14
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v15, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	global_load_b32 v12, v[12:13], off
	v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
	s_or_b32 s15, vcc_lo, s15
	s_waitcnt vmcnt(0)
	global_store_b32 v[3:4], v12, off
	v_add_co_u32 v3, s0, v3, s6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow86
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15kExtractPatchesPfS_S_S_S_iiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 43
		.amdhsa_next_free_sgpr 37
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15kExtractPatchesPfS_S_S_S_iiiiii, .Lfunc_end0-_Z15kExtractPatchesPfS_S_S_S_iiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3588
; NumSgprs: 39
; NumVgprs: 43
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 39
; NumVGPRsForWavesPerEU: 43
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15kExtractPatchesPfS_S_S_S_iiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     39
    .sgpr_spill_count: 0
    .symbol:         _Z15kExtractPatchesPfS_S_S_S_iiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     43
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
