#include <stdio.h>

__global__ void cycfold_multichannel(const float2 *pol0, const float2 *pol1,
        const double *phase, const double *step,
        const int fftlen, const int overlap, const int nbin, const int nlag,
        const int num_fft,
        float2 *xx, float2 *yy, float2 *xy, unsigned *hits) {

	// Lag is specified with threadIdx.x and blockIdx.x since there could be
	// more lags than allowed threads.
    const int ilaga = threadIdx.x;
    const int nlaga = blockDim.x;
    const int ilagb = blockIdx.x;
    const int ilag = ilagb*nlaga + ilaga;
    // Phase bin is blockIdx.y
    const int ibin = blockIdx.y;
    // Filterbank channel is blockIdx.z
    const int ichan = blockIdx.z;


    const int num_valid_samples = fftlen - overlap;

	// accumulators for the various lag terms
    float2 foldxxlag = make_float2(0,0);
    float2 foldyylag = make_float2(0,0);
    float2 foldxylag = make_float2(0,0);
    __shared__ int samp0;
    __shared__ int samp1;
    // Number of hits for this phase/lag bin
    int foldcount = 0;


    for (int ifft=0; ifft < num_fft; ifft++){
    	//Pointers to the first valid sample for this channel and fft
        const float2 *ptr0 = pol0 +ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
        const float2 *ptr1 = pol1 + ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
        // Fold info
        const double bin0 = phase[ifft];
        const double bins_per_sample = step[ifft];   // bins/sample
        const double samples_per_bin = 1.0/bins_per_sample; // samples/bin
        const int num_turns = ((double)num_valid_samples*bins_per_sample)/(double)nbin + 2;

        // Loop over number of pulse periods in data block
        for (int iturn=0; iturn<num_turns; iturn++) {

            // Determine range of samples needed for this bin, turn
        	if(ilaga == 0){
				samp0 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin)+0.5;
				samp1 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin+1)+0.5;
	            // Range checks
	            if (samp0<0) { samp0=0; }
	            if (samp1<0) { samp1=0; }
	            if (samp0>num_valid_samples) { samp0=num_valid_samples; }
	            if (samp1>num_valid_samples) { samp1=num_valid_samples; }
        	}
        	__syncthreads();


            // Read in and add samples
            int lag_index;
            for (int isamp=samp0; isamp<samp1; isamp++) {
                lag_index = isamp + ilag -nlag/2;
                if((lag_index >= 0) && (lag_index < num_valid_samples)){
                    float2 p0 = ptr0[isamp];
                    float2 p0lag = ptr0[lag_index];
                    float2 p1 = ptr1[isamp];
                    float2 p1lag = ptr1[lag_index];
                    // <Pol0 x Pol0_lag*>
                    foldxxlag.x += p0.x*p0lag.x + p0.y*p0lag.y;
                    foldxxlag.y += p0.y*p0lag.x - p0.x*p0lag.y;

                    // <Pol1 x Pol1_lag*>
                    foldyylag.x += p1.x*p1lag.x + p1.y*p1lag.y;
                    foldyylag.y += p1.y*p1lag.x - p1.x*p1lag.y;

                    // <Pol0 x Pol1_lag*>
                    foldxylag.x += p0.x*p1lag.x + p0.y*p1lag.y;
                    foldxylag.y += p0.y*p1lag.x - p0.x*p1lag.y;
                    foldcount++;
                }
            }
        }

    }
    xx[ichan*nlag*nbin+nlag*ibin+ilag] = foldxxlag;
    yy[ichan*nlag*nbin+nlag*ibin+ilag] = foldyylag;
    xy[ichan*nlag*nbin+nlag*ibin+ilag] = foldxylag;
    hits[ichan*nlag*nbin+nlag*ibin+ilag] = foldcount;
}

	.file	"tmpxft_0031f586_00000000-6_multichannel_shared.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
	.type	_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, @function
_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	296(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	304(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	312(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	88(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	320(%rsp), %rax
	movl	%r8d, 44(%rsp)
	movl	%r9d, 40(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	288(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	$1, 104(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	88(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 288
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, .-_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
	.globl	_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
	.type	_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, @function
_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z72__device_stub__Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_PjPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
	.cfi_endproc
.LFE2052:
	.size	_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj, .-_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20cycfold_multichannelPK6float2S1_PKdS3_iiiiiPS_S4_S4_Pj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

__global__ void cycfold_multichannel(const float2 *pol0, const float2 *pol1,
        const double *phase, const double *step,
        const int fftlen, const int overlap, const int nbin, const int nlag,
        const int num_fft,
        float2 *xx, float2 *yy, float2 *xy, unsigned *hits) {

	// Lag is specified with threadIdx.x and blockIdx.x since there could be
	// more lags than allowed threads.
    const int ilaga = threadIdx.x;
    const int nlaga = blockDim.x;
    const int ilagb = blockIdx.x;
    const int ilag = ilagb*nlaga + ilaga;
    // Phase bin is blockIdx.y
    const int ibin = blockIdx.y;
    // Filterbank channel is blockIdx.z
    const int ichan = blockIdx.z;


    const int num_valid_samples = fftlen - overlap;

	// accumulators for the various lag terms
    float2 foldxxlag = make_float2(0,0);
    float2 foldyylag = make_float2(0,0);
    float2 foldxylag = make_float2(0,0);
    __shared__ int samp0;
    __shared__ int samp1;
    // Number of hits for this phase/lag bin
    int foldcount = 0;


    for (int ifft=0; ifft < num_fft; ifft++){
    	//Pointers to the first valid sample for this channel and fft
        const float2 *ptr0 = pol0 +ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
        const float2 *ptr1 = pol1 + ichan*fftlen*num_fft + ifft*fftlen + overlap/2;
        // Fold info
        const double bin0 = phase[ifft];
        const double bins_per_sample = step[ifft];   // bins/sample
        const double samples_per_bin = 1.0/bins_per_sample; // samples/bin
        const int num_turns = ((double)num_valid_samples*bins_per_sample)/(double)nbin + 2;

        // Loop over number of pulse periods in data block
        for (int iturn=0; iturn<num_turns; iturn++) {

            // Determine range of samples needed for this bin, turn
        	if(ilaga == 0){
				samp0 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin)+0.5;
				samp1 = samples_per_bin*((double)ibin-bin0+(double)iturn*nbin+1)+0.5;
	            // Range checks
	            if (samp0<0) { samp0=0; }
	            if (samp1<0) { samp1=0; }
	            if (samp0>num_valid_samples) { samp0=num_valid_samples; }
	            if (samp1>num_valid_samples) { samp1=num_valid_samples; }
        	}
        	__syncthreads();


            // Read in and add samples
            int lag_index;
            for (int isamp=samp0; isamp<samp1; isamp++) {
                lag_index = isamp + ilag -nlag/2;
                if((lag_index >= 0) && (lag_index < num_valid_samples)){
                    float2 p0 = ptr0[isamp];
                    float2 p0lag = ptr0[lag_index];
                    float2 p1 = ptr1[isamp];
                    float2 p1lag = ptr1[lag_index];
                    // <Pol0 x Pol0_lag*>
                    foldxxlag.x += p0.x*p0lag.x + p0.y*p0lag.y;
                    foldxxlag.y += p0.y*p0lag.x - p0.x*p0lag.y;

                    // <Pol1 x Pol1_lag*>
                    foldyylag.x += p1.x*p1lag.x + p1.y*p1lag.y;
                    foldyylag.y += p1.y*p1lag.x - p1.x*p1lag.y;

                    // <Pol0 x Pol1_lag*>
                    foldxylag.x += p0.x*p1lag.x + p0.y*p1lag.y;
                    foldxylag.y += p0.y*p1lag.x - p0.x*p1lag.y;
                    foldcount++;
                }
            }
        }

    }
    xx[ichan*nlag*nbin+nlag*ibin+ilag] = foldxxlag;
    yy[ichan*nlag*nbin+nlag*ibin+ilag] = foldyylag;
    xy[ichan*nlag*nbin+nlag*ibin+ilag] = foldxylag;
    hits[ichan*nlag*nbin+nlag*ibin+ilag] = foldcount;
}

	.text
	.file	"multichannel_shared.hip"
	.globl	_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj # -- Begin function _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.type	_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@function
_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj: # @_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, .Lfunc_end0-_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@object # @_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.section	.rodata,"a",@progbits
	.globl	_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.p2align	3, 0x0
_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj:
	.quad	_Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.size	_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj"
	.size	.L__unnamed_1, 77

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj ; -- Begin function _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.globl	_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
	.p2align	8
	.type	_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj,@function
_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj: ; @_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x64
	s_load_b32 s23, s[0:1], 0x30
	s_load_b128 s[16:19], s[0:1], 0x20
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_cmp_lt_i32 s23, 1
	s_mul_i32 s22, s13, s2
	s_mov_b32 s13, 0
	s_cbranch_scc1 .LBB0_20
; %bb.1:                                ; %.lr.ph179
	s_load_b256 s[4:11], s[0:1], 0x0
	s_sub_i32 s24, s16, s17
	s_mul_i32 s3, s15, s16
	v_cvt_f64_i32_e32 v[7:8], s18
	s_mul_i32 s20, s3, s23
	v_cvt_f64_i32_e32 v[9:10], s14
	v_cvt_f64_i32_e32 v[11:12], s24
	s_ashr_i32 s21, s20, 31
	v_cmp_eq_u32_e64 s2, 0, v0
	s_lshl_b64 s[28:29], s[20:21], 3
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v23, 0
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v1, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v5, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s3, s4, s28
	s_addc_u32 s12, s5, s29
	s_lshr_b32 s20, s17, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s17, s17, s20
	s_mov_b32 s20, s13
	s_ashr_i32 s26, s17, 1
	s_ashr_i32 s27, s26, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[30:31], s[26:27], 3
	s_add_u32 s17, s3, s30
	s_addc_u32 s25, s12, s31
	s_add_u32 s3, s6, s28
	s_addc_u32 s12, s7, s29
	s_add_u32 s26, s3, s30
	s_addc_u32 s27, s12, s31
	s_lshr_b32 s3, s19, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s19, s3
	s_ashr_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s3, s22, s3
	s_add_u32 s12, s30, s28
	s_addc_u32 s21, s31, s29
	s_or_b32 s12, s12, 4
	v_add_nc_u32_e32 v24, s3, v0
	s_add_u32 s28, s4, s12
	s_addc_u32 s29, s5, s21
	s_add_u32 s30, s6, s12
	s_addc_u32 s31, s7, s21
	s_mov_b32 s12, s13
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_15 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[12:13], 3
	s_add_u32 s6, s10, s4
	s_addc_u32 s7, s11, s5
	s_load_b64 s[6:7], s[6:7], 0x0
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[15:16], s[6:7], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[17:18], null, v[7:8], v[7:8], v[15:16]
	v_rcp_f64_e32 v[19:20], v[17:18]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
	v_div_scale_f64 v[21:22], vcc_lo, v[15:16], v[7:8], v[15:16]
	v_mul_f64 v[25:26], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[17:18], v[25:26], v[21:22]
	v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[15:16], v[17:18], v[7:8], v[15:16]
	v_add_f64 v[15:16], v[15:16], 2.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v25, v[15:16]
	v_cmp_gt_i32_e32 vcc_lo, 1, v25
	s_cbranch_vccnz .LBB0_19
; %bb.3:                                ; %.lr.ph161
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_div_scale_f64 v[15:16], null, s[6:7], s[6:7], 1.0
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, s[6:7], 1.0
	s_mul_i32 s34, s12, s16
	s_ashr_i32 s21, s20, 31
	s_ashr_i32 s35, s34, 31
	s_lshl_b64 s[36:37], s[20:21], 3
	s_lshl_b64 s[34:35], s[34:35], 3
	s_mov_b32 s38, 0
	s_add_u32 s21, s17, s34
	s_addc_u32 s33, s25, s35
	s_add_u32 s34, s26, s34
	s_addc_u32 s35, s27, s35
	s_add_u32 s4, s8, s4
	s_addc_u32 s5, s9, s5
	s_load_b64 s[4:5], s[4:5], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[17:18], v[9:10], -s[4:5]
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	v_div_fixup_f64 v[15:16], v[15:16], s[6:7], 1.0
	s_add_u32 s6, s28, s36
	s_addc_u32 s7, s29, s37
	s_add_u32 s36, s30, s36
	s_addc_u32 s37, s31, s37
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_15 Depth 3
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_13
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[7:8], v[19:20], v[17:18]
	v_add_f64 v[26:27], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[15:16], v[21:22], 0.5
	v_fma_f64 v[26:27], v[15:16], v[26:27], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v21, v[21:22]
	v_cvt_i32_f64_e32 v22, v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e32 vcc_lo, -1, v21
	v_readfirstlane_b32 s4, v22
	ds_store_b64 v14, v[21:22]
	s_cbranch_vccnz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v21, 0
	ds_store_b32 v14, v14
.LBB0_7:                                ;   in Loop: Header=BB0_4 Depth=2
	s_cmp_gt_i32 s4, -1
	s_cbranch_scc1 .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s4, 0
	ds_store_b32 v14, v14 offset:4
.LBB0_9:                                ;   in Loop: Header=BB0_4 Depth=2
	v_cmp_ge_i32_e32 vcc_lo, s24, v21
	s_cbranch_vccnz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v13, s24
	ds_store_b32 v14, v13
.LBB0_11:                               ;   in Loop: Header=BB0_4 Depth=2
	s_cmp_le_i32 s4, s24
	s_cbranch_scc1 .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=2
	v_mov_b32_e32 v13, s24
	ds_store_b32 v14, v13 offset:4
.LBB0_13:                               ; %Flow250
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b64 v[21:22], v14
	s_waitcnt lgkmcnt(0)
	v_readfirstlane_b32 s4, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_i32_e32 vcc_lo, s4, v22
	s_cbranch_vccnz .LBB0_18
; %bb.14:                               ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_ashr_i32 s5, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[40:41], s[4:5], 3
	s_add_u32 s5, s6, s40
	s_addc_u32 s39, s7, s41
	s_add_u32 s40, s36, s40
	s_addc_u32 s41, s37, s41
.LBB0_15:                               ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v13, s4, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v13
	v_cmp_gt_i32_e64 s3, s24, v13
	s_and_b32 s42, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s42
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=3
	v_lshlrev_b64 v[26:27], 3, v[13:14]
	s_add_u32 s42, s5, -4
	s_addc_u32 s43, s39, -1
	s_add_u32 s44, s40, -4
	s_addc_u32 s45, s41, -1
	v_add_nc_u32_e32 v23, 1, v23
	v_add_co_u32 v28, vcc_lo, s21, v26
	v_add_co_ci_u32_e32 v29, vcc_lo, s33, v27, vcc_lo
	v_add_co_u32 v26, vcc_lo, s34, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s35, v27, vcc_lo
	global_load_b64 v[28:29], v[28:29], off
	global_load_b64 v[26:27], v[26:27], off
	s_load_b64 s[42:43], s[42:43], 0x0
	s_load_b64 s[44:45], s[44:45], 0x0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f32_e32 v21, s42, v29
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v13, s43, v29 :: v_dual_mul_f32 v30, s44, v27
	v_mul_f32_e32 v31, s43, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fma_f32 v21, s43, v28, -v21
	v_mul_f32_e32 v29, s45, v27
	v_mul_f32_e32 v27, s42, v27
	v_fmac_f32_e32 v13, s42, v28
	v_fma_f32 v28, s45, v26, -v30
	v_dual_add_f32 v2, v2, v21 :: v_dual_fmac_f32 v29, s44, v26
	v_fmac_f32_e32 v31, s42, v26
	v_fma_f32 v26, s43, v26, -v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_add_f32 v1, v1, v13 :: v_dual_add_f32 v4, v4, v28
	v_add_f32_e32 v3, v3, v29
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_add_f32 v5, v5, v31 :: v_dual_add_f32 v6, v6, v26
.LBB0_17:                               ;   in Loop: Header=BB0_15 Depth=3
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s4, s4, 1
	s_add_u32 s5, s5, 8
	v_cmp_ge_i32_e32 vcc_lo, s4, v22
	s_addc_u32 s39, s39, 0
	s_add_u32 s40, s40, 8
	s_addc_u32 s41, s41, 0
	s_cbranch_vccz .LBB0_15
.LBB0_18:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_4 Depth=2
	v_add_f64 v[19:20], v[19:20], 1.0
	s_add_i32 s38, s38, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s38, v25
	s_cbranch_vccz .LBB0_4
.LBB0_19:                               ; %._crit_edge162
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s12, s12, 1
	s_add_i32 s20, s20, s16
	s_cmp_eq_u32 s12, s23
	s_cbranch_scc0 .LBB0_2
	s_branch .LBB0_21
.LBB0_20:
	v_dual_mov_b32 v23, 0 :: v_dual_mov_b32 v4, 0
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, 0
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v5, 0
.LBB0_21:                               ; %Flow254
	s_mul_i32 s8, s15, s18
	s_load_b256 s[0:7], s[0:1], 0x38
	s_add_i32 s8, s8, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s19
	v_add3_u32 v7, s8, s22, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[9:10], 3, v[7:8]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s0, v9
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v10, vcc_lo
	v_add_co_u32 v13, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	global_store_b64 v[11:12], v[1:2], off
	global_store_b64 v[13:14], v[3:4], off
	global_store_b64 v[9:10], v[5:6], off
	global_store_b32 v[7:8], v23, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
		.amdhsa_group_segment_fixed_size 8
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 32
		.amdhsa_next_free_sgpr 46
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj, .Lfunc_end0-_Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1344
; NumSgprs: 48
; NumVgprs: 32
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 48
; NumVGPRsForWavesPerEU: 32
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj
    .private_segment_fixed_size: 0
    .sgpr_count:     48
    .sgpr_spill_count: 0
    .symbol:         _Z20cycfold_multichannelPK15HIP_vector_typeIfLj2EES2_PKdS4_iiiiiPS0_S5_S5_Pj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     32
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
