/**
 * block loading rho calculation. should be much faster
 * system('nvcc -ptx citydist_rho4.cu')
 * iA is multiple of chunk (16)
*/

#include <cuda_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC (1+6*2)
// #define NC (9)
#define CHUNK 16
#define SINGLE_INF (3.402E+38)

/** Main entry point.
 * Works out where the current thread should read/write to global memory
 * and calls doIterations to do the actual work.
 * Step through one B at a time
 */
__global__ void eucldist_sorted_rho_exp(float const *A, float *D, int const nA, int const nneigh, int const nC, float const dc){
    int iA = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK;    
    int tx = threadIdx.x;
    __shared__ float sA[NC][CHUNK];
    __shared__ float rho1[NTHREADS][CHUNK];
    
    // cache A
    if (tx < nC){ //use tx as iC
        for (int i=0; i<CHUNK; ++i){
            if (iA+i < nA){
                sA[tx][i] = A[tx + (iA+i)*nC];
            }else{
                sA[tx][i] = SINGLE_INF;
            }   
        }
    }
    for (int i=0; i<CHUNK; ++i) rho1[tx][i] = 0.0f;
    __syncthreads();
    
    // fill in the shared memory A
    float dc2 = dc*dc;
    int iB_min = MAX(iA - nneigh, 0);
    int iB_max = MIN(iA + nneigh + CHUNK - 1, nA-1);
    int iB = iB_min + tx; //MAX(tx, iB_min); // tx is index for B    
    while (iB <= iB_max){
        float dist[CHUNK];
        // calculate distance to B        
        for (int i=0; i<CHUNK; ++i) dist[i] = 0.0f;
        for (int iC=0; iC<nC; ++iC){
            float Btemp = A[iC + iB*nC];
            for (int i=0; i<CHUNK; ++i){
                float temp = Btemp - sA[iC][i];
                dist[i] += temp * temp;
            }            
        }          
        for (int i=0; i<CHUNK; ++i){            
            int dab = ABS(iA+i-iB);
            if (dab<=nneigh){
                if (iA+i < nA && iA+i != iB){
                    rho1[tx][i] += expf(-1*dist[i]/dc2);
                }
            }
        }
        iB += blockDim.x;
    } // while
    
    // final count
    __syncthreads();    
    // if (tx < CHUNK) D[iA+tx] = rho1[tx];
    if (tx < CHUNK){
        float sum = 0.0f;
        for (int tx1=0; tx1<blockDim.x; ++tx1)
            sum += rho1[tx1][tx];
        if (iA+tx<nA) D[iA+tx] = sum;
    }
} // func
	.file	"tmpxft_00377dc3_00000000-6_eucldist_sorted_rho_exp.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z23eucldist_sorted_rho_expPKfPfiiifPKfPfiiif
	.type	_Z50__device_stub__Z23eucldist_sorted_rho_expPKfPfiiifPKfPfiiif, @function
_Z50__device_stub__Z23eucldist_sorted_rho_expPKfPfiiifPKfPfiiif:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movss	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z23eucldist_sorted_rho_expPKfPfiiif(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z50__device_stub__Z23eucldist_sorted_rho_expPKfPfiiifPKfPfiiif, .-_Z50__device_stub__Z23eucldist_sorted_rho_expPKfPfiiifPKfPfiiif
	.globl	_Z23eucldist_sorted_rho_expPKfPfiiif
	.type	_Z23eucldist_sorted_rho_expPKfPfiiif, @function
_Z23eucldist_sorted_rho_expPKfPfiiif:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z23eucldist_sorted_rho_expPKfPfiiifPKfPfiiif
	.cfi_endproc
.LFE2033:
	.size	_Z23eucldist_sorted_rho_expPKfPfiiif, .-_Z23eucldist_sorted_rho_expPKfPfiiif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z23eucldist_sorted_rho_expPKfPfiiif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z23eucldist_sorted_rho_expPKfPfiiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * block loading rho calculation. should be much faster
 * system('nvcc -ptx citydist_rho4.cu')
 * iA is multiple of chunk (16)
*/

#include <hip/hip_runtime.h>
// #include "cublas_v2.h"
#include <math.h>
#define ABS(my_val) ((my_val) < 0) ? (-1*(my_val)) : (my_val)
#define MIN(A,B) ((A)<(B)) ? (A) : (B)
#define MAX(A,B) ((A)>(B)) ? (A) : (B)
#define NTHREADS 128
#define NC (1+6*2)
// #define NC (9)
#define CHUNK 16
#define SINGLE_INF (3.402E+38)

/** Main entry point.
 * Works out where the current thread should read/write to global memory
 * and calls doIterations to do the actual work.
 * Step through one B at a time
 */
__global__ void eucldist_sorted_rho_exp(float const *A, float *D, int const nA, int const nneigh, int const nC, float const dc){
    int iA = (blockIdx.x + blockIdx.y * gridDim.x) * CHUNK;    
    int tx = threadIdx.x;
    __shared__ float sA[NC][CHUNK];
    __shared__ float rho1[NTHREADS][CHUNK];
    
    // cache A
    if (tx < nC){ //use tx as iC
        for (int i=0; i<CHUNK; ++i){
            if (iA+i < nA){
                sA[tx][i] = A[tx + (iA+i)*nC];
            }else{
                sA[tx][i] = SINGLE_INF;
            }   
        }
    }
    for (int i=0; i<CHUNK; ++i) rho1[tx][i] = 0.0f;
    __syncthreads();
    
    // fill in the shared memory A
    float dc2 = dc*dc;
    int iB_min = MAX(iA - nneigh, 0);
    int iB_max = MIN(iA + nneigh + CHUNK - 1, nA-1);
    int iB = iB_min + tx; //MAX(tx, iB_min); // tx is index for B    
    while (iB <= iB_max){
        float dist[CHUNK];
        // calculate distance to B        
        for (int i=0; i<CHUNK; ++i) dist[i] = 0.0f;
        for (int iC=0; iC<nC; ++iC){
            float Btemp = A[iC + iB*nC];
            for (int i=0; i<CHUNK; ++i){
                float temp = Btemp - sA[iC][i];
                dist[i] += temp * temp;
            }            
        }          
        for (int i=0; i<CHUNK; ++i){            
            int dab = ABS(iA+i-iB);
            if (dab<=nneigh){
                if (iA+i < nA && iA+i != iB){
                    rho1[tx][i] += expf(-1*dist[i]/dc2);
                }
            }
        }
        iB += blockDim.x;
    } // while
    
    // final count
    __syncthreads();    
    // if (tx < CHUNK) D[iA+tx] = rho1[tx];
    if (tx < CHUNK){
        float sum = 0.0f;
        for (int tx1=0; tx1<blockDim.x; ++tx1)
            sum += rho1[tx1][tx];
        if (iA+tx<nA) D[iA+tx] = sum;
    }
} // func
	.text
	.file	"eucldist_sorted_rho_exp.hip"
	.globl	_Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif # -- Begin function _Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif
	.type	_Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif,@function
_Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif: # @_Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movss	%xmm0, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23eucldist_sorted_rho_expPKfPfiiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif, .Lfunc_end0-_Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23eucldist_sorted_rho_expPKfPfiiif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23eucldist_sorted_rho_expPKfPfiiif,@object # @_Z23eucldist_sorted_rho_expPKfPfiiif
	.section	.rodata,"a",@progbits
	.globl	_Z23eucldist_sorted_rho_expPKfPfiiif
	.p2align	3, 0x0
_Z23eucldist_sorted_rho_expPKfPfiiif:
	.quad	_Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif
	.size	_Z23eucldist_sorted_rho_expPKfPfiiif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z23eucldist_sorted_rho_expPKfPfiiif"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__eucldist_sorted_rho_expPKfPfiiif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23eucldist_sorted_rho_expPKfPfiiif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23eucldist_sorted_rho_expPKfPfiiif ; -- Begin function _Z23eucldist_sorted_rho_expPKfPfiiif
	.globl	_Z23eucldist_sorted_rho_expPKfPfiiif
	.p2align	8
	.type	_Z23eucldist_sorted_rho_expPKfPfiiif,@function
_Z23eucldist_sorted_rho_expPKfPfiiif:   ; @_Z23eucldist_sorted_rho_expPKfPfiiif
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s12, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s0, s14
	s_lshl_b32 s15, s12, 4
	v_cmpx_gt_i32_e64 s10, v0
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.preheader122.preheader
	s_mul_i32 s12, s10, s12
	v_lshl_add_u32 v3, v0, 6, 0x2000
	v_lshl_add_u32 v1, s12, 4, v0
	s_mov_b32 s12, 0
	s_mov_b32 s13, s15
.LBB0_2:                                ; %.preheader122
                                        ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 0x7f7ff023
	s_cmp_ge_i32 s13, s8
	s_cbranch_scc1 .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v4, s12, v3
	v_add_nc_u32_e32 v1, s10, v1
	s_add_i32 s12, s12, 4
	s_add_i32 s13, s13, 1
	s_cmp_eq_u32 s12, 64
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v2
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %Flow221
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b32_e32 v17, 6, v0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, 0
.LBB0_6:                                ; %.loopexit
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s1, v17
	s_add_i32 s1, s1, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 64
	ds_store_b32 v2, v1
	s_cbranch_scc0 .LBB0_6
; %bb.7:
	s_sub_i32 s1, s15, s9
	s_add_i32 s12, s9, s15
	s_max_i32 s1, s1, 0
	s_add_i32 s12, s12, 15
	v_add_nc_u32_e32 v18, s1, v0
	s_add_i32 s1, s8, -1
	s_mov_b32 s17, 0
	s_min_i32 s16, s12, s1
	s_mov_b32 s18, exec_lo
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_ge_i32_e64 s16, v18
	s_cbranch_execz .LBB0_21
; %bb.8:                                ; %.preheader121.lr.ph
	s_load_b32 s1, s[2:3], 0xc
	s_cmp_gt_i32 s10, 0
	v_mov_b32_e32 v19, 0
	s_cselect_b32 s19, -1, 0
	s_lshl_b32 s0, s0, 4
	s_lshl_b32 s12, s14, 4
	v_subrev_nc_u32_e32 v1, s0, v18
	v_mul_f32_e64 v20, s11, s11
	v_sub_nc_u32_e32 v22, s15, v18
	v_mov_b32_e32 v23, v19
	s_add_i32 s14, s0, s12
	v_subrev_nc_u32_e32 v21, s12, v1
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s1, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s20, 0, s11
.LBB0_9:                                ; %.preheader121
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_10 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;       Child Loop BB0_14 Depth 3
                                        ;     Child Loop BB0_17 Depth 2
	s_mov_b64 s[0:1], 0
.LBB0_10:                               ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 16
	v_movreld_b32_e32 v1, 0
	s_cbranch_scc0 .LBB0_10
; %bb.11:                               ; %.preheader120
                                        ;   in Loop: Header=BB0_9 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s19
	s_cbranch_vccnz .LBB0_16
; %bb.12:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_9 Depth=1
	v_mul_lo_u32 v24, v18, s10
	s_mov_b32 s12, 0
	s_movk_i32 s13, 0x2000
.LBB0_13:                               ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_14 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, s12, v24
	s_mov_b64 s[0:1], 0
	s_mov_b32 s21, s13
	v_ashrrev_i32_e32 v26, 31, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	v_add_co_u32 v25, vcc_lo, s4, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v26, vcc_lo, s5, v26, vcc_lo
	global_load_b32 v25, v[25:26], off
.LBB0_14:                               ;   Parent Loop BB0_9 Depth=1
                                        ;     Parent Loop BB0_13 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v26, s21
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	v_movrels_b32_e32 v27, v1
	s_addc_u32 s1, s1, 0
	ds_load_b32 v26, v26
	s_add_i32 s21, s21, 4
	s_cmp_eq_u32 s0, 16
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v26, v25, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v26, v26
	v_movreld_b32_e32 v1, v27
	s_cbranch_scc0 .LBB0_14
; %bb.15:                               ;   in Loop: Header=BB0_13 Depth=2
	s_add_i32 s12, s12, 1
	s_add_i32 s13, s13, 64
	s_cmp_eq_u32 s12, s10
	s_cbranch_scc0 .LBB0_13
.LBB0_16:                               ; %Flow217
                                        ;   in Loop: Header=BB0_9 Depth=1
	v_mov_b32_e32 v24, v17
	s_mov_b64 s[12:13], 0
.LBB0_17:                               ;   Parent Loop BB0_9 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v25, s12, v22
	s_add_i32 s0, s14, s12
	s_cmp_lt_i32 s0, s8
	v_cmp_ne_u32_e64 s0, s12, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v26, 0, v25
	s_cselect_b32 s1, -1, 0
	v_max_i32_e32 v25, v25, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, s9, v25
	s_and_b32 s1, s1, vcc_lo
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=2
	s_mov_b32 m0, s12
	v_movrels_b32_e32 v25, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v26, null, v20, v20, -v25
	v_div_scale_f32 v29, vcc_lo, -v25, v20, -v25
	v_rcp_f32_e32 v27, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v26, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v27
	v_mul_f32_e32 v28, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v26, v28, v29
	v_fmac_f32_e32 v28, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v26, v28, v29
	v_div_fmas_f32 v26, v26, v27, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v25, v26, v20, -v25
	v_mul_f32_e32 v26, 0x3fb8aa3b, v25
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v27, 0x3fb8aa3b, v25, -v26
	v_rndne_f32_e32 v28, v26
	v_dual_fmac_f32 v27, 0x32a5705f, v25 :: v_dual_sub_f32 v26, v26, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v26, v26, v27
	v_cvt_i32_f32_e32 v27, v28
	ds_load_b32 v28, v24
	v_exp_f32_e32 v26, v26
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v26, v26, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, 0, v26, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v25
	v_cndmask_b32_e32 v25, 0x7f800000, v26, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v25, v25, v28
	ds_store_b32 v24, v25
.LBB0_19:                               ;   in Loop: Header=BB0_17 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v24, 4, v24
	s_add_u32 s12, s12, 1
	s_addc_u32 s13, s13, 0
	s_cmp_eq_u32 s12, 16
	s_cbranch_scc0 .LBB0_17
; %bb.20:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v18, s11, v18
	v_add_co_u32 v21, vcc_lo, v21, s11
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, s16, v18
	v_add_co_u32 v22, s0, v22, s20
	v_add_co_ci_u32_e64 v23, s0, 0, v23, s0
	s_or_b32 s17, vcc_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s17
	s_cbranch_execnz .LBB0_9
.LBB0_21:                               ; %Flow219
	s_or_b32 exec_lo, exec_lo, s18
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 16, v0
	s_cbranch_execz .LBB0_28
; %bb.22:                               ; %.preheader
	s_load_b32 s0, s[2:3], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB0_25
; %bb.23:                               ; %.lr.ph137.preheader
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
.LBB0_24:                               ; %.lr.ph137
                                        ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v3, v1
	v_add_nc_u32_e32 v1, 64, v1
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	s_cbranch_scc0 .LBB0_24
	s_branch .LBB0_26
.LBB0_25:
	v_mov_b32_e32 v2, 0
.LBB0_26:                               ; %Flow214
	v_or_b32_e32 v0, s15, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s8, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_28:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23eucldist_sorted_rho_expPKfPfiiif
		.amdhsa_group_segment_fixed_size 9024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 31
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23eucldist_sorted_rho_expPKfPfiiif, .Lfunc_end0-_Z23eucldist_sorted_rho_expPKfPfiiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1140
; NumSgprs: 24
; NumVgprs: 31
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 9024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 31
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 9024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23eucldist_sorted_rho_expPKfPfiiif
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z23eucldist_sorted_rho_expPKfPfiiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     31
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
