/* Furthest point sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 * Happy Mid-Autumn Festival! :)
 */
#include <stdio.h>
#include <iostream>

__device__ int get_batch_id(int* accu_list, int batch_size, int id) {
    for (int b=0; b<batch_size-1; b++) {
        if (id >= accu_list[b]) {
            if(id < accu_list[b+1])
                return b;
        }
    }
    return batch_size - 1;
}


__global__ void get_roi_bbox_gpu_kernel(int batch_size, int npoint, int nbbox, int bbox_attr,
                                        int diff_thres, float expand_ratio,
                                        const float* input_coors,
                                        const float* gt_bbox,
                                        const int* input_num_list,
                                        const float* anchor_size,
                                        int* input_accu_list,
                                        float* roi_bbox,
                                        int* roi_conf,
                                        int* roi_diff) {

    const float anchor_diag = sqrtf(anchor_size[0]*anchor_size[0] + anchor_size[1]*anchor_size[1]);
    int point_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (point_id < npoint) {
        // Initialize all the bbox with 0.1*0.1*0.1 dimension for lateral loss calculation.
        roi_bbox[point_id * 7 + 0] = 0.1;
        roi_bbox[point_id * 7 + 1] = 0.1;
        roi_bbox[point_id * 7 + 2] = 0.1;
        roi_conf[point_id] = 0;
        roi_diff[point_id] = -1;
        float point_x = input_coors[point_id * 3 + 0];
        float point_y = input_coors[point_id * 3 + 1];
        float point_z = input_coors[point_id * 3 + 2];
        int batch_id = get_batch_id(input_accu_list, batch_size, point_id);
        for (int i=0; i<nbbox; i++) {
            float bbox_w = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 0];
            float bbox_l = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 1];
            float bbox_h = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 2];
            float bbox_x = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 3];
            float bbox_y = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 4];
            float bbox_z = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 5];
            float bbox_r = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 6];
            float bbox_cls = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 7];
            float bbox_diff = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 8];
            if (bbox_l*bbox_h*bbox_w > 0) {
                float rel_point_x = point_x - bbox_x;
                float rel_point_y = point_y - bbox_y;
                float rel_point_z = point_z - bbox_z;
                float rot_rel_point_x = rel_point_x*cosf(bbox_r) + rel_point_y*sinf(bbox_r);
                float rot_rel_point_y = -rel_point_x*sinf(bbox_r) + rel_point_y*cosf(bbox_r);
                if (abs(rot_rel_point_x)<=bbox_w * (1 + expand_ratio) / 2 &&
                    abs(rot_rel_point_y)<=bbox_l * (1 + expand_ratio) / 2 &&
                    abs(rel_point_z)<=bbox_h * (1 + expand_ratio) / 2) {

                    roi_bbox[point_id * 7 + 0] = bbox_w;
                    roi_bbox[point_id * 7 + 1] = bbox_l;
                    roi_bbox[point_id * 7 + 2] = bbox_h;
                    roi_bbox[point_id * 7 + 3] = bbox_x;
                    roi_bbox[point_id * 7 + 4] = bbox_y;
                    roi_bbox[point_id * 7 + 5] = bbox_z;
                    roi_bbox[point_id * 7 + 6] = bbox_r;

                    if (bbox_diff <= diff_thres && bbox_cls == 0) {
                        // Here we only take cars into consideration, while vans are excluded and give the foreground labels as -1 (ignored).
                        // TODO: need to change the category class accordingly to the expected detection target.
                        roi_conf[point_id] = 1;
                        roi_diff[point_id] = bbox_diff;
                    }else{ // ignore
                        roi_conf[point_id] = -1;
                        roi_diff[point_id] = -1;
                    }
                }
            }
        }
    }
}


void get_roi_bbox_gpu_launcher(int batch_size, int npoint, int nbbox, int bbox_attr,
                               int diff_thres, float expand_ratio,
                               const float* input_coors,
                               const float* gt_bbox,
                               const int* input_num_list,
                               const float* anchor_size,
                               int* input_accu_list,
                               float* roi_bbox,
                               int* roi_conf,
                               int* roi_diff) {
    if (batch_size * nbbox * bbox_attr <=0 || npoint <=0) {
        printf("GetRoIBbox Op exited unexpectedly due to invalid CUDA input dimension.\n");
        return;
    }
    int blockSize;      // The launch configurator returned block size
    int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch
    int gridSize;       // The actual grid size needed, based on input size

    cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, get_roi_bbox_gpu_kernel, 0, npoint);
    gridSize = (npoint + blockSize - 1) / blockSize;
    get_roi_bbox_gpu_kernel<<<gridSize, blockSize>>>(batch_size, npoint, nbbox, bbox_attr,
                                                     diff_thres, expand_ratio,
                                                     input_coors,
                                                     gt_bbox,
                                                     input_num_list,
                                                     anchor_size,
                                                     input_accu_list,
                                                     roi_bbox,
                                                     roi_conf,
                                                     roi_diff);
}

	.file	"tmpxft_0026ef8f_00000000-6_get_roi_bbox.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12get_batch_idPiii
	.type	_Z12get_batch_idPiii, @function
_Z12get_batch_idPiii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z12get_batch_idPiii, .-_Z12get_batch_idPiii
	.globl	_Z69__device_stub__Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_iiiiifPKfS0_PKiS0_PiPfS3_S3_
	.type	_Z69__device_stub__Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_iiiiifPKfS0_PKiS0_PiPfS3_S3_, @function
_Z69__device_stub__Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_iiiiifPKfS0_PKiS0_PiPfS3_S3_:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	304(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 56(%rsp)
	movq	312(%rsp), %rax
	movl	%edx, 84(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 48(%rsp)
	movq	320(%rsp), %rax
	movl	%ecx, 80(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 40(%rsp)
	movq	328(%rsp), %rax
	movl	%r8d, 76(%rsp)
	movq	%rax, 32(%rsp)
	movq	336(%rsp), %rax
	movq	%r9, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	344(%rsp), %rax
	movss	%xmm0, 72(%rsp)
	movq	%rax, 16(%rsp)
	movq	352(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	84(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	112(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 320
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L4:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z69__device_stub__Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_iiiiifPKfS0_PKiS0_PiPfS3_S3_, .-_Z69__device_stub__Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_iiiiifPKfS0_PKiS0_PiPfS3_S3_
	.globl	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.type	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, @function
_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z69__device_stub__Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_iiiiifPKfS0_PKiS0_PiPfS3_S3_
	.cfi_endproc
.LFE3662:
	.size	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, .-_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GetRoIBbox Op exited unexpectedly due to invalid CUDA input dimension.\n"
	.text
	.globl	_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_
	.type	_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_, @function
_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$296, %rsp
	.cfi_def_cfa_offset 352
	movq	352(%rsp), %rax
	movl	%r8d, 8(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 24(%rsp)
	movq	360(%rsp), %rax
	movss	%xmm0, 12(%rsp)
	movq	%rax, 32(%rsp)
	movq	368(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	376(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	384(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	392(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	400(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	movl	%edi, %eax
	imull	%edx, %eax
	imull	%ecx, %eax
	testl	%eax, %eax
	jle	.L24
	movl	%esi, %ebp
	testl	%esi, %esi
	jg	.L11
.L24:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L27
	addq	$296, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L11:
	.cfi_restore_state
	movl	%edi, %r13d
	leaq	96(%rsp), %rdi
	movl	%edx, %r14d
	movl	%ecx, %r15d
	call	cudaGetDevice@PLT
	testl	%eax, %eax
	jne	.L15
	movl	96(%rsp), %edx
	leaq	100(%rsp), %rdi
	movl	$39, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L15
	movl	96(%rsp), %edx
	leaq	104(%rsp), %rdi
	movl	$10, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L15
	movl	96(%rsp), %edx
	leaq	108(%rsp), %rdi
	movl	$1, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L15
	movl	96(%rsp), %edx
	leaq	112(%rsp), %rdi
	movl	$16, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L15
	leaq	136(%rsp), %rdi
	leaq	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_(%rip), %rsi
	call	cudaFuncGetAttributes@PLT
	testl	%eax, %eax
	jne	.L15
	movl	100(%rsp), %eax
	movl	160(%rsp), %r9d
	movl	104(%rsp), %r10d
	movl	%eax, 4(%rsp)
	movl	108(%rsp), %eax
	cmpl	%eax, %r9d
	cmovg	%eax, %r9d
	cmpl	%ebp, %r9d
	cmovg	%ebp, %r9d
	xorl	%r11d, %r11d
	xorl	%r12d, %r12d
	leal	-1(%r10,%r9), %ebx
	movl	%ebx, %eax
	cltd
	idivl	%r10d
	subl	%edx, %ebx
.L17:
	testl	%ebx, %ebx
	jle	.L15
	cmpl	%ebx, %r9d
	movl	%ebx, %edx
	leaq	124(%rsp), %rdi
	movl	%r11d, 92(%rsp)
	cmovle	%r9d, %edx
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	movl	%r10d, 88(%rsp)
	leaq	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_(%rip), %rsi
	movl	%r9d, 84(%rsp)
	movl	%edx, 80(%rsp)
	call	cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
	testl	%eax, %eax
	jne	.L15
	movl	80(%rsp), %edx
	movl	124(%rsp), %eax
	movl	92(%rsp), %r11d
	movl	84(%rsp), %r9d
	imull	%edx, %eax
	movl	88(%rsp), %r10d
	cmpl	%r11d, %eax
	jle	.L18
	movl	%eax, %r11d
	movl	%edx, %r12d
.L18:
	cmpl	%r11d, 4(%rsp)
	je	.L15
	subl	%r10d, %ebx
	jmp	.L17
.L15:
	leal	-1(%r12,%rbp), %eax
	movl	%r12d, 124(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rcx
	cltd
	idivl	%r12d
	movq	%rcx, 116(%rsp)
	movl	120(%rsp), %esi
	movq	%rcx, 128(%rsp)
	movl	132(%rsp), %ecx
	movq	124(%rsp), %rdx
	movl	%eax, 112(%rsp)
	movq	112(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L27
	movq	72(%rsp), %rax
	movq	16(%rsp), %r9
	movl	%r15d, %ecx
	movl	%r14d, %edx
	movss	12(%rsp), %xmm0
	movl	8(%rsp), %r8d
	movl	%ebp, %esi
	movl	%r13d, %edi
	movq	%rax, 400(%rsp)
	movq	64(%rsp), %rax
	movq	%rax, 392(%rsp)
	movq	56(%rsp), %rax
	movq	%rax, 384(%rsp)
	movq	48(%rsp), %rax
	movq	%rax, 376(%rsp)
	movq	40(%rsp), %rax
	movq	%rax, 368(%rsp)
	movq	32(%rsp), %rax
	movq	%rax, 360(%rsp)
	movq	24(%rsp), %rax
	movq	%rax, 352(%rsp)
	addq	$296, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z69__device_stub__Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_iiiiifPKfS0_PKiS0_PiPfS3_S3_
.L10:
	.cfi_restore_state
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
.L27:
	call	__stack_chk_fail@PLT
.L22:
	addq	$296, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_, .-_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_
	.section	.rodata.str1.1
.LC1:
	.string	"_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Furthest point sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 * Happy Mid-Autumn Festival! :)
 */

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>

__device__ int get_batch_id(int* accu_list, int batch_size, int id) {
    for (int b=0; b<batch_size-1; b++) {
        if (id >= accu_list[b]) {
            if(id < accu_list[b+1])
                return b;
        }
    }
    return batch_size - 1;
}


__global__ void get_roi_bbox_gpu_kernel(int batch_size, int npoint, int nbbox, int bbox_attr,
                                        int diff_thres, float expand_ratio,
                                        const float* input_coors,
                                        const float* gt_bbox,
                                        const int* input_num_list,
                                        const float* anchor_size,
                                        int* input_accu_list,
                                        float* roi_bbox,
                                        int* roi_conf,
                                        int* roi_diff) {

    const float anchor_diag = sqrtf(anchor_size[0]*anchor_size[0] + anchor_size[1]*anchor_size[1]);
    int point_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (point_id < npoint) {
        // Initialize all the bbox with 0.1*0.1*0.1 dimension for lateral loss calculation.
        roi_bbox[point_id * 7 + 0] = 0.1;
        roi_bbox[point_id * 7 + 1] = 0.1;
        roi_bbox[point_id * 7 + 2] = 0.1;
        roi_conf[point_id] = 0;
        roi_diff[point_id] = -1;
        float point_x = input_coors[point_id * 3 + 0];
        float point_y = input_coors[point_id * 3 + 1];
        float point_z = input_coors[point_id * 3 + 2];
        int batch_id = get_batch_id(input_accu_list, batch_size, point_id);
        for (int i=0; i<nbbox; i++) {
            float bbox_w = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 0];
            float bbox_l = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 1];
            float bbox_h = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 2];
            float bbox_x = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 3];
            float bbox_y = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 4];
            float bbox_z = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 5];
            float bbox_r = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 6];
            float bbox_cls = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 7];
            float bbox_diff = gt_bbox[batch_id*nbbox*bbox_attr + i*bbox_attr + 8];
            if (bbox_l*bbox_h*bbox_w > 0) {
                float rel_point_x = point_x - bbox_x;
                float rel_point_y = point_y - bbox_y;
                float rel_point_z = point_z - bbox_z;
                float rot_rel_point_x = rel_point_x*cosf(bbox_r) + rel_point_y*sinf(bbox_r);
                float rot_rel_point_y = -rel_point_x*sinf(bbox_r) + rel_point_y*cosf(bbox_r);
                if (abs(rot_rel_point_x)<=bbox_w * (1 + expand_ratio) / 2 &&
                    abs(rot_rel_point_y)<=bbox_l * (1 + expand_ratio) / 2 &&
                    abs(rel_point_z)<=bbox_h * (1 + expand_ratio) / 2) {

                    roi_bbox[point_id * 7 + 0] = bbox_w;
                    roi_bbox[point_id * 7 + 1] = bbox_l;
                    roi_bbox[point_id * 7 + 2] = bbox_h;
                    roi_bbox[point_id * 7 + 3] = bbox_x;
                    roi_bbox[point_id * 7 + 4] = bbox_y;
                    roi_bbox[point_id * 7 + 5] = bbox_z;
                    roi_bbox[point_id * 7 + 6] = bbox_r;

                    if (bbox_diff <= diff_thres && bbox_cls == 0) {
                        // Here we only take cars into consideration, while vans are excluded and give the foreground labels as -1 (ignored).
                        // TODO: need to change the category class accordingly to the expected detection target.
                        roi_conf[point_id] = 1;
                        roi_diff[point_id] = bbox_diff;
                    }else{ // ignore
                        roi_conf[point_id] = -1;
                        roi_diff[point_id] = -1;
                    }
                }
            }
        }
    }
}


void get_roi_bbox_gpu_launcher(int batch_size, int npoint, int nbbox, int bbox_attr,
                               int diff_thres, float expand_ratio,
                               const float* input_coors,
                               const float* gt_bbox,
                               const int* input_num_list,
                               const float* anchor_size,
                               int* input_accu_list,
                               float* roi_bbox,
                               int* roi_conf,
                               int* roi_diff) {
    if (batch_size * nbbox * bbox_attr <=0 || npoint <=0) {
        printf("GetRoIBbox Op exited unexpectedly due to invalid CUDA input dimension.\n");
        return;
    }
    int blockSize;      // The launch configurator returned block size
    int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch
    int gridSize;       // The actual grid size needed, based on input size

    hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, get_roi_bbox_gpu_kernel, 0, npoint);
    gridSize = (npoint + blockSize - 1) / blockSize;
    get_roi_bbox_gpu_kernel<<<gridSize, blockSize>>>(batch_size, npoint, nbbox, bbox_attr,
                                                     diff_thres, expand_ratio,
                                                     input_coors,
                                                     gt_bbox,
                                                     input_num_list,
                                                     anchor_size,
                                                     input_accu_list,
                                                     roi_bbox,
                                                     roi_conf,
                                                     roi_diff);
}

	.text
	.file	"get_roi_bbox.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_ # -- Begin function _Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.type	_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_,@function
_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_: # @_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movss	%xmm0, (%r8)
	leaq	40(%rsp), %r10
	movq	%r9, (%r10)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, .Lfunc_end0-_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_ # -- Begin function _Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_
	.type	_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_,@function
_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_: # @_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testl	%esi, %esi
	jle	.LBB1_5
# %bb.1:
	movl	%ecx, %r14d
	movl	%edx, %r15d
	movl	%edi, %r13d
	movl	%edx, %eax
	imull	%edi, %eax
	imull	%ecx, %eax
	testl	%eax, %eax
	jle	.LBB1_5
# %bb.2:
	movl	%r8d, %ebp
	movl	%esi, %r12d
	movss	%xmm0, 12(%rsp)                 # 4-byte Spill
	movq	%r9, 72(%rsp)                   # 8-byte Spill
	movq	192(%rsp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	184(%rsp), %rax
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movq	176(%rsp), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movq	168(%rsp), %rax
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	160(%rsp), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	152(%rsp), %rax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	movq	144(%rsp), %rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	leaq	80(%rsp), %rdi
	leaq	84(%rsp), %rbx
	movl	$_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, %edx
	movq	%rbx, %rsi
	xorl	%ecx, %ecx
	movl	%r12d, %r8d
	callq	hipOccupancyMaxPotentialBlockSize
	movl	(%rbx), %ecx
	leal	(%r12,%rcx), %eax
	decl	%eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	btsq	$32, %rax
	btsq	$32, %rcx
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%r14d, %ecx
	movl	%ebp, %r8d
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	80(%rsp), %r9                   # 8-byte Reload
	pushq	24(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	40(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	88(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	120(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB1_4:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_5:
	.cfi_def_cfa_offset 144
	movl	$.Lstr, %edi
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end1:
	.size	_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_, .Lfunc_end1-_Z25get_roi_bbox_gpu_launcheriiiiifPKfS0_PKiS0_PiPfS3_S3_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_,@object # @_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.section	.rodata,"a",@progbits
	.globl	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.p2align	3, 0x0
_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_:
	.quad	_Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.size	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_"
	.size	.L__unnamed_1, 56

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"GetRoIBbox Op exited unexpectedly due to invalid CUDA input dimension."
	.size	.Lstr, 71

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_ ; -- Begin function _Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.globl	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
	.p2align	8
	.type	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_,@function
_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_: ; @_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x64
	s_load_b128 s[16:19], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s17, v1
	s_cbranch_execz .LBB0_37
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x38
	v_mul_lo_u32 v3, v1, 7
	s_load_b128 s[12:15], s[0:1], 0x18
	v_lshl_add_u32 v5, v1, 1, v1
	v_mov_b32_e32 v2, 0x3dcccccd
	s_load_b64 s[0:1], s[0:1], 0x10
	v_mov_b32_e32 v0, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_mov_b32_e32 v3, v2
	v_mov_b32_e32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v11, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, s12, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	global_store_b96 v[11:12], v[2:4], off
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s6, s16, -1
	global_load_b96 v[8:10], v[5:6], off
	s_cmp_lt_i32 s16, 2
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v15, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v4, vcc_lo
	global_store_b32 v[13:14], v2, off
	global_store_b32 v[15:16], v0, off
	s_cbranch_scc1 .LBB0_9
; %bb.2:                                ; %.lr.ph.i.preheader
	v_mov_b32_e32 v0, 0
	s_add_u32 s2, s4, 4
	s_addc_u32 s3, s5, 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB0_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v2, v0, s[2:3] offset:-4
	s_mov_b32 s8, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e64 s7, v2, v1
	v_cmpx_le_i32_e64 v2, v1
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v2, v0, s[2:3]
	s_and_not1_b32 s7, s7, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, v2, v1
	s_and_b32 s9, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s7, s7, s9
.LBB0_5:                                ; %Flow239
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_mov_b32_e32 v2, s5
	s_mov_b32 s9, -1
	s_and_saveexec_b32 s8, s7
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s5, s5, 1
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s6, s5
	v_mov_b32_e32 v2, s6
	s_cselect_b32 s7, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s9, s7, exec_lo
; %bb.7:                                ; %Flow240
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, exec_lo, s9
	s_or_b32 s4, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_3
; %bb.8:                                ; %Flow241
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_9:                                ; %_Z12get_batch_idPiii.exit
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB0_37
; %bb.10:                               ; %.lr.ph
	v_min_i32_e32 v0, s6, v2
	v_add_f32_e64 v20, s1, 1.0
	s_mul_i32 s1, s19, s18
	v_cvt_f32_i32_e32 v21, s0
	v_dual_mov_b32 v22, -1 :: v_dual_mov_b32 v23, 1
	v_mul_lo_u32 v17, s1, v0
	v_mov_b32_e32 v19, 0
	s_mov_b32 s2, 0x7fffff
	s_mov_b32 s3, 0xb94c1982
	s_mov_b32 s4, 0x37d75334
.LBB0_11:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v18, 31, v17
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_lshlrev_b64 v[0:1], 2, v[17:18]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v24, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v25, vcc_lo, s15, v1, vcc_lo
	s_clause 0x2
	global_load_b128 v[4:7], v[24:25], off
	global_load_b128 v[0:3], v[24:25], off offset:16
	global_load_b32 v24, v[24:25], off offset:32
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v18, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v4, v18
	v_cmpx_lt_f32_e32 0, v18
	s_cbranch_execz .LBB0_36
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v25, 0x7fffffff, v2
	v_cmp_ngt_f32_e64 s6, 0x48000000, |v2|
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s6
	s_xor_b32 s7, exec_lo, s0
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_11 Depth=1
	v_lshrrev_b32_e32 v31, 23, v25
	v_and_or_b32 v34, v25, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v32, 0xffffff88, v31
	v_mad_u64_u32 v[26:27], null, 0xfe5163ab, v34, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v32
	v_cndmask_b32_e64 v33, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v18, v27 :: v_dual_add_nc_u32 v33, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[27:28], null, 0x3c439041, v34, v[18:19]
	v_cmp_lt_u32_e64 s0, 31, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v35, 0, 0xffffffe0, s0
	v_dual_mov_b32 v18, v28 :: v_dual_add_nc_u32 v35, v35, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[28:29], null, 0xdb629599, v34, v[18:19]
	v_cmp_lt_u32_e64 s1, 31, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v18, v29
	v_cndmask_b32_e32 v26, v28, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, 0xf534ddc0, v34, v[18:19]
	v_dual_mov_b32 v18, v30 :: v_dual_cndmask_b32 v27, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0xfc2757d1, v34, v[18:19]
	v_cndmask_b32_e64 v26, v27, v26, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v31
	v_mad_u64_u32 v[31:32], null, 0x4e441529, v34, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v32
	v_mad_u64_u32 v[32:33], null, 0xa2f9836e, v34, v[18:19]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v34, v31, v29, vcc_lo
	v_add_nc_u32_e32 v18, v18, v35
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v32, v32, v30 :: v_dual_cndmask_b32 v31, v33, v31
	v_cndmask_b32_e32 v30, v30, v28, vcc_lo
	v_sub_nc_u32_e32 v33, 32, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v29, v32, v34, s0
	v_cndmask_b32_e64 v31, v31, v32, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v34, v30, s0
	v_cndmask_b32_e64 v30, v30, v27, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v31, v31, v29, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v29, v29, v32, s1
	v_cndmask_b32_e64 v32, v32, v30, s1
	v_cndmask_b32_e64 v26, v30, v26, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v31, v29, v33
	v_alignbit_b32 v28, v29, v32, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v18, v34, v31 :: v_dual_cndmask_b32 v27, v28, v29
	v_alignbit_b32 v31, v32, v26, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v28, v18, 29, 1
	v_alignbit_b32 v29, v18, v27, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v31, v31, v32, vcc_lo
	v_sub_nc_u32_e32 v30, 0, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v27, v31, 30
	v_alignbit_b32 v26, v31, v26, 30
	v_xor_b32_e32 v29, v29, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v27, v27, v30
	v_xor_b32_e32 v26, v26, v30
	v_lshrrev_b32_e32 v30, 29, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v32, v29
	v_lshrrev_b32_e32 v18, 30, v18
	v_lshlrev_b32_e32 v30, 31, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v32, 32, v32
	v_or_b32_e32 v33, 0.5, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v31, 31, v32
	v_lshlrev_b32_e32 v34, 23, v32
	v_alignbit_b32 v29, v29, v27, v31
	v_alignbit_b32 v26, v27, v26, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v33, v33, v34
	v_alignbit_b32 v27, v29, v26, 9
	v_lshrrev_b32_e32 v29, 9, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v31, v27
	v_min_u32_e32 v31, 32, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v35, 31, v31
	v_alignbit_b32 v26, v27, v26, v35
	v_or_b32_e32 v27, v29, v33
	v_add_lshl_u32 v29, v31, v32, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v26, 9, v26
	v_mul_f32_e32 v31, 0x3fc90fda, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v26, v26, v29
	v_fma_f32 v29, 0x3fc90fda, v27, -v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v26, 0x33000000, v26
	v_fmac_f32_e32 v29, 0x33a22168, v27
	v_add_nc_u32_e32 v27, v28, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v26, v26, v30
	v_fmac_f32_e32 v29, 0x3fc90fda, v26
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v26, v31, v29
.LBB0_14:                               ; %Flow235
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_and_not1_saveexec_b32 s0, s7
; %bb.15:                               ;   in Loop: Header=BB0_11 Depth=1
	v_mul_f32_e64 v18, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v18, v18
	v_fma_f32 v26, 0xbfc90fda, v18, |v2|
	v_cvt_i32_f32_e32 v27, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v26, 0xb3a22168, v18
	v_fmac_f32_e32 v26, 0xa7c234c4, v18
; %bb.16:                               ; %_ZL4cosff.exit
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr28
	s_and_saveexec_b32 s0, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s0
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_11 Depth=1
	v_lshrrev_b32_e32 v33, 23, v25
	v_and_or_b32 v36, v25, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v34, 0xffffff88, v33
	v_mad_u64_u32 v[28:29], null, 0xfe5163ab, v36, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v34
	v_cndmask_b32_e64 v35, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v18, v29 :: v_dual_add_nc_u32 v35, v35, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[29:30], null, 0x3c439041, v36, v[18:19]
	v_cmp_lt_u32_e64 s0, 31, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v37, 0, 0xffffffe0, s0
	v_dual_mov_b32 v18, v30 :: v_dual_add_nc_u32 v37, v37, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[30:31], null, 0xdb629599, v36, v[18:19]
	v_cmp_lt_u32_e64 s1, 31, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v18, v31
	v_cndmask_b32_e32 v28, v30, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[31:32], null, 0xf534ddc0, v36, v[18:19]
	v_dual_mov_b32 v18, v32 :: v_dual_cndmask_b32 v29, v31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[32:33], null, 0xfc2757d1, v36, v[18:19]
	v_cndmask_b32_e64 v28, v29, v28, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v33
	v_mad_u64_u32 v[33:34], null, 0x4e441529, v36, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v34
	v_mad_u64_u32 v[34:35], null, 0xa2f9836e, v36, v[18:19]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v36, v33, v31, vcc_lo
	v_add_nc_u32_e32 v18, v18, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v34, v34, v32 :: v_dual_cndmask_b32 v33, v35, v33
	v_cndmask_b32_e32 v32, v32, v30, vcc_lo
	v_sub_nc_u32_e32 v35, 32, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v34, v36, s0
	v_cndmask_b32_e64 v33, v33, v34, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v34, v36, v32, s0
	v_cndmask_b32_e64 v32, v32, v29, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v33, v33, v31, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v31, v31, v34, s1
	v_cndmask_b32_e64 v34, v34, v32, s1
	v_cndmask_b32_e64 v28, v32, v28, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v33, v31, v35
	v_alignbit_b32 v30, v31, v34, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v18, v36, v33 :: v_dual_cndmask_b32 v29, v30, v31
	v_alignbit_b32 v33, v34, v28, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v30, v18, 29, 1
	v_alignbit_b32 v31, v18, v29, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v33, v33, v34, vcc_lo
	v_sub_nc_u32_e32 v32, 0, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v29, v29, v33, 30
	v_alignbit_b32 v28, v33, v28, 30
	v_xor_b32_e32 v31, v31, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v29, v29, v32
	v_xor_b32_e32 v28, v28, v32
	v_lshrrev_b32_e32 v32, 29, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v34, v31
	v_lshrrev_b32_e32 v18, 30, v18
	v_lshlrev_b32_e32 v32, 31, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v34, 32, v34
	v_or_b32_e32 v35, 0.5, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v33, 31, v34
	v_lshlrev_b32_e32 v36, 23, v34
	v_alignbit_b32 v31, v31, v29, v33
	v_alignbit_b32 v28, v29, v28, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v35, v35, v36
	v_alignbit_b32 v29, v31, v28, 9
	v_lshrrev_b32_e32 v31, 9, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v33, v29
	v_min_u32_e32 v33, 32, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v37, 31, v33
	v_alignbit_b32 v28, v29, v28, v37
	v_or_b32_e32 v29, v31, v35
	v_add_lshl_u32 v31, v33, v34, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v28, 9, v28
	v_mul_f32_e32 v33, 0x3fc90fda, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v28, v28, v31
	v_fma_f32 v31, 0x3fc90fda, v29, -v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v28, 0x33000000, v28
	v_fmac_f32_e32 v31, 0x33a22168, v29
	v_add_nc_u32_e32 v29, v30, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v28, v28, v32
	v_fmac_f32_e32 v31, 0x3fc90fda, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v28, v33, v31
.LBB0_18:                               ; %Flow234
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_and_not1_saveexec_b32 s0, s7
; %bb.19:                               ;   in Loop: Header=BB0_11 Depth=1
	v_mul_f32_e64 v18, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v18, v18
	v_fma_f32 v28, 0xbfc90fda, v18, |v2|
	v_cvt_i32_f32_e32 v29, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, 0xb3a22168, v18
	v_fmac_f32_e32 v28, 0xa7c234c4, v18
; %bb.20:                               ; %_ZL4sinff.exit
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr31
                                        ; implicit-def: $vgpr30
	s_and_saveexec_b32 s0, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_11 Depth=1
	v_lshrrev_b32_e32 v35, 23, v25
	v_and_or_b32 v38, v25, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v36, 0xffffff88, v35
	v_mad_u64_u32 v[30:31], null, 0xfe5163ab, v38, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v36
	v_cndmask_b32_e64 v37, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v18, v31 :: v_dual_add_nc_u32 v37, v37, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[31:32], null, 0x3c439041, v38, v[18:19]
	v_cmp_lt_u32_e64 s0, 31, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v39, 0, 0xffffffe0, s0
	v_dual_mov_b32 v18, v32 :: v_dual_add_nc_u32 v39, v39, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[32:33], null, 0xdb629599, v38, v[18:19]
	v_cmp_lt_u32_e64 s1, 31, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v18, v33
	v_cndmask_b32_e32 v30, v32, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[33:34], null, 0xf534ddc0, v38, v[18:19]
	v_dual_mov_b32 v18, v34 :: v_dual_cndmask_b32 v31, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[34:35], null, 0xfc2757d1, v38, v[18:19]
	v_cndmask_b32_e64 v30, v31, v30, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v35
	v_mad_u64_u32 v[35:36], null, 0x4e441529, v38, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v36
	v_mad_u64_u32 v[36:37], null, 0xa2f9836e, v38, v[18:19]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v38, v35, v33, vcc_lo
	v_add_nc_u32_e32 v18, v18, v39
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v36, v36, v34 :: v_dual_cndmask_b32 v35, v37, v35
	v_cndmask_b32_e32 v34, v34, v32, vcc_lo
	v_sub_nc_u32_e32 v37, 32, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v33, v36, v38, s0
	v_cndmask_b32_e64 v35, v35, v36, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v36, v38, v34, s0
	v_cndmask_b32_e64 v34, v34, v31, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v35, v35, v33, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v33, v33, v36, s1
	v_cndmask_b32_e64 v36, v36, v34, s1
	v_cndmask_b32_e64 v30, v34, v30, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v35, v33, v37
	v_alignbit_b32 v32, v33, v36, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v18, v38, v35 :: v_dual_cndmask_b32 v31, v32, v33
	v_alignbit_b32 v35, v36, v30, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v32, v18, 29, 1
	v_alignbit_b32 v33, v18, v31, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v35, v35, v36, vcc_lo
	v_sub_nc_u32_e32 v34, 0, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v31, v35, 30
	v_alignbit_b32 v30, v35, v30, 30
	v_xor_b32_e32 v33, v33, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v31, v31, v34
	v_xor_b32_e32 v30, v30, v34
	v_lshrrev_b32_e32 v34, 29, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v36, v33
	v_lshrrev_b32_e32 v18, 30, v18
	v_lshlrev_b32_e32 v34, 31, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v36, 32, v36
	v_or_b32_e32 v37, 0.5, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v35, 31, v36
	v_lshlrev_b32_e32 v38, 23, v36
	v_alignbit_b32 v33, v33, v31, v35
	v_alignbit_b32 v30, v31, v30, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v37, v37, v38
	v_alignbit_b32 v31, v33, v30, 9
	v_lshrrev_b32_e32 v33, 9, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v35, v31
	v_min_u32_e32 v35, 32, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v39, 31, v35
	v_alignbit_b32 v30, v31, v30, v39
	v_or_b32_e32 v31, v33, v37
	v_add_lshl_u32 v33, v35, v36, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v30, 9, v30
	v_mul_f32_e32 v35, 0x3fc90fda, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v30, v30, v33
	v_fma_f32 v33, 0x3fc90fda, v31, -v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v30, 0x33000000, v30
	v_fmac_f32_e32 v33, 0x33a22168, v31
	v_add_nc_u32_e32 v31, v32, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v30, v30, v34
	v_fmac_f32_e32 v33, 0x3fc90fda, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v30, v35, v33
.LBB0_22:                               ; %Flow233
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_and_not1_saveexec_b32 s0, s7
; %bb.23:                               ;   in Loop: Header=BB0_11 Depth=1
	v_mul_f32_e64 v18, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v18, v18
	v_fma_f32 v30, 0xbfc90fda, v18, |v2|
	v_cvt_i32_f32_e32 v31, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, 0xb3a22168, v18
	v_fmac_f32_e32 v30, 0xa7c234c4, v18
; %bb.24:                               ; %_ZL4sinff.exit164
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr32
                                        ; implicit-def: $vgpr18
	s_and_saveexec_b32 s0, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_11 Depth=1
	v_lshrrev_b32_e32 v37, 23, v25
	v_and_or_b32 v40, v25, s2, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v38, 0xffffff88, v37
	v_mad_u64_u32 v[32:33], null, 0xfe5163ab, v40, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v38
	v_cndmask_b32_e64 v39, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v18, v33 :: v_dual_add_nc_u32 v39, v39, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[33:34], null, 0x3c439041, v40, v[18:19]
	v_cmp_lt_u32_e64 s0, 31, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v41, 0, 0xffffffe0, s0
	v_dual_mov_b32 v18, v34 :: v_dual_add_nc_u32 v41, v41, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[34:35], null, 0xdb629599, v40, v[18:19]
	v_cmp_lt_u32_e64 s1, 31, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v18, v35
	v_cndmask_b32_e32 v32, v34, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[35:36], null, 0xf534ddc0, v40, v[18:19]
	v_dual_mov_b32 v18, v36 :: v_dual_cndmask_b32 v33, v35, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[36:37], null, 0xfc2757d1, v40, v[18:19]
	v_cndmask_b32_e64 v32, v33, v32, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v37
	v_mad_u64_u32 v[37:38], null, 0x4e441529, v40, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v18, v38
	v_mad_u64_u32 v[38:39], null, 0xa2f9836e, v40, v[18:19]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v40, v37, v35, vcc_lo
	v_add_nc_u32_e32 v18, v18, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v38, v38, v36 :: v_dual_cndmask_b32 v37, v39, v37
	v_cndmask_b32_e32 v36, v36, v34, vcc_lo
	v_sub_nc_u32_e32 v39, 32, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v35, v38, v40, s0
	v_cndmask_b32_e64 v37, v37, v38, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v38, v40, v36, s0
	v_cndmask_b32_e64 v36, v36, v33, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v37, v37, v35, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v35, v35, v38, s1
	v_cndmask_b32_e64 v38, v38, v36, s1
	v_cndmask_b32_e64 v32, v36, v32, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v37, v35, v39
	v_alignbit_b32 v34, v35, v38, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v18, v40, v37 :: v_dual_cndmask_b32 v33, v34, v35
	v_alignbit_b32 v37, v38, v32, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v34, v18, 29, 1
	v_alignbit_b32 v35, v18, v33, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v37, v37, v38, vcc_lo
	v_sub_nc_u32_e32 v36, 0, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v33, v33, v37, 30
	v_alignbit_b32 v32, v37, v32, 30
	v_xor_b32_e32 v35, v35, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v33, v33, v36
	v_xor_b32_e32 v32, v32, v36
	v_lshrrev_b32_e32 v36, 29, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v38, v35
	v_lshlrev_b32_e32 v36, 31, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v38, 32, v38
	v_or_b32_e32 v39, 0.5, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v37, 31, v38
	v_lshlrev_b32_e32 v40, 23, v38
	v_alignbit_b32 v35, v35, v33, v37
	v_alignbit_b32 v32, v33, v32, v37
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v39, v39, v40
	v_alignbit_b32 v33, v35, v32, 9
	v_lshrrev_b32_e32 v35, 9, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v37, v33
	v_min_u32_e32 v37, 32, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v41, 31, v37
	v_alignbit_b32 v32, v33, v32, v41
	v_or_b32_e32 v33, v35, v39
	v_add_lshl_u32 v35, v37, v38, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v32, 9, v32
	v_mul_f32_e32 v37, 0x3fc90fda, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v32, v32, v35
	v_fma_f32 v35, 0x3fc90fda, v33, -v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v32, 0x33000000, v32
	v_fmac_f32_e32 v35, 0x33a22168, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v32, v32, v36
	v_fmac_f32_e32 v35, 0x3fc90fda, v32
	v_lshrrev_b32_e32 v32, 30, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, v37, v35
	v_add_nc_u32_e32 v32, v34, v32
.LBB0_26:                               ; %Flow232
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_and_not1_saveexec_b32 s0, s6
; %bb.27:                               ;   in Loop: Header=BB0_11 Depth=1
	v_mul_f32_e64 v18, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v32, v18
	v_fma_f32 v18, 0xbfc90fda, v32, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, 0xb3a22168, v32
	v_fmac_f32_e32 v18, 0xa7c234c4, v32
	v_cvt_i32_f32_e32 v32, v32
; %bb.28:                               ; %_ZL4cosff.exit170
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v33, v26, v26 :: v_dual_and_b32 v34, 1, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v35, v28, v28 :: v_dual_fmaak_f32 v36, s3, v33, 0x3c0881c4
	v_dual_fmaak_f32 v37, s4, v33, 0xbab64f3b :: v_dual_fmaak_f32 v40, s4, v35, 0xbab64f3b
	v_lshlrev_b32_e32 v27, 30, v27
	v_dual_fmaak_f32 v39, s3, v35, 0x3c0881c4 :: v_dual_and_b32 v38, 1, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v36, v33, v36, 0xbe2aaa9d
	v_dual_fmaak_f32 v37, v33, v37, 0x3d2aabf7 :: v_dual_fmaak_f32 v40, v35, v40, 0x3d2aabf7
	v_lshlrev_b32_e32 v29, 30, v29
	v_cmp_eq_u32_e32 vcc_lo, 0, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v36, v33, v36 :: v_dual_fmaak_f32 v39, v35, v39, 0xbe2aaa9d
	v_dual_fmaak_f32 v37, v33, v37, 0xbf000004 :: v_dual_fmaak_f32 v40, v35, v40, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v26, v26, v36 :: v_dual_mul_f32 v39, v35, v39
	v_fma_f32 v33, v33, v37, 1.0
	v_and_b32_e32 v29, 0x80000000, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v35, v35, v40, 1.0
	v_fmac_f32_e32 v28, v28, v39
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v26, -v26, v33, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v38
	v_and_b32_e32 v27, 0x80000000, v27
	v_xor_b32_e32 v29, v25, v29
	v_cndmask_b32_e32 v28, v35, v28, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v27, v27, v26
	v_sub_f32_e32 v26, v9, v0
	v_xor3_b32 v28, v29, v28, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v28, 0x7fc00000, v28, vcc_lo
	v_cndmask_b32_e32 v29, 0x7fc00000, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v27, v8, v7 :: v_dual_mul_f32 v28, v26, v28
	v_dual_mul_f32 v33, v20, v4 :: v_dual_fmac_f32 v28, v27, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, 0.5, v33
	v_cmp_le_f32_e64 s0, |v28|, v29
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_36
; %bb.29:                               ;   in Loop: Header=BB0_11 Depth=1
	v_dual_mul_f32 v28, v30, v30 :: v_dual_and_b32 v29, 1, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v33, v18, v18 :: v_dual_fmaak_f32 v34, s3, v28, 0x3c0881c4
	v_dual_fmaak_f32 v38, s3, v33, 0x3c0881c4 :: v_dual_lshlrev_b32 v31, 30, v31
	v_dual_fmaak_f32 v37, s4, v33, 0xbab64f3b :: v_dual_lshlrev_b32 v36, 30, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v34, v28, v34, 0xbe2aaa9d
	v_fmaak_f32 v35, s4, v28, 0xbab64f3b
	v_fmaak_f32 v38, v33, v38, 0xbe2aaa9d
	v_and_b32_e32 v31, 0x80000000, v31
	v_cmp_eq_u32_e64 s0, 0, v29
	v_mul_f32_e32 v34, v28, v34
	v_dual_fmaak_f32 v35, v28, v35, 0x3d2aabf7 :: v_dual_and_b32 v32, 1, v32
	v_fmaak_f32 v37, v33, v37, 0x3d2aabf7
	v_xor_b32_e32 v25, v25, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v30, v30, v34 :: v_dual_fmaak_f32 v35, v28, v35, 0xbf000004
	v_and_b32_e32 v29, 0x80000000, v36
	v_fmaak_f32 v37, v33, v37, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v28, v28, v35, 1.0
	v_fma_f32 v31, v33, v37, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v28, v28, v30, s0
	v_cmp_eq_u32_e64 s0, 0, v32
	v_xor3_b32 v25, v25, v28, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v25, 0x7fc00000, v25, vcc_lo
	v_mul_f32_e32 v25, v27, v25
	v_dual_mul_f32 v27, v20, v5 :: v_dual_mul_f32 v38, v33, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v18, v18, v38
	v_cndmask_b32_e64 v18, -v18, v31, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v18, v29, v18
	v_cndmask_b32_e32 v18, 0x7fc00000, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v18, v26, v18, -v25
	v_mul_f32_e32 v25, 0.5, v27
	v_cmp_le_f32_e64 s0, |v18|, v25
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_36
; %bb.30:                               ;   in Loop: Header=BB0_11 Depth=1
	v_dual_mul_f32 v18, v20, v6 :: v_dual_sub_f32 v25, v10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, 0.5, v18
	v_cmp_le_f32_e64 s0, |v25|, v18
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_36
; %bb.31:                               ;   in Loop: Header=BB0_11 Depth=1
	s_waitcnt vmcnt(0)
	v_cmp_nle_f32_e32 vcc_lo, v24, v21
	v_cmp_neq_f32_e64 s0, 0, v3
	s_clause 0x1
	global_store_b128 v[11:12], v[4:7], off
	global_store_b96 v[11:12], v[0:2], off offset:16
	s_or_b32 s1, vcc_lo, s0
                                        ; implicit-def: $sgpr0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s1
	s_xor_b32 s1, exec_lo, s6
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_11 Depth=1
	s_mov_b32 s0, -1
	global_store_b32 v[13:14], v22, off
                                        ; implicit-def: $vgpr24
.LBB0_33:                               ; %Flow
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_saveexec_b32 s1, s1
	v_mov_b32_e32 v0, s0
	s_xor_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_11 Depth=1
	v_cvt_i32_f32_e32 v0, v24
	global_store_b32 v[13:14], v23, off
.LBB0_35:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	global_store_b32 v[15:16], v0, off
.LBB0_36:                               ; %Flow236
                                        ;   in Loop: Header=BB0_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v17, s19, v17
	s_add_i32 s18, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 0
	s_cbranch_scc1 .LBB0_11
.LBB0_37:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 42
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_, .Lfunc_end0-_Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4416
; NumSgprs: 22
; NumVgprs: 42
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 42
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z23get_roi_bbox_gpu_kerneliiiiifPKfS0_PKiS0_PiPfS3_S3_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     42
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
