// (c) Copyright 2013 Lev Barash, Landau Institute for Theoretical Physics, Russian Academy of Sciences
// This is supplement to the paper:
// L.Yu. Barash, L.N. Shchur, "PRAND: GPU accelerated parallel random number generation library: Using most reliable algorithms and applying parallelism of modern GPUs and CPUs".
// e-mail: barash @ itp.ac.ru (remove space)

#include<stdio.h>

#define gm31_CUDA_CALL(x) do { if((x) != cudaSuccess) { printf("Error: %s at %s:%d\n",cudaGetErrorString(cudaGetLastError()),__FILE__,__LINE__); exit(1);}} while(0)

#define gm31_BLOCKS  512
#define gm31_THREADS 128
#define gm31_ARRAY_SECTIONS  (gm31_BLOCKS*gm31_THREADS/32)

#define gm31_qg    30064771058ULL
#define gm31_g     2147483647
#define gm31_halfg 1073741824
#define gm31_k     11
#define gm31_q     14

typedef struct{
  unsigned xN[32],xP[32];
} gm31_state;

typedef struct{
  unsigned xN[64] __attribute__ ((aligned(16))),
           xP[64] __attribute__ ((aligned(16)));
} gm31_sse_state;

unsigned gm31_Consts[16] __attribute__ ((aligned(16))) =
{4294967222UL,36UL,4294967222UL,36UL,gm31_k,0,gm31_k,0,gm31_q,0,gm31_q,0,gm31_g,0,gm31_g,0};

__host__ unsigned int gm31_sse_generate_(gm31_sse_state* state){
  unsigned output1,output2;
  asm volatile("\n" \
      "movaps 48(%3),%%xmm5\n" \
      "\n" \
      "movaps (%1),%%xmm0\n" \
      "movaps %%xmm0,%%xmm7\n" \
      "movaps (%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm0\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm0\n" \
      "psubq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm0\n" \
      "paddq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,(%1)\n" \
      "movaps %%xmm7,(%2)\n" \
      "\n" \
      "movaps 16(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 16(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,16(%1)\n" \
      "movaps %%xmm7,16(%2)\n" \
      "\n" \
      "movaps 32(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 32(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,32(%1)\n" \
      "movaps %%xmm7,32(%2)\n" \
      "\n" \
      "movaps 48(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 48(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,48(%1)\n" \
      "movaps %%xmm7,48(%2)\n" \
      "\n" \
      "shufps $136,%%xmm1,%%xmm0\n" \
      "shufps $136,%%xmm3,%%xmm2\n" \
      "psrld  $30,%%xmm0\n" \
      "psrld  $30,%%xmm2\n" \
      "packssdw %%xmm2,%%xmm0\n" \
      "\n" \
      "movaps 64(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 64(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,64(%1)\n" \
      "movaps %%xmm7,64(%2)\n" \
      "\n" \
      "movaps 80(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 80(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,80(%1)\n" \
      "movaps %%xmm7,80(%2)\n" \
      "\n" \
      "movaps 96(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 96(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,96(%1)\n" \
      "movaps %%xmm7,96(%2)\n" \
      "\n" \
      "movaps 112(%1),%%xmm4\n" \
      "movaps %%xmm4,%%xmm7\n" \
      "movaps 112(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm4\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm4\n" \
      "psubq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm4\n" \
      "paddq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,112(%1)\n" \
      "movaps %%xmm7,112(%2)\n" \
      "\n" \
      "shufps $136,%%xmm2,%%xmm1\n" \
      "shufps $136,%%xmm4,%%xmm3\n" \
      "psrld  $30,%%xmm1\n" \
      "psrld  $30,%%xmm3\n" \
      "packssdw %%xmm3,%%xmm1\n" \
      "\n" \
      "packsswb %%xmm1,%%xmm0\n" \
      "psllw $7,%%xmm0\n" \
      "pmovmskb %%xmm0,%0\n" \
      "":"=r"(output1):"r"(state->xN),"r"(state->xP),"r"(gm31_Consts));
  asm volatile("\n" \
      "movaps 128(%1),%%xmm0\n" \
      "movaps %%xmm0,%%xmm7\n" \
      "movaps 128(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm0\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm0\n" \
      "psubq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm0\n" \
      "paddq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,128(%1)\n" \
      "movaps %%xmm7,128(%2)\n" \
      "\n" \
      "movaps 144(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 144(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,144(%1)\n" \
      "movaps %%xmm7,144(%2)\n" \
      "\n" \
      "movaps 160(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 160(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,160(%1)\n" \
      "movaps %%xmm7,160(%2)\n" \
      "\n" \
      "movaps 176(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 176(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,176(%1)\n" \
      "movaps %%xmm7,176(%2)\n" \
      "\n" \
      "shufps $136,%%xmm1,%%xmm0\n" \
      "shufps $136,%%xmm3,%%xmm2\n" \
      "psrld  $30,%%xmm0\n" \
      "psrld  $30,%%xmm2\n" \
      "packssdw %%xmm2,%%xmm0\n" \
      "\n" \
      "movaps 192(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 192(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,192(%1)\n" \
      "movaps %%xmm7,192(%2)\n" \
      "\n" \
      "movaps 208(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 208(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,208(%1)\n" \
      "movaps %%xmm7,208(%2)\n" \
      "\n" \
      "movaps 224(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 224(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,224(%1)\n" \
      "movaps %%xmm7,224(%2)\n" \
      "\n" \
      "movaps 240(%1),%%xmm4\n" \
      "movaps %%xmm4,%%xmm7\n" \
      "movaps 240(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm4\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm4\n" \
      "psubq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm4\n" \
      "paddq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,240(%1)\n" \
      "movaps %%xmm7,240(%2)\n" \
      "\n" \
      "shufps $136,%%xmm2,%%xmm1\n" \
      "shufps $136,%%xmm4,%%xmm3\n" \
      "psrld  $30,%%xmm1\n" \
      "psrld  $30,%%xmm3\n" \
      "packssdw %%xmm3,%%xmm1\n" \
      "\n" \
      "packsswb %%xmm1,%%xmm0\n" \
      "psllw $7,%%xmm0\n" \
      "pmovmskb %%xmm0,%0\n" \
      "shll $16,%0\n" \
      "":"=r"(output2):"r"(state->xN),"r"(state->xP),"r"(gm31_Consts));
  asm volatile("\n" \
      "addl %1,%0\n" \
      "\n" \
      "":"=r"(output2):"r"(output1),"0"(output2));
  return output2;
}

__device__ __host__ void gm31_get_sse_state_(gm31_state* state,gm31_sse_state* sse_state){
  int i;
  for(i=0;i<32;i++) {
    sse_state->xN[2*i]=state->xN[i]; sse_state->xP[2*i]=state->xP[i];
    sse_state->xN[2*i+1]=sse_state->xP[2*i+1]=0;
  }
}

__device__ __host__ unsigned gm31_mod_g(unsigned long long x){ // returns x (mod g)
  unsigned long long F,G; G=x;
  do{ F=(G>>31); G = (G-(F<<31)+F); } while(G>gm31_g);
  return G;
}

__device__ __host__ unsigned gm31_CNext(unsigned N,unsigned P){
  unsigned long long curr1,curr2,curr3;
  curr1=(unsigned long long)gm31_k*(unsigned long long)N; 
  curr2=(unsigned long long)gm31_q*(unsigned long long)P; 
  curr3=gm31_mod_g(gm31_qg+curr1-curr2); return curr3;
}

__device__ __host__ unsigned gm31_CNext2(unsigned N,unsigned P,unsigned myk,unsigned myq){
  unsigned long long curr1,curr2,curr3;
  curr1=(unsigned long long)myk*(unsigned long long)N;
  curr2=(unsigned long long)myq*(unsigned long long)P;
  curr3=gm31_mod_g((unsigned long long)myq*(unsigned long long)gm31_g+curr1-curr2);
  return curr3;
}

__device__ __host__ unsigned gm31_GetNextN(unsigned x0,unsigned x1,unsigned n){ // returns x_{2^n}
  unsigned myk=gm31_k,myq=gm31_q,i,x=x1;
  for(i=0;i<n;i++){
    x=gm31_CNext2(x,x0,myk,myq);
    myk=gm31_CNext2(myk,2,myk,myq);
    myq=gm31_CNext2(myq,0,myq,0);
  }
  return x;
}

__device__ __host__ unsigned gm31_GetNextAny(unsigned x0,unsigned x1,unsigned long long N){ // returns x_N
  unsigned long long i; unsigned xp=x0,xn=x1,xpnew,xnnew,shift=0;
  i=N; while(i>0){
    if(i%2==1){                        // xp,xn ----> 2^shift
      xpnew=gm31_GetNextN(xp,xn,shift);
      xnnew=gm31_GetNextN(xn,gm31_CNext(xn,xp),shift);
      xp=xpnew; xn=xnnew;
    }
    i/=2; shift++;
  }
  return xp;
}

__device__ __host__ void gm31_skipahead_(gm31_state* state, unsigned long long offset){
  unsigned xn,xp,j; 
  for(j=0;j<32;j++){
    xp=gm31_GetNextAny(state->xP[j],state->xN[j],offset);
    xn=gm31_GetNextAny(state->xP[j],state->xN[j],offset+1);
    state->xP[j]=xp; state->xN[j]=xn;
  }
}

__device__ __host__ void gm31_init_(gm31_state* state){
  unsigned x0=554937932UL,x1=1253942293UL,xp,xn,j;
  for(j=0;j<32;j++){
    xp=gm31_GetNextAny(x0,x1,144115183781032008ULL);
    xn=gm31_GetNextAny(x0,x1,144115183781032009ULL);
    state->xP[j]=xp; state->xN[j]=xn; x0=xp; x1=xn;
  }
}

__device__ __host__ void gm31_init_short_sequence_(gm31_state* state,unsigned SequenceNumber){
  gm31_init_(state);                     // 0 <= SequenceNumber < 10^9;   length of each sequence <= 8*10^7
  gm31_skipahead_(state,82927047ULL*(unsigned long long)SequenceNumber);
}

__device__ __host__ void gm31_init_medium_sequence_(gm31_state* state,unsigned SequenceNumber){
  gm31_init_(state);                     // 0 <= SequenceNumber < 10^7;   length of each sequence <= 8*10^9
  gm31_skipahead_(state,8799201913ULL*(unsigned long long)SequenceNumber);
}

__device__ __host__ void gm31_init_long_sequence_(gm31_state* state,unsigned SequenceNumber){
  gm31_init_(state);                     // 0 <= SequenceNumber < 10^5;   length of each sequence <= 8*10^11
  gm31_skipahead_(state,828317697521ULL*(unsigned long long)SequenceNumber);
}

__device__ __host__ unsigned int gm31_generate_(gm31_state* state){
  int i; unsigned temp,sum=0,bit=1;
  for(i=0;i<32;i++){
    temp=gm31_CNext(state->xN[i],state->xP[i]);
    state->xP[i]=state->xN[i]; state->xN[i]=temp;
    sum += ((temp<gm31_halfg)?0:bit); bit*=2;
  }
  return sum;
}

__device__ __host__ float gm31_generate_uniform_float_(gm31_state* state){
  int i; unsigned temp,sum=0,bit=1;
  for(i=0;i<32;i++){
    temp=gm31_CNext(state->xN[i],state->xP[i]);
    state->xP[i]=state->xN[i]; state->xN[i]=temp;
    sum += ((temp<gm31_halfg)?0:bit); bit*=2;
  }
  return ((float) sum) * 2.3283064365386963e-10;
}

__host__ void gm31_print_state_(gm31_state* state){int i;
    printf("Generator State:\nxN={");
    for(i=0;i<32;i++) {printf("%u",state->xN[i]%gm31_g); printf((i<31)?",":"}\nxP={");}
    for(i=0;i<32;i++) {printf("%u",state->xP[i]%gm31_g); printf((i<31)?",":"}\n\n");}
}

__host__ void gm31_print_sse_state_(gm31_sse_state* state){int i;
    printf("Generator State:\nxN={");
    for(i=0;i<32;i++) {printf("%u",state->xN[2*i]%gm31_g); printf((i<31)?",":"}\nxP={");}
    for(i=0;i<32;i++) {printf("%u",state->xP[2*i]%gm31_g); printf((i<31)?",":"}\n\n");}
}

__global__ void gm31_kernel_generate_array(gm31_state* state, unsigned int* out, long* length) {
    unsigned temp,i,orbit,seqNum; long offset;

    __shared__ unsigned xP[gm31_THREADS];  // one generator per s=32 threads, i.e. one orbit
    __shared__ unsigned xN[gm31_THREADS];  // per thread, i.e. blockDim.x orbits per block
    __shared__ unsigned  a[gm31_THREADS];  // array "a" contains corresponding parts of output

    orbit   = threadIdx.x % 32;
    seqNum  = (threadIdx.x + blockIdx.x * blockDim.x)>>5;  // RNG_sequence index
    offset  = seqNum*(*length);                            // start of the section in the output array

    xP[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset);
    xN[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset+1);

    for(i=0;i<(*length);i++){       // each s=32 threads result in "length" values in the output array

      temp = gm31_CNext( xN[threadIdx.x], xP[threadIdx.x] );
      xP[threadIdx.x] = xN[threadIdx.x]; xN[threadIdx.x] = temp; 
      a[threadIdx.x]  = (temp < gm31_halfg ? 0 : (1<<orbit) );

      __syncthreads();
      if((orbit&3)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+1]+a[threadIdx.x+2]+a[threadIdx.x+3];
      __syncthreads();
      if((orbit&15)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+4]+a[threadIdx.x+8]+a[threadIdx.x+12];
      __syncthreads();
      if(orbit==0){ out[offset+i]=a[threadIdx.x]+a[threadIdx.x+16]; }

    }
}

__host__ void gm31_generate_gpu_array_(gm31_state* state, unsigned int* dev_out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(cudaMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(cudaMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(cudaMemcpy(dev_state,state,sizeof(gm31_state),cudaMemcpyHostToDevice));
   gm31_CUDA_CALL(cudaMemcpy(dev_length,&mylength,sizeof(long),cudaMemcpyHostToDevice));

   gm31_kernel_generate_array<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(cudaGetLastError());
   
   gm31_CUDA_CALL(cudaFree(dev_state)); gm31_CUDA_CALL(cudaFree(dev_length));

}

__global__ void gm31_kernel_generate_array_float(gm31_state* state, float* out, long* length) {
    unsigned temp,sum,i,orbit,seqNum; long offset;

    __shared__ unsigned xP[gm31_THREADS];  // one generator per s=32 threads, i.e. one orbit
    __shared__ unsigned xN[gm31_THREADS];  // per thread, i.e. blockDim.x orbits per block
    __shared__ unsigned  a[gm31_THREADS];  // array "a" contains corresponding parts of output

    orbit   = threadIdx.x % 32;
    seqNum  = (threadIdx.x + blockIdx.x * blockDim.x)>>5;  // RNG_sequence index
    offset  = seqNum*(*length);                            // start of the section in the output array

    xP[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset);
    xN[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset+1);

    for(i=0;i<(*length);i++){       // each s=32 threads result in "length" values in the output array

      temp = gm31_CNext( xN[threadIdx.x], xP[threadIdx.x] );
      xP[threadIdx.x] = xN[threadIdx.x]; xN[threadIdx.x] = temp; 
      a[threadIdx.x]  = (temp < gm31_halfg ? 0 : (1<<orbit) );

      __syncthreads();
      if((orbit&3)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+1]+a[threadIdx.x+2]+a[threadIdx.x+3];
      __syncthreads();
      if((orbit&15)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+4]+a[threadIdx.x+8]+a[threadIdx.x+12];
      __syncthreads();
      if(orbit==0){ sum=a[threadIdx.x]+a[threadIdx.x+16];  out[offset+i]=((float)sum) * 2.3283064365386963e-10; }

    }
}

__host__ void gm31_generate_gpu_array_float_(gm31_state* state, float* dev_out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(cudaMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(cudaMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(cudaMemcpy(dev_state,state,sizeof(gm31_state),cudaMemcpyHostToDevice));
   gm31_CUDA_CALL(cudaMemcpy(dev_length,&mylength,sizeof(long),cudaMemcpyHostToDevice));

   gm31_kernel_generate_array_float<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(cudaGetLastError());
   
   gm31_CUDA_CALL(cudaFree(dev_state)); gm31_CUDA_CALL(cudaFree(dev_length));

}

__global__ void gm31_kernel_generate_array_double(gm31_state* state, double* out, long* length) {
    unsigned temp,sum,i,orbit,seqNum; long offset;

    __shared__ unsigned xP[gm31_THREADS];  // one generator per s=32 threads, i.e. one orbit
    __shared__ unsigned xN[gm31_THREADS];  // per thread, i.e. blockDim.x orbits per block
    __shared__ unsigned  a[gm31_THREADS];  // array "a" contains corresponding parts of output

    orbit   = threadIdx.x % 32;
    seqNum  = (threadIdx.x + blockIdx.x * blockDim.x)>>5;  // RNG_sequence index
    offset  = seqNum*(*length);                            // start of the section in the output array

    xP[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset);
    xN[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset+1);

    for(i=0;i<(*length);i++){       // each s=32 threads result in "length" values in the output array

      temp = gm31_CNext( xN[threadIdx.x], xP[threadIdx.x] );
      xP[threadIdx.x] = xN[threadIdx.x]; xN[threadIdx.x] = temp; 
      a[threadIdx.x]  = (temp < gm31_halfg ? 0 : (1<<orbit) );

      __syncthreads();
      if((orbit&3)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+1]+a[threadIdx.x+2]+a[threadIdx.x+3];
      __syncthreads();
      if((orbit&15)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+4]+a[threadIdx.x+8]+a[threadIdx.x+12];
      __syncthreads();
      if(orbit==0){ sum=a[threadIdx.x]+a[threadIdx.x+16];  out[offset+i]=((double)sum) * 2.3283064365386963e-10; }

    }
}

__host__ void gm31_generate_gpu_array_double_(gm31_state* state, double* dev_out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(cudaMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(cudaMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(cudaMemcpy(dev_state,state,sizeof(gm31_state),cudaMemcpyHostToDevice));
   gm31_CUDA_CALL(cudaMemcpy(dev_length,&mylength,sizeof(long),cudaMemcpyHostToDevice));

   gm31_kernel_generate_array_double<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(cudaGetLastError());
   
   gm31_CUDA_CALL(cudaFree(dev_state)); gm31_CUDA_CALL(cudaFree(dev_length));

}

__host__ void gm31_generate_array_(gm31_state* state, unsigned int* out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   unsigned int* dev_out;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(cudaMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(cudaMalloc((void**)&dev_out,mylength*gm31_ARRAY_SECTIONS*sizeof(unsigned int)));
   gm31_CUDA_CALL(cudaMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(cudaMemcpy(dev_state,state,sizeof(gm31_state),cudaMemcpyHostToDevice));
   gm31_CUDA_CALL(cudaMemcpy(dev_length,&mylength,sizeof(long),cudaMemcpyHostToDevice));

   gm31_kernel_generate_array<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(cudaGetLastError());
   
   gm31_CUDA_CALL(cudaMemcpy(out,dev_out,length*sizeof(unsigned int),cudaMemcpyDeviceToHost));
   gm31_CUDA_CALL(cudaFree(dev_state)); gm31_CUDA_CALL(cudaFree(dev_out)); 
   gm31_CUDA_CALL(cudaFree(dev_length));

}

	.file	"tmpxft_00302122_00000000-6__gm31.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2049:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2049:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z18gm31_sse_generate_P14gm31_sse_state
	.type	_Z18gm31_sse_generate_P14gm31_sse_state, @function
_Z18gm31_sse_generate_P14gm31_sse_state:
.LFB2027:
	.cfi_startproc
	endbr64
	leaq	256(%rdi), %rax
	leaq	gm31_Consts(%rip), %rdx
#APP
# 34 "/home/ubuntu/Datasets/stackv2/train-structured/sbinet-staging/3photons/master/Random/aesb_v1_0/source/_gm31.cu" 1
	
movaps 48(%rdx),%xmm5

movaps (%rdi),%xmm0
movaps %xmm0,%xmm7
movaps (%rax),%xmm6
pmuludq 16(%rdx),%xmm0
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm0
psubq %xmm6,%xmm0
movaps %xmm0,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm0
paddq %xmm6,%xmm0
movaps %xmm0,(%rdi)
movaps %xmm7,(%rax)

movaps 16(%rdi),%xmm1
movaps %xmm1,%xmm7
movaps 16(%rax),%xmm6
pmuludq 16(%rdx),%xmm1
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm1
psubq %xmm6,%xmm1
movaps %xmm1,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm1
paddq %xmm6,%xmm1
movaps %xmm1,16(%rdi)
movaps %xmm7,16(%rax)

movaps 32(%rdi),%xmm2
movaps %xmm2,%xmm7
movaps 32(%rax),%xmm6
pmuludq 16(%rdx),%xmm2
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm2
psubq %xmm6,%xmm2
movaps %xmm2,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm2
paddq %xmm6,%xmm2
movaps %xmm2,32(%rdi)
movaps %xmm7,32(%rax)

movaps 48(%rdi),%xmm3
movaps %xmm3,%xmm7
movaps 48(%rax),%xmm6
pmuludq 16(%rdx),%xmm3
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm3
psubq %xmm6,%xmm3
movaps %xmm3,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm3
paddq %xmm6,%xmm3
movaps %xmm3,48(%rdi)
movaps %xmm7,48(%rax)

shufps $136,%xmm1,%xmm0
shufps $136,%xmm3,%xmm2
psrld  $30,%xmm0
psrld  $30,%xmm2
packssdw %xmm2,%xmm0

movaps 64(%rdi),%xmm1
movaps %xmm1,%xmm7
movaps 64(%rax),%xmm6
pmuludq 16(%rdx),%xmm1
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm1
psubq %xmm6,%xmm1
movaps %xmm1,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm1
paddq %xmm6,%xmm1
movaps %xmm1,64(%rdi)
movaps %xmm7,64(%rax)

movaps 80(%rdi),%xmm2
movaps %xmm2,%xmm7
movaps 80(%rax),%xmm6
pmuludq 16(%rdx),%xmm2
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm2
psubq %xmm6,%xmm2
movaps %xmm2,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm2
paddq %xmm6,%xmm2
movaps %xmm2,80(%rdi)
movaps %xmm7,80(%rax)

movaps 96(%rdi),%xmm3
movaps %xmm3,%xmm7
movaps 96(%rax),%xmm6
pmuludq 16(%rdx),%xmm3
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm3
psubq %xmm6,%xmm3
movaps %xmm3,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm3
paddq %xmm6,%xmm3
movaps %xmm3,96(%rdi)
movaps %xmm7,96(%rax)

movaps 112(%rdi),%xmm4
movaps %xmm4,%xmm7
movaps 112(%rax),%xmm6
pmuludq 16(%rdx),%xmm4
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm4
psubq %xmm6,%xmm4
movaps %xmm4,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm4
paddq %xmm6,%xmm4
movaps %xmm4,112(%rdi)
movaps %xmm7,112(%rax)

shufps $136,%xmm2,%xmm1
shufps $136,%xmm4,%xmm3
psrld  $30,%xmm1
psrld  $30,%xmm3
packssdw %xmm3,%xmm1

packsswb %xmm1,%xmm0
psllw $7,%xmm0
pmovmskb %xmm0,%ecx

# 0 "" 2
# 165 "/home/ubuntu/Datasets/stackv2/train-structured/sbinet-staging/3photons/master/Random/aesb_v1_0/source/_gm31.cu" 1
	
movaps 128(%rdi),%xmm0
movaps %xmm0,%xmm7
movaps 128(%rax),%xmm6
pmuludq 16(%rdx),%xmm0
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm0
psubq %xmm6,%xmm0
movaps %xmm0,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm0
paddq %xmm6,%xmm0
movaps %xmm0,128(%rdi)
movaps %xmm7,128(%rax)

movaps 144(%rdi),%xmm1
movaps %xmm1,%xmm7
movaps 144(%rax),%xmm6
pmuludq 16(%rdx),%xmm1
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm1
psubq %xmm6,%xmm1
movaps %xmm1,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm1
paddq %xmm6,%xmm1
movaps %xmm1,144(%rdi)
movaps %xmm7,144(%rax)

movaps 160(%rdi),%xmm2
movaps %xmm2,%xmm7
movaps 160(%rax),%xmm6
pmuludq 16(%rdx),%xmm2
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm2
psubq %xmm6,%xmm2
movaps %xmm2,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm2
paddq %xmm6,%xmm2
movaps %xmm2,160(%rdi)
movaps %xmm7,160(%rax)

movaps 176(%rdi),%xmm3
movaps %xmm3,%xmm7
movaps 176(%rax),%xmm6
pmuludq 16(%rdx),%xmm3
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm3
psubq %xmm6,%xmm3
movaps %xmm3,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm3
paddq %xmm6,%xmm3
movaps %xmm3,176(%rdi)
movaps %xmm7,176(%rax)

shufps $136,%xmm1,%xmm0
shufps $136,%xmm3,%xmm2
psrld  $30,%xmm0
psrld  $30,%xmm2
packssdw %xmm2,%xmm0

movaps 192(%rdi),%xmm1
movaps %xmm1,%xmm7
movaps 192(%rax),%xmm6
pmuludq 16(%rdx),%xmm1
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm1
psubq %xmm6,%xmm1
movaps %xmm1,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm1
paddq %xmm6,%xmm1
movaps %xmm1,192(%rdi)
movaps %xmm7,192(%rax)

movaps 208(%rdi),%xmm2
movaps %xmm2,%xmm7
movaps 208(%rax),%xmm6
pmuludq 16(%rdx),%xmm2
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm2
psubq %xmm6,%xmm2
movaps %xmm2,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm2
paddq %xmm6,%xmm2
movaps %xmm2,208(%rdi)
movaps %xmm7,208(%rax)

movaps 224(%rdi),%xmm3
movaps %xmm3,%xmm7
movaps 224(%rax),%xmm6
pmuludq 16(%rdx),%xmm3
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm3
psubq %xmm6,%xmm3
movaps %xmm3,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm3
paddq %xmm6,%xmm3
movaps %xmm3,224(%rdi)
movaps %xmm7,224(%rax)

movaps 240(%rdi),%xmm4
movaps %xmm4,%xmm7
movaps 240(%rax),%xmm6
pmuludq 16(%rdx),%xmm4
pmuludq 32(%rdx),%xmm6
paddq (%rdx),%xmm4
psubq %xmm6,%xmm4
movaps %xmm4,%xmm6
psrlq $31,%xmm6
andps %xmm5,%xmm4
paddq %xmm6,%xmm4
movaps %xmm4,240(%rdi)
movaps %xmm7,240(%rax)

shufps $136,%xmm2,%xmm1
shufps $136,%xmm4,%xmm3
psrld  $30,%xmm1
psrld  $30,%xmm3
packssdw %xmm3,%xmm1

packsswb %xmm1,%xmm0
psllw $7,%xmm0
pmovmskb %xmm0,%eax
shll $16,%eax

# 0 "" 2
# 295 "/home/ubuntu/Datasets/stackv2/train-structured/sbinet-staging/3photons/master/Random/aesb_v1_0/source/_gm31.cu" 1
	
addl %ecx,%eax


# 0 "" 2
#NO_APP
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z18gm31_sse_generate_P14gm31_sse_state, .-_Z18gm31_sse_generate_P14gm31_sse_state
	.globl	_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state
	.type	_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state, @function
_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state:
.LFB2028:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L4:
	movl	(%rdi,%rax,4), %edx
	movl	%edx, (%rsi,%rax,8)
	movl	128(%rdi,%rax,4), %edx
	movl	%edx, 256(%rsi,%rax,8)
	xorl	%edx, %edx
	movl	%edx, 260(%rsi,%rax,8)
	movl	%edx, 4(%rsi,%rax,8)
	incq	%rax
	cmpq	$32, %rax
	jne	.L4
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state, .-_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state
	.globl	_Z10gm31_mod_gy
	.type	_Z10gm31_mod_gy, @function
_Z10gm31_mod_gy:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	movl	$2147483648, %edx
.L8:
	movq	%rax, %rcx
	andl	$2147483647, %eax
	shrq	$31, %rcx
	addq	%rcx, %rax
	cmpq	%rdx, %rax
	jnb	.L8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z10gm31_mod_gy, .-_Z10gm31_mod_gy
	.globl	_Z10gm31_CNextjj
	.type	_Z10gm31_CNextjj, @function
_Z10gm31_CNextjj:
.LFB2030:
	.cfi_startproc
	endbr64
	movabsq	$30064771058, %rax
	movl	%edi, %edi
	movl	%esi, %esi
	imulq	$11, %rdi, %rdi
	imulq	$14, %rsi, %rsi
	subq	%rsi, %rdi
	addq	%rax, %rdi
	jmp	_Z10gm31_mod_gy
	.cfi_endproc
.LFE2030:
	.size	_Z10gm31_CNextjj, .-_Z10gm31_CNextjj
	.globl	_Z11gm31_CNext2jjjj
	.type	_Z11gm31_CNext2jjjj, @function
_Z11gm31_CNext2jjjj:
.LFB2031:
	.cfi_startproc
	endbr64
	movl	%edi, %eax
	movl	%esi, %esi
	movl	$2147483647, %edi
	movl	%ecx, %ecx
	subq	%rsi, %rdi
	movl	%edx, %edx
	imulq	%rcx, %rdi
	imulq	%rax, %rdx
	addq	%rdx, %rdi
	jmp	_Z10gm31_mod_gy
	.cfi_endproc
.LFE2031:
	.size	_Z11gm31_CNext2jjjj, .-_Z11gm31_CNext2jjjj
	.globl	_Z13gm31_GetNextNjjj
	.type	_Z13gm31_GetNextNjjj, @function
_Z13gm31_GetNextNjjj:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%edx, %r11d
	movl	%esi, %r9d
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	$14, %r8d
	movl	%edi, %ebx
	movl	$11, %r10d
.L13:
	cmpq	%r11, %rbp
	je	.L16
	movl	%r8d, %ecx
	movl	%r10d, %edx
	movl	%r9d, %edi
	movl	%ebx, %esi
	call	_Z11gm31_CNext2jjjj
	movl	%r8d, %ecx
	movl	%r10d, %edx
	movl	%r10d, %edi
	movl	$2, %esi
	movl	%eax, %r9d
	incq	%rbp
	call	_Z11gm31_CNext2jjjj
	movl	%r8d, %edi
	imulq	%rdi, %rdi
	movl	%eax, %r10d
	call	_Z10gm31_mod_gy
	movl	%eax, %r8d
	jmp	.L13
.L16:
	movl	%r9d, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z13gm31_GetNextNjjj, .-_Z13gm31_GetNextNjjj
	.globl	_Z15gm31_GetNextAnyjjy
	.type	_Z15gm31_GetNextAnyjjy, @function
_Z15gm31_GetNextAnyjjy:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%esi, %ebx
.L18:
	testq	%r12, %r12
	je	.L25
	testl	$1, %r12d
	je	.L19
	movl	%r13d, %edx
	movl	%ebx, %esi
	movl	%ebp, %edi
	call	_Z13gm31_GetNextNjjj
	movl	%ebp, %esi
	movl	%ebx, %edi
	movl	%eax, %r14d
	call	_Z10gm31_CNextjj
	movl	%ebx, %edi
	movl	%r13d, %edx
	movl	%r14d, %ebp
	movl	%eax, %esi
	call	_Z13gm31_GetNextNjjj
	movl	%eax, %ebx
.L19:
	shrq	%r12
	incl	%r13d
	jmp	.L18
.L25:
	popq	%rbx
	.cfi_def_cfa_offset 40
	movl	%ebp, %eax
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z15gm31_GetNextAnyjjy, .-_Z15gm31_GetNextAnyjjy
	.globl	_Z15gm31_skipahead_P10gm31_statey
	.type	_Z15gm31_skipahead_P10gm31_statey, @function
_Z15gm31_skipahead_P10gm31_statey:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	1(%rsi), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	leaq	128(%rdi), %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	pushq	%rdx
	.cfi_def_cfa_offset 64
.L27:
	movl	(%rbx), %r15d
	movl	128(%rbx), %edi
	movq	%rbp, %rdx
	addq	$4, %rbx
	movl	%r15d, %esi
	movl	%edi, 4(%rsp)
	call	_Z15gm31_GetNextAnyjjy
	movl	4(%rsp), %edi
	movq	%r14, %rdx
	movl	%r15d, %esi
	movl	%eax, %r12d
	call	_Z15gm31_GetNextAnyjjy
	movl	%r12d, 124(%rbx)
	movl	%eax, -4(%rbx)
	cmpq	%r13, %rbx
	jne	.L27
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z15gm31_skipahead_P10gm31_statey, .-_Z15gm31_skipahead_P10gm31_statey
	.globl	_Z10gm31_init_P10gm31_state
	.type	_Z10gm31_init_P10gm31_state, @function
_Z10gm31_init_P10gm31_state:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movabsq	$144115183781032008, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	$554937932, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	$1253942293, %ebx
.L31:
	movl	%ebx, %esi
	movl	%r12d, %edi
	movl	%r12d, %r15d
	movq	%r14, %rdx
	call	_Z15gm31_GetNextAnyjjy
	movl	%ebx, %esi
	movl	%r15d, %edi
	movabsq	$144115183781032009, %rdx
	movl	%eax, %r12d
	call	_Z15gm31_GetNextAnyjjy
	movl	%r12d, 128(%r13,%rbp)
	movl	%eax, 0(%r13,%rbp)
	addq	$4, %rbp
	movl	%eax, %ebx
	cmpq	$128, %rbp
	jne	.L31
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z10gm31_init_P10gm31_state, .-_Z10gm31_init_P10gm31_state
	.globl	_Z25gm31_init_short_sequence_P10gm31_statej
	.type	_Z25gm31_init_short_sequence_P10gm31_statej, @function
_Z25gm31_init_short_sequence_P10gm31_statej:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%esi, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 24
	movq	%rdi, (%rsp)
	call	_Z10gm31_init_P10gm31_state
	movl	%ebx, %esi
	movq	(%rsp), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 16
	imulq	$82927047, %rsi, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_Z15gm31_skipahead_P10gm31_statey
	.cfi_endproc
.LFE2036:
	.size	_Z25gm31_init_short_sequence_P10gm31_statej, .-_Z25gm31_init_short_sequence_P10gm31_statej
	.globl	_Z26gm31_init_medium_sequence_P10gm31_statej
	.type	_Z26gm31_init_medium_sequence_P10gm31_statej, @function
_Z26gm31_init_medium_sequence_P10gm31_statej:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%esi, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 24
	movq	%rdi, (%rsp)
	call	_Z10gm31_init_P10gm31_state
	movl	%ebx, %esi
	movq	(%rsp), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 16
	movabsq	$8799201913, %rax
	popq	%rbx
	.cfi_def_cfa_offset 8
	imulq	%rax, %rsi
	jmp	_Z15gm31_skipahead_P10gm31_statey
	.cfi_endproc
.LFE2037:
	.size	_Z26gm31_init_medium_sequence_P10gm31_statej, .-_Z26gm31_init_medium_sequence_P10gm31_statej
	.globl	_Z24gm31_init_long_sequence_P10gm31_statej
	.type	_Z24gm31_init_long_sequence_P10gm31_statej, @function
_Z24gm31_init_long_sequence_P10gm31_statej:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%esi, %ebx
	pushq	%rax
	.cfi_def_cfa_offset 24
	movq	%rdi, (%rsp)
	call	_Z10gm31_init_P10gm31_state
	movl	%ebx, %esi
	movq	(%rsp), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 16
	movabsq	$828317697521, %rax
	popq	%rbx
	.cfi_def_cfa_offset 8
	imulq	%rax, %rsi
	jmp	_Z15gm31_skipahead_P10gm31_statey
	.cfi_endproc
.LFE2038:
	.size	_Z24gm31_init_long_sequence_P10gm31_statej, .-_Z24gm31_init_long_sequence_P10gm31_statej
	.globl	_Z14gm31_generate_P10gm31_state
	.type	_Z14gm31_generate_P10gm31_state, @function
_Z14gm31_generate_P10gm31_state:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %r8
	movl	$1, %r10d
	xorl	%r9d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebp, %ebp
	leaq	128(%rdi), %rbx
.L42:
	movl	(%r8), %r11d
	movl	128(%r8), %esi
	movl	%r11d, %edi
	call	_Z10gm31_CNextjj
	movl	%r11d, 128(%r8)
	cmpl	$1073741824, %eax
	movl	%eax, (%r8)
	movl	%ebp, %eax
	cmovnb	%r10d, %eax
	addq	$4, %r8
	addl	%r10d, %r10d
	addl	%eax, %r9d
	cmpq	%rbx, %r8
	jne	.L42
	movl	%r9d, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z14gm31_generate_P10gm31_state, .-_Z14gm31_generate_P10gm31_state
	.globl	_Z28gm31_generate_uniform_float_P10gm31_state
	.type	_Z28gm31_generate_uniform_float_P10gm31_state, @function
_Z28gm31_generate_uniform_float_P10gm31_state:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %r8
	movl	$1, %r10d
	xorl	%r9d, %r9d
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	xorl	%ebp, %ebp
	leaq	128(%rdi), %rbx
.L48:
	movl	(%r8), %r11d
	movl	128(%r8), %esi
	movl	%r11d, %edi
	call	_Z10gm31_CNextjj
	movl	%r11d, 128(%r8)
	cmpl	$1073741824, %eax
	movl	%eax, (%r8)
	movl	%ebp, %eax
	cmovnb	%r10d, %eax
	addq	$4, %r8
	addl	%r10d, %r10d
	addl	%eax, %r9d
	cmpq	%rbx, %r8
	jne	.L48
	cvtsi2ssq	%r9, %xmm0
	mulss	.LC0(%rip), %xmm0
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z28gm31_generate_uniform_float_P10gm31_state, .-_Z28gm31_generate_uniform_float_P10gm31_state
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	","
.LC2:
	.string	"}\nxP={"
.LC3:
	.string	"}\n\n"
.LC4:
	.string	"Generator State:\nxN={"
.LC5:
	.string	"%u"
	.text
	.globl	_Z17gm31_print_state_P10gm31_state
	.type	_Z17gm31_print_state_P10gm31_state, @function
_Z17gm31_print_state_P10gm31_state:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	.LC5(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	movl	$2, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
.L56:
	movl	0(%rbp,%rbx,4), %eax
	movl	$2147483647, %ecx
	xorl	%edx, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	divl	%ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$31, %rbx
	movl	$2, %edi
	leaq	.LC1(%rip), %rax
	leaq	.LC2(%rip), %rsi
	cmovne	%rax, %rsi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$32, %rbx
	jne	.L56
	xorl	%ebx, %ebx
	leaq	.LC3(%rip), %r13
.L58:
	movl	$2147483647, %ecx
	xorl	%edx, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	movl	128(%rbp,%rbx,4), %eax
	divl	%ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$31, %rbx
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	cmove	%r13, %rsi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$32, %rbx
	jne	.L58
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z17gm31_print_state_P10gm31_state, .-_Z17gm31_print_state_P10gm31_state
	.globl	_Z21gm31_print_sse_state_P14gm31_sse_state
	.type	_Z21gm31_print_sse_state_P14gm31_sse_state, @function
_Z21gm31_print_sse_state_P14gm31_sse_state:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	.LC5(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	movl	$2, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rdx
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
.L66:
	movl	0(%rbp,%rbx,8), %eax
	movl	$2147483647, %ecx
	xorl	%edx, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	divl	%ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$31, %rbx
	movl	$2, %edi
	leaq	.LC1(%rip), %rax
	leaq	.LC2(%rip), %rsi
	cmovne	%rax, %rsi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$32, %rbx
	jne	.L66
	xorl	%ebx, %ebx
	leaq	.LC3(%rip), %r13
.L68:
	movl	$2147483647, %ecx
	xorl	%edx, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	movl	256(%rbp,%rbx,8), %eax
	divl	%ecx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	$31, %rbx
	movl	$2, %edi
	leaq	.LC1(%rip), %rsi
	cmove	%r13, %rsi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$32, %rbx
	jne	.L68
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z21gm31_print_sse_state_P14gm31_sse_state, .-_Z21gm31_print_sse_state_P14gm31_sse_state
	.globl	_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl
	.type	_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl, @function
_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L74:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl, .-_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl
	.globl	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl
	.type	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl, @function
_Z26gm31_kernel_generate_arrayP10gm31_statePjPl:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl
	.cfi_endproc
.LFE2072:
	.size	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl, .-_Z26gm31_kernel_generate_arrayP10gm31_statePjPl
	.section	.rodata.str1.1
.LC6:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/sbinet-staging/3photons/master/Random/aesb_v1_0/source/_gm31.cu"
.LC7:
	.string	"Error: %s at %s:%d\n"
	.text
	.globl	_Z24gm31_generate_gpu_array_P10gm31_statePjl
	.type	_Z24gm31_generate_gpu_array_P10gm31_statePjl, @function
_Z24gm31_generate_gpu_array_P10gm31_statePjl:
.LFB2043:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdx, %rcx
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rsi, %rbx
	movl	$2048, %esi
	subq	$72, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rdx, %rax
	cqto
	idivq	%rsi
	movq	%rax, %rdx
	salq	$11, %rdx
	cmpq	%rcx, %rdx
	jge	.L80
	incq	%rax
.L80:
	leaq	16(%rsp), %rdi
	movl	$256, %esi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L81
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$457, %r8d
	movq	%rax, %rdx
	jmp	.L91
.L81:
	leaq	24(%rsp), %rdi
	movl	$8, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L82
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$458, %r8d
	movq	%rax, %rdx
.L91:
	movl	$2, %edi
	leaq	.LC6(%rip), %rcx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L82:
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$256, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L83
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$459, %r8d
	movq	%rax, %rdx
	jmp	.L91
.L83:
	movq	24(%rsp), %rdi
	leaq	8(%rsp), %rsi
	movl	$1, %ecx
	movl	$8, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L84
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$460, %r8d
	movq	%rax, %rdx
	jmp	.L91
.L84:
	movl	$33554433, %edx
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L85
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	call	_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl
.L85:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L86
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$463, %r8d
	movq	%rax, %rdx
	jmp	.L91
.L86:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	jne	.L92
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	je	.L79
.L92:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$465, %r8d
	movq	%rax, %rdx
	jmp	.L91
.L79:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L89
	call	__stack_chk_fail@PLT
.L89:
	addq	$72, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2043:
	.size	_Z24gm31_generate_gpu_array_P10gm31_statePjl, .-_Z24gm31_generate_gpu_array_P10gm31_statePjl
	.globl	_Z20gm31_generate_array_P10gm31_statePjl
	.type	_Z20gm31_generate_array_P10gm31_statePjl, @function
_Z20gm31_generate_array_P10gm31_statePjl:
.LFB2046:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$2048, %ecx
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdx, %rbx
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rdx, %rax
	cqto
	idivq	%rcx
	movq	%rax, %rdx
	salq	$11, %rdx
	cmpq	%rbx, %rdx
	jge	.L94
	incq	%rax
.L94:
	leaq	8(%rsp), %rdi
	movl	$256, %esi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L95
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$578, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L95:
	movq	(%rsp), %rsi
	leaq	16(%rsp), %rdi
	salq	$13, %rsi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L96
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$579, %r8d
	movq	%rax, %rdx
.L108:
	movl	$2, %edi
	leaq	.LC6(%rip), %rcx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L96:
	leaq	24(%rsp), %rdi
	movl	$8, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L97
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$580, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L97:
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$256, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L98
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$581, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L98:
	movq	24(%rsp), %rdi
	movq	%rsp, %rsi
	movl	$1, %ecx
	movl	$8, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L99
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$582, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L99:
	movl	$33554433, %edx
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L100
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z61__device_stub__Z26gm31_kernel_generate_arrayP10gm31_statePjPlP10gm31_statePjPl
.L100:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L101
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$585, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L101:
	movq	16(%rsp), %rsi
	leaq	0(,%rbx,4), %rdx
	movl	$2, %ecx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L102
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$587, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L102:
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	jne	.L109
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	je	.L104
.L109:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$588, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L104:
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	je	.L93
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$589, %r8d
	movq	%rax, %rdx
	jmp	.L108
.L93:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L106
	call	__stack_chk_fail@PLT
.L106:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z20gm31_generate_array_P10gm31_statePjl, .-_Z20gm31_generate_array_P10gm31_statePjl
	.globl	_Z67__device_stub__Z32gm31_kernel_generate_array_floatP10gm31_statePfPlP10gm31_statePfPl
	.type	_Z67__device_stub__Z32gm31_kernel_generate_array_floatP10gm31_statePfPlP10gm31_statePfPl, @function
_Z67__device_stub__Z32gm31_kernel_generate_array_floatP10gm31_statePfPlP10gm31_statePfPl:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L110
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L110:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L112
	call	__stack_chk_fail@PLT
.L112:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z67__device_stub__Z32gm31_kernel_generate_array_floatP10gm31_statePfPlP10gm31_statePfPl, .-_Z67__device_stub__Z32gm31_kernel_generate_array_floatP10gm31_statePfPlP10gm31_statePfPl
	.globl	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
	.type	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl, @function
_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z32gm31_kernel_generate_array_floatP10gm31_statePfPlP10gm31_statePfPl
	.cfi_endproc
.LFE2074:
	.size	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl, .-_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
	.globl	_Z30gm31_generate_gpu_array_float_P10gm31_statePfl
	.type	_Z30gm31_generate_gpu_array_float_P10gm31_statePfl, @function
_Z30gm31_generate_gpu_array_float_P10gm31_statePfl:
.LFB2044:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdx, %rcx
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rsi, %rbx
	movl	$2048, %esi
	subq	$72, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rdx, %rax
	cqto
	idivq	%rsi
	movq	%rax, %rdx
	salq	$11, %rdx
	cmpq	%rcx, %rdx
	jge	.L116
	incq	%rax
.L116:
	leaq	16(%rsp), %rdi
	movl	$256, %esi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L117
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$507, %r8d
	movq	%rax, %rdx
	jmp	.L127
.L117:
	leaq	24(%rsp), %rdi
	movl	$8, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L118
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$508, %r8d
	movq	%rax, %rdx
.L127:
	movl	$2, %edi
	leaq	.LC6(%rip), %rcx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L118:
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$256, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L119
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$509, %r8d
	movq	%rax, %rdx
	jmp	.L127
.L119:
	movq	24(%rsp), %rdi
	leaq	8(%rsp), %rsi
	movl	$1, %ecx
	movl	$8, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L120
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$510, %r8d
	movq	%rax, %rdx
	jmp	.L127
.L120:
	movl	$33554433, %edx
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L121
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	call	_Z67__device_stub__Z32gm31_kernel_generate_array_floatP10gm31_statePfPlP10gm31_statePfPl
.L121:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L122
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$513, %r8d
	movq	%rax, %rdx
	jmp	.L127
.L122:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	jne	.L128
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	je	.L115
.L128:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$515, %r8d
	movq	%rax, %rdx
	jmp	.L127
.L115:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L125
	call	__stack_chk_fail@PLT
.L125:
	addq	$72, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z30gm31_generate_gpu_array_float_P10gm31_statePfl, .-_Z30gm31_generate_gpu_array_float_P10gm31_statePfl
	.globl	_Z68__device_stub__Z33gm31_kernel_generate_array_doubleP10gm31_statePdPlP10gm31_statePdPl
	.type	_Z68__device_stub__Z33gm31_kernel_generate_array_doubleP10gm31_statePdPlP10gm31_statePdPl, @function
_Z68__device_stub__Z33gm31_kernel_generate_array_doubleP10gm31_statePdPlP10gm31_statePdPl:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L129
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L129:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L131
	call	__stack_chk_fail@PLT
.L131:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z68__device_stub__Z33gm31_kernel_generate_array_doubleP10gm31_statePdPlP10gm31_statePdPl, .-_Z68__device_stub__Z33gm31_kernel_generate_array_doubleP10gm31_statePdPlP10gm31_statePdPl
	.globl	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.type	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl, @function
_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z68__device_stub__Z33gm31_kernel_generate_array_doubleP10gm31_statePdPlP10gm31_statePdPl
	.cfi_endproc
.LFE2076:
	.size	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl, .-_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.globl	_Z31gm31_generate_gpu_array_double_P10gm31_statePdl
	.type	_Z31gm31_generate_gpu_array_double_P10gm31_statePdl, @function
_Z31gm31_generate_gpu_array_double_P10gm31_statePdl:
.LFB2045:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdx, %rcx
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rsi, %rbx
	movl	$2048, %esi
	subq	$72, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movq	%rdx, %rax
	cqto
	idivq	%rsi
	movq	%rax, %rdx
	salq	$11, %rdx
	cmpq	%rcx, %rdx
	jge	.L135
	incq	%rax
.L135:
	leaq	16(%rsp), %rdi
	movl	$256, %esi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L136
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$557, %r8d
	movq	%rax, %rdx
	jmp	.L146
.L136:
	leaq	24(%rsp), %rdi
	movl	$8, %esi
	call	cudaMalloc@PLT
	testl	%eax, %eax
	je	.L137
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$558, %r8d
	movq	%rax, %rdx
.L146:
	movl	$2, %edi
	leaq	.LC6(%rip), %rcx
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L137:
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$256, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L138
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$559, %r8d
	movq	%rax, %rdx
	jmp	.L146
.L138:
	movq	24(%rsp), %rdi
	leaq	8(%rsp), %rsi
	movl	$1, %ecx
	movl	$8, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L139
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$560, %r8d
	movq	%rax, %rdx
	jmp	.L146
.L139:
	movl	$33554433, %edx
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	salq	$9, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L140
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%rbx, %rsi
	call	_Z68__device_stub__Z33gm31_kernel_generate_array_doubleP10gm31_statePdPlP10gm31_statePdPl
.L140:
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L141
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$563, %r8d
	movq	%rax, %rdx
	jmp	.L146
.L141:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	jne	.L147
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	testl	%eax, %eax
	je	.L134
.L147:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$565, %r8d
	movq	%rax, %rdx
	jmp	.L146
.L134:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L144
	call	__stack_chk_fail@PLT
.L144:
	addq	$72, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2045:
	.size	_Z31gm31_generate_gpu_array_double_P10gm31_statePdl, .-_Z31gm31_generate_gpu_array_double_P10gm31_statePdl
	.section	.rodata.str1.1
.LC8:
	.string	"_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl"
.LC9:
	.string	"_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl"
.LC10:
	.string	"_Z26gm31_kernel_generate_arrayP10gm31_statePjPl"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2078:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2078:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	gm31_Consts
	.data
	.align 16
	.type	gm31_Consts, @object
	.size	gm31_Consts, 64
gm31_Consts:
	.long	-74
	.long	36
	.long	-74
	.long	36
	.long	11
	.long	0
	.long	11
	.long	0
	.long	14
	.long	0
	.long	14
	.long	0
	.long	2147483647
	.long	0
	.long	2147483647
	.long	0
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	796917760
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// (c) Copyright 2013 Lev Barash, Landau Institute for Theoretical Physics, Russian Academy of Sciences
// This is supplement to the paper:
// L.Yu. Barash, L.N. Shchur, "PRAND: GPU accelerated parallel random number generation library: Using most reliable algorithms and applying parallelism of modern GPUs and CPUs".
// e-mail: barash @ itp.ac.ru (remove space)


#include <hip/hip_runtime.h>
#include<stdio.h>

#define gm31_CUDA_CALL(x) do { if((x) != hipSuccess) { printf("Error: %s at %s:%d\n",hipGetErrorString(hipGetLastError()),__FILE__,__LINE__); exit(1);}} while(0)

#define gm31_BLOCKS  512
#define gm31_THREADS 128
#define gm31_ARRAY_SECTIONS  (gm31_BLOCKS*gm31_THREADS/32)

#define gm31_qg    30064771058ULL
#define gm31_g     2147483647
#define gm31_halfg 1073741824
#define gm31_k     11
#define gm31_q     14

typedef struct{
  unsigned xN[32],xP[32];
} gm31_state;

typedef struct{
  unsigned xN[64] __attribute__ ((aligned(16))),
           xP[64] __attribute__ ((aligned(16)));
} gm31_sse_state;

unsigned gm31_Consts[16] __attribute__ ((aligned(16))) =
{4294967222UL,36UL,4294967222UL,36UL,gm31_k,0,gm31_k,0,gm31_q,0,gm31_q,0,gm31_g,0,gm31_g,0};

__host__ unsigned int gm31_sse_generate_(gm31_sse_state* state){
  unsigned output1,output2;
  asm volatile("\n" \
      "movaps 48(%3),%%xmm5\n" \
      "\n" \
      "movaps (%1),%%xmm0\n" \
      "movaps %%xmm0,%%xmm7\n" \
      "movaps (%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm0\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm0\n" \
      "psubq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm0\n" \
      "paddq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,(%1)\n" \
      "movaps %%xmm7,(%2)\n" \
      "\n" \
      "movaps 16(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 16(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,16(%1)\n" \
      "movaps %%xmm7,16(%2)\n" \
      "\n" \
      "movaps 32(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 32(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,32(%1)\n" \
      "movaps %%xmm7,32(%2)\n" \
      "\n" \
      "movaps 48(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 48(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,48(%1)\n" \
      "movaps %%xmm7,48(%2)\n" \
      "\n" \
      "shufps $136,%%xmm1,%%xmm0\n" \
      "shufps $136,%%xmm3,%%xmm2\n" \
      "psrld  $30,%%xmm0\n" \
      "psrld  $30,%%xmm2\n" \
      "packssdw %%xmm2,%%xmm0\n" \
      "\n" \
      "movaps 64(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 64(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,64(%1)\n" \
      "movaps %%xmm7,64(%2)\n" \
      "\n" \
      "movaps 80(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 80(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,80(%1)\n" \
      "movaps %%xmm7,80(%2)\n" \
      "\n" \
      "movaps 96(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 96(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,96(%1)\n" \
      "movaps %%xmm7,96(%2)\n" \
      "\n" \
      "movaps 112(%1),%%xmm4\n" \
      "movaps %%xmm4,%%xmm7\n" \
      "movaps 112(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm4\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm4\n" \
      "psubq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm4\n" \
      "paddq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,112(%1)\n" \
      "movaps %%xmm7,112(%2)\n" \
      "\n" \
      "shufps $136,%%xmm2,%%xmm1\n" \
      "shufps $136,%%xmm4,%%xmm3\n" \
      "psrld  $30,%%xmm1\n" \
      "psrld  $30,%%xmm3\n" \
      "packssdw %%xmm3,%%xmm1\n" \
      "\n" \
      "packsswb %%xmm1,%%xmm0\n" \
      "psllw $7,%%xmm0\n" \
      "pmovmskb %%xmm0,%0\n" \
      "":"=r"(output1):"r"(state->xN),"r"(state->xP),"r"(gm31_Consts));
  asm volatile("\n" \
      "movaps 128(%1),%%xmm0\n" \
      "movaps %%xmm0,%%xmm7\n" \
      "movaps 128(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm0\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm0\n" \
      "psubq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm0\n" \
      "paddq %%xmm6,%%xmm0\n" \
      "movaps %%xmm0,128(%1)\n" \
      "movaps %%xmm7,128(%2)\n" \
      "\n" \
      "movaps 144(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 144(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,144(%1)\n" \
      "movaps %%xmm7,144(%2)\n" \
      "\n" \
      "movaps 160(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 160(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,160(%1)\n" \
      "movaps %%xmm7,160(%2)\n" \
      "\n" \
      "movaps 176(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 176(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,176(%1)\n" \
      "movaps %%xmm7,176(%2)\n" \
      "\n" \
      "shufps $136,%%xmm1,%%xmm0\n" \
      "shufps $136,%%xmm3,%%xmm2\n" \
      "psrld  $30,%%xmm0\n" \
      "psrld  $30,%%xmm2\n" \
      "packssdw %%xmm2,%%xmm0\n" \
      "\n" \
      "movaps 192(%1),%%xmm1\n" \
      "movaps %%xmm1,%%xmm7\n" \
      "movaps 192(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm1\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm1\n" \
      "psubq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm1\n" \
      "paddq %%xmm6,%%xmm1\n" \
      "movaps %%xmm1,192(%1)\n" \
      "movaps %%xmm7,192(%2)\n" \
      "\n" \
      "movaps 208(%1),%%xmm2\n" \
      "movaps %%xmm2,%%xmm7\n" \
      "movaps 208(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm2\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm2\n" \
      "psubq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm2\n" \
      "paddq %%xmm6,%%xmm2\n" \
      "movaps %%xmm2,208(%1)\n" \
      "movaps %%xmm7,208(%2)\n" \
      "\n" \
      "movaps 224(%1),%%xmm3\n" \
      "movaps %%xmm3,%%xmm7\n" \
      "movaps 224(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm3\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm3\n" \
      "psubq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm3\n" \
      "paddq %%xmm6,%%xmm3\n" \
      "movaps %%xmm3,224(%1)\n" \
      "movaps %%xmm7,224(%2)\n" \
      "\n" \
      "movaps 240(%1),%%xmm4\n" \
      "movaps %%xmm4,%%xmm7\n" \
      "movaps 240(%2),%%xmm6\n" \
      "pmuludq 16(%3),%%xmm4\n" \
      "pmuludq 32(%3),%%xmm6\n" \
      "paddq (%3),%%xmm4\n" \
      "psubq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,%%xmm6\n" \
      "psrlq $31,%%xmm6\n" \
      "andps %%xmm5,%%xmm4\n" \
      "paddq %%xmm6,%%xmm4\n" \
      "movaps %%xmm4,240(%1)\n" \
      "movaps %%xmm7,240(%2)\n" \
      "\n" \
      "shufps $136,%%xmm2,%%xmm1\n" \
      "shufps $136,%%xmm4,%%xmm3\n" \
      "psrld  $30,%%xmm1\n" \
      "psrld  $30,%%xmm3\n" \
      "packssdw %%xmm3,%%xmm1\n" \
      "\n" \
      "packsswb %%xmm1,%%xmm0\n" \
      "psllw $7,%%xmm0\n" \
      "pmovmskb %%xmm0,%0\n" \
      "shll $16,%0\n" \
      "":"=r"(output2):"r"(state->xN),"r"(state->xP),"r"(gm31_Consts));
  asm volatile("\n" \
      "addl %1,%0\n" \
      "\n" \
      "":"=r"(output2):"r"(output1),"0"(output2));
  return output2;
}

__device__ __host__ void gm31_get_sse_state_(gm31_state* state,gm31_sse_state* sse_state){
  int i;
  for(i=0;i<32;i++) {
    sse_state->xN[2*i]=state->xN[i]; sse_state->xP[2*i]=state->xP[i];
    sse_state->xN[2*i+1]=sse_state->xP[2*i+1]=0;
  }
}

__device__ __host__ unsigned gm31_mod_g(unsigned long long x){ // returns x (mod g)
  unsigned long long F,G; G=x;
  do{ F=(G>>31); G = (G-(F<<31)+F); } while(G>gm31_g);
  return G;
}

__device__ __host__ unsigned gm31_CNext(unsigned N,unsigned P){
  unsigned long long curr1,curr2,curr3;
  curr1=(unsigned long long)gm31_k*(unsigned long long)N; 
  curr2=(unsigned long long)gm31_q*(unsigned long long)P; 
  curr3=gm31_mod_g(gm31_qg+curr1-curr2); return curr3;
}

__device__ __host__ unsigned gm31_CNext2(unsigned N,unsigned P,unsigned myk,unsigned myq){
  unsigned long long curr1,curr2,curr3;
  curr1=(unsigned long long)myk*(unsigned long long)N;
  curr2=(unsigned long long)myq*(unsigned long long)P;
  curr3=gm31_mod_g((unsigned long long)myq*(unsigned long long)gm31_g+curr1-curr2);
  return curr3;
}

__device__ __host__ unsigned gm31_GetNextN(unsigned x0,unsigned x1,unsigned n){ // returns x_{2^n}
  unsigned myk=gm31_k,myq=gm31_q,i,x=x1;
  for(i=0;i<n;i++){
    x=gm31_CNext2(x,x0,myk,myq);
    myk=gm31_CNext2(myk,2,myk,myq);
    myq=gm31_CNext2(myq,0,myq,0);
  }
  return x;
}

__device__ __host__ unsigned gm31_GetNextAny(unsigned x0,unsigned x1,unsigned long long N){ // returns x_N
  unsigned long long i; unsigned xp=x0,xn=x1,xpnew,xnnew,shift=0;
  i=N; while(i>0){
    if(i%2==1){                        // xp,xn ----> 2^shift
      xpnew=gm31_GetNextN(xp,xn,shift);
      xnnew=gm31_GetNextN(xn,gm31_CNext(xn,xp),shift);
      xp=xpnew; xn=xnnew;
    }
    i/=2; shift++;
  }
  return xp;
}

__device__ __host__ void gm31_skipahead_(gm31_state* state, unsigned long long offset){
  unsigned xn,xp,j; 
  for(j=0;j<32;j++){
    xp=gm31_GetNextAny(state->xP[j],state->xN[j],offset);
    xn=gm31_GetNextAny(state->xP[j],state->xN[j],offset+1);
    state->xP[j]=xp; state->xN[j]=xn;
  }
}

__device__ __host__ void gm31_init_(gm31_state* state){
  unsigned x0=554937932UL,x1=1253942293UL,xp,xn,j;
  for(j=0;j<32;j++){
    xp=gm31_GetNextAny(x0,x1,144115183781032008ULL);
    xn=gm31_GetNextAny(x0,x1,144115183781032009ULL);
    state->xP[j]=xp; state->xN[j]=xn; x0=xp; x1=xn;
  }
}

__device__ __host__ void gm31_init_short_sequence_(gm31_state* state,unsigned SequenceNumber){
  gm31_init_(state);                     // 0 <= SequenceNumber < 10^9;   length of each sequence <= 8*10^7
  gm31_skipahead_(state,82927047ULL*(unsigned long long)SequenceNumber);
}

__device__ __host__ void gm31_init_medium_sequence_(gm31_state* state,unsigned SequenceNumber){
  gm31_init_(state);                     // 0 <= SequenceNumber < 10^7;   length of each sequence <= 8*10^9
  gm31_skipahead_(state,8799201913ULL*(unsigned long long)SequenceNumber);
}

__device__ __host__ void gm31_init_long_sequence_(gm31_state* state,unsigned SequenceNumber){
  gm31_init_(state);                     // 0 <= SequenceNumber < 10^5;   length of each sequence <= 8*10^11
  gm31_skipahead_(state,828317697521ULL*(unsigned long long)SequenceNumber);
}

__device__ __host__ unsigned int gm31_generate_(gm31_state* state){
  int i; unsigned temp,sum=0,bit=1;
  for(i=0;i<32;i++){
    temp=gm31_CNext(state->xN[i],state->xP[i]);
    state->xP[i]=state->xN[i]; state->xN[i]=temp;
    sum += ((temp<gm31_halfg)?0:bit); bit*=2;
  }
  return sum;
}

__device__ __host__ float gm31_generate_uniform_float_(gm31_state* state){
  int i; unsigned temp,sum=0,bit=1;
  for(i=0;i<32;i++){
    temp=gm31_CNext(state->xN[i],state->xP[i]);
    state->xP[i]=state->xN[i]; state->xN[i]=temp;
    sum += ((temp<gm31_halfg)?0:bit); bit*=2;
  }
  return ((float) sum) * 2.3283064365386963e-10;
}

__host__ void gm31_print_state_(gm31_state* state){int i;
    printf("Generator State:\nxN={");
    for(i=0;i<32;i++) {printf("%u",state->xN[i]%gm31_g); printf((i<31)?",":"}\nxP={");}
    for(i=0;i<32;i++) {printf("%u",state->xP[i]%gm31_g); printf((i<31)?",":"}\n\n");}
}

__host__ void gm31_print_sse_state_(gm31_sse_state* state){int i;
    printf("Generator State:\nxN={");
    for(i=0;i<32;i++) {printf("%u",state->xN[2*i]%gm31_g); printf((i<31)?",":"}\nxP={");}
    for(i=0;i<32;i++) {printf("%u",state->xP[2*i]%gm31_g); printf((i<31)?",":"}\n\n");}
}

__global__ void gm31_kernel_generate_array(gm31_state* state, unsigned int* out, long* length) {
    unsigned temp,i,orbit,seqNum; long offset;

    __shared__ unsigned xP[gm31_THREADS];  // one generator per s=32 threads, i.e. one orbit
    __shared__ unsigned xN[gm31_THREADS];  // per thread, i.e. blockDim.x orbits per block
    __shared__ unsigned  a[gm31_THREADS];  // array "a" contains corresponding parts of output

    orbit   = threadIdx.x % 32;
    seqNum  = (threadIdx.x + blockIdx.x * blockDim.x)>>5;  // RNG_sequence index
    offset  = seqNum*(*length);                            // start of the section in the output array

    xP[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset);
    xN[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset+1);

    for(i=0;i<(*length);i++){       // each s=32 threads result in "length" values in the output array

      temp = gm31_CNext( xN[threadIdx.x], xP[threadIdx.x] );
      xP[threadIdx.x] = xN[threadIdx.x]; xN[threadIdx.x] = temp; 
      a[threadIdx.x]  = (temp < gm31_halfg ? 0 : (1<<orbit) );

      __syncthreads();
      if((orbit&3)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+1]+a[threadIdx.x+2]+a[threadIdx.x+3];
      __syncthreads();
      if((orbit&15)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+4]+a[threadIdx.x+8]+a[threadIdx.x+12];
      __syncthreads();
      if(orbit==0){ out[offset+i]=a[threadIdx.x]+a[threadIdx.x+16]; }

    }
}

__host__ void gm31_generate_gpu_array_(gm31_state* state, unsigned int* dev_out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(hipMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(hipMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(hipMemcpy(dev_state,state,sizeof(gm31_state),hipMemcpyHostToDevice));
   gm31_CUDA_CALL(hipMemcpy(dev_length,&mylength,sizeof(long),hipMemcpyHostToDevice));

   gm31_kernel_generate_array<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(hipGetLastError());
   
   gm31_CUDA_CALL(hipFree(dev_state)); gm31_CUDA_CALL(hipFree(dev_length));

}

__global__ void gm31_kernel_generate_array_float(gm31_state* state, float* out, long* length) {
    unsigned temp,sum,i,orbit,seqNum; long offset;

    __shared__ unsigned xP[gm31_THREADS];  // one generator per s=32 threads, i.e. one orbit
    __shared__ unsigned xN[gm31_THREADS];  // per thread, i.e. blockDim.x orbits per block
    __shared__ unsigned  a[gm31_THREADS];  // array "a" contains corresponding parts of output

    orbit   = threadIdx.x % 32;
    seqNum  = (threadIdx.x + blockIdx.x * blockDim.x)>>5;  // RNG_sequence index
    offset  = seqNum*(*length);                            // start of the section in the output array

    xP[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset);
    xN[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset+1);

    for(i=0;i<(*length);i++){       // each s=32 threads result in "length" values in the output array

      temp = gm31_CNext( xN[threadIdx.x], xP[threadIdx.x] );
      xP[threadIdx.x] = xN[threadIdx.x]; xN[threadIdx.x] = temp; 
      a[threadIdx.x]  = (temp < gm31_halfg ? 0 : (1<<orbit) );

      __syncthreads();
      if((orbit&3)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+1]+a[threadIdx.x+2]+a[threadIdx.x+3];
      __syncthreads();
      if((orbit&15)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+4]+a[threadIdx.x+8]+a[threadIdx.x+12];
      __syncthreads();
      if(orbit==0){ sum=a[threadIdx.x]+a[threadIdx.x+16];  out[offset+i]=((float)sum) * 2.3283064365386963e-10; }

    }
}

__host__ void gm31_generate_gpu_array_float_(gm31_state* state, float* dev_out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(hipMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(hipMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(hipMemcpy(dev_state,state,sizeof(gm31_state),hipMemcpyHostToDevice));
   gm31_CUDA_CALL(hipMemcpy(dev_length,&mylength,sizeof(long),hipMemcpyHostToDevice));

   gm31_kernel_generate_array_float<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(hipGetLastError());
   
   gm31_CUDA_CALL(hipFree(dev_state)); gm31_CUDA_CALL(hipFree(dev_length));

}

__global__ void gm31_kernel_generate_array_double(gm31_state* state, double* out, long* length) {
    unsigned temp,sum,i,orbit,seqNum; long offset;

    __shared__ unsigned xP[gm31_THREADS];  // one generator per s=32 threads, i.e. one orbit
    __shared__ unsigned xN[gm31_THREADS];  // per thread, i.e. blockDim.x orbits per block
    __shared__ unsigned  a[gm31_THREADS];  // array "a" contains corresponding parts of output

    orbit   = threadIdx.x % 32;
    seqNum  = (threadIdx.x + blockIdx.x * blockDim.x)>>5;  // RNG_sequence index
    offset  = seqNum*(*length);                            // start of the section in the output array

    xP[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset);
    xN[threadIdx.x]=gm31_GetNextAny(state->xP[orbit],state->xN[orbit],offset+1);

    for(i=0;i<(*length);i++){       // each s=32 threads result in "length" values in the output array

      temp = gm31_CNext( xN[threadIdx.x], xP[threadIdx.x] );
      xP[threadIdx.x] = xN[threadIdx.x]; xN[threadIdx.x] = temp; 
      a[threadIdx.x]  = (temp < gm31_halfg ? 0 : (1<<orbit) );

      __syncthreads();
      if((orbit&3)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+1]+a[threadIdx.x+2]+a[threadIdx.x+3];
      __syncthreads();
      if((orbit&15)==0) a[threadIdx.x] = a[threadIdx.x]+a[threadIdx.x+4]+a[threadIdx.x+8]+a[threadIdx.x+12];
      __syncthreads();
      if(orbit==0){ sum=a[threadIdx.x]+a[threadIdx.x+16];  out[offset+i]=((double)sum) * 2.3283064365386963e-10; }

    }
}

__host__ void gm31_generate_gpu_array_double_(gm31_state* state, double* dev_out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(hipMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(hipMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(hipMemcpy(dev_state,state,sizeof(gm31_state),hipMemcpyHostToDevice));
   gm31_CUDA_CALL(hipMemcpy(dev_length,&mylength,sizeof(long),hipMemcpyHostToDevice));

   gm31_kernel_generate_array_double<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(hipGetLastError());
   
   gm31_CUDA_CALL(hipFree(dev_state)); gm31_CUDA_CALL(hipFree(dev_length));

}

__host__ void gm31_generate_array_(gm31_state* state, unsigned int* out, long length){

   long          mylength = length/gm31_ARRAY_SECTIONS;
   gm31_state*   dev_state;
   unsigned int* dev_out;
   long*         dev_length;

   if((mylength*gm31_ARRAY_SECTIONS)<length) mylength++;

   gm31_CUDA_CALL(hipMalloc((void**)&dev_state,sizeof(gm31_state)));
   gm31_CUDA_CALL(hipMalloc((void**)&dev_out,mylength*gm31_ARRAY_SECTIONS*sizeof(unsigned int)));
   gm31_CUDA_CALL(hipMalloc((void**)&dev_length,sizeof(long)));
   gm31_CUDA_CALL(hipMemcpy(dev_state,state,sizeof(gm31_state),hipMemcpyHostToDevice));
   gm31_CUDA_CALL(hipMemcpy(dev_length,&mylength,sizeof(long),hipMemcpyHostToDevice));

   gm31_kernel_generate_array<<<gm31_BLOCKS,gm31_THREADS>>>(dev_state,dev_out,dev_length);
   gm31_CUDA_CALL(hipGetLastError());
   
   gm31_CUDA_CALL(hipMemcpy(out,dev_out,length*sizeof(unsigned int),hipMemcpyDeviceToHost));
   gm31_CUDA_CALL(hipFree(dev_state)); gm31_CUDA_CALL(hipFree(dev_out)); 
   gm31_CUDA_CALL(hipFree(dev_length));

}

	.text
	.file	"_gm31.hip"
	.globl	_Z18gm31_sse_generate_P14gm31_sse_state # -- Begin function _Z18gm31_sse_generate_P14gm31_sse_state
	.type	_Z18gm31_sse_generate_P14gm31_sse_state,@function
_Z18gm31_sse_generate_P14gm31_sse_state: # @_Z18gm31_sse_generate_P14gm31_sse_state
	.cfi_startproc
# %bb.0:
	leaq	256(%rdi), %rax
	movl	$gm31_Consts, %ecx
	#APP

	movaps	48(%rcx), %xmm5

	movaps	(%rdi), %xmm0
	movaps	%xmm0, %xmm7
	movaps	(%rax), %xmm6
	pmuludq	16(%rcx), %xmm0
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm0
	psubq	%xmm6, %xmm0
	movaps	%xmm0, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm0
	paddq	%xmm6, %xmm0
	movaps	%xmm0, (%rdi)
	movaps	%xmm7, (%rax)

	movaps	16(%rdi), %xmm1
	movaps	%xmm1, %xmm7
	movaps	16(%rax), %xmm6
	pmuludq	16(%rcx), %xmm1
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm1
	psubq	%xmm6, %xmm1
	movaps	%xmm1, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm1
	paddq	%xmm6, %xmm1
	movaps	%xmm1, 16(%rdi)
	movaps	%xmm7, 16(%rax)

	movaps	32(%rdi), %xmm2
	movaps	%xmm2, %xmm7
	movaps	32(%rax), %xmm6
	pmuludq	16(%rcx), %xmm2
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm2
	psubq	%xmm6, %xmm2
	movaps	%xmm2, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm2
	paddq	%xmm6, %xmm2
	movaps	%xmm2, 32(%rdi)
	movaps	%xmm7, 32(%rax)

	movaps	48(%rdi), %xmm3
	movaps	%xmm3, %xmm7
	movaps	48(%rax), %xmm6
	pmuludq	16(%rcx), %xmm3
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm3
	psubq	%xmm6, %xmm3
	movaps	%xmm3, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm3
	paddq	%xmm6, %xmm3
	movaps	%xmm3, 48(%rdi)
	movaps	%xmm7, 48(%rax)

	shufps	$136, %xmm1, %xmm0              # xmm0 = xmm0[0,2],xmm1[0,2]
	shufps	$136, %xmm3, %xmm2              # xmm2 = xmm2[0,2],xmm3[0,2]
	psrld	$30, %xmm0
	psrld	$30, %xmm2
	packssdw	%xmm2, %xmm0

	movaps	64(%rdi), %xmm1
	movaps	%xmm1, %xmm7
	movaps	64(%rax), %xmm6
	pmuludq	16(%rcx), %xmm1
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm1
	psubq	%xmm6, %xmm1
	movaps	%xmm1, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm1
	paddq	%xmm6, %xmm1
	movaps	%xmm1, 64(%rdi)
	movaps	%xmm7, 64(%rax)

	movaps	80(%rdi), %xmm2
	movaps	%xmm2, %xmm7
	movaps	80(%rax), %xmm6
	pmuludq	16(%rcx), %xmm2
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm2
	psubq	%xmm6, %xmm2
	movaps	%xmm2, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm2
	paddq	%xmm6, %xmm2
	movaps	%xmm2, 80(%rdi)
	movaps	%xmm7, 80(%rax)

	movaps	96(%rdi), %xmm3
	movaps	%xmm3, %xmm7
	movaps	96(%rax), %xmm6
	pmuludq	16(%rcx), %xmm3
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm3
	psubq	%xmm6, %xmm3
	movaps	%xmm3, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm3
	paddq	%xmm6, %xmm3
	movaps	%xmm3, 96(%rdi)
	movaps	%xmm7, 96(%rax)

	movaps	112(%rdi), %xmm4
	movaps	%xmm4, %xmm7
	movaps	112(%rax), %xmm6
	pmuludq	16(%rcx), %xmm4
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm4
	psubq	%xmm6, %xmm4
	movaps	%xmm4, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm4
	paddq	%xmm6, %xmm4
	movaps	%xmm4, 112(%rdi)
	movaps	%xmm7, 112(%rax)

	shufps	$136, %xmm2, %xmm1              # xmm1 = xmm1[0,2],xmm2[0,2]
	shufps	$136, %xmm4, %xmm3              # xmm3 = xmm3[0,2],xmm4[0,2]
	psrld	$30, %xmm1
	psrld	$30, %xmm3
	packssdw	%xmm3, %xmm1

	packsswb	%xmm1, %xmm0
	psllw	$7, %xmm0
	pmovmskb	%xmm0, %edx

	#NO_APP
	#APP

	movaps	128(%rdi), %xmm0
	movaps	%xmm0, %xmm7
	movaps	128(%rax), %xmm6
	pmuludq	16(%rcx), %xmm0
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm0
	psubq	%xmm6, %xmm0
	movaps	%xmm0, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm0
	paddq	%xmm6, %xmm0
	movaps	%xmm0, 128(%rdi)
	movaps	%xmm7, 128(%rax)

	movaps	144(%rdi), %xmm1
	movaps	%xmm1, %xmm7
	movaps	144(%rax), %xmm6
	pmuludq	16(%rcx), %xmm1
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm1
	psubq	%xmm6, %xmm1
	movaps	%xmm1, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm1
	paddq	%xmm6, %xmm1
	movaps	%xmm1, 144(%rdi)
	movaps	%xmm7, 144(%rax)

	movaps	160(%rdi), %xmm2
	movaps	%xmm2, %xmm7
	movaps	160(%rax), %xmm6
	pmuludq	16(%rcx), %xmm2
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm2
	psubq	%xmm6, %xmm2
	movaps	%xmm2, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm2
	paddq	%xmm6, %xmm2
	movaps	%xmm2, 160(%rdi)
	movaps	%xmm7, 160(%rax)

	movaps	176(%rdi), %xmm3
	movaps	%xmm3, %xmm7
	movaps	176(%rax), %xmm6
	pmuludq	16(%rcx), %xmm3
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm3
	psubq	%xmm6, %xmm3
	movaps	%xmm3, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm3
	paddq	%xmm6, %xmm3
	movaps	%xmm3, 176(%rdi)
	movaps	%xmm7, 176(%rax)

	shufps	$136, %xmm1, %xmm0              # xmm0 = xmm0[0,2],xmm1[0,2]
	shufps	$136, %xmm3, %xmm2              # xmm2 = xmm2[0,2],xmm3[0,2]
	psrld	$30, %xmm0
	psrld	$30, %xmm2
	packssdw	%xmm2, %xmm0

	movaps	192(%rdi), %xmm1
	movaps	%xmm1, %xmm7
	movaps	192(%rax), %xmm6
	pmuludq	16(%rcx), %xmm1
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm1
	psubq	%xmm6, %xmm1
	movaps	%xmm1, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm1
	paddq	%xmm6, %xmm1
	movaps	%xmm1, 192(%rdi)
	movaps	%xmm7, 192(%rax)

	movaps	208(%rdi), %xmm2
	movaps	%xmm2, %xmm7
	movaps	208(%rax), %xmm6
	pmuludq	16(%rcx), %xmm2
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm2
	psubq	%xmm6, %xmm2
	movaps	%xmm2, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm2
	paddq	%xmm6, %xmm2
	movaps	%xmm2, 208(%rdi)
	movaps	%xmm7, 208(%rax)

	movaps	224(%rdi), %xmm3
	movaps	%xmm3, %xmm7
	movaps	224(%rax), %xmm6
	pmuludq	16(%rcx), %xmm3
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm3
	psubq	%xmm6, %xmm3
	movaps	%xmm3, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm3
	paddq	%xmm6, %xmm3
	movaps	%xmm3, 224(%rdi)
	movaps	%xmm7, 224(%rax)

	movaps	240(%rdi), %xmm4
	movaps	%xmm4, %xmm7
	movaps	240(%rax), %xmm6
	pmuludq	16(%rcx), %xmm4
	pmuludq	32(%rcx), %xmm6
	paddq	(%rcx), %xmm4
	psubq	%xmm6, %xmm4
	movaps	%xmm4, %xmm6
	psrlq	$31, %xmm6
	andps	%xmm5, %xmm4
	paddq	%xmm6, %xmm4
	movaps	%xmm4, 240(%rdi)
	movaps	%xmm7, 240(%rax)

	shufps	$136, %xmm2, %xmm1              # xmm1 = xmm1[0,2],xmm2[0,2]
	shufps	$136, %xmm4, %xmm3              # xmm3 = xmm3[0,2],xmm4[0,2]
	psrld	$30, %xmm1
	psrld	$30, %xmm3
	packssdw	%xmm3, %xmm1

	packsswb	%xmm1, %xmm0
	psllw	$7, %xmm0
	pmovmskb	%xmm0, %eax
	shll	$16, %eax

	#NO_APP
	#APP

	addl	%edx, %eax


	#NO_APP
	retq
.Lfunc_end0:
	.size	_Z18gm31_sse_generate_P14gm31_sse_state, .Lfunc_end0-_Z18gm31_sse_generate_P14gm31_sse_state
	.cfi_endproc
                                        # -- End function
	.globl	_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state # -- Begin function _Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state
	.type	_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state,@function
_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state: # @_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state
	.cfi_startproc
# %bb.0:
	movq	$-32, %rax
	xorl	%ecx, %ecx
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	128(%rdi,%rax,4), %edx
	movl	%edx, 256(%rsi,%rax,8)
	movl	256(%rdi,%rax,4), %edx
	movl	%edx, 512(%rsi,%rax,8)
	movl	%ecx, 516(%rsi,%rax,8)
	movl	%ecx, 260(%rsi,%rax,8)
	incq	%rax
	jne	.LBB1_1
# %bb.2:
	retq
.Lfunc_end1:
	.size	_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state, .Lfunc_end1-_Z19gm31_get_sse_state_P10gm31_stateP14gm31_sse_state
	.cfi_endproc
                                        # -- End function
	.globl	_Z10gm31_mod_gy                 # -- Begin function _Z10gm31_mod_gy
	.type	_Z10gm31_mod_gy,@function
_Z10gm31_mod_gy:                        # @_Z10gm31_mod_gy
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	movl	$2147483647, %ecx               # imm = 0x7FFFFFFF
.LBB2_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rax, %rdx
	shrq	$31, %rdx
	andq	%rcx, %rax
	addq	%rdx, %rax
	cmpq	%rcx, %rax
	ja	.LBB2_1
# %bb.2:
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end2:
	.size	_Z10gm31_mod_gy, .Lfunc_end2-_Z10gm31_mod_gy
	.cfi_endproc
                                        # -- End function
	.globl	_Z10gm31_CNextjj                # -- Begin function _Z10gm31_CNextjj
	.type	_Z10gm31_CNextjj,@function
_Z10gm31_CNextjj:                       # @_Z10gm31_CNextjj
	.cfi_startproc
# %bb.0:
	movl	%edi, %eax
	leaq	(%rax,%rax,4), %rcx
	leaq	(%rax,%rcx,2), %rcx
	movl	%esi, %eax
	imulq	$-14, %rax, %rdx
	movabsq	$30064771058, %rax              # imm = 0x6FFFFFFF2
	addq	%rcx, %rax
	addq	%rdx, %rax
	movl	$2147483647, %ecx               # imm = 0x7FFFFFFF
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rax, %rdx
	shrq	$31, %rdx
	andq	%rcx, %rax
	addq	%rdx, %rax
	cmpq	%rcx, %rax
	ja	.LBB3_1
# %bb.2:                                # %_Z10gm31_mod_gy.exit
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end3:
	.size	_Z10gm31_CNextjj, .Lfunc_end3-_Z10gm31_CNextjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z11gm31_CNext2jjjj             # -- Begin function _Z11gm31_CNext2jjjj
	.type	_Z11gm31_CNext2jjjj,@function
_Z11gm31_CNext2jjjj:                    # @_Z11gm31_CNext2jjjj
	.cfi_startproc
# %bb.0:
	movl	%edx, %eax
	movl	%edi, %edx
	imulq	%rax, %rdx
	movl	%ecx, %edi
	movl	%esi, %esi
	movl	$2147483647, %ecx               # imm = 0x7FFFFFFF
	movl	$2147483647, %eax               # imm = 0x7FFFFFFF
	subq	%rsi, %rax
	imulq	%rdi, %rax
	addq	%rdx, %rax
.LBB4_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rax, %rdx
	shrq	$31, %rdx
	andq	%rcx, %rax
	addq	%rdx, %rax
	cmpq	%rcx, %rax
	ja	.LBB4_1
# %bb.2:                                # %_Z10gm31_mod_gy.exit
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end4:
	.size	_Z11gm31_CNext2jjjj, .Lfunc_end4-_Z11gm31_CNext2jjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z13gm31_GetNextNjjj            # -- Begin function _Z13gm31_GetNextNjjj
	.type	_Z13gm31_GetNextNjjj,@function
_Z13gm31_GetNextNjjj:                   # @_Z13gm31_GetNextNjjj
	.cfi_startproc
# %bb.0:
	movl	%esi, %eax
	testl	%edx, %edx
	je	.LBB5_9
# %bb.1:                                # %.lr.ph
	movl	%edi, %edi
	movl	$2147483647, %ecx               # imm = 0x7FFFFFFF
	movl	$2147483647, %esi               # imm = 0x7FFFFFFF
	subq	%rdi, %rsi
	movl	$11, %r9d
	movl	$14, %edi
	xorl	%r8d, %r8d
.LBB5_2:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB5_3 Depth 2
                                        #     Child Loop BB5_5 Depth 2
                                        #     Child Loop BB5_7 Depth 2
	movl	%r9d, %r10d
	movl	%eax, %r9d
	imulq	%r10, %r9
	movq	%rdi, %rax
	imulq	%rsi, %rax
	addq	%r9, %rax
.LBB5_3:                                #   Parent Loop BB5_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%rax, %r9
	shrq	$31, %r9
	andq	%rcx, %rax
	addq	%r9, %rax
	cmpq	%rcx, %rax
	ja	.LBB5_3
# %bb.4:                                # %_Z11gm31_CNext2jjjj.exit
                                        #   in Loop: Header=BB5_2 Depth=1
	imulq	%r10, %r10
	imulq	$2147483645, %rdi, %r9          # imm = 0x7FFFFFFD
	addq	%r10, %r9
.LBB5_5:                                #   Parent Loop BB5_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r9, %r10
	shrq	$31, %r10
	andq	%rcx, %r9
	addq	%r10, %r9
	cmpq	%rcx, %r9
	ja	.LBB5_5
# %bb.6:                                # %_Z11gm31_CNext2jjjj.exit19
                                        #   in Loop: Header=BB5_2 Depth=1
	imulq	%rdi, %rdi
.LBB5_7:                                #   Parent Loop BB5_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%rdi, %r10
	shrq	$31, %r10
	andq	%rcx, %rdi
	addq	%r10, %rdi
	cmpq	%rcx, %rdi
	ja	.LBB5_7
# %bb.8:                                # %_Z11gm31_CNext2jjjj.exit21
                                        #   in Loop: Header=BB5_2 Depth=1
	incl	%r8d
	cmpl	%edx, %r8d
	jne	.LBB5_2
.LBB5_9:                                # %._crit_edge
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end5:
	.size	_Z13gm31_GetNextNjjj, .Lfunc_end5-_Z13gm31_GetNextNjjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z15gm31_GetNextAnyjjy          # -- Begin function _Z15gm31_GetNextAnyjjy
	.type	_Z15gm31_GetNextAnyjjy,@function
_Z15gm31_GetNextAnyjjy:                 # @_Z15gm31_GetNextAnyjjy
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebx
	testq	%rdx, %rdx
	je	.LBB6_7
# %bb.1:                                # %.lr.ph.preheader
	movq	%rdx, %r14
	movl	%esi, %r15d
	xorl	%ebp, %ebp
	movl	$2147483647, %r13d              # imm = 0x7FFFFFFF
.LBB6_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_4 Depth 2
	testb	$1, %r14b
	je	.LBB6_6
# %bb.3:                                #   in Loop: Header=BB6_2 Depth=1
	movl	%r15d, %eax
	leaq	(%rax,%rax,4), %rcx
	leaq	(%rax,%rcx,2), %rax
	movabsq	$30064771058, %rcx              # imm = 0x6FFFFFFF2
	addq	%rcx, %rax
	movl	%ebx, %ecx
	imulq	$-14, %rcx, %r12
	addq	%rax, %r12
.LBB6_4:                                #   Parent Loop BB6_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r12, %rax
	shrq	$31, %rax
	andq	%r13, %r12
	addq	%rax, %r12
	cmpq	%r13, %r12
	ja	.LBB6_4
# %bb.5:                                # %_Z10gm31_CNextjj.exit
                                        #   in Loop: Header=BB6_2 Depth=1
	movl	%ebx, %edi
	movl	%r15d, %esi
	movl	%ebp, %edx
	callq	_Z13gm31_GetNextNjjj
	movl	%eax, %ebx
	movl	%r15d, %edi
	movl	%r12d, %esi
	movl	%ebp, %edx
	callq	_Z13gm31_GetNextNjjj
	movl	%eax, %r15d
.LBB6_6:                                #   in Loop: Header=BB6_2 Depth=1
	movq	%r14, %rax
	shrq	%rax
	incl	%ebp
	cmpq	$1, %r14
	movq	%rax, %r14
	ja	.LBB6_2
.LBB6_7:                                # %._crit_edge
	movl	%ebx, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z15gm31_GetNextAnyjjy, .Lfunc_end6-_Z15gm31_GetNextAnyjjy
	.cfi_endproc
                                        # -- End function
	.globl	_Z15gm31_skipahead_P10gm31_statey # -- Begin function _Z15gm31_skipahead_P10gm31_statey
	.type	_Z15gm31_skipahead_P10gm31_statey,@function
_Z15gm31_skipahead_P10gm31_statey:      # @_Z15gm31_skipahead_P10gm31_statey
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %r14
	movq	%rsi, (%rsp)                    # 8-byte Spill
	leaq	1(%rsi), %r15
	movq	$-32, %rbx
.LBB7_1:                                # =>This Inner Loop Header: Depth=1
	movl	128(%r14,%rbx,4), %ebp
	movl	256(%r14,%rbx,4), %r12d
	movl	%r12d, %edi
	movl	%ebp, %esi
	movq	(%rsp), %rdx                    # 8-byte Reload
	callq	_Z15gm31_GetNextAnyjjy
	movl	%eax, %r13d
	movl	%r12d, %edi
	movl	%ebp, %esi
	movq	%r15, %rdx
	callq	_Z15gm31_GetNextAnyjjy
	movl	%r13d, 256(%r14,%rbx,4)
	movl	%eax, 128(%r14,%rbx,4)
	incq	%rbx
	jne	.LBB7_1
# %bb.2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z15gm31_skipahead_P10gm31_statey, .Lfunc_end7-_Z15gm31_skipahead_P10gm31_statey
	.cfi_endproc
                                        # -- End function
	.globl	_Z10gm31_init_P10gm31_state     # -- Begin function _Z10gm31_init_P10gm31_state
	.type	_Z10gm31_init_P10gm31_state,@function
_Z10gm31_init_P10gm31_state:            # @_Z10gm31_init_P10gm31_state
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rbx
	movl	$1253942293, %ebp               # imm = 0x4ABDA415
	movl	$554937932, %r12d               # imm = 0x2113AE4C
	movq	$-32, %r14
	movabsq	$144115183781032008, %rax       # imm = 0x1FFFFFF00023048
	leaq	1(%rax), %r15
.LBB8_1:                                # =>This Inner Loop Header: Depth=1
	movl	%r12d, %edi
	movl	%ebp, %esi
	movabsq	$144115183781032008, %rdx       # imm = 0x1FFFFFF00023048
	callq	_Z15gm31_GetNextAnyjjy
	movl	%eax, %r13d
	movl	%r12d, %edi
	movl	%ebp, %esi
	movq	%r15, %rdx
	callq	_Z15gm31_GetNextAnyjjy
	movl	%eax, %ebp
	movl	%r13d, 256(%rbx,%r14,4)
	movl	%eax, 128(%rbx,%r14,4)
	movl	%r13d, %r12d
	incq	%r14
	jne	.LBB8_1
# %bb.2:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z10gm31_init_P10gm31_state, .Lfunc_end8-_Z10gm31_init_P10gm31_state
	.cfi_endproc
                                        # -- End function
	.globl	_Z25gm31_init_short_sequence_P10gm31_statej # -- Begin function _Z25gm31_init_short_sequence_P10gm31_statej
	.type	_Z25gm31_init_short_sequence_P10gm31_statej,@function
_Z25gm31_init_short_sequence_P10gm31_statej: # @_Z25gm31_init_short_sequence_P10gm31_statej
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	callq	_Z10gm31_init_P10gm31_state
	movl	%ebx, %eax
	imulq	$82927047, %rax, %rsi           # imm = 0x4F15DC7
	movq	%r14, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z15gm31_skipahead_P10gm31_statey # TAILCALL
.Lfunc_end9:
	.size	_Z25gm31_init_short_sequence_P10gm31_statej, .Lfunc_end9-_Z25gm31_init_short_sequence_P10gm31_statej
	.cfi_endproc
                                        # -- End function
	.globl	_Z26gm31_init_medium_sequence_P10gm31_statej # -- Begin function _Z26gm31_init_medium_sequence_P10gm31_statej
	.type	_Z26gm31_init_medium_sequence_P10gm31_statej,@function
_Z26gm31_init_medium_sequence_P10gm31_statej: # @_Z26gm31_init_medium_sequence_P10gm31_statej
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	callq	_Z10gm31_init_P10gm31_state
	movl	%ebx, %eax
	movabsq	$8799201913, %rsi               # imm = 0x20C792A79
	imulq	%rax, %rsi
	movq	%r14, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z15gm31_skipahead_P10gm31_statey # TAILCALL
.Lfunc_end10:
	.size	_Z26gm31_init_medium_sequence_P10gm31_statej, .Lfunc_end10-_Z26gm31_init_medium_sequence_P10gm31_statej
	.cfi_endproc
                                        # -- End function
	.globl	_Z24gm31_init_long_sequence_P10gm31_statej # -- Begin function _Z24gm31_init_long_sequence_P10gm31_statej
	.type	_Z24gm31_init_long_sequence_P10gm31_statej,@function
_Z24gm31_init_long_sequence_P10gm31_statej: # @_Z24gm31_init_long_sequence_P10gm31_statej
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	callq	_Z10gm31_init_P10gm31_state
	movl	%ebx, %eax
	movabsq	$828317697521, %rsi             # imm = 0xC0DB9505F1
	imulq	%rax, %rsi
	movq	%r14, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_Z15gm31_skipahead_P10gm31_statey # TAILCALL
.Lfunc_end11:
	.size	_Z24gm31_init_long_sequence_P10gm31_statej, .Lfunc_end11-_Z24gm31_init_long_sequence_P10gm31_statej
	.cfi_endproc
                                        # -- End function
	.globl	_Z14gm31_generate_P10gm31_state # -- Begin function _Z14gm31_generate_P10gm31_state
	.type	_Z14gm31_generate_P10gm31_state,@function
_Z14gm31_generate_P10gm31_state:        # @_Z14gm31_generate_P10gm31_state
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	xorl	%ecx, %ecx
	movl	$1, %edx
	movabsq	$30064771058, %rsi              # imm = 0x6FFFFFFF2
	movl	$2147483647, %r8d               # imm = 0x7FFFFFFF
	xorl	%r9d, %r9d
	xorl	%eax, %eax
.LBB12_1:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB12_2 Depth 2
	movl	(%rdi,%r9,4), %r10d
	movl	128(%rdi,%r9,4), %r11d
	leaq	(%r10,%r10,4), %rbx
	leaq	(%r10,%rbx,2), %rbx
	addq	%rsi, %rbx
	imulq	$-14, %r11, %r11
	addq	%rbx, %r11
.LBB12_2:                               #   Parent Loop BB12_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r11, %rbx
	shrq	$31, %rbx
	andq	%r8, %r11
	addq	%rbx, %r11
	cmpq	%r8, %r11
	ja	.LBB12_2
# %bb.3:                                # %_Z10gm31_CNextjj.exit
                                        #   in Loop: Header=BB12_1 Depth=1
	movl	%r10d, 128(%rdi,%r9,4)
	movl	%r11d, (%rdi,%r9,4)
	cmpl	$1073741824, %r11d              # imm = 0x40000000
	movl	%edx, %r10d
	cmovbl	%ecx, %r10d
	addl	%r10d, %eax
	addl	%edx, %edx
	incq	%r9
	cmpq	$32, %r9
	jne	.LBB12_1
# %bb.4:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z14gm31_generate_P10gm31_state, .Lfunc_end12-_Z14gm31_generate_P10gm31_state
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z28gm31_generate_uniform_float_P10gm31_state
.LCPI13_0:
	.long	0x2f800000                      # float 2.32830644E-10
	.text
	.globl	_Z28gm31_generate_uniform_float_P10gm31_state
	.type	_Z28gm31_generate_uniform_float_P10gm31_state,@function
_Z28gm31_generate_uniform_float_P10gm31_state: # @_Z28gm31_generate_uniform_float_P10gm31_state
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	xorl	%eax, %eax
	movl	$1, %ecx
	movabsq	$30064771058, %rdx              # imm = 0x6FFFFFFF2
	movl	$2147483647, %esi               # imm = 0x7FFFFFFF
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
.LBB13_1:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_2 Depth 2
	movl	(%rdi,%r8,4), %r10d
	movl	128(%rdi,%r8,4), %r11d
	leaq	(%r10,%r10,4), %rbx
	leaq	(%r10,%rbx,2), %rbx
	addq	%rdx, %rbx
	imulq	$-14, %r11, %r11
	addq	%rbx, %r11
.LBB13_2:                               #   Parent Loop BB13_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r11, %rbx
	shrq	$31, %rbx
	andq	%rsi, %r11
	addq	%rbx, %r11
	cmpq	%rsi, %r11
	ja	.LBB13_2
# %bb.3:                                # %_Z10gm31_CNextjj.exit
                                        #   in Loop: Header=BB13_1 Depth=1
	movl	%r10d, 128(%rdi,%r8,4)
	movl	%r11d, (%rdi,%r8,4)
	cmpl	$1073741824, %r11d              # imm = 0x40000000
	movl	%ecx, %r10d
	cmovbl	%eax, %r10d
	addl	%r10d, %r9d
	addl	%ecx, %ecx
	incq	%r8
	cmpq	$32, %r8
	jne	.LBB13_1
# %bb.4:
	movl	%r9d, %eax
	cvtsi2ss	%rax, %xmm0
	mulss	.LCPI13_0(%rip), %xmm0
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z28gm31_generate_uniform_float_P10gm31_state, .Lfunc_end13-_Z28gm31_generate_uniform_float_P10gm31_state
	.cfi_endproc
                                        # -- End function
	.globl	_Z17gm31_print_state_P10gm31_state # -- Begin function _Z17gm31_print_state_P10gm31_state
	.type	_Z17gm31_print_state_P10gm31_state,@function
_Z17gm31_print_state_P10gm31_state:     # @_Z17gm31_print_state_P10gm31_state
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movq	$-32, %r14
	movl	$.L.str.3, %r15d
.LBB14_1:                               # =>This Inner Loop Header: Depth=1
	movl	128(%rbx,%r14,4), %eax
	leaq	(%rax,%rax,2), %rcx
	shrq	$32, %rcx
	movl	%eax, %edx
	subl	%ecx, %edx
	shrl	%edx
	addl	%ecx, %edx
	shrl	$30, %edx
	movl	%edx, %esi
	shll	$31, %esi
	orl	%edx, %esi
	addl	%eax, %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	movl	$.L.str.2, %edi
	cmoveq	%r15, %rdi
	xorl	%eax, %eax
	callq	printf
	testq	%r14, %r14
	jne	.LBB14_1
# %bb.2:                                # %.preheader.preheader
	movq	$-32, %r14
	movl	$.L.str.4, %r15d
.LBB14_3:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	256(%rbx,%r14,4), %eax
	leaq	(%rax,%rax,2), %rcx
	shrq	$32, %rcx
	movl	%eax, %edx
	subl	%ecx, %edx
	shrl	%edx
	addl	%ecx, %edx
	shrl	$30, %edx
	movl	%edx, %esi
	shll	$31, %esi
	orl	%edx, %esi
	addl	%eax, %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	movl	$.L.str.2, %edi
	cmoveq	%r15, %rdi
	xorl	%eax, %eax
	callq	printf
	testq	%r14, %r14
	jne	.LBB14_3
# %bb.4:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z17gm31_print_state_P10gm31_state, .Lfunc_end14-_Z17gm31_print_state_P10gm31_state
	.cfi_endproc
                                        # -- End function
	.globl	_Z21gm31_print_sse_state_P14gm31_sse_state # -- Begin function _Z21gm31_print_sse_state_P14gm31_sse_state
	.type	_Z21gm31_print_sse_state_P14gm31_sse_state,@function
_Z21gm31_print_sse_state_P14gm31_sse_state: # @_Z21gm31_print_sse_state_P14gm31_sse_state
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %rbx
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.3, %r14d
	xorl	%r15d, %r15d
.LBB15_1:                               # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,8), %eax
	leaq	(%rax,%rax,2), %rcx
	shrq	$32, %rcx
	movl	%eax, %edx
	subl	%ecx, %edx
	shrl	%edx
	addl	%ecx, %edx
	shrl	$30, %edx
	movl	%edx, %esi
	shll	$31, %esi
	orl	%edx, %esi
	addl	%eax, %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	cmpq	$31, %r15
	movl	$.L.str.2, %edi
	cmoveq	%r14, %rdi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$32, %r15
	jne	.LBB15_1
# %bb.2:                                # %.preheader.preheader
	movq	$-32, %r14
	movl	$.L.str.4, %r15d
.LBB15_3:                               # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	512(%rbx,%r14,8), %eax
	leaq	(%rax,%rax,2), %rcx
	shrq	$32, %rcx
	movl	%eax, %edx
	subl	%ecx, %edx
	shrl	%edx
	addl	%ecx, %edx
	shrl	$30, %edx
	movl	%edx, %esi
	shll	$31, %esi
	orl	%edx, %esi
	addl	%eax, %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	movl	$.L.str.2, %edi
	cmoveq	%r15, %rdi
	xorl	%eax, %eax
	callq	printf
	testq	%r14, %r14
	jne	.LBB15_3
# %bb.4:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z21gm31_print_sse_state_P14gm31_sse_state, .Lfunc_end15-_Z21gm31_print_sse_state_P14gm31_sse_state
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl # -- Begin function _Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl
	.type	_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl,@function
_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl: # @_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26gm31_kernel_generate_arrayP10gm31_statePjPl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl, .Lfunc_end16-_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl
	.cfi_endproc
                                        # -- End function
	.globl	_Z24gm31_generate_gpu_array_P10gm31_statePjl # -- Begin function _Z24gm31_generate_gpu_array_P10gm31_statePjl
	.type	_Z24gm31_generate_gpu_array_P10gm31_statePjl,@function
_Z24gm31_generate_gpu_array_P10gm31_statePjl: # @_Z24gm31_generate_gpu_array_P10gm31_statePjl
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	leaq	2047(%rdx), %rcx
	testq	%rdx, %rdx
	cmovnsq	%rdx, %rcx
	movq	%rcx, %rax
	sarq	$11, %rax
	movq	%rax, 16(%rsp)
	andq	$-2048, %rcx                    # imm = 0xF800
	cmpq	%rdx, %rcx
	jge	.LBB17_2
# %bb.1:
	incq	%rax
	movq	%rax, 16(%rsp)
.LBB17_2:
	leaq	8(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB17_3
# %bb.5:
	movq	%rsp, %rdi
	movl	$8, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB17_6
# %bb.7:
	movq	8(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB17_8
# %bb.9:
	movq	(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$8, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB17_10
# %bb.11:
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	384(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB17_13
# %bb.12:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rdx
	movq	%rbx, %rsi
	callq	_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl
.LBB17_13:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB17_14
# %bb.15:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB17_16
# %bb.17:
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB17_16
# %bb.18:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB17_16:
	.cfi_def_cfa_offset 48
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$467, %ecx                      # imm = 0x1D3
	jmp	.LBB17_4
.LBB17_3:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$459, %ecx                      # imm = 0x1CB
	jmp	.LBB17_4
.LBB17_6:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$460, %ecx                      # imm = 0x1CC
	jmp	.LBB17_4
.LBB17_8:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$461, %ecx                      # imm = 0x1CD
	jmp	.LBB17_4
.LBB17_10:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$462, %ecx                      # imm = 0x1CE
	jmp	.LBB17_4
.LBB17_14:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$465, %ecx                      # imm = 0x1D1
.LBB17_4:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end17:
	.size	_Z24gm31_generate_gpu_array_P10gm31_statePjl, .Lfunc_end17-_Z24gm31_generate_gpu_array_P10gm31_statePjl
	.cfi_endproc
                                        # -- End function
	.globl	_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl # -- Begin function _Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl
	.type	_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl,@function
_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl: # @_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl, .Lfunc_end18-_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl
	.cfi_endproc
                                        # -- End function
	.globl	_Z30gm31_generate_gpu_array_float_P10gm31_statePfl # -- Begin function _Z30gm31_generate_gpu_array_float_P10gm31_statePfl
	.type	_Z30gm31_generate_gpu_array_float_P10gm31_statePfl,@function
_Z30gm31_generate_gpu_array_float_P10gm31_statePfl: # @_Z30gm31_generate_gpu_array_float_P10gm31_statePfl
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	leaq	2047(%rdx), %rcx
	testq	%rdx, %rdx
	cmovnsq	%rdx, %rcx
	movq	%rcx, %rax
	sarq	$11, %rax
	movq	%rax, 16(%rsp)
	andq	$-2048, %rcx                    # imm = 0xF800
	cmpq	%rdx, %rcx
	jge	.LBB19_2
# %bb.1:
	incq	%rax
	movq	%rax, 16(%rsp)
.LBB19_2:
	leaq	8(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB19_3
# %bb.5:
	movq	%rsp, %rdi
	movl	$8, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB19_6
# %bb.7:
	movq	8(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB19_8
# %bb.9:
	movq	(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$8, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB19_10
# %bb.11:
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	384(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB19_13
# %bb.12:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rdx
	movq	%rbx, %rsi
	callq	_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl
.LBB19_13:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB19_14
# %bb.15:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB19_16
# %bb.17:
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB19_16
# %bb.18:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB19_16:
	.cfi_def_cfa_offset 48
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$517, %ecx                      # imm = 0x205
	jmp	.LBB19_4
.LBB19_3:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$509, %ecx                      # imm = 0x1FD
	jmp	.LBB19_4
.LBB19_6:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$510, %ecx                      # imm = 0x1FE
	jmp	.LBB19_4
.LBB19_8:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$511, %ecx                      # imm = 0x1FF
	jmp	.LBB19_4
.LBB19_10:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$512, %ecx                      # imm = 0x200
	jmp	.LBB19_4
.LBB19_14:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$515, %ecx                      # imm = 0x203
.LBB19_4:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end19:
	.size	_Z30gm31_generate_gpu_array_float_P10gm31_statePfl, .Lfunc_end19-_Z30gm31_generate_gpu_array_float_P10gm31_statePfl
	.cfi_endproc
                                        # -- End function
	.globl	_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl # -- Begin function _Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.type	_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl,@function
_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl: # @_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl, .Lfunc_end20-_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.cfi_endproc
                                        # -- End function
	.globl	_Z31gm31_generate_gpu_array_double_P10gm31_statePdl # -- Begin function _Z31gm31_generate_gpu_array_double_P10gm31_statePdl
	.type	_Z31gm31_generate_gpu_array_double_P10gm31_statePdl,@function
_Z31gm31_generate_gpu_array_double_P10gm31_statePdl: # @_Z31gm31_generate_gpu_array_double_P10gm31_statePdl
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	leaq	2047(%rdx), %rcx
	testq	%rdx, %rdx
	cmovnsq	%rdx, %rcx
	movq	%rcx, %rax
	sarq	$11, %rax
	movq	%rax, 16(%rsp)
	andq	$-2048, %rcx                    # imm = 0xF800
	cmpq	%rdx, %rcx
	jge	.LBB21_2
# %bb.1:
	incq	%rax
	movq	%rax, 16(%rsp)
.LBB21_2:
	leaq	8(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB21_3
# %bb.5:
	movq	%rsp, %rdi
	movl	$8, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB21_6
# %bb.7:
	movq	8(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB21_8
# %bb.9:
	movq	(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$8, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB21_10
# %bb.11:
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	384(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB21_13
# %bb.12:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rdx
	movq	%rbx, %rsi
	callq	_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl
.LBB21_13:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB21_14
# %bb.15:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB21_16
# %bb.17:
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB21_16
# %bb.18:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB21_16:
	.cfi_def_cfa_offset 48
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$567, %ecx                      # imm = 0x237
	jmp	.LBB21_4
.LBB21_3:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$559, %ecx                      # imm = 0x22F
	jmp	.LBB21_4
.LBB21_6:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$560, %ecx                      # imm = 0x230
	jmp	.LBB21_4
.LBB21_8:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$561, %ecx                      # imm = 0x231
	jmp	.LBB21_4
.LBB21_10:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$562, %ecx                      # imm = 0x232
	jmp	.LBB21_4
.LBB21_14:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$565, %ecx                      # imm = 0x235
.LBB21_4:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end21:
	.size	_Z31gm31_generate_gpu_array_double_P10gm31_statePdl, .Lfunc_end21-_Z31gm31_generate_gpu_array_double_P10gm31_statePdl
	.cfi_endproc
                                        # -- End function
	.globl	_Z20gm31_generate_array_P10gm31_statePjl # -- Begin function _Z20gm31_generate_array_P10gm31_statePjl
	.type	_Z20gm31_generate_array_P10gm31_statePjl,@function
_Z20gm31_generate_array_P10gm31_statePjl: # @_Z20gm31_generate_array_P10gm31_statePjl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdx, %rbx
	movq	%rsi, %r14
	movq	%rdi, %r15
	leaq	2047(%rdx), %rax
	testq	%rdx, %rdx
	cmovnsq	%rdx, %rax
	movq	%rax, %r12
	sarq	$11, %r12
	movq	%r12, 32(%rsp)
	andq	$-2048, %rax                    # imm = 0xF800
	cmpq	%rdx, %rax
	jge	.LBB22_2
# %bb.1:
	incq	%r12
	movq	%r12, 32(%rsp)
.LBB22_2:
	leaq	24(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB22_3
# %bb.5:
	shlq	$13, %r12
	leaq	16(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB22_6
# %bb.7:
	leaq	8(%rsp), %rdi
	movl	$8, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB22_8
# %bb.9:
	movq	24(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB22_10
# %bb.11:
	movq	8(%rsp), %rdi
	leaq	32(%rsp), %rsi
	movl	$8, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB22_12
# %bb.13:
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	384(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB22_15
# %bb.14:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	callq	_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl
.LBB22_15:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB22_16
# %bb.17:
	movq	16(%rsp), %rsi
	shlq	$2, %rbx
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB22_18
# %bb.19:
	movq	24(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB22_20
# %bb.21:
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB22_20
# %bb.22:
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB22_23
# %bb.24:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB22_20:
	.cfi_def_cfa_offset 80
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$590, %ecx                      # imm = 0x24E
	jmp	.LBB22_4
.LBB22_3:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$580, %ecx                      # imm = 0x244
	jmp	.LBB22_4
.LBB22_6:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$581, %ecx                      # imm = 0x245
	jmp	.LBB22_4
.LBB22_8:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$582, %ecx                      # imm = 0x246
	jmp	.LBB22_4
.LBB22_10:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$583, %ecx                      # imm = 0x247
	jmp	.LBB22_4
.LBB22_12:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$584, %ecx                      # imm = 0x248
	jmp	.LBB22_4
.LBB22_16:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$587, %ecx                      # imm = 0x24B
	jmp	.LBB22_4
.LBB22_18:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$589, %ecx                      # imm = 0x24D
	jmp	.LBB22_4
.LBB22_23:
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movl	$.L.str.6, %edx
	movq	%rax, %rsi
	movl	$591, %ecx                      # imm = 0x24F
.LBB22_4:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end22:
	.size	_Z20gm31_generate_array_P10gm31_statePjl, .Lfunc_end22-_Z20gm31_generate_array_P10gm31_statePjl
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB23_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB23_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26gm31_kernel_generate_arrayP10gm31_statePjPl, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end23:
	.size	__hip_module_ctor, .Lfunc_end23-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB24_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB24_2:
	retq
.Lfunc_end24:
	.size	__hip_module_dtor, .Lfunc_end24-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	gm31_Consts,@object             # @gm31_Consts
	.data
	.globl	gm31_Consts
	.p2align	4, 0x0
gm31_Consts:
	.long	4294967222                      # 0xffffffb6
	.long	36                              # 0x24
	.long	4294967222                      # 0xffffffb6
	.long	36                              # 0x24
	.long	11                              # 0xb
	.long	0                               # 0x0
	.long	11                              # 0xb
	.long	0                               # 0x0
	.long	14                              # 0xe
	.long	0                               # 0x0
	.long	14                              # 0xe
	.long	0                               # 0x0
	.long	2147483647                      # 0x7fffffff
	.long	0                               # 0x0
	.long	2147483647                      # 0x7fffffff
	.long	0                               # 0x0
	.size	gm31_Consts, 64

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Generator State:\nxN={"
	.size	.L.str, 22

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%u"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	","
	.size	.L.str.2, 2

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"}\nxP={"
	.size	.L.str.3, 7

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"}\n\n"
	.size	.L.str.4, 4

	.type	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl,@object # @_Z26gm31_kernel_generate_arrayP10gm31_statePjPl
	.section	.rodata,"a",@progbits
	.globl	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl
	.p2align	3, 0x0
_Z26gm31_kernel_generate_arrayP10gm31_statePjPl:
	.quad	_Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl
	.size	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl, 8

	.type	.L.str.5,@object                # @.str.5
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.5:
	.asciz	"Error: %s at %s:%d\n"
	.size	.L.str.5, 20

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/sbinet-staging/3photons/master/Random/aesb_v1_0/source/_gm31.hip"
	.size	.L.str.6, 127

	.type	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl,@object # @_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
	.section	.rodata,"a",@progbits
	.globl	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
	.p2align	3, 0x0
_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl:
	.quad	_Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl
	.size	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl, 8

	.type	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl,@object # @_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.globl	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.p2align	3, 0x0
_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl:
	.quad	_Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.size	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26gm31_kernel_generate_arrayP10gm31_statePjPl"
	.size	.L__unnamed_1, 48

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl"
	.size	.L__unnamed_2, 54

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl"
	.size	.L__unnamed_3, 55

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__gm31_kernel_generate_arrayP10gm31_statePjPl
	.addrsig_sym _Z47__device_stub__gm31_kernel_generate_array_floatP10gm31_statePfPl
	.addrsig_sym _Z48__device_stub__gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym gm31_Consts
	.addrsig_sym _Z26gm31_kernel_generate_arrayP10gm31_statePjPl
	.addrsig_sym _Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
	.addrsig_sym _Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl ; -- Begin function _Z26gm31_kernel_generate_arrayP10gm31_statePjPl
	.globl	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl
	.p2align	8
	.type	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl,@function
_Z26gm31_kernel_generate_arrayP10gm31_statePjPl: ; @_Z26gm31_kernel_generate_arrayP10gm31_statePjPl
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v8, 31, v0
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 2, v8
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v10, v1, s[4:5] offset:128
	global_load_b32 v9, v1, s[4:5]
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[0:1], s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_lshrrev_b32_e32 v5, 5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s0, v5, 0
	v_mad_u64_u32 v[3:4], null, s1, v5, v[2:3]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v7, v10
	v_cmpx_ne_u64_e32 0, v[1:2]
	s_cbranch_execz .LBB0_26
; %bb.1:                                ; %.lr.ph.i.preheader
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v7, v10
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, v9
	s_mov_b64 s[2:3], 0x80000000
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0
.LBB0_2:                                ; %.lr.ph.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;       Child Loop BB0_8 Depth 3
                                        ;       Child Loop BB0_10 Depth 3
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_16 Depth 2
                                        ;       Child Loop BB0_17 Depth 3
                                        ;       Child Loop BB0_19 Depth 3
                                        ;       Child Loop BB0_21 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 1, v3
	s_mov_b32 s15, exec_lo
	v_cmpx_eq_u32_e32 1, v5
	s_cbranch_execz .LBB0_24
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v5, v11
	s_cmp_lg_u32 s14, 0
	s_cselect_b32 s16, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_12
; %bb.4:                                ; %.lr.ph.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_sub_co_u32 v12, s4, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v13, null, 0, 0, s4
	v_mov_b32_e32 v5, v11
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s17, 0
.LBB0_5:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;       Child Loop BB0_8 Depth 3
                                        ;       Child Loop BB0_10 Depth 3
	v_mul_lo_u32 v6, s5, v12
	v_mul_lo_u32 v16, s4, v13
	v_mad_u64_u32 v[14:15], null, s4, v12, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v16, v6
	v_mad_u64_u32 v[16:17], null, s10, v5, v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v5, v16 :: v_dual_mov_b32 v6, v17
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[14:15], 31, v[5:6]
	v_and_b32_e32 v5, 0x7fffffff, v5
	v_add_co_u32 v5, vcc_lo, v5, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v15, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[5:6]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %_Z11gm31_CNext2jjjj.exit.i.i
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s18, s5, 0x7ffffffd
	s_mul_hi_u32 s19, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s20, s4, 0x7ffffffd
	s_add_i32 s19, s19, s18
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s19
.LBB0_8:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s18, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_8
; %bb.9:                                ; %_Z11gm31_CNext2jjjj.exit19.i.i
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB0_10:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_10
; %bb.11:                               ; %_Z11gm31_CNext2jjjj.exit21.i.i
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s14
	s_cbranch_scc1 .LBB0_5
.LBB0_12:                               ; %_Z13gm31_GetNextNjjj.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, 11, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, v7, -14, v[12:13]
	v_sub_nc_u32_e32 v7, v15, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v14, -14
	v_add_co_ci_u32_e32 v7, vcc_lo, 6, v7, vcc_lo
.LBB0_13:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_13
; %bb.14:                               ; %_Z10gm31_CNextjj.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_23
; %bb.15:                               ; %.lr.ph.i23.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_sub_co_u32 v11, s4, 0x7fffffff, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v12, null, 0, 0, s4
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s16, 0
.LBB0_16:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_17 Depth 3
                                        ;       Child Loop BB0_19 Depth 3
                                        ;       Child Loop BB0_21 Depth 3
	v_mul_lo_u32 v7, s5, v11
	v_mul_lo_u32 v15, s4, v12
	v_mad_u64_u32 v[13:14], null, s4, v11, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v15, v7
	v_mad_u64_u32 v[15:16], null, s10, v6, v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v6, v15 :: v_dual_mov_b32 v7, v16
.LBB0_17:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[13:14], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v14, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_17
; %bb.18:                               ; %_Z11gm31_CNext2jjjj.exit.i31.i
                                        ;   in Loop: Header=BB0_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s17, s5, 0x7ffffffd
	s_mul_hi_u32 s18, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s19, s4, 0x7ffffffd
	s_add_i32 s18, s18, s17
	s_add_u32 s10, s10, s19
	s_addc_u32 s11, s11, s18
.LBB0_19:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s17, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB0_19
; %bb.20:                               ; %_Z11gm31_CNext2jjjj.exit19.i34.i
                                        ;   in Loop: Header=BB0_16 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB0_21:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_21
; %bb.22:                               ; %_Z11gm31_CNext2jjjj.exit21.i36.i
                                        ;   in Loop: Header=BB0_16 Depth=2
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, s14
	s_cbranch_scc1 .LBB0_16
.LBB0_23:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v11, v6
	v_mov_b32_e32 v7, v5
.LBB0_24:                               ; %Flow209
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_lshrrev_b64 v[5:6], 1, v[3:4]
	v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_2
; %bb.25:                               ; %Flow210
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_26:                               ; %Flow211
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_co_u32 v3, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	v_lshlrev_b32_e32 v11, 2, v0
	s_mov_b32 s12, exec_lo
	ds_store_b32 v11, v7 offset:1024
	v_cmpx_ne_u64_e32 0, v[3:4]
	s_cbranch_execz .LBB0_52
; %bb.27:                               ; %.lr.ph.i28.preheader
	s_mov_b64 s[2:3], 0x80000000
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0
.LBB0_28:                               ; %.lr.ph.i28
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_31 Depth 2
                                        ;       Child Loop BB0_32 Depth 3
                                        ;       Child Loop BB0_34 Depth 3
                                        ;       Child Loop BB0_36 Depth 3
                                        ;     Child Loop BB0_39 Depth 2
                                        ;     Child Loop BB0_42 Depth 2
                                        ;       Child Loop BB0_43 Depth 3
                                        ;       Child Loop BB0_45 Depth 3
                                        ;       Child Loop BB0_47 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 1, v3
	s_mov_b32 s15, exec_lo
	v_cmpx_eq_u32_e32 1, v5
	s_cbranch_execz .LBB0_50
; %bb.29:                               ;   in Loop: Header=BB0_28 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, v9
	s_cmp_lg_u32 s14, 0
	s_cselect_b32 s16, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_38
; %bb.30:                               ; %.lr.ph.i.i36
                                        ;   in Loop: Header=BB0_28 Depth=1
	v_sub_co_u32 v7, s4, 0x7fffffff, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v12, null, 0, 0, s4
	v_mov_b32_e32 v5, v9
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s17, 0
.LBB0_31:                               ;   Parent Loop BB0_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_32 Depth 3
                                        ;       Child Loop BB0_34 Depth 3
                                        ;       Child Loop BB0_36 Depth 3
	v_mul_lo_u32 v6, s5, v7
	v_mul_lo_u32 v15, s4, v12
	v_mad_u64_u32 v[13:14], null, s4, v7, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v15, v6
	v_mad_u64_u32 v[15:16], null, s10, v5, v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v5, v15 :: v_dual_mov_b32 v6, v16
.LBB0_32:                               ;   Parent Loop BB0_28 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[13:14], 31, v[5:6]
	v_and_b32_e32 v5, 0x7fffffff, v5
	v_add_co_u32 v5, vcc_lo, v5, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v14, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[5:6]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_32
; %bb.33:                               ; %_Z11gm31_CNext2jjjj.exit.i.i44
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s18, s5, 0x7ffffffd
	s_mul_hi_u32 s19, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s20, s4, 0x7ffffffd
	s_add_i32 s19, s19, s18
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s19
.LBB0_34:                               ;   Parent Loop BB0_28 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s18, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_34
; %bb.35:                               ; %_Z11gm31_CNext2jjjj.exit19.i.i47
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB0_36:                               ;   Parent Loop BB0_28 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_36
; %bb.37:                               ; %_Z11gm31_CNext2jjjj.exit21.i.i49
                                        ;   in Loop: Header=BB0_31 Depth=2
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s14
	s_cbranch_scc1 .LBB0_31
.LBB0_38:                               ; %_Z13gm31_GetNextNjjj.exit.i51
                                        ;   in Loop: Header=BB0_28 Depth=1
	v_mad_u64_u32 v[6:7], null, v9, 11, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v10, -14, v[6:7]
	v_sub_nc_u32_e32 v7, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v12, -14
	v_add_co_ci_u32_e32 v7, vcc_lo, 6, v7, vcc_lo
.LBB0_39:                               ;   Parent Loop BB0_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_39
; %bb.40:                               ; %_Z10gm31_CNextjj.exit.i55
                                        ;   in Loop: Header=BB0_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_49
; %bb.41:                               ; %.lr.ph.i23.i56
                                        ;   in Loop: Header=BB0_28 Depth=1
	v_sub_co_u32 v9, s4, 0x7fffffff, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v10, null, 0, 0, s4
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s16, 0
.LBB0_42:                               ;   Parent Loop BB0_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_43 Depth 3
                                        ;       Child Loop BB0_45 Depth 3
                                        ;       Child Loop BB0_47 Depth 3
	v_mul_lo_u32 v7, s5, v9
	v_mul_lo_u32 v14, s4, v10
	v_mad_u64_u32 v[12:13], null, s4, v9, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v13, v13, v14, v7
	v_mad_u64_u32 v[14:15], null, s10, v6, v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
.LBB0_43:                               ;   Parent Loop BB0_28 Depth=1
                                        ;     Parent Loop BB0_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_43
; %bb.44:                               ; %_Z11gm31_CNext2jjjj.exit.i31.i64
                                        ;   in Loop: Header=BB0_42 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s17, s5, 0x7ffffffd
	s_mul_hi_u32 s18, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s19, s4, 0x7ffffffd
	s_add_i32 s18, s18, s17
	s_add_u32 s10, s10, s19
	s_addc_u32 s11, s11, s18
.LBB0_45:                               ;   Parent Loop BB0_28 Depth=1
                                        ;     Parent Loop BB0_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s17, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB0_45
; %bb.46:                               ; %_Z11gm31_CNext2jjjj.exit19.i34.i67
                                        ;   in Loop: Header=BB0_42 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB0_47:                               ;   Parent Loop BB0_28 Depth=1
                                        ;     Parent Loop BB0_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_47
; %bb.48:                               ; %_Z11gm31_CNext2jjjj.exit21.i36.i69
                                        ;   in Loop: Header=BB0_42 Depth=2
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, s14
	s_cbranch_scc1 .LBB0_42
.LBB0_49:                               ;   in Loop: Header=BB0_28 Depth=1
	v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v5
.LBB0_50:                               ; %Flow203
                                        ;   in Loop: Header=BB0_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_lshrrev_b64 v[5:6], 1, v[3:4]
	v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_28
; %bb.51:                               ; %Flow204
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_52:                               ; %Flow205
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_cmp_lt_i64_e64 s0, s[0:1], 1
	v_add_nc_u32_e32 v3, 0x400, v11
	ds_store_b32 v11, v10 offset:512
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_63
; %bb.53:                               ; %.lr.ph
	v_dual_mov_b32 v12, 0 :: v_dual_and_b32 v7, 3, v0
	v_and_b32_e32 v0, 15, v0
	v_lshlrev_b32_e64 v5, v8, 1
	v_cmp_eq_u32_e64 s2, 0, v8
	v_add_nc_u32_e32 v4, 0x200, v11
	v_add_nc_u32_e32 v6, 8, v11
	v_cmp_eq_u32_e64 s1, 0, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_eq_u32_e64 s0, 0, v7
	v_add_nc_u32_e32 v2, 16, v11
	v_add_nc_u32_e32 v7, 32, v11
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v9, 48, v11
	s_mov_b64 s[4:5], 0x80000000
	v_add_co_u32 v8, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v1, vcc_lo
	s_mov_b32 s7, 0
	s_mov_b64 s[10:11], 0
	s_mov_b32 s6, s7
.LBB0_54:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_55 Depth 2
	ds_load_b32 v14, v3
	ds_load_b32 v13, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(1)
	v_mad_u64_u32 v[0:1], null, v14, -14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v14
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[14:15], null, v13, 11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v14, -14
	v_add_co_ci_u32_e32 v1, vcc_lo, 6, v15, vcc_lo
.LBB0_55:                               ;   Parent Loop BB0_54 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[14:15], 31, v[0:1]
	v_and_b32_e32 v0, 0x7fffffff, v0
	v_add_co_u32 v0, vcc_lo, v0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v15, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_55
; %bb.56:                               ; %_Z10gm31_CNextjj.exit
                                        ;   in Loop: Header=BB0_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_lt_u32_e32 vcc_lo, 0x3fffffff, v0
	v_cndmask_b32_e32 v1, 0, v5, vcc_lo
	ds_store_b32 v3, v13
	ds_store_b32 v4, v0
	ds_store_b32 v11, v1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_54 Depth=1
	ds_load_2addr_b32 v[0:1], v11 offset1:1
	ds_load_2addr_b32 v[13:14], v6 offset1:1
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v0, v1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v13, v14
	ds_store_b32 v11, v0
.LBB0_58:                               ;   in Loop: Header=BB0_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB0_60
; %bb.59:                               ;   in Loop: Header=BB0_54 Depth=1
	ds_load_b32 v0, v11
	ds_load_b32 v1, v2
	ds_load_b32 v13, v7
	ds_load_b32 v14, v9
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v0, v1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v13, v14
	ds_store_b32 v11, v0
.LBB0_60:                               ;   in Loop: Header=BB0_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_62
; %bb.61:                               ;   in Loop: Header=BB0_54 Depth=1
	ds_load_2addr_b32 v[0:1], v11 offset1:16
	s_lshl_b64 s[10:11], s[10:11], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v13, vcc_lo, v8, s10
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v10, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v1, v0
	global_store_b32 v[13:14], v0, off
.LBB0_62:                               ;   in Loop: Header=BB0_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b64 v[0:1], v12, s[8:9]
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[10:11], s[6:7]
	s_waitcnt vmcnt(0)
	v_cmp_lt_i64_e32 vcc_lo, s[6:7], v[0:1]
	s_cbranch_vccnz .LBB0_54
.LBB0_63:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26gm31_kernel_generate_arrayP10gm31_statePjPl
		.amdhsa_group_segment_fixed_size 1536
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26gm31_kernel_generate_arrayP10gm31_statePjPl, .Lfunc_end0-_Z26gm31_kernel_generate_arrayP10gm31_statePjPl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2596
; NumSgprs: 23
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1536 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl ; -- Begin function _Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
	.globl	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
	.p2align	8
	.type	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl,@function
_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl: ; @_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v8, 31, v0
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 2, v8
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v10, v1, s[4:5] offset:128
	global_load_b32 v9, v1, s[4:5]
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[0:1], s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_lshrrev_b32_e32 v5, 5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s0, v5, 0
	v_mad_u64_u32 v[3:4], null, s1, v5, v[2:3]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v7, v10
	v_cmpx_ne_u64_e32 0, v[1:2]
	s_cbranch_execz .LBB1_26
; %bb.1:                                ; %.lr.ph.i.preheader
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v7, v10
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, v9
	s_mov_b64 s[2:3], 0x80000000
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0
.LBB1_2:                                ; %.lr.ph.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_5 Depth 2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;       Child Loop BB1_8 Depth 3
                                        ;       Child Loop BB1_10 Depth 3
                                        ;     Child Loop BB1_13 Depth 2
                                        ;     Child Loop BB1_16 Depth 2
                                        ;       Child Loop BB1_17 Depth 3
                                        ;       Child Loop BB1_19 Depth 3
                                        ;       Child Loop BB1_21 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 1, v3
	s_mov_b32 s15, exec_lo
	v_cmpx_eq_u32_e32 1, v5
	s_cbranch_execz .LBB1_24
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v5, v11
	s_cmp_lg_u32 s14, 0
	s_cselect_b32 s16, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_12
; %bb.4:                                ; %.lr.ph.i.i
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_sub_co_u32 v12, s4, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v13, null, 0, 0, s4
	v_mov_b32_e32 v5, v11
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s17, 0
.LBB1_5:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;       Child Loop BB1_8 Depth 3
                                        ;       Child Loop BB1_10 Depth 3
	v_mul_lo_u32 v6, s5, v12
	v_mul_lo_u32 v16, s4, v13
	v_mad_u64_u32 v[14:15], null, s4, v12, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v16, v6
	v_mad_u64_u32 v[16:17], null, s10, v5, v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v5, v16 :: v_dual_mov_b32 v6, v17
.LBB1_6:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[14:15], 31, v[5:6]
	v_and_b32_e32 v5, 0x7fffffff, v5
	v_add_co_u32 v5, vcc_lo, v5, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v15, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[5:6]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_6
; %bb.7:                                ; %_Z11gm31_CNext2jjjj.exit.i.i
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s18, s5, 0x7ffffffd
	s_mul_hi_u32 s19, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s20, s4, 0x7ffffffd
	s_add_i32 s19, s19, s18
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s19
.LBB1_8:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s18, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_8
; %bb.9:                                ; %_Z11gm31_CNext2jjjj.exit19.i.i
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB1_10:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB1_10
; %bb.11:                               ; %_Z11gm31_CNext2jjjj.exit21.i.i
                                        ;   in Loop: Header=BB1_5 Depth=2
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s14
	s_cbranch_scc1 .LBB1_5
.LBB1_12:                               ; %_Z13gm31_GetNextNjjj.exit.i
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, 11, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, v7, -14, v[12:13]
	v_sub_nc_u32_e32 v7, v15, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v14, -14
	v_add_co_ci_u32_e32 v7, vcc_lo, 6, v7, vcc_lo
.LBB1_13:                               ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_13
; %bb.14:                               ; %_Z10gm31_CNextjj.exit.i
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_23
; %bb.15:                               ; %.lr.ph.i23.i
                                        ;   in Loop: Header=BB1_2 Depth=1
	v_sub_co_u32 v11, s4, 0x7fffffff, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v12, null, 0, 0, s4
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s16, 0
.LBB1_16:                               ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_17 Depth 3
                                        ;       Child Loop BB1_19 Depth 3
                                        ;       Child Loop BB1_21 Depth 3
	v_mul_lo_u32 v7, s5, v11
	v_mul_lo_u32 v15, s4, v12
	v_mad_u64_u32 v[13:14], null, s4, v11, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v15, v7
	v_mad_u64_u32 v[15:16], null, s10, v6, v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v6, v15 :: v_dual_mov_b32 v7, v16
.LBB1_17:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[13:14], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v14, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_17
; %bb.18:                               ; %_Z11gm31_CNext2jjjj.exit.i31.i
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s17, s5, 0x7ffffffd
	s_mul_hi_u32 s18, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s19, s4, 0x7ffffffd
	s_add_i32 s18, s18, s17
	s_add_u32 s10, s10, s19
	s_addc_u32 s11, s11, s18
.LBB1_19:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s17, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB1_19
; %bb.20:                               ; %_Z11gm31_CNext2jjjj.exit19.i34.i
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB1_21:                               ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB1_21
; %bb.22:                               ; %_Z11gm31_CNext2jjjj.exit21.i36.i
                                        ;   in Loop: Header=BB1_16 Depth=2
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, s14
	s_cbranch_scc1 .LBB1_16
.LBB1_23:                               ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v11, v6
	v_mov_b32_e32 v7, v5
.LBB1_24:                               ; %Flow210
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_lshrrev_b64 v[5:6], 1, v[3:4]
	v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_2
; %bb.25:                               ; %Flow211
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_26:                               ; %Flow212
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_co_u32 v3, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	v_lshlrev_b32_e32 v11, 2, v0
	s_mov_b32 s12, exec_lo
	ds_store_b32 v11, v7 offset:1024
	v_cmpx_ne_u64_e32 0, v[3:4]
	s_cbranch_execz .LBB1_52
; %bb.27:                               ; %.lr.ph.i29.preheader
	s_mov_b64 s[2:3], 0x80000000
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0
.LBB1_28:                               ; %.lr.ph.i29
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_31 Depth 2
                                        ;       Child Loop BB1_32 Depth 3
                                        ;       Child Loop BB1_34 Depth 3
                                        ;       Child Loop BB1_36 Depth 3
                                        ;     Child Loop BB1_39 Depth 2
                                        ;     Child Loop BB1_42 Depth 2
                                        ;       Child Loop BB1_43 Depth 3
                                        ;       Child Loop BB1_45 Depth 3
                                        ;       Child Loop BB1_47 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 1, v3
	s_mov_b32 s15, exec_lo
	v_cmpx_eq_u32_e32 1, v5
	s_cbranch_execz .LBB1_50
; %bb.29:                               ;   in Loop: Header=BB1_28 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, v9
	s_cmp_lg_u32 s14, 0
	s_cselect_b32 s16, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB1_38
; %bb.30:                               ; %.lr.ph.i.i37
                                        ;   in Loop: Header=BB1_28 Depth=1
	v_sub_co_u32 v7, s4, 0x7fffffff, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v12, null, 0, 0, s4
	v_mov_b32_e32 v5, v9
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s17, 0
.LBB1_31:                               ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_32 Depth 3
                                        ;       Child Loop BB1_34 Depth 3
                                        ;       Child Loop BB1_36 Depth 3
	v_mul_lo_u32 v6, s5, v7
	v_mul_lo_u32 v15, s4, v12
	v_mad_u64_u32 v[13:14], null, s4, v7, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v15, v6
	v_mad_u64_u32 v[15:16], null, s10, v5, v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v5, v15 :: v_dual_mov_b32 v6, v16
.LBB1_32:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[13:14], 31, v[5:6]
	v_and_b32_e32 v5, 0x7fffffff, v5
	v_add_co_u32 v5, vcc_lo, v5, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v14, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[5:6]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_32
; %bb.33:                               ; %_Z11gm31_CNext2jjjj.exit.i.i45
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s18, s5, 0x7ffffffd
	s_mul_hi_u32 s19, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s20, s4, 0x7ffffffd
	s_add_i32 s19, s19, s18
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s19
.LBB1_34:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s18, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_34
; %bb.35:                               ; %_Z11gm31_CNext2jjjj.exit19.i.i48
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB1_36:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB1_36
; %bb.37:                               ; %_Z11gm31_CNext2jjjj.exit21.i.i50
                                        ;   in Loop: Header=BB1_31 Depth=2
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s14
	s_cbranch_scc1 .LBB1_31
.LBB1_38:                               ; %_Z13gm31_GetNextNjjj.exit.i52
                                        ;   in Loop: Header=BB1_28 Depth=1
	v_mad_u64_u32 v[6:7], null, v9, 11, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v10, -14, v[6:7]
	v_sub_nc_u32_e32 v7, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v12, -14
	v_add_co_ci_u32_e32 v7, vcc_lo, 6, v7, vcc_lo
.LBB1_39:                               ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB1_39
; %bb.40:                               ; %_Z10gm31_CNextjj.exit.i56
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB1_49
; %bb.41:                               ; %.lr.ph.i23.i57
                                        ;   in Loop: Header=BB1_28 Depth=1
	v_sub_co_u32 v9, s4, 0x7fffffff, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v10, null, 0, 0, s4
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s16, 0
.LBB1_42:                               ;   Parent Loop BB1_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_43 Depth 3
                                        ;       Child Loop BB1_45 Depth 3
                                        ;       Child Loop BB1_47 Depth 3
	v_mul_lo_u32 v7, s5, v9
	v_mul_lo_u32 v14, s4, v10
	v_mad_u64_u32 v[12:13], null, s4, v9, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v13, v13, v14, v7
	v_mad_u64_u32 v[14:15], null, s10, v6, v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
.LBB1_43:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_43
; %bb.44:                               ; %_Z11gm31_CNext2jjjj.exit.i31.i65
                                        ;   in Loop: Header=BB1_42 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s17, s5, 0x7ffffffd
	s_mul_hi_u32 s18, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s19, s4, 0x7ffffffd
	s_add_i32 s18, s18, s17
	s_add_u32 s10, s10, s19
	s_addc_u32 s11, s11, s18
.LBB1_45:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s17, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB1_45
; %bb.46:                               ; %_Z11gm31_CNext2jjjj.exit19.i34.i68
                                        ;   in Loop: Header=BB1_42 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB1_47:                               ;   Parent Loop BB1_28 Depth=1
                                        ;     Parent Loop BB1_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB1_47
; %bb.48:                               ; %_Z11gm31_CNext2jjjj.exit21.i36.i70
                                        ;   in Loop: Header=BB1_42 Depth=2
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, s14
	s_cbranch_scc1 .LBB1_42
.LBB1_49:                               ;   in Loop: Header=BB1_28 Depth=1
	v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v5
.LBB1_50:                               ; %Flow204
                                        ;   in Loop: Header=BB1_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_lshrrev_b64 v[5:6], 1, v[3:4]
	v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_28
; %bb.51:                               ; %Flow205
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_52:                               ; %Flow206
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_cmp_lt_i64_e64 s0, s[0:1], 1
	v_add_nc_u32_e32 v3, 0x400, v11
	ds_store_b32 v11, v10 offset:512
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_63
; %bb.53:                               ; %.lr.ph
	v_and_b32_e32 v7, 3, v0
	v_dual_mov_b32 v13, 0 :: v_dual_and_b32 v0, 15, v0
	v_add_nc_u32_e32 v4, 0x200, v11
	v_lshlrev_b32_e64 v5, v8, 1
	v_add_nc_u32_e32 v6, 8, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_eq_u32_e64 s1, 0, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_cmp_eq_u32_e64 s0, 0, v7
	v_add_nc_u32_e32 v7, 16, v11
	v_add_nc_u32_e32 v2, 32, v11
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v9, 48, v11
	v_cmp_eq_u32_e64 s2, 0, v8
	v_add_co_u32 v10, vcc_lo, s6, v0
	v_add_nc_u32_e32 v8, 64, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v1, vcc_lo
	s_mov_b32 s7, 0
	s_mov_b64 s[4:5], 0x80000000
	s_mov_b64 s[10:11], 0
	s_mov_b32 s6, s7
.LBB1_54:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_55 Depth 2
	ds_load_b32 v15, v3
	ds_load_b32 v14, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(1)
	v_mad_u64_u32 v[0:1], null, v15, -14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v15
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[15:16], null, v14, 11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v15, -14
	v_add_co_ci_u32_e32 v1, vcc_lo, 6, v16, vcc_lo
.LBB1_55:                               ;   Parent Loop BB1_54 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[15:16], 31, v[0:1]
	v_and_b32_e32 v0, 0x7fffffff, v0
	v_add_co_u32 v0, vcc_lo, v0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v16, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_55
; %bb.56:                               ; %_Z10gm31_CNextjj.exit
                                        ;   in Loop: Header=BB1_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_lt_u32_e32 vcc_lo, 0x3fffffff, v0
	v_cndmask_b32_e32 v1, 0, v5, vcc_lo
	ds_store_b32 v3, v14
	ds_store_b32 v4, v0
	ds_store_b32 v11, v1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB1_58
; %bb.57:                               ;   in Loop: Header=BB1_54 Depth=1
	ds_load_2addr_b32 v[0:1], v11 offset1:1
	ds_load_2addr_b32 v[14:15], v6 offset1:1
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v0, v1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v14, v15
	ds_store_b32 v11, v0
.LBB1_58:                               ;   in Loop: Header=BB1_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB1_60
; %bb.59:                               ;   in Loop: Header=BB1_54 Depth=1
	ds_load_b32 v0, v11
	ds_load_b32 v1, v7
	ds_load_b32 v14, v2
	ds_load_b32 v15, v9
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v0, v1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v14, v15
	ds_store_b32 v11, v0
.LBB1_60:                               ;   in Loop: Header=BB1_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_62
; %bb.61:                               ;   in Loop: Header=BB1_54 Depth=1
	ds_load_b32 v0, v11
	ds_load_b32 v1, v8
	s_lshl_b64 s[10:11], s[10:11], 2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, v0
	v_mul_f32_e32 v14, 0x2f800000, v0
	v_add_co_u32 v0, vcc_lo, v10, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v12, vcc_lo
	global_store_b32 v[0:1], v14, off
.LBB1_62:                               ;   in Loop: Header=BB1_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b64 v[0:1], v13, s[8:9]
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[10:11], s[6:7]
	s_waitcnt vmcnt(0)
	v_cmp_lt_i64_e32 vcc_lo, s[6:7], v[0:1]
	s_cbranch_vccnz .LBB1_54
.LBB1_63:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
		.amdhsa_group_segment_fixed_size 1536
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl, .Lfunc_end1-_Z32gm31_kernel_generate_array_floatP10gm31_statePfPl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2624
; NumSgprs: 23
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1536 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl ; -- Begin function _Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.globl	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
	.p2align	8
	.type	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl,@function
_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl: ; @_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
; %bb.0:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[0:1], 0x10
	v_and_b32_e32 v8, 31, v0
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 2, v8
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b32 v10, v1, s[4:5] offset:128
	global_load_b32 v9, v1, s[4:5]
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[0:1], s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_lshrrev_b32_e32 v5, 5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s0, v5, 0
	v_mad_u64_u32 v[3:4], null, s1, v5, v[2:3]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v7, v10
	v_cmpx_ne_u64_e32 0, v[1:2]
	s_cbranch_execz .LBB2_26
; %bb.1:                                ; %.lr.ph.i.preheader
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v7, v10
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v11, v9
	s_mov_b64 s[2:3], 0x80000000
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0
.LBB2_2:                                ; %.lr.ph.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_5 Depth 2
                                        ;       Child Loop BB2_6 Depth 3
                                        ;       Child Loop BB2_8 Depth 3
                                        ;       Child Loop BB2_10 Depth 3
                                        ;     Child Loop BB2_13 Depth 2
                                        ;     Child Loop BB2_16 Depth 2
                                        ;       Child Loop BB2_17 Depth 3
                                        ;       Child Loop BB2_19 Depth 3
                                        ;       Child Loop BB2_21 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 1, v3
	s_mov_b32 s15, exec_lo
	v_cmpx_eq_u32_e32 1, v5
	s_cbranch_execz .LBB2_24
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v5, v11
	s_cmp_lg_u32 s14, 0
	s_cselect_b32 s16, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB2_12
; %bb.4:                                ; %.lr.ph.i.i
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_sub_co_u32 v12, s4, 0x7fffffff, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v13, null, 0, 0, s4
	v_mov_b32_e32 v5, v11
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s17, 0
.LBB2_5:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_6 Depth 3
                                        ;       Child Loop BB2_8 Depth 3
                                        ;       Child Loop BB2_10 Depth 3
	v_mul_lo_u32 v6, s5, v12
	v_mul_lo_u32 v16, s4, v13
	v_mad_u64_u32 v[14:15], null, s4, v12, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v15, v15, v16, v6
	v_mad_u64_u32 v[16:17], null, s10, v5, v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v5, v16 :: v_dual_mov_b32 v6, v17
.LBB2_6:                                ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[14:15], 31, v[5:6]
	v_and_b32_e32 v5, 0x7fffffff, v5
	v_add_co_u32 v5, vcc_lo, v5, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v15, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[5:6]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB2_6
; %bb.7:                                ; %_Z11gm31_CNext2jjjj.exit.i.i
                                        ;   in Loop: Header=BB2_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s18, s5, 0x7ffffffd
	s_mul_hi_u32 s19, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s20, s4, 0x7ffffffd
	s_add_i32 s19, s19, s18
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s19
.LBB2_8:                                ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s18, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB2_8
; %bb.9:                                ; %_Z11gm31_CNext2jjjj.exit19.i.i
                                        ;   in Loop: Header=BB2_5 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB2_10:                               ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB2_10
; %bb.11:                               ; %_Z11gm31_CNext2jjjj.exit21.i.i
                                        ;   in Loop: Header=BB2_5 Depth=2
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s14
	s_cbranch_scc1 .LBB2_5
.LBB2_12:                               ; %_Z13gm31_GetNextNjjj.exit.i
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_mad_u64_u32 v[12:13], null, v11, 11, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, v7, -14, v[12:13]
	v_sub_nc_u32_e32 v7, v15, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v14, -14
	v_add_co_ci_u32_e32 v7, vcc_lo, 6, v7, vcc_lo
.LBB2_13:                               ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB2_13
; %bb.14:                               ; %_Z10gm31_CNextjj.exit.i
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB2_23
; %bb.15:                               ; %.lr.ph.i23.i
                                        ;   in Loop: Header=BB2_2 Depth=1
	v_sub_co_u32 v11, s4, 0x7fffffff, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v12, null, 0, 0, s4
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s16, 0
.LBB2_16:                               ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_17 Depth 3
                                        ;       Child Loop BB2_19 Depth 3
                                        ;       Child Loop BB2_21 Depth 3
	v_mul_lo_u32 v7, s5, v11
	v_mul_lo_u32 v15, s4, v12
	v_mad_u64_u32 v[13:14], null, s4, v11, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v15, v7
	v_mad_u64_u32 v[15:16], null, s10, v6, v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v6, v15 :: v_dual_mov_b32 v7, v16
.LBB2_17:                               ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[13:14], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v14, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB2_17
; %bb.18:                               ; %_Z11gm31_CNext2jjjj.exit.i31.i
                                        ;   in Loop: Header=BB2_16 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s17, s5, 0x7ffffffd
	s_mul_hi_u32 s18, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s19, s4, 0x7ffffffd
	s_add_i32 s18, s18, s17
	s_add_u32 s10, s10, s19
	s_addc_u32 s11, s11, s18
.LBB2_19:                               ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s17, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB2_19
; %bb.20:                               ; %_Z11gm31_CNext2jjjj.exit19.i34.i
                                        ;   in Loop: Header=BB2_16 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB2_21:                               ;   Parent Loop BB2_2 Depth=1
                                        ;     Parent Loop BB2_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB2_21
; %bb.22:                               ; %_Z11gm31_CNext2jjjj.exit21.i36.i
                                        ;   in Loop: Header=BB2_16 Depth=2
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, s14
	s_cbranch_scc1 .LBB2_16
.LBB2_23:                               ;   in Loop: Header=BB2_2 Depth=1
	v_mov_b32_e32 v11, v6
	v_mov_b32_e32 v7, v5
.LBB2_24:                               ; %Flow210
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_lshrrev_b64 v[5:6], 1, v[3:4]
	v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB2_2
; %bb.25:                               ; %Flow211
	s_or_b32 exec_lo, exec_lo, s13
.LBB2_26:                               ; %Flow212
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_co_u32 v3, vcc_lo, v1, 1
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	v_lshlrev_b32_e32 v11, 2, v0
	s_mov_b32 s12, exec_lo
	ds_store_b32 v11, v7 offset:1024
	v_cmpx_ne_u64_e32 0, v[3:4]
	s_cbranch_execz .LBB2_52
; %bb.27:                               ; %.lr.ph.i29.preheader
	s_mov_b64 s[2:3], 0x80000000
	s_mov_b32 s13, 0
	s_mov_b32 s14, 0
.LBB2_28:                               ; %.lr.ph.i29
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_31 Depth 2
                                        ;       Child Loop BB2_32 Depth 3
                                        ;       Child Loop BB2_34 Depth 3
                                        ;       Child Loop BB2_36 Depth 3
                                        ;     Child Loop BB2_39 Depth 2
                                        ;     Child Loop BB2_42 Depth 2
                                        ;       Child Loop BB2_43 Depth 3
                                        ;       Child Loop BB2_45 Depth 3
                                        ;       Child Loop BB2_47 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 1, v3
	s_mov_b32 s15, exec_lo
	v_cmpx_eq_u32_e32 1, v5
	s_cbranch_execz .LBB2_50
; %bb.29:                               ;   in Loop: Header=BB2_28 Depth=1
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v5, v9
	s_cmp_lg_u32 s14, 0
	s_cselect_b32 s16, -1, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB2_38
; %bb.30:                               ; %.lr.ph.i.i37
                                        ;   in Loop: Header=BB2_28 Depth=1
	v_sub_co_u32 v7, s4, 0x7fffffff, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v12, null, 0, 0, s4
	v_mov_b32_e32 v5, v9
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s17, 0
.LBB2_31:                               ;   Parent Loop BB2_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_32 Depth 3
                                        ;       Child Loop BB2_34 Depth 3
                                        ;       Child Loop BB2_36 Depth 3
	v_mul_lo_u32 v6, s5, v7
	v_mul_lo_u32 v15, s4, v12
	v_mad_u64_u32 v[13:14], null, s4, v7, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v14, v14, v15, v6
	v_mad_u64_u32 v[15:16], null, s10, v5, v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v5, v15 :: v_dual_mov_b32 v6, v16
.LBB2_32:                               ;   Parent Loop BB2_28 Depth=1
                                        ;     Parent Loop BB2_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[13:14], 31, v[5:6]
	v_and_b32_e32 v5, 0x7fffffff, v5
	v_add_co_u32 v5, vcc_lo, v5, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v14, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[5:6]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB2_32
; %bb.33:                               ; %_Z11gm31_CNext2jjjj.exit.i.i45
                                        ;   in Loop: Header=BB2_31 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s18, s5, 0x7ffffffd
	s_mul_hi_u32 s19, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s20, s4, 0x7ffffffd
	s_add_i32 s19, s19, s18
	s_add_u32 s10, s10, s20
	s_addc_u32 s11, s11, s19
.LBB2_34:                               ;   Parent Loop BB2_28 Depth=1
                                        ;     Parent Loop BB2_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s18, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB2_34
; %bb.35:                               ; %_Z11gm31_CNext2jjjj.exit19.i.i48
                                        ;   in Loop: Header=BB2_31 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB2_36:                               ;   Parent Loop BB2_28 Depth=1
                                        ;     Parent Loop BB2_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB2_36
; %bb.37:                               ; %_Z11gm31_CNext2jjjj.exit21.i.i50
                                        ;   in Loop: Header=BB2_31 Depth=2
	s_add_i32 s17, s17, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s17, s14
	s_cbranch_scc1 .LBB2_31
.LBB2_38:                               ; %_Z13gm31_GetNextNjjj.exit.i52
                                        ;   in Loop: Header=BB2_28 Depth=1
	v_mad_u64_u32 v[6:7], null, v9, 11, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v10, -14, v[6:7]
	v_sub_nc_u32_e32 v7, v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v12, -14
	v_add_co_ci_u32_e32 v7, vcc_lo, 6, v7, vcc_lo
.LBB2_39:                               ;   Parent Loop BB2_28 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s4, vcc_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB2_39
; %bb.40:                               ; %_Z10gm31_CNextjj.exit.i56
                                        ;   in Loop: Header=BB2_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB2_49
; %bb.41:                               ; %.lr.ph.i23.i57
                                        ;   in Loop: Header=BB2_28 Depth=1
	v_sub_co_u32 v9, s4, 0x7fffffff, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v10, null, 0, 0, s4
	s_mov_b64 s[10:11], 11
	s_mov_b64 s[4:5], 14
	s_mov_b32 s16, 0
.LBB2_42:                               ;   Parent Loop BB2_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_43 Depth 3
                                        ;       Child Loop BB2_45 Depth 3
                                        ;       Child Loop BB2_47 Depth 3
	v_mul_lo_u32 v7, s5, v9
	v_mul_lo_u32 v14, s4, v10
	v_mad_u64_u32 v[12:13], null, s4, v9, 0
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v13, v13, v14, v7
	v_mad_u64_u32 v[14:15], null, s10, v6, v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v6, v14 :: v_dual_mov_b32 v7, v15
.LBB2_43:                               ;   Parent Loop BB2_28 Depth=1
                                        ;     Parent Loop BB2_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[12:13], 31, v[6:7]
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_add_co_u32 v6, vcc_lo, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v13, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[6:7]
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB2_43
; %bb.44:                               ; %_Z11gm31_CNext2jjjj.exit.i31.i65
                                        ;   in Loop: Header=BB2_42 Depth=2
	s_or_b32 exec_lo, exec_lo, s11
	s_mul_i32 s17, s5, 0x7ffffffd
	s_mul_hi_u32 s18, s4, 0x7ffffffd
	s_mul_hi_u32 s11, s10, s10
	s_mul_i32 s10, s10, s10
	s_mul_i32 s19, s4, 0x7ffffffd
	s_add_i32 s18, s18, s17
	s_add_u32 s10, s10, s19
	s_addc_u32 s11, s11, s18
.LBB2_45:                               ;   Parent Loop BB2_28 Depth=1
                                        ;     Parent Loop BB2_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[10:11], 31
	s_bitset0_b32 s10, 31
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s17, 0x7fffffff, s[10:11]
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccnz .LBB2_45
; %bb.46:                               ; %_Z11gm31_CNext2jjjj.exit19.i34.i68
                                        ;   in Loop: Header=BB2_42 Depth=2
	s_mul_i32 s5, s4, s5
	s_mul_hi_u32 s11, s4, s4
	s_mul_i32 s4, s4, s4
	s_add_i32 s11, s11, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s5, s11, s5
.LBB2_47:                               ;   Parent Loop BB2_28 Depth=1
                                        ;     Parent Loop BB2_42 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_lshr_b64 s[18:19], s[4:5], 31
	s_bitset0_b32 s4, 31
	s_add_u32 s4, s4, s18
	s_addc_u32 s5, 0, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s11, 0x7fffffff, s[4:5]
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB2_47
; %bb.48:                               ; %_Z11gm31_CNext2jjjj.exit21.i36.i70
                                        ;   in Loop: Header=BB2_42 Depth=2
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s16, s14
	s_cbranch_scc1 .LBB2_42
.LBB2_49:                               ;   in Loop: Header=BB2_28 Depth=1
	v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v5
.LBB2_50:                               ; %Flow204
                                        ;   in Loop: Header=BB2_28 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	v_lshrrev_b64 v[5:6], 1, v[3:4]
	v_cmp_gt_u64_e32 vcc_lo, 2, v[3:4]
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
	s_or_b32 s13, vcc_lo, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB2_28
; %bb.51:                               ; %Flow205
	s_or_b32 exec_lo, exec_lo, s13
.LBB2_52:                               ; %Flow206
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_cmp_lt_i64_e64 s0, s[0:1], 1
	v_add_nc_u32_e32 v3, 0x400, v11
	ds_store_b32 v11, v10 offset:512
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB2_63
; %bb.53:                               ; %.lr.ph
	v_and_b32_e32 v7, 3, v0
	v_dual_mov_b32 v13, 0 :: v_dual_and_b32 v0, 15, v0
	v_add_nc_u32_e32 v4, 0x200, v11
	v_lshlrev_b32_e64 v5, v8, 1
	v_add_nc_u32_e32 v6, 8, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_eq_u32_e64 s1, 0, v0
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_cmp_eq_u32_e64 s0, 0, v7
	v_add_nc_u32_e32 v7, 16, v11
	v_add_nc_u32_e32 v2, 32, v11
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v9, 48, v11
	v_cmp_eq_u32_e64 s2, 0, v8
	v_add_co_u32 v10, vcc_lo, s6, v0
	v_add_nc_u32_e32 v8, 64, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v1, vcc_lo
	s_mov_b32 s7, 0
	s_mov_b64 s[4:5], 0x80000000
	s_mov_b64 s[10:11], 0
	s_mov_b32 s6, s7
.LBB2_54:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_55 Depth 2
	ds_load_b32 v15, v3
	ds_load_b32 v14, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(1)
	v_mad_u64_u32 v[0:1], null, v15, -14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v15
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[15:16], null, v14, 11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v15, -14
	v_add_co_ci_u32_e32 v1, vcc_lo, 6, v16, vcc_lo
.LBB2_55:                               ;   Parent Loop BB2_54 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b64 v[15:16], 31, v[0:1]
	v_and_b32_e32 v0, 0x7fffffff, v0
	v_add_co_u32 v0, vcc_lo, v0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v16, vcc_lo
	v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_55
; %bb.56:                               ; %_Z10gm31_CNextjj.exit
                                        ;   in Loop: Header=BB2_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_lt_u32_e32 vcc_lo, 0x3fffffff, v0
	v_cndmask_b32_e32 v1, 0, v5, vcc_lo
	ds_store_b32 v3, v14
	ds_store_b32 v4, v0
	ds_store_b32 v11, v1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB2_58
; %bb.57:                               ;   in Loop: Header=BB2_54 Depth=1
	ds_load_2addr_b32 v[0:1], v11 offset1:1
	ds_load_2addr_b32 v[14:15], v6 offset1:1
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v0, v1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v14, v15
	ds_store_b32 v11, v0
.LBB2_58:                               ;   in Loop: Header=BB2_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB2_60
; %bb.59:                               ;   in Loop: Header=BB2_54 Depth=1
	ds_load_b32 v0, v11
	ds_load_b32 v1, v7
	ds_load_b32 v14, v2
	ds_load_b32 v15, v9
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v0, v1, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v0, v14, v15
	ds_store_b32 v11, v0
.LBB2_60:                               ;   in Loop: Header=BB2_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_62
; %bb.61:                               ;   in Loop: Header=BB2_54 Depth=1
	ds_load_b32 v0, v11
	ds_load_b32 v1, v8
	s_lshl_b64 s[10:11], s[10:11], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, vcc_lo, v10, s10
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v12, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v1, v0
	v_cvt_f64_u32_e32 v[0:1], v0
	s_delay_alu instid0(VALU_DEP_1)
	v_ldexp_f64 v[0:1], v[0:1], 0xffffffe0
	global_store_b64 v[14:15], v[0:1], off
.LBB2_62:                               ;   in Loop: Header=BB2_54 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	global_load_b64 v[0:1], v13, s[8:9]
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b64 s[10:11], s[6:7]
	s_waitcnt vmcnt(0)
	v_cmp_lt_i64_e32 vcc_lo, s[6:7], v[0:1]
	s_cbranch_vccnz .LBB2_54
.LBB2_63:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
		.amdhsa_group_segment_fixed_size 1536
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl, .Lfunc_end2-_Z33gm31_kernel_generate_array_doubleP10gm31_statePdPl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2632
; NumSgprs: 23
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1536 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1536
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26gm31_kernel_generate_arrayP10gm31_statePjPl
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z26gm31_kernel_generate_arrayP10gm31_statePjPl.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
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amdhsa.version:
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...

	.end_amdgpu_metadata
