
// Babak Poursartip
// 09/28/2020

// warp divergence

//>>>>>>>>>>>>>>. to check the branch_efficiency:
// nvcc -G 2_warp_divergence.cu  -o 2_warp_divergence.out
// sudo nvprof --metrics branch_efficiency  ./2_warp_divergence.out
// here is the outpu:

/*
starts ...
size: 4194304 - block.x: 128 - grid.x: 32768
==32934== NVPROF is profiling process 32934, command: ./2_warp_divergence.out
execution time without warp divergence: 0.192828 
execution time with warp divergence: 0.008774 
done.
==32934== Profiling application: ./2_warp_divergence.out
==32934== Profiling result:
==32934== Metric result:
Invocations                               Metric Name                        Metric Description         Min         Max         Avg
Device "NVIDIA GeForce GT 1030 (0)"
   Kernel: code_without_divergence(void)
         1                         branch_efficiency                         Branch Efficiency     100.00%     100.00%     100.00%
   Kernel: code_with_divergence(void)
         1                         branch_efficiency                         Branch Efficiency      83.33%      83.33%      83.33%

*/

#include <iostream>
#include <time.h>

__global__ void code_without_divergence() 
{
  int gid = blockDim.x * blockIdx.x + threadIdx.x;

  float a = 0, b = 0;

  int warp_id = gid / 64;

  if (warp_id % 2 == 0) {
    a = 100.0;
    b = 50.0;
  } else {
    a = 200.0;
    b = 72.0;
  }
}

__global__ void code_with_divergence() 
{
  int gid = blockDim.x * blockIdx.x + threadIdx.x;

  float a = 0, b = 0;

  if (gid % 2 == 0) {
    a = 100.0;
    b = 50.0;
  } else {
    a = 200.0;
    b = 72.0;
  }
}

int main() {
  printf(" starts ...\n");

  int size = 1 << 22;
  
  dim3 block(128);
  dim3 grid((size + block.x - 1) / block.x);
  printf(" size: %d - block.x: %d - grid.x: %d\n", size, block.x, grid.x);
  
  clock_t start, end;

  start = clock();
  code_without_divergence<<<grid, block>>>();
  cudaDeviceSynchronize();
  end = clock();
  printf(" execution time without warp divergence: %4.6f \n", (double)((double)(end - start) / CLOCKS_PER_SEC));

  start = clock();
  code_with_divergence<<<grid, block>>>();
  cudaDeviceSynchronize();
  end = clock();
  printf(" execution time with warp divergence: %4.6f \n", (double)((double)(end - start) / CLOCKS_PER_SEC));

  cudaDeviceSynchronize();
  printf(" done.\n");

  return 0;
}
	.file	"tmpxft_0035d961_00000000-6_2_warp_divergence.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z23code_without_divergencevv
	.type	_Z42__device_stub__Z23code_without_divergencevv, @function
_Z42__device_stub__Z23code_without_divergencevv:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z23code_without_divergencev(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L2:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z42__device_stub__Z23code_without_divergencevv, .-_Z42__device_stub__Z23code_without_divergencevv
	.globl	_Z23code_without_divergencev
	.type	_Z23code_without_divergencev, @function
_Z23code_without_divergencev:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z23code_without_divergencevv
	.cfi_endproc
.LFE3661:
	.size	_Z23code_without_divergencev, .-_Z23code_without_divergencev
	.globl	_Z39__device_stub__Z20code_with_divergencevv
	.type	_Z39__device_stub__Z20code_with_divergencevv, @function
_Z39__device_stub__Z20code_with_divergencevv:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z20code_with_divergencev(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L8:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z39__device_stub__Z20code_with_divergencevv, .-_Z39__device_stub__Z20code_with_divergencevv
	.globl	_Z20code_with_divergencev
	.type	_Z20code_with_divergencev, @function
_Z20code_with_divergencev:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z20code_with_divergencevv
	.cfi_endproc
.LFE3663:
	.size	_Z20code_with_divergencev, .-_Z20code_with_divergencev
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	" starts ...\n"
.LC1:
	.string	" size: %d - block.x: %d - grid.x: %d\n"
.LC3:
	.string	" execution time without warp divergence: %4.6f \n"
.LC4:
	.string	" execution time with warp divergence: %4.6f \n"
.LC5:
	.string	" done.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
	movl	$32768, %r8d
	xorl	%eax, %eax
	movl	$128, %ecx
	movl	$4194304, %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	call	clock@PLT
	movl	$131073, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$33554433, %edx
	salq	$15, %rdi
	movq	%rax, %rbx
	movl	$1, %ecx
	salq	$7, %rdx
	movl	$1, %esi
	movq	%rdi, 20(%rsp)
	movl	$1, 28(%rsp)
	movq	%rdx, 8(%rsp)
	movl	$1, 16(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	call	_Z42__device_stub__Z23code_without_divergencevv
.L14:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	subq	%rbx, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC2(%rip), %xmm0
	call	__printf_chk@PLT
	call	clock@PLT
	movl	16(%rsp), %ecx
	movl	28(%rsp), %esi
	xorl	%r9d, %r9d
	movq	8(%rsp), %rdx
	movq	20(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rax, %rbx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	call	_Z39__device_stub__Z20code_with_divergencevv
.L15:
	call	cudaDeviceSynchronize@PLT
	call	clock@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	subq	%rbx, %rax
	cvtsi2sdq	%rax, %xmm0
	movb	$1, %al
	divsd	.LC2(%rip), %xmm0
	call	__printf_chk@PLT
	call	cudaDeviceSynchronize@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z20code_with_divergencev"
.LC7:
	.string	"_Z23code_without_divergencev"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3665:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z20code_with_divergencev(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z23code_without_divergencev(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3665:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


// Babak Poursartip
// 09/28/2020

// warp divergence

//>>>>>>>>>>>>>>. to check the branch_efficiency:
// nvcc -G 2_warp_divergence.cu  -o 2_warp_divergence.out
// sudo nvprof --metrics branch_efficiency  ./2_warp_divergence.out
// here is the outpu:

/*
starts ...
size: 4194304 - block.x: 128 - grid.x: 32768
==32934== NVPROF is profiling process 32934, command: ./2_warp_divergence.out
execution time without warp divergence: 0.192828 
execution time with warp divergence: 0.008774 
done.
==32934== Profiling application: ./2_warp_divergence.out
==32934== Profiling result:
==32934== Metric result:
Invocations                               Metric Name                        Metric Description         Min         Max         Avg
Device "NVIDIA GeForce GT 1030 (0)"
   Kernel: code_without_divergence(void)
         1                         branch_efficiency                         Branch Efficiency     100.00%     100.00%     100.00%
   Kernel: code_with_divergence(void)
         1                         branch_efficiency                         Branch Efficiency      83.33%      83.33%      83.33%

*/


#include <hip/hip_runtime.h>
#include <iostream>
#include <time.h>

__global__ void code_without_divergence() 
{
  int gid = blockDim.x * blockIdx.x + threadIdx.x;

  float a = 0, b = 0;

  int warp_id = gid / 64;

  if (warp_id % 2 == 0) {
    a = 100.0;
    b = 50.0;
  } else {
    a = 200.0;
    b = 72.0;
  }
}

__global__ void code_with_divergence() 
{
  int gid = blockDim.x * blockIdx.x + threadIdx.x;

  float a = 0, b = 0;

  if (gid % 2 == 0) {
    a = 100.0;
    b = 50.0;
  } else {
    a = 200.0;
    b = 72.0;
  }
}

int main() {
  printf(" starts ...\n");

  int size = 1 << 22;
  
  dim3 block(128);
  dim3 grid((size + block.x - 1) / block.x);
  printf(" size: %d - block.x: %d - grid.x: %d\n", size, block.x, grid.x);
  
  clock_t start, end;

  start = clock();
  code_without_divergence<<<grid, block>>>();
  hipDeviceSynchronize();
  end = clock();
  printf(" execution time without warp divergence: %4.6f \n", (double)((double)(end - start) / CLOCKS_PER_SEC));

  start = clock();
  code_with_divergence<<<grid, block>>>();
  hipDeviceSynchronize();
  end = clock();
  printf(" execution time with warp divergence: %4.6f \n", (double)((double)(end - start) / CLOCKS_PER_SEC));

  hipDeviceSynchronize();
  printf(" done.\n");

  return 0;
}
	.text
	.file	"2_warp_divergence.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z38__device_stub__code_without_divergencev # -- Begin function _Z38__device_stub__code_without_divergencev
	.type	_Z38__device_stub__code_without_divergencev,@function
_Z38__device_stub__code_without_divergencev: # @_Z38__device_stub__code_without_divergencev
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z23code_without_divergencev, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z38__device_stub__code_without_divergencev, .Lfunc_end0-_Z38__device_stub__code_without_divergencev
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__code_with_divergencev # -- Begin function _Z35__device_stub__code_with_divergencev
	.type	_Z35__device_stub__code_with_divergencev,@function
_Z35__device_stub__code_with_divergencev: # @_Z35__device_stub__code_with_divergencev
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z20code_with_divergencev, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z35__device_stub__code_with_divergencev, .Lfunc_end1-_Z35__device_stub__code_with_divergencev
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294967424, %rbx               # imm = 0x100000080
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.L.str.1, %edi
	movl	$4194304, %esi                  # imm = 0x400000
	movl	$128, %edx
	movl	$32768, %ecx                    # imm = 0x8000
	xorl	%eax, %eax
	callq	printf
	callq	clock
	movq	%rax, %r15
	leaq	32640(%rbx), %r14
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	callq	_Z38__device_stub__code_without_divergencev
.LBB2_2:
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r15, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	callq	clock
	movq	%rax, %r15
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	callq	_Z35__device_stub__code_with_divergencev
.LBB2_4:
	callq	hipDeviceSynchronize
	callq	clock
	subq	%r15, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	callq	hipDeviceSynchronize
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23code_without_divergencev, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20code_with_divergencev, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z23code_without_divergencev,@object # @_Z23code_without_divergencev
	.section	.rodata,"a",@progbits
	.globl	_Z23code_without_divergencev
	.p2align	3, 0x0
_Z23code_without_divergencev:
	.quad	_Z38__device_stub__code_without_divergencev
	.size	_Z23code_without_divergencev, 8

	.type	_Z20code_with_divergencev,@object # @_Z20code_with_divergencev
	.globl	_Z20code_with_divergencev
	.p2align	3, 0x0
_Z20code_with_divergencev:
	.quad	_Z35__device_stub__code_with_divergencev
	.size	_Z20code_with_divergencev, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	" size: %d - block.x: %d - grid.x: %d\n"
	.size	.L.str.1, 38

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" execution time without warp divergence: %4.6f \n"
	.size	.L.str.2, 49

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" execution time with warp divergence: %4.6f \n"
	.size	.L.str.3, 46

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z23code_without_divergencev"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z20code_with_divergencev"
	.size	.L__unnamed_2, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	" starts ..."
	.size	.Lstr, 12

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	" done."
	.size	.Lstr.1, 7

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z38__device_stub__code_without_divergencev
	.addrsig_sym _Z35__device_stub__code_with_divergencev
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z23code_without_divergencev
	.addrsig_sym _Z20code_with_divergencev
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z23code_without_divergencev ; -- Begin function _Z23code_without_divergencev
	.globl	_Z23code_without_divergencev
	.p2align	8
	.type	_Z23code_without_divergencev,@function
_Z23code_without_divergencev:           ; @_Z23code_without_divergencev
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23code_without_divergencev
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z23code_without_divergencev, .Lfunc_end0-_Z23code_without_divergencev
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20code_with_divergencev ; -- Begin function _Z20code_with_divergencev
	.globl	_Z20code_with_divergencev
	.p2align	8
	.type	_Z20code_with_divergencev,@function
_Z20code_with_divergencev:              ; @_Z20code_with_divergencev
; %bb.0:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20code_with_divergencev
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 0
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 0
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 1
		.amdhsa_next_free_sgpr 1
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z20code_with_divergencev, .Lfunc_end1-_Z20code_with_divergencev
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4
; NumSgprs: 0
; NumVgprs: 0
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 1
; NumVGPRsForWavesPerEU: 1
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23code_without_divergencev
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z23code_without_divergencev.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:           []
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 4
    .kernarg_segment_size: 0
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20code_with_divergencev
    .private_segment_fixed_size: 0
    .sgpr_count:     0
    .sgpr_spill_count: 0
    .symbol:         _Z20code_with_divergencev.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     0
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
