#include <stdio.h>
#include <stdint.h>
#include <math.h>
#include <unistd.h>
#include <stdlib.h>
#include <cuda.h>
#include <ctime>
#include <iostream>


// timing of functions
clock_t start,end;


/* invert and square every element of the input array in parallel */
__global__ void _innergpu_2_sqr(double *psum, int64_t panel)
{
    int64_t globalIdx;
    int64_t tndx = threadIdx.x;
    int64_t bndx=  blockIdx.x;
    int64_t bdim=  blockDim.x;

    globalIdx = bdim * ( bndx + panel * bdim) + tndx + 1;

    double  r = 1.0/(double)globalIdx;
    double r2 = r*r;
    //printf("bdim = %li, bndx = %li, tndx = %li, globalIdx = %li\n",bdim,bndx,tndx,globalIdx);
    atomicAdd(&psum[tndx],r2);
}

int main()
{

    int64_t   N = 16000000000;
    //int64_t   N = 1600000;
    //int Nthr=1024;
    int i , Nthr=1024;
    int64_t Nblocks,Npanels, j;

    double sum = 0.0;
    int64_t _N;

    _N = N - (N %  Nthr);
    Npanels = 1;
    Nblocks = (int64_t)ceil((double)_N/(double)Nthr);
    //printf(" original: N = %li, _N = %li, Npanels = %li, Nblocks = %li\n",N,_N,Npanels,Nblocks);
    if (Nblocks > Nthr*Nthr) {
        Nblocks = Nthr*Nthr;
        Npanels = (int64_t)ceil((double)_N/((double)Nthr*(double)Nblocks));
    }

    double *ps_h, *ps_d;
    start = std::clock();
    //printf("post: N = %li, _N = %li, Npanels = %li, Nblocks = %li\n",N,_N,Npanels,Nblocks);
    ps_h = (double*)calloc(Nthr,sizeof(double));
    cudaMalloc(  &ps_d, Nthr * sizeof(double) );
    cudaMemcpy(ps_d,ps_h,Nthr*sizeof(double), cudaMemcpyHostToDevice);

    // we will handle the remaining portions on CPU, here
    for(i = N ; i>_N; i--) {
      sum += pow(1.0/(double)i,2.0);
    }

    // first compute inverse square
    for (j=0;j<Npanels;j++) {
       _innergpu_2_sqr<<< Nblocks, Nthr >>>(ps_d,j);
    }
    //_innergpu_2_sqr<<< _N, 1 >>>(ps_d);
    cudaMemcpy(ps_h,ps_d,Nthr*sizeof(double), cudaMemcpyDeviceToHost);
    for(i = 0 ; i<Nthr; i++) {
      //printf("ps_h[%li]=%18.15f, sum=%18.15f\n",i,ps_h[i],sum);
      sum += ps_h[i];
    }

    end = std::clock();


    // Clean up
    cudaFree(ps_d);
    free(ps_h);

    printf("sum = %18.16f\n",sum);
}

	.file	"tmpxft_002f7e7b_00000000-6_rzf_CUDA.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3651:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3651:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z15_innergpu_2_sqrPdlPdl
	.type	_Z36__device_stub__Z15_innergpu_2_sqrPdlPdl, @function
_Z36__device_stub__Z15_innergpu_2_sqrPdlPdl:
.LFB3673:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15_innergpu_2_sqrPdl(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3673:
	.size	_Z36__device_stub__Z15_innergpu_2_sqrPdlPdl, .-_Z36__device_stub__Z15_innergpu_2_sqrPdlPdl
	.globl	_Z15_innergpu_2_sqrPdl
	.type	_Z15_innergpu_2_sqrPdl, @function
_Z15_innergpu_2_sqrPdl:
.LFB3674:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z15_innergpu_2_sqrPdlPdl
	.cfi_endproc
.LFE3674:
	.size	_Z15_innergpu_2_sqrPdl, .-_Z15_innergpu_2_sqrPdl
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"sum = %18.16f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3648:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movabsq	$4294968320, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	clock@PLT
	movl	$8, %esi
	movl	$1024, %edi
	movq	%rax, start(%rip)
	call	calloc@PLT
	leaq	24(%rsp), %rdi
	movl	$8192, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$8192, %edx
	call	cudaMemcpy@PLT
.L10:
	movl	$4097, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	salq	$20, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	24(%rsp), %rdi
	movq	%rbp, %rsi
	call	_Z36__device_stub__Z15_innergpu_2_sqrPdlPdl
.L9:
	incq	%rbp
	cmpq	$15, %rbp
	jne	.L10
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$8192, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
	xorps	%xmm0, %xmm0
.L11:
	addsd	(%rbx,%rax,8), %xmm0
	incq	%rax
	cmpq	$1024, %rax
	jne	.L11
	movsd	%xmm0, 8(%rsp)
	call	clock@PLT
	movq	24(%rsp), %rdi
	movq	%rax, end(%rip)
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movsd	8(%rsp), %xmm0
	leaq	.LC1(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3648:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z15_innergpu_2_sqrPdl"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3676:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z15_innergpu_2_sqrPdl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3676:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	end
	.bss
	.align 8
	.type	end, @object
	.size	end, 8
end:
	.zero	8
	.globl	start
	.align 8
	.type	start, @object
	.size	start, 8
start:
	.zero	8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdint.h>
#include <math.h>
#include <unistd.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <ctime>
#include <iostream>


// timing of functions
clock_t start,end;


/* invert and square every element of the input array in parallel */
__global__ void _innergpu_2_sqr(double *psum, int64_t panel)
{
    int64_t globalIdx;
    int64_t tndx = threadIdx.x;
    int64_t bndx=  blockIdx.x;
    int64_t bdim=  blockDim.x;

    globalIdx = bdim * ( bndx + panel * bdim) + tndx + 1;

    double  r = 1.0/(double)globalIdx;
    double r2 = r*r;
    //printf("bdim = %li, bndx = %li, tndx = %li, globalIdx = %li\n",bdim,bndx,tndx,globalIdx);
    atomicAdd(&psum[tndx],r2);
}

int main()
{

    int64_t   N = 16000000000;
    //int64_t   N = 1600000;
    //int Nthr=1024;
    int i , Nthr=1024;
    int64_t Nblocks,Npanels, j;

    double sum = 0.0;
    int64_t _N;

    _N = N - (N %  Nthr);
    Npanels = 1;
    Nblocks = (int64_t)ceil((double)_N/(double)Nthr);
    //printf(" original: N = %li, _N = %li, Npanels = %li, Nblocks = %li\n",N,_N,Npanels,Nblocks);
    if (Nblocks > Nthr*Nthr) {
        Nblocks = Nthr*Nthr;
        Npanels = (int64_t)ceil((double)_N/((double)Nthr*(double)Nblocks));
    }

    double *ps_h, *ps_d;
    start = std::clock();
    //printf("post: N = %li, _N = %li, Npanels = %li, Nblocks = %li\n",N,_N,Npanels,Nblocks);
    ps_h = (double*)calloc(Nthr,sizeof(double));
    hipMalloc(  &ps_d, Nthr * sizeof(double) );
    hipMemcpy(ps_d,ps_h,Nthr*sizeof(double), hipMemcpyHostToDevice);

    // we will handle the remaining portions on CPU, here
    for(i = N ; i>_N; i--) {
      sum += pow(1.0/(double)i,2.0);
    }

    // first compute inverse square
    for (j=0;j<Npanels;j++) {
       _innergpu_2_sqr<<< Nblocks, Nthr >>>(ps_d,j);
    }
    //_innergpu_2_sqr<<< _N, 1 >>>(ps_d);
    hipMemcpy(ps_h,ps_d,Nthr*sizeof(double), hipMemcpyDeviceToHost);
    for(i = 0 ; i<Nthr; i++) {
      //printf("ps_h[%li]=%18.15f, sum=%18.15f\n",i,ps_h[i],sum);
      sum += ps_h[i];
    }

    end = std::clock();


    // Clean up
    hipFree(ps_d);
    free(ps_h);

    printf("sum = %18.16f\n",sum);
}

	.text
	.file	"rzf_CUDA.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z30__device_stub___innergpu_2_sqrPdl # -- Begin function _Z30__device_stub___innergpu_2_sqrPdl
	.type	_Z30__device_stub___innergpu_2_sqrPdl,@function
_Z30__device_stub___innergpu_2_sqrPdl:  # @_Z30__device_stub___innergpu_2_sqrPdl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15_innergpu_2_sqrPdl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub___innergpu_2_sqrPdl, .Lfunc_end0-_Z30__device_stub___innergpu_2_sqrPdl
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294968320, %r14               # imm = 0x100000400
	callq	clock
	movq	%rax, start(%rip)
	movl	$1024, %edi                     # imm = 0x400
	movl	$8, %esi
	callq	calloc
	movq	%rax, %rbx
	leaq	8(%rsp), %r15
	movl	$8192, %esi                     # imm = 0x2000
	movq	%r15, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$8192, %edx                     # imm = 0x2000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%r15d, %r15d
	leaq	1047552(%r14), %r12
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:                                #   in Loop: Header=BB1_1 Depth=1
	movq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	_Z30__device_stub___innergpu_2_sqrPdl
.LBB1_3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r15
	cmpq	$15, %r15
	jne	.LBB1_1
# %bb.4:
	movq	8(%rsp), %rsi
	movl	$8192, %edx                     # imm = 0x2000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorpd	%xmm0, %xmm0
	xorl	%eax, %eax
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	addsd	(%rbx,%rax,8), %xmm0
	incq	%rax
	cmpq	$1024, %rax                     # imm = 0x400
	jne	.LBB1_5
# %bb.6:
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	callq	clock
	movq	%rax, end(%rip)
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movl	$.L.str, %edi
	movsd	16(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15_innergpu_2_sqrPdl, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	start,@object                   # @start
	.bss
	.globl	start
	.p2align	3, 0x0
start:
	.quad	0                               # 0x0
	.size	start, 8

	.type	end,@object                     # @end
	.globl	end
	.p2align	3, 0x0
end:
	.quad	0                               # 0x0
	.size	end, 8

	.type	_Z15_innergpu_2_sqrPdl,@object  # @_Z15_innergpu_2_sqrPdl
	.section	.rodata,"a",@progbits
	.globl	_Z15_innergpu_2_sqrPdl
	.p2align	3, 0x0
_Z15_innergpu_2_sqrPdl:
	.quad	_Z30__device_stub___innergpu_2_sqrPdl
	.size	_Z15_innergpu_2_sqrPdl, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"sum = %18.16f\n"
	.size	.L.str, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15_innergpu_2_sqrPdl"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub___innergpu_2_sqrPdl
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15_innergpu_2_sqrPdl
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15_innergpu_2_sqrPdl  ; -- Begin function _Z15_innergpu_2_sqrPdl
	.globl	_Z15_innergpu_2_sqrPdl
	.p2align	8
	.type	_Z15_innergpu_2_sqrPdl,@function
_Z15_innergpu_2_sqrPdl:                 ; @_Z15_innergpu_2_sqrPdl
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v12, 3, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s4, s3
	s_mul_hi_u32 s5, s4, s2
	s_mul_i32 s2, s4, s2
	s_add_i32 s5, s5, s3
	s_add_u32 s2, s2, s15
	v_mad_u64_u32 v[2:3], null, s2, s4, v[0:1]
	s_addc_u32 s2, s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v3
	v_mad_u64_u32 v[3:4], null, s2, s4, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v3
	v_add_co_u32 v3, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_u32_e32 v[3:4], v3
	v_cvt_f64_i32_e32 v[1:2], v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[1:2], v[1:2], 32
	v_add_f64 v[4:5], v[1:2], v[3:4]
	global_load_b64 v[2:3], v12, s[0:1]
	v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[0:1], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[6:7], v[0:1], 1.0
	v_fma_f64 v[0:1], v[0:1], v[8:9], v[0:1]
	v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[0:1]
	v_fma_f64 v[6:7], -v[6:7], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[0:1], v[6:7], v[0:1], v[10:11]
	v_add_co_u32 v6, s0, s0, v12
	v_add_co_ci_u32_e64 v7, null, s1, 0, s0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[0:1], v[4:5], 1.0
	v_mul_f64 v[4:5], v[0:1], v[0:1]
.LBB0_1:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[2:3], v[4:5]
	global_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_1
; %bb.2:                                ; %atomicrmw.end
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15_innergpu_2_sqrPdl
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15_innergpu_2_sqrPdl, .Lfunc_end0-_Z15_innergpu_2_sqrPdl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15_innergpu_2_sqrPdl
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15_innergpu_2_sqrPdl.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
