/*

Simulation of flow inside a 2D square cavity
using the lattice Boltzmann method (LBM)

Written by:       Abhijit Joshi (abhijit@accelereyes.com)

Last modified on: Thursday, July 18 2013 @12:08 pm

Build instructions: make (uses Makefile present in this folder)

Run instructions: optirun ./gpu_lbm

*/

#include<iostream>
#include<stdio.h>
#include<ctime>        // clock_t, clock(), CLOCKS_PER_SEC

// problem parameters

const int     N = 128;                  // number of node points along X and Y (cavity length in lattice units)
const int     TIME_STEPS = 1000000;     // number of time steps for which the simulation is run
const double  REYNOLDS_NUMBER = 1E6;    // REYNOLDS_NUMBER = LID_VELOCITY * N / kinematicViscosity

// don't change these unless you know what you are doing

const int     Q = 9;                    // number of discrete velocity aections used
const double  DENSITY = 2.7;            // fluid density in lattice units
const double  LID_VELOCITY = 0.05;      // lid velocity in lattice units

// D2Q9 parameters 

__constant__ double ex[Q];
__constant__ double ey[Q];
__constant__ int oppos[Q];
__constant__ double wt[Q];

// populate D3Q19 parameters and copy them to __constant__ memory on the GPU

void D3Q9(double *ex_h, double *ey_h, int *oppos_h, double *wt_h)
{
    // D2Q9 model base velocities and weights

    ex_h[0] =  0.0;   ey_h[0] =  0.0;   wt_h[0] = 4.0 /  9.0;
    ex_h[1] =  1.0;   ey_h[1] =  0.0;   wt_h[1] = 1.0 /  9.0;
    ex_h[2] =  0.0;   ey_h[2] =  1.0;   wt_h[2] = 1.0 /  9.0;
    ex_h[3] = -1.0;   ey_h[3] =  0.0;   wt_h[3] = 1.0 /  9.0;
    ex_h[4] =  0.0;   ey_h[4] = -1.0;   wt_h[4] = 1.0 /  9.0;
    ex_h[5] =  1.0;   ey_h[5] =  1.0;   wt_h[5] = 1.0 / 36.0;
    ex_h[6] = -1.0;   ey_h[6] =  1.0;   wt_h[6] = 1.0 / 36.0;
    ex_h[7] = -1.0;   ey_h[7] = -1.0;   wt_h[7] = 1.0 / 36.0;
    ex_h[8] =  1.0;   ey_h[8] = -1.0;   wt_h[8] = 1.0 / 36.0;

    // define opposite (anti) aections (useful for implementing bounce back)

    oppos_h[0] = 0;      //      6        2        5
    oppos_h[1] = 3;      //               ^
    oppos_h[2] = 4;      //               |
    oppos_h[3] = 1;      //               |
    oppos_h[4] = 2;      //      3 <----- 0 -----> 1
    oppos_h[5] = 7;      //               |
    oppos_h[6] = 8;      //               |
    oppos_h[7] = 5;      //               v
    oppos_h[8] = 6;      //      7        4        8

    // copy to constant (read-only) memory
    cudaMemcpyToSymbol(ex,    ex_h,    Q * sizeof(double));  // x-component of velocity direction
    cudaMemcpyToSymbol(ey,    ey_h,    Q * sizeof(double));  // y-component of velocity direction
    cudaMemcpyToSymbol(oppos, oppos_h, Q * sizeof(int));     // opposite direction for each velocity direction
    cudaMemcpyToSymbol(wt,    wt_h,    Q * sizeof(double));  // weight factor for velocity direction
}

// initialize values for aection vectors, density, velocity and distribution functions on the GPU

__global__ void initialize(const int N, const int Q, const double DENSITY, const double LID_VELOCITY, 
                           double *rho, double *ux, double *uy, double* sigma, 
                           double *f, double *feq, double *f_new)
{
    // compute the global "i" and "j" location handled by this thread

    const int i = blockIdx.x * blockDim.x + threadIdx.x ;
    const int j = blockIdx.y * blockDim.y + threadIdx.y ;

    // bound checking
    if( (i > (N-1)) || (j > (N-1)) ) return;

    // natural index for location (i,j)

    const int index = i*N+j;  // column-ordering

    // initialize density and velocity fields inside the cavity

      rho[index] = DENSITY;   // density
       ux[index] = 0.0;       // x-component of velocity
       uy[index] = 0.0;       // x-component of velocity
    sigma[index] = 0.0;       // rate-of-strain field

    // specify boundary condition for the moving lid

    if(j==0) ux[index] = LID_VELOCITY;

    // assign initial values for distribution functions
    // along various aections using equilibriu, functions

    #pragma unroll
    for(int a=0;a<Q;a++) {

        int index_f = a + index*Q;

        double edotu = ex[a]*ux[index] + ey[a]*uy[index];
        double udotu = ux[index]*ux[index] + uy[index]*uy[index];

        feq[index_f]   = rho[index] * wt[a] * (1.0 + 3.0*edotu + 4.5*edotu*edotu - 1.5*udotu);
        f[index_f]     = feq[index_f];
        f_new[index_f] = feq[index_f];

    }
}

// this function updates the values of the distribution functions at all points along all directions
// carries out one lattice time-step (streaming + collision) in the algorithm

__global__ void collideAndStream(// READ-ONLY parameters (used by this function but not changed)
                                 const int N, const int Q, const double DENSITY, const double LID_VELOCITY, const double REYNOLDS_NUMBER,
                                 // READ + WRITE parameters (get updated in this function)
                                 double *rho,         // density
                                 double *ux,         // X-velocity
                                 double *uy,         // Y-velocity
                                 double *sigma,      // rate-of-strain
                                 double *f,          // distribution function
                                 double *feq,        // equilibrium distribution function
                                 double *f_new)      // new distribution function
{
    // compute the global "i" and "j" location handled by this thread

    const int i = blockIdx.x * blockDim.x + threadIdx.x ;
    const int j = blockIdx.y * blockDim.y + threadIdx.y ;

    // bound checking
    if( (i < 1) || (i > (N-2)) || (j < 1) || (j > (N-2)) ) return;

    // natural index
    const int index = i*N + j;  // column-major ordering

    // calculate fluid viscosity based on the Reynolds number
    double kinematicViscosity = LID_VELOCITY * (double) N / REYNOLDS_NUMBER;

    // calculate relaxation time tau
    double tau =  0.5 + 3.0 * kinematicViscosity;

    // collision
    #pragma unroll
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        double edotu = ex[a]*ux[index] + ey[a]*uy[index];
        double udotu = ux[index]*ux[index] + uy[index]*uy[index];
        feq[index_f] = rho[index] * wt[a] * (1 + 3*edotu + 4.5*edotu*edotu - 1.5*udotu);
    }

    // streaming from interior node points

    #pragma unroll
    for(int a=0;a<Q;a++) {

        int index_f = a + index*Q;
        int index_nbr = (i+ex[a])*N + (j+ey[a]);
        int index_nbr_f = a + index_nbr * Q;
        int indexoppos = oppos[a] + index*Q;

        double tau_eff, tau_t, C_Smagorinsky;  // turbulence model parameters

        C_Smagorinsky = 0.16;

        // tau_t = additional contribution to the relaxation time 
        //         because of the "eddy viscosity" model
        // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
        // REFERENCE: Krafczyk M., Tolke J. and Luo L.-S. (2003)
        //            Large-Eddy Simulations with a Multiple-Relaxation-Time LBE Model
        //            International Journal of Modern Physics B, Vol.17, 33-39
        // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

        tau_t = 0.5*(pow(pow(tau,2) + 18.0*pow(C_Smagorinsky,2)*sigma[index],0.5) - tau);

        // the effective relaxation time accounts for the additional "eddy viscosity"
        // effects. Note that tau_eff now varies from point to point in the domain, and is
        // larger for large strain rates. If the strain rate is zero, tau_eff = 0 and we
        // revert back to the original (laminar) LBM scheme where tau_eff = tau.

        tau_eff = tau + tau_t;

        // post-collision distribution at (i,j) along "a"
        double f_plus = f[index_f] - (f[index_f] - feq[index_f])/tau_eff;

        int iS = i + ex[a]; int jS = j + ey[a];

        if((iS==0) || (iS==N-1) || (jS==0) || (jS==N-1)) {
            // bounce back
            double ubdote = ux[index_nbr]*ex[a] + uy[index_nbr]*ey[a];
            f_new[indexoppos] = f_plus - 6.0 * DENSITY * wt[a] * ubdote;
        }
        else {
            // stream to neighbor
            f_new[index_nbr_f] = f_plus;
        }
    }
}

__global__ void everythingElse( // READ-ONLY parameters (used by this function but not changed)
                                const int N, const int Q, const double DENSITY, const double LID_VELOCITY, const double REYNOLDS_NUMBER,
                                // READ + WRITE parameters (get updated in this function)
                                double *rho,         // density
                                double *ux,         // X-velocity
                                double *uy,         // Y-velocity
                                double *sigma,      // rate-of-strain
                                double *f,          // distribution function
                                double *feq,        // equilibrium distribution function
                                double *f_new)      // new distribution function
{
    // compute the global "i" and "j" location of this thread

    const int i = blockIdx.x * blockDim.x + threadIdx.x;
    const int j = blockIdx.y * blockDim.y + threadIdx.y;

    // bound checking
    if( (i < 1) || (i > (N-2)) || (j < 1) || (j > (N-2)) ) return;

    // natural index
    const int index = i*N + j;  // column-major ordering

    // push f_new into f
    #pragma unroll
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        f[index_f] = f_new[index_f];
    }

    // update density at interior nodes
    rho[index]=0.0;
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        rho[index] += f_new[index_f];
    }

    // update velocity at interior nodes
    double velx=0.0;
    double vely=0.0;
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        velx += f_new[index_f]*ex[a];
        vely += f_new[index_f]*ey[a];
    }
    ux[index] = velx/rho[index];
    uy[index] = vely/rho[index];

    // update the rate-of-strain field
    double sum_xx = 0.0, sum_xy = 0.0, sum_xz = 0.0;
    double sum_yx = 0.0, sum_yy = 0.0, sum_yz = 0.0;
    double sum_zx = 0.0, sum_zy = 0.0, sum_zz = 0.0;
    for(int a=1; a<Q; a++)
    {
        int index_f = a + index*Q;

        sum_xx = sum_xx + (f_new[index_f] - feq[index_f])*ex[a]*ex[a];
        sum_xy = sum_xy + (f_new[index_f] - feq[index_f])*ex[a]*ey[a];
        sum_xz = 0.0;
        sum_yx = sum_xy;
        sum_yy = sum_yy + (f_new[index_f] - feq[index_f])*ey[a]*ey[a];
        sum_yz = 0.0;
        sum_zx = 0.0;
        sum_zy = 0.0;
        sum_zz = 0.0;
    }

    // evaluate |S| (magnitude of the strain-rate)
    sigma[index] = pow(sum_xx,2) + pow(sum_xy,2) + pow(sum_xz,2)
                 + pow(sum_yx,2) + pow(sum_yy,2) + pow(sum_yz,2)
                 + pow(sum_zx,2) + pow(sum_zy,2) + pow(sum_zz,2);

    sigma[index] = pow(sigma[index],0.5);
}

int main(int argc, char* argv[])
{
        // allocate memory on the GPU

        // distribution functions
        double *f, *feq, *f_new;
        cudaMalloc((void **)&f,N*N*Q*sizeof(double));
        cudaMalloc((void **)&feq,N*N*Q*sizeof(double));
        cudaMalloc((void **)&f_new,N*N*Q*sizeof(double));

        // density and velocity
        double *rho, *ux, *uy;
        cudaMalloc((void **)&rho,N*N*sizeof(double));
        cudaMalloc((void **)&ux,N*N*sizeof(double));
        cudaMalloc((void **)&uy,N*N*sizeof(double));

        // rate-of-strain
        double *sigma;
        cudaMalloc((void **)&sigma,N*N*sizeof(double));

        // allocate space for D3Q9 parameters on the host
        double *ex_h    = new double[Q];
        double *ey_h    = new double[Q];
        int *oppos_h = new int[Q];
        double *wt_h = new double[Q];

        // fill D3Q9 parameters in constant memory on the GPU
        D3Q9(ex_h, ey_h, oppos_h, wt_h);

        // assign a 2D distribution of CUDA "threads" within each CUDA "block"    
        int threadsAlongX=16, threadsAlongY=16;
        dim3 dimBlock(threadsAlongX, threadsAlongY, 1);

        // calculate number of blocks along X and Y in a 2D CUDA "grid"
        dim3 dimGrid( ceil(float(N)/float(dimBlock.x)), ceil(float(N)/float(dimBlock.y)), 1 );

        // launch GPU kernel to initialize all fields
        initialize<<<dimGrid,dimBlock>>>(N, Q, DENSITY, LID_VELOCITY,
                                         rho, ux, uy, sigma,
                                         f, feq, f_new);

        // time integration
        int time=0;
        clock_t t0, tN;
	t0 = clock();
        while(time<TIME_STEPS) {

            time++;


            collideAndStream<<<dimGrid,dimBlock >>>(N, Q, DENSITY, LID_VELOCITY, REYNOLDS_NUMBER,
                                                    rho, ux, uy, sigma,
                                                    f, feq, f_new);

            // collideAndStream and everythingElse were originally one kernel
            // they were separated out to make all threads synchronize globally
            // before moving on to the next set of calculations

            everythingElse<<<dimGrid,dimBlock >>>(N, Q, DENSITY, LID_VELOCITY, REYNOLDS_NUMBER,
                                                  rho, ux, uy, sigma,
                                                  f, feq, f_new);
            tN = clock() - t0;
	    std::cout << "Lattice time " << time 
                      << " clock ticks " << tN 
                      << " wall clock time " << tN/CLOCKS_PER_SEC 
                      << " lattice time steps per second = " << (float) CLOCKS_PER_SEC * time / (float) tN 
                      << std::endl;

        }

    // added this in for flushing nvprof output to screen
    cudaDeviceReset();

    return 0;
}

	.file	"tmpxft_002feb22_00000000-6_gpu_lbm.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4D3Q9PdS_PiS_
	.type	_Z4D3Q9PdS_PiS_, @function
_Z4D3Q9PdS_PiS_:
.LFB3635:
	.cfi_startproc
	endbr64
	movsd	.LC2(%rip), %xmm1
	movq	.LC1(%rip), %rax
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1, %r8d
	movsd	.LC4(%rip), %xmm0
	movsd	.LC3(%rip), %xmm2
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdx, %r12
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rsi, %rbp
	movq	%rcx, %rbx
	movq	$0x000000000, (%rdi)
	movq	$0x000000000, (%rsi)
	movq	%rax, (%rcx)
	movl	$3, %eax
	movsd	%xmm1, 8(%rdi)
	salq	$32, %rax
	movq	$0x000000000, 8(%rsi)
	movsd	%xmm2, 8(%rcx)
	movq	$0x000000000, 16(%rdi)
	movsd	%xmm1, 16(%rsi)
	movsd	%xmm2, 16(%rcx)
	movsd	%xmm0, 24(%rdi)
	movq	$0x000000000, 24(%rsi)
	movsd	%xmm2, 24(%rcx)
	movq	$0x000000000, 32(%rdi)
	movsd	%xmm0, 32(%rsi)
	movsd	%xmm2, 32(%rcx)
	movsd	.LC5(%rip), %xmm2
	movsd	%xmm1, 40(%rdi)
	movsd	%xmm1, 40(%rsi)
	movsd	%xmm2, 40(%rcx)
	movsd	%xmm0, 48(%rdi)
	movsd	%xmm1, 48(%rsi)
	movsd	%xmm2, 48(%rcx)
	movsd	%xmm0, 56(%rdi)
	movsd	%xmm0, 56(%rsi)
	movsd	%xmm2, 56(%rcx)
	movsd	%xmm1, 64(%rdi)
	movsd	%xmm0, 64(%rsi)
	movq	%rdi, %rsi
	leaq	_ZL2ex(%rip), %rdi
	movsd	%xmm2, 64(%rcx)
	xorl	%ecx, %ecx
	movq	%rax, (%rdx)
	movl	$1073741825, %eax
	salq	$2, %rax
	movl	$6, 32(%rdx)
	movq	%rax, 8(%rdx)
	movabsq	$30064771074, %rax
	movq	%rax, 16(%rdx)
	movl	$2684354561, %eax
	salq	$3, %rax
	movq	%rax, 24(%rdx)
	movl	$72, %edx
	call	cudaMemcpyToSymbol@PLT
	movq	%rbp, %rsi
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movl	$72, %edx
	leaq	_ZL2ey(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movq	%r12, %rsi
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movl	$36, %edx
	leaq	_ZL5oppos(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	movq	%rbx, %rsi
	movl	$1, %r8d
	popq	%rbx
	.cfi_def_cfa_offset 24
	xorl	%ecx, %ecx
	popq	%rbp
	.cfi_def_cfa_offset 16
	movl	$72, %edx
	popq	%r12
	.cfi_def_cfa_offset 8
	leaq	_ZL2wt(%rip), %rdi
	jmp	cudaMemcpyToSymbol@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z4D3Q9PdS_PiS_, .-_Z4D3Q9PdS_PiS_
	.globl	_Z46__device_stub__Z10initializeiiddPdS_S_S_S_S_S_iiddPdS_S_S_S_S_S_
	.type	_Z46__device_stub__Z10initializeiiddPdS_S_S_S_S_S_iiddPdS_S_S_S_S_S_, @function
_Z46__device_stub__Z10initializeiiddPdS_S_S_S_S_S_iiddPdS_S_S_S_S_S_:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	256(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	96(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	264(%rsp), %rax
	movq	%rdx, 48(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	272(%rsp), %rax
	movq	%rcx, 40(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, (%rsp)
	movsd	%xmm0, 64(%rsp)
	movsd	%xmm1, 56(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z10initializeiiddPdS_S_S_S_S_S_(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L4:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z46__device_stub__Z10initializeiiddPdS_S_S_S_S_S_iiddPdS_S_S_S_S_S_, .-_Z46__device_stub__Z10initializeiiddPdS_S_S_S_S_S_iiddPdS_S_S_S_S_S_
	.globl	_Z10initializeiiddPdS_S_S_S_S_S_
	.type	_Z10initializeiiddPdS_S_S_S_S_S_, @function
_Z10initializeiiddPdS_S_S_S_S_S_:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z10initializeiiddPdS_S_S_S_S_S_iiddPdS_S_S_S_S_S_
	.cfi_endproc
.LFE3662:
	.size	_Z10initializeiiddPdS_S_S_S_S_S_, .-_Z10initializeiiddPdS_S_S_S_S_S_
	.globl	_Z53__device_stub__Z16collideAndStreamiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	.type	_Z53__device_stub__Z16collideAndStreamiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_, @function
_Z53__device_stub__Z16collideAndStreamiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	304(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	112(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movsd	%xmm0, 80(%rsp)
	movsd	%xmm1, 72(%rsp)
	movsd	%xmm2, 64(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z16collideAndStreamiidddPdS_S_S_S_S_S_(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L10:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z53__device_stub__Z16collideAndStreamiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_, .-_Z53__device_stub__Z16collideAndStreamiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	.globl	_Z16collideAndStreamiidddPdS_S_S_S_S_S_
	.type	_Z16collideAndStreamiidddPdS_S_S_S_S_S_, @function
_Z16collideAndStreamiidddPdS_S_S_S_S_S_:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z16collideAndStreamiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	.cfi_endproc
.LFE3664:
	.size	_Z16collideAndStreamiidddPdS_S_S_S_S_S_, .-_Z16collideAndStreamiidddPdS_S_S_S_S_S_
	.globl	_Z51__device_stub__Z14everythingElseiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	.type	_Z51__device_stub__Z14everythingElseiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_, @function
_Z51__device_stub__Z14everythingElseiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_:
.LFB3665:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 16(%rsp)
	movq	304(%rsp), %rax
	movq	%rcx, 48(%rsp)
	leaq	112(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 8(%rsp)
	movsd	%xmm0, 80(%rsp)
	movsd	%xmm1, 72(%rsp)
	movsd	%xmm2, 64(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z14everythingElseiidddPdS_S_S_S_S_S_(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L15:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3665:
	.size	_Z51__device_stub__Z14everythingElseiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_, .-_Z51__device_stub__Z14everythingElseiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	.globl	_Z14everythingElseiidddPdS_S_S_S_S_S_
	.type	_Z14everythingElseiidddPdS_S_S_S_S_S_, @function
_Z14everythingElseiidddPdS_S_S_S_S_S_:
.LFB3666:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z14everythingElseiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	.cfi_endproc
.LFE3666:
	.size	_Z14everythingElseiidddPdS_S_S_S_S_S_, .-_Z14everythingElseiidddPdS_S_S_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC9:
	.string	"Lattice time "
.LC10:
	.string	" clock ticks "
.LC11:
	.string	" wall clock time "
.LC12:
	.string	" lattice time steps per second = "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$1179648, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$96, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1179648, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1179648, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	movl	$131072, %esi
	leaq	56(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$72, %edi
	call	_Znam@PLT
	movl	$72, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movl	$36, %edi
	movq	%rax, %rbp
	call	_Znam@PLT
	movl	$72, %edi
	movq	%rax, %r12
	call	_Znam@PLT
	movq	%r12, %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	movq	%rax, %rcx
	call	_Z4D3Q9PdS_PiS_
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$34359738376, %rdi
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	$1, 84(%rsp)
	movq	%rdi, 76(%rsp)
	movq	%rdx, 64(%rsp)
	movl	$1, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	%rcx
	.cfi_def_cfa_offset 136
	movl	$9, %esi
	movl	$128, %edi
	movsd	.LC6(%rip), %xmm1
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movsd	.LC7(%rip), %xmm0
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	88(%rsp), %r9
	movq	80(%rsp), %r8
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	call	_Z46__device_stub__Z10initializeiiddPdS_S_S_S_S_S_iiddPdS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 128
.L21:
	call	clock@PLT
	xorl	%ebx, %ebx
	movq	%rax, %rbp
.L24:
	movl	72(%rsp), %ecx
	movq	64(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	76(%rsp), %rdi
	movl	84(%rsp), %esi
	incl	%ebx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	%rdx
	.cfi_def_cfa_offset 136
	movsd	.LC8(%rip), %xmm2
	movl	$9, %esi
	movl	$128, %edi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movsd	.LC6(%rip), %xmm1
	movsd	.LC7(%rip), %xmm0
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	88(%rsp), %r9
	movq	80(%rsp), %r8
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	call	_Z53__device_stub__Z16collideAndStreamiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 128
.L22:
	movl	72(%rsp), %ecx
	movq	64(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	76(%rsp), %rdi
	movl	84(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	%rax
	.cfi_def_cfa_offset 136
	movsd	.LC8(%rip), %xmm2
	movl	$9, %esi
	movl	$128, %edi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movsd	.LC6(%rip), %xmm1
	movsd	.LC7(%rip), %xmm0
	pushq	32(%rsp)
	.cfi_def_cfa_offset 152
	pushq	32(%rsp)
	.cfi_def_cfa_offset 160
	movq	88(%rsp), %r9
	movq	80(%rsp), %r8
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	call	_Z51__device_stub__Z14everythingElseiidddPdS_S_S_S_S_S_iidddPdS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_def_cfa_offset 128
.L23:
	call	clock@PLT
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	subq	%rbp, %rax
	movq	%rax, %r12
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	leaq	.LC11(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$1000000, %ecx
	movq	%rax, %rdi
	movq	%r12, %rax
	cqto
	idivq	%rcx
	movq	%rax, %rsi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	leaq	.LC12(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtsi2ssl	%ebx, %xmm0
	mulss	.LC13(%rip), %xmm0
	cvtsi2ssq	%r12, %xmm1
	movq	%rax, %rdi
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	cmpl	$1000000, %ebx
	jne	.L24
	call	cudaDeviceReset@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$96, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC14:
	.string	"_Z14everythingElseiidddPdS_S_S_S_S_S_"
.LC15:
	.string	"_Z16collideAndStreamiidddPdS_S_S_S_S_S_"
.LC16:
	.string	"_Z10initializeiiddPdS_S_S_S_S_S_"
.LC17:
	.string	"ex"
.LC18:
	.string	"ey"
.LC19:
	.string	"oppos"
.LC20:
	.string	"wt"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3668:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14everythingElseiidddPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16collideAndStreamiidddPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10initializeiiddPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movl	$72, %r9d
	leaq	_ZL2ex(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL2ey(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$36, %r9d
	leaq	_ZL5oppos(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL2wt(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3668:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL2wt
	.comm	_ZL2wt,72,32
	.local	_ZL5oppos
	.comm	_ZL5oppos,36,32
	.local	_ZL2ey
	.comm	_ZL2ey,72,32
	.local	_ZL2ex
	.comm	_ZL2ex,72,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	477218588
	.long	1071411655
	.align 8
.LC2:
	.long	0
	.long	1072693248
	.align 8
.LC3:
	.long	477218588
	.long	1069314503
	.align 8
.LC4:
	.long	0
	.long	-1074790400
	.align 8
.LC5:
	.long	477218588
	.long	1067217351
	.align 8
.LC6:
	.long	-1717986918
	.long	1068079513
	.align 8
.LC7:
	.long	-1717986918
	.long	1074108825
	.align 8
.LC8:
	.long	0
	.long	1093567616
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC13:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*

Simulation of flow inside a 2D square cavity
using the lattice Boltzmann method (LBM)

Written by:       Abhijit Joshi (abhijit@accelereyes.com)

Last modified on: Thursday, July 18 2013 @12:08 pm

Build instructions: make (uses Makefile present in this folder)

Run instructions: optirun ./gpu_lbm

*/


#include <hip/hip_runtime.h>
#include<iostream>
#include<stdio.h>
#include<ctime>        // clock_t, clock(), CLOCKS_PER_SEC

// problem parameters

const int     N = 128;                  // number of node points along X and Y (cavity length in lattice units)
const int     TIME_STEPS = 1000000;     // number of time steps for which the simulation is run
const double  REYNOLDS_NUMBER = 1E6;    // REYNOLDS_NUMBER = LID_VELOCITY * N / kinematicViscosity

// don't change these unless you know what you are doing

const int     Q = 9;                    // number of discrete velocity aections used
const double  DENSITY = 2.7;            // fluid density in lattice units
const double  LID_VELOCITY = 0.05;      // lid velocity in lattice units

// D2Q9 parameters 

__constant__ double ex[Q];
__constant__ double ey[Q];
__constant__ int oppos[Q];
__constant__ double wt[Q];

// populate D3Q19 parameters and copy them to __constant__ memory on the GPU

void D3Q9(double *ex_h, double *ey_h, int *oppos_h, double *wt_h)
{
    // D2Q9 model base velocities and weights

    ex_h[0] =  0.0;   ey_h[0] =  0.0;   wt_h[0] = 4.0 /  9.0;
    ex_h[1] =  1.0;   ey_h[1] =  0.0;   wt_h[1] = 1.0 /  9.0;
    ex_h[2] =  0.0;   ey_h[2] =  1.0;   wt_h[2] = 1.0 /  9.0;
    ex_h[3] = -1.0;   ey_h[3] =  0.0;   wt_h[3] = 1.0 /  9.0;
    ex_h[4] =  0.0;   ey_h[4] = -1.0;   wt_h[4] = 1.0 /  9.0;
    ex_h[5] =  1.0;   ey_h[5] =  1.0;   wt_h[5] = 1.0 / 36.0;
    ex_h[6] = -1.0;   ey_h[6] =  1.0;   wt_h[6] = 1.0 / 36.0;
    ex_h[7] = -1.0;   ey_h[7] = -1.0;   wt_h[7] = 1.0 / 36.0;
    ex_h[8] =  1.0;   ey_h[8] = -1.0;   wt_h[8] = 1.0 / 36.0;

    // define opposite (anti) aections (useful for implementing bounce back)

    oppos_h[0] = 0;      //      6        2        5
    oppos_h[1] = 3;      //               ^
    oppos_h[2] = 4;      //               |
    oppos_h[3] = 1;      //               |
    oppos_h[4] = 2;      //      3 <----- 0 -----> 1
    oppos_h[5] = 7;      //               |
    oppos_h[6] = 8;      //               |
    oppos_h[7] = 5;      //               v
    oppos_h[8] = 6;      //      7        4        8

    // copy to constant (read-only) memory
    hipMemcpyToSymbol(HIP_SYMBOL(ex),    ex_h,    Q * sizeof(double));  // x-component of velocity direction
    hipMemcpyToSymbol(HIP_SYMBOL(ey),    ey_h,    Q * sizeof(double));  // y-component of velocity direction
    hipMemcpyToSymbol(HIP_SYMBOL(oppos), oppos_h, Q * sizeof(int));     // opposite direction for each velocity direction
    hipMemcpyToSymbol(HIP_SYMBOL(wt),    wt_h,    Q * sizeof(double));  // weight factor for velocity direction
}

// initialize values for aection vectors, density, velocity and distribution functions on the GPU

__global__ void initialize(const int N, const int Q, const double DENSITY, const double LID_VELOCITY, 
                           double *rho, double *ux, double *uy, double* sigma, 
                           double *f, double *feq, double *f_new)
{
    // compute the global "i" and "j" location handled by this thread

    const int i = blockIdx.x * blockDim.x + threadIdx.x ;
    const int j = blockIdx.y * blockDim.y + threadIdx.y ;

    // bound checking
    if( (i > (N-1)) || (j > (N-1)) ) return;

    // natural index for location (i,j)

    const int index = i*N+j;  // column-ordering

    // initialize density and velocity fields inside the cavity

      rho[index] = DENSITY;   // density
       ux[index] = 0.0;       // x-component of velocity
       uy[index] = 0.0;       // x-component of velocity
    sigma[index] = 0.0;       // rate-of-strain field

    // specify boundary condition for the moving lid

    if(j==0) ux[index] = LID_VELOCITY;

    // assign initial values for distribution functions
    // along various aections using equilibriu, functions

    #pragma unroll
    for(int a=0;a<Q;a++) {

        int index_f = a + index*Q;

        double edotu = ex[a]*ux[index] + ey[a]*uy[index];
        double udotu = ux[index]*ux[index] + uy[index]*uy[index];

        feq[index_f]   = rho[index] * wt[a] * (1.0 + 3.0*edotu + 4.5*edotu*edotu - 1.5*udotu);
        f[index_f]     = feq[index_f];
        f_new[index_f] = feq[index_f];

    }
}

// this function updates the values of the distribution functions at all points along all directions
// carries out one lattice time-step (streaming + collision) in the algorithm

__global__ void collideAndStream(// READ-ONLY parameters (used by this function but not changed)
                                 const int N, const int Q, const double DENSITY, const double LID_VELOCITY, const double REYNOLDS_NUMBER,
                                 // READ + WRITE parameters (get updated in this function)
                                 double *rho,         // density
                                 double *ux,         // X-velocity
                                 double *uy,         // Y-velocity
                                 double *sigma,      // rate-of-strain
                                 double *f,          // distribution function
                                 double *feq,        // equilibrium distribution function
                                 double *f_new)      // new distribution function
{
    // compute the global "i" and "j" location handled by this thread

    const int i = blockIdx.x * blockDim.x + threadIdx.x ;
    const int j = blockIdx.y * blockDim.y + threadIdx.y ;

    // bound checking
    if( (i < 1) || (i > (N-2)) || (j < 1) || (j > (N-2)) ) return;

    // natural index
    const int index = i*N + j;  // column-major ordering

    // calculate fluid viscosity based on the Reynolds number
    double kinematicViscosity = LID_VELOCITY * (double) N / REYNOLDS_NUMBER;

    // calculate relaxation time tau
    double tau =  0.5 + 3.0 * kinematicViscosity;

    // collision
    #pragma unroll
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        double edotu = ex[a]*ux[index] + ey[a]*uy[index];
        double udotu = ux[index]*ux[index] + uy[index]*uy[index];
        feq[index_f] = rho[index] * wt[a] * (1 + 3*edotu + 4.5*edotu*edotu - 1.5*udotu);
    }

    // streaming from interior node points

    #pragma unroll
    for(int a=0;a<Q;a++) {

        int index_f = a + index*Q;
        int index_nbr = (i+ex[a])*N + (j+ey[a]);
        int index_nbr_f = a + index_nbr * Q;
        int indexoppos = oppos[a] + index*Q;

        double tau_eff, tau_t, C_Smagorinsky;  // turbulence model parameters

        C_Smagorinsky = 0.16;

        // tau_t = additional contribution to the relaxation time 
        //         because of the "eddy viscosity" model
        // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
        // REFERENCE: Krafczyk M., Tolke J. and Luo L.-S. (2003)
        //            Large-Eddy Simulations with a Multiple-Relaxation-Time LBE Model
        //            International Journal of Modern Physics B, Vol.17, 33-39
        // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

        tau_t = 0.5*(pow(pow(tau,2) + 18.0*pow(C_Smagorinsky,2)*sigma[index],0.5) - tau);

        // the effective relaxation time accounts for the additional "eddy viscosity"
        // effects. Note that tau_eff now varies from point to point in the domain, and is
        // larger for large strain rates. If the strain rate is zero, tau_eff = 0 and we
        // revert back to the original (laminar) LBM scheme where tau_eff = tau.

        tau_eff = tau + tau_t;

        // post-collision distribution at (i,j) along "a"
        double f_plus = f[index_f] - (f[index_f] - feq[index_f])/tau_eff;

        int iS = i + ex[a]; int jS = j + ey[a];

        if((iS==0) || (iS==N-1) || (jS==0) || (jS==N-1)) {
            // bounce back
            double ubdote = ux[index_nbr]*ex[a] + uy[index_nbr]*ey[a];
            f_new[indexoppos] = f_plus - 6.0 * DENSITY * wt[a] * ubdote;
        }
        else {
            // stream to neighbor
            f_new[index_nbr_f] = f_plus;
        }
    }
}

__global__ void everythingElse( // READ-ONLY parameters (used by this function but not changed)
                                const int N, const int Q, const double DENSITY, const double LID_VELOCITY, const double REYNOLDS_NUMBER,
                                // READ + WRITE parameters (get updated in this function)
                                double *rho,         // density
                                double *ux,         // X-velocity
                                double *uy,         // Y-velocity
                                double *sigma,      // rate-of-strain
                                double *f,          // distribution function
                                double *feq,        // equilibrium distribution function
                                double *f_new)      // new distribution function
{
    // compute the global "i" and "j" location of this thread

    const int i = blockIdx.x * blockDim.x + threadIdx.x;
    const int j = blockIdx.y * blockDim.y + threadIdx.y;

    // bound checking
    if( (i < 1) || (i > (N-2)) || (j < 1) || (j > (N-2)) ) return;

    // natural index
    const int index = i*N + j;  // column-major ordering

    // push f_new into f
    #pragma unroll
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        f[index_f] = f_new[index_f];
    }

    // update density at interior nodes
    rho[index]=0.0;
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        rho[index] += f_new[index_f];
    }

    // update velocity at interior nodes
    double velx=0.0;
    double vely=0.0;
    for(int a=0;a<Q;a++) {
        int index_f = a + index*Q;
        velx += f_new[index_f]*ex[a];
        vely += f_new[index_f]*ey[a];
    }
    ux[index] = velx/rho[index];
    uy[index] = vely/rho[index];

    // update the rate-of-strain field
    double sum_xx = 0.0, sum_xy = 0.0, sum_xz = 0.0;
    double sum_yx = 0.0, sum_yy = 0.0, sum_yz = 0.0;
    double sum_zx = 0.0, sum_zy = 0.0, sum_zz = 0.0;
    for(int a=1; a<Q; a++)
    {
        int index_f = a + index*Q;

        sum_xx = sum_xx + (f_new[index_f] - feq[index_f])*ex[a]*ex[a];
        sum_xy = sum_xy + (f_new[index_f] - feq[index_f])*ex[a]*ey[a];
        sum_xz = 0.0;
        sum_yx = sum_xy;
        sum_yy = sum_yy + (f_new[index_f] - feq[index_f])*ey[a]*ey[a];
        sum_yz = 0.0;
        sum_zx = 0.0;
        sum_zy = 0.0;
        sum_zz = 0.0;
    }

    // evaluate |S| (magnitude of the strain-rate)
    sigma[index] = pow(sum_xx,2) + pow(sum_xy,2) + pow(sum_xz,2)
                 + pow(sum_yx,2) + pow(sum_yy,2) + pow(sum_yz,2)
                 + pow(sum_zx,2) + pow(sum_zy,2) + pow(sum_zz,2);

    sigma[index] = pow(sigma[index],0.5);
}

int main(int argc, char* argv[])
{
        // allocate memory on the GPU

        // distribution functions
        double *f, *feq, *f_new;
        hipMalloc((void **)&f,N*N*Q*sizeof(double));
        hipMalloc((void **)&feq,N*N*Q*sizeof(double));
        hipMalloc((void **)&f_new,N*N*Q*sizeof(double));

        // density and velocity
        double *rho, *ux, *uy;
        hipMalloc((void **)&rho,N*N*sizeof(double));
        hipMalloc((void **)&ux,N*N*sizeof(double));
        hipMalloc((void **)&uy,N*N*sizeof(double));

        // rate-of-strain
        double *sigma;
        hipMalloc((void **)&sigma,N*N*sizeof(double));

        // allocate space for D3Q9 parameters on the host
        double *ex_h    = new double[Q];
        double *ey_h    = new double[Q];
        int *oppos_h = new int[Q];
        double *wt_h = new double[Q];

        // fill D3Q9 parameters in constant memory on the GPU
        D3Q9(ex_h, ey_h, oppos_h, wt_h);

        // assign a 2D distribution of CUDA "threads" within each CUDA "block"    
        int threadsAlongX=16, threadsAlongY=16;
        dim3 dimBlock(threadsAlongX, threadsAlongY, 1);

        // calculate number of blocks along X and Y in a 2D CUDA "grid"
        dim3 dimGrid( ceil(float(N)/float(dimBlock.x)), ceil(float(N)/float(dimBlock.y)), 1 );

        // launch GPU kernel to initialize all fields
        initialize<<<dimGrid,dimBlock>>>(N, Q, DENSITY, LID_VELOCITY,
                                         rho, ux, uy, sigma,
                                         f, feq, f_new);

        // time integration
        int time=0;
        clock_t t0, tN;
	t0 = clock();
        while(time<TIME_STEPS) {

            time++;


            collideAndStream<<<dimGrid,dimBlock >>>(N, Q, DENSITY, LID_VELOCITY, REYNOLDS_NUMBER,
                                                    rho, ux, uy, sigma,
                                                    f, feq, f_new);

            // collideAndStream and everythingElse were originally one kernel
            // they were separated out to make all threads synchronize globally
            // before moving on to the next set of calculations

            everythingElse<<<dimGrid,dimBlock >>>(N, Q, DENSITY, LID_VELOCITY, REYNOLDS_NUMBER,
                                                  rho, ux, uy, sigma,
                                                  f, feq, f_new);
            tN = clock() - t0;
	    std::cout << "Lattice time " << time 
                      << " clock ticks " << tN 
                      << " wall clock time " << tN/CLOCKS_PER_SEC 
                      << " lattice time steps per second = " << (float) CLOCKS_PER_SEC * time / (float) tN 
                      << std::endl;

        }

    // added this in for flushing nvprof output to screen
    hipDeviceReset();

    return 0;
}

	.text
	.file	"gpu_lbm.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z4D3Q9PdS_PiS_
.LCPI0_0:
	.long	0                               # 0x0
	.long	3                               # 0x3
	.long	4                               # 0x4
	.long	1                               # 0x1
.LCPI0_1:
	.long	2                               # 0x2
	.long	7                               # 0x7
	.long	8                               # 0x8
	.long	5                               # 0x5
	.text
	.globl	_Z4D3Q9PdS_PiS_
	.type	_Z4D3Q9PdS_PiS_,@function
_Z4D3Q9PdS_PiS_:                        # @_Z4D3Q9PdS_PiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %rsi
	xorl	%eax, %eax
	movq	%rax, (%rdi)
	movq	%rax, (%r15)
	movabsq	$4601678019255453468, %rcx      # imm = 0x3FDC71C71C71C71C
	movq	%rcx, (%rbx)
	movabsq	$4607182418800017408, %rcx      # imm = 0x3FF0000000000000
	movq	%rcx, 8(%rdi)
	movq	%rax, 8(%r15)
	movabsq	$4592670820000712476, %rdx      # imm = 0x3FBC71C71C71C71C
	movq	%rdx, 8(%rbx)
	movq	%rax, 16(%rdi)
	movq	%rcx, 16(%r15)
	movq	%rdx, 16(%rbx)
	movabsq	$-4616189618054758400, %rdi     # imm = 0xBFF0000000000000
	movq	%rdi, 24(%rsi)
	movq	%rax, 24(%r15)
	movq	%rdx, 24(%rbx)
	movq	%rax, 32(%rsi)
	movq	%rdi, 32(%r15)
	movq	%rdx, 32(%rbx)
	movq	%rcx, 40(%rsi)
	movq	%rcx, 40(%r15)
	movabsq	$4583663620745971484, %rax      # imm = 0x3F9C71C71C71C71C
	movq	%rax, 40(%rbx)
	movq	%rdi, 48(%rsi)
	movq	%rcx, 48(%r15)
	movq	%rax, 48(%rbx)
	movq	%rdi, 56(%rsi)
	movq	%rdi, 56(%r15)
	movq	%rax, 56(%rbx)
	movq	%rcx, 64(%rsi)
	movq	%rdi, 64(%r15)
	movq	%rax, 64(%rbx)
	movaps	.LCPI0_0(%rip), %xmm0           # xmm0 = [0,3,4,1]
	movups	%xmm0, (%r14)
	movaps	.LCPI0_1(%rip), %xmm0           # xmm0 = [2,7,8,5]
	movups	%xmm0, 16(%r14)
	movl	$6, 32(%r14)
	movl	$ex, %edi
	movl	$72, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$ey, %edi
	movl	$72, %edx
	movq	%r15, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$oppos, %edi
	movl	$36, %edx
	movq	%r14, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	movl	$wt, %edi
	movl	$72, %edx
	movq	%rbx, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	hipMemcpyToSymbol               # TAILCALL
.Lfunc_end0:
	.size	_Z4D3Q9PdS_PiS_, .Lfunc_end0-_Z4D3Q9PdS_PiS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_ # -- Begin function _Z25__device_stub__initializeiiddPdS_S_S_S_S_S_
	.type	_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_,@function
_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_: # @_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	72(%rsp), %rsi
	movsd	%xmm0, (%rsi)
	leaq	64(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	56(%rsp), %r11
	movq	%rdx, (%r11)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%rdx, 40(%rbx)
	movq	%rcx, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10initializeiiddPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_, .Lfunc_end1-_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_ # -- Begin function _Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_
	.type	_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_,@function
_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_: # @_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	movq	%rsp, %rdi
	movl	%esi, (%rdi)
	leaq	72(%rsp), %rsi
	movsd	%xmm0, (%rsi)
	leaq	64(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	56(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	48(%rsp), %r14
	movq	%rdx, (%r14)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%rdx, 48(%rbx)
	movq	%rcx, 56(%rbx)
	movq	%r8, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16collideAndStreamiidddPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_, .Lfunc_end2-_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_ # -- Begin function _Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_
	.type	_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_,@function
_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_: # @_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	movq	%rsp, %rdi
	movl	%esi, (%rdi)
	leaq	72(%rsp), %rsi
	movsd	%xmm0, (%rsi)
	leaq	64(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	56(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	48(%rsp), %r14
	movq	%rdx, (%r14)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%rdx, 48(%rbx)
	movq	%rcx, 56(%rbx)
	movq	%r8, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14everythingElseiidddPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_, .Lfunc_end3-_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x400599999999999a              # double 2.7000000000000002
.LCPI4_1:
	.quad	0x3fa999999999999a              # double 0.050000000000000003
.LCPI4_2:
	.quad	0x412e848000000000              # double 1.0E+6
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI4_3:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$68719476752, %rbx              # imm = 0x1000000010
	movabsq	$34359738376, %r14              # imm = 0x800000008
	leaq	48(%rsp), %rdi
	movl	$1179648, %esi                  # imm = 0x120000
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movl	$1179648, %esi                  # imm = 0x120000
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movl	$1179648, %esi                  # imm = 0x120000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	movl	$72, %edi
	callq	_Znam
	movq	%rax, %r15
	movl	$72, %edi
	callq	_Znam
	movq	%rax, %r12
	movl	$36, %edi
	callq	_Znam
	movq	%rax, %r13
	movl	$72, %edi
	callq	_Znam
	movq	%r15, %rdi
	movq	%r12, %rsi
	movq	%r13, %rdx
	movq	%rax, %rcx
	callq	_Z4D3Q9PdS_PiS_
	movl	$1, %ebp
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_2
# %bb.1:
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movq	(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movsd	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	.LCPI4_1(%rip), %xmm1           # xmm1 = mem[0],zero
	movl	$128, %edi
	movl	$9, %esi
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB4_2:
	callq	clock
	movq	%rax, %r15
.LBB4_3:                                # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_5
# %bb.4:                                #   in Loop: Header=BB4_3 Depth=1
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movq	(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$128, %edi
	movl	$9, %esi
	movsd	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	.LCPI4_1(%rip), %xmm1           # xmm1 = mem[0],zero
	movsd	.LCPI4_2(%rip), %xmm2           # xmm2 = mem[0],zero
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB4_5:                                #   in Loop: Header=BB4_3 Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_7
# %bb.6:                                #   in Loop: Header=BB4_3 Depth=1
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movq	(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$128, %edi
	movl	$9, %esi
	movsd	.LCPI4_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	.LCPI4_1(%rip), %xmm1           # xmm1 = mem[0],zero
	movsd	.LCPI4_2(%rip), %xmm2           # xmm2 = mem[0],zero
	pushq	40(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	56(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	72(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB4_7:                                #   in Loop: Header=BB4_3 Depth=1
	callq	clock
	movq	%rax, %r12
	subq	%r15, %r12
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$13, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %r13
	movl	$.L.str.1, %esi
	movl	$13, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %r13
	movl	$.L.str.2, %esi
	movl	$17, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rax
	movabsq	$4835703278458516699, %rcx      # imm = 0x431BDE82D7B634DB
	imulq	%rcx
	movq	%rdx, %rsi
	shrq	$63, %rsi
	sarq	$18, %rdx
	addq	%rdx, %rsi
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %r13
	movl	$.L.str.3, %esi
	movl	$33, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebp, %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r12, %xmm1
	mulss	.LCPI4_3(%rip), %xmm0
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movq	%r13, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incl	%ebp
	cmpl	$1000001, %ebp                  # imm = 0xF4241
	jne	.LBB4_3
# %bb.8:
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10initializeiiddPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16collideAndStreamiidddPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14everythingElseiidddPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$ex, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$ey, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$oppos, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movl	$36, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$wt, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movl	$72, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	ex,@object                      # @ex
	.local	ex
	.comm	ex,72,16
	.type	ey,@object                      # @ey
	.local	ey
	.comm	ey,72,16
	.type	oppos,@object                   # @oppos
	.local	oppos
	.comm	oppos,36,16
	.type	wt,@object                      # @wt
	.local	wt
	.comm	wt,72,16
	.type	_Z10initializeiiddPdS_S_S_S_S_S_,@object # @_Z10initializeiiddPdS_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z10initializeiiddPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z10initializeiiddPdS_S_S_S_S_S_:
	.quad	_Z25__device_stub__initializeiiddPdS_S_S_S_S_S_
	.size	_Z10initializeiiddPdS_S_S_S_S_S_, 8

	.type	_Z16collideAndStreamiidddPdS_S_S_S_S_S_,@object # @_Z16collideAndStreamiidddPdS_S_S_S_S_S_
	.globl	_Z16collideAndStreamiidddPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z16collideAndStreamiidddPdS_S_S_S_S_S_:
	.quad	_Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_
	.size	_Z16collideAndStreamiidddPdS_S_S_S_S_S_, 8

	.type	_Z14everythingElseiidddPdS_S_S_S_S_S_,@object # @_Z14everythingElseiidddPdS_S_S_S_S_S_
	.globl	_Z14everythingElseiidddPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z14everythingElseiidddPdS_S_S_S_S_S_:
	.quad	_Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_
	.size	_Z14everythingElseiidddPdS_S_S_S_S_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Lattice time "
	.size	.L.str, 14

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" clock ticks "
	.size	.L.str.1, 14

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" wall clock time "
	.size	.L.str.2, 18

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" lattice time steps per second = "
	.size	.L.str.3, 34

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10initializeiiddPdS_S_S_S_S_S_"
	.size	.L__unnamed_1, 33

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z16collideAndStreamiidddPdS_S_S_S_S_S_"
	.size	.L__unnamed_2, 40

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z14everythingElseiidddPdS_S_S_S_S_S_"
	.size	.L__unnamed_3, 38

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"ex"
	.size	.L__unnamed_4, 3

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"ey"
	.size	.L__unnamed_5, 3

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"oppos"
	.size	.L__unnamed_6, 6

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"wt"
	.size	.L__unnamed_7, 3

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__initializeiiddPdS_S_S_S_S_S_
	.addrsig_sym _Z31__device_stub__collideAndStreamiidddPdS_S_S_S_S_S_
	.addrsig_sym _Z29__device_stub__everythingElseiidddPdS_S_S_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym ex
	.addrsig_sym ey
	.addrsig_sym oppos
	.addrsig_sym wt
	.addrsig_sym _Z10initializeiiddPdS_S_S_S_S_S_
	.addrsig_sym _Z16collideAndStreamiidddPdS_S_S_S_S_S_
	.addrsig_sym _Z14everythingElseiidddPdS_S_S_S_S_S_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10initializeiiddPdS_S_S_S_S_S_ ; -- Begin function _Z10initializeiiddPdS_S_S_S_S_S_
	.globl	_Z10initializeiiddPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z10initializeiiddPdS_S_S_S_S_S_,@function
_Z10initializeiiddPdS_S_S_S_S_S_:       ; @_Z10initializeiiddPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x5c
	s_load_b64 s[2:3], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, s15, s5, v[3:4]
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	s_mov_b32 s4, exec_lo
	v_max_i32_e32 v1, v0, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_6
; %bb.1:
	s_load_b512 s[4:19], s[0:1], 0x8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[6:7], null, v0, s2, v[8:9]
	s_mov_b32 s20, 0
	s_mov_b32 s2, exec_lo
	s_mov_b32 s21, s20
	v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[9:10], 3, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v9
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v10, vcc_lo
	v_add_co_u32 v4, vcc_lo, s12, v9
	v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s14, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v10, vcc_lo
	global_store_b64 v[0:1], v[13:14], off
	global_store_b64 v[2:3], v[11:12], off
	global_store_b64 v[4:5], v[11:12], off
	global_store_b64 v[9:10], v[11:12], off
	v_cmpx_eq_u32_e32 0, v8
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_dual_mov_b32 v7, s6 :: v_dual_mov_b32 v8, s7
	global_store_b64 v[2:3], v[7:8], off
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_lt_i32 s3, 1
	s_cbranch_scc1 .LBB0_6
; %bb.4:                                ; %.lr.ph
	v_mul_lo_u32 v6, v6, s3
	s_load_b64 s[6:7], s[0:1], 0x48
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ex@rel32@lo+4
	s_addc_u32 s1, s1, ex@rel32@hi+12
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, ey@rel32@lo+4
	s_addc_u32 s5, s5, ey@rel32@hi+12
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[6:7]
	v_add_co_u32 v6, vcc_lo, s18, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, s16, v10
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v11, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, vcc_lo, s6, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, wt@rel32@lo+4
	s_addc_u32 s7, s7, wt@rel32@hi+12
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[12:13], v[4:5], off
	global_load_b64 v[14:15], v[2:3], off
	global_load_b64 v[16:17], v[0:1], off
	s_load_b64 s[8:9], s[4:5], 0x0
	s_add_i32 s3, s3, -1
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_mul_f64 v[18:19], s[8:9], v[12:13]
	s_load_b64 s[8:9], s[0:1], 0x0
	v_mul_f64 v[12:13], v[12:13], v[12:13]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], s[8:9], v[14:15], v[18:19]
	s_load_b64 s[8:9], s[6:7], 0x0
	v_fma_f64 v[12:13], v[14:15], v[14:15], v[12:13]
	s_add_u32 s6, s6, 8
	s_addc_u32 s7, s7, 0
	s_cmp_lg_u32 s3, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f64 v[16:17], v[16:17], s[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], 0x40080000, v[18:19], 1.0
	v_mul_f64 v[22:23], 0x40120000, v[18:19]
	v_fma_f64 v[14:15], v[18:19], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], 0xbff80000, v[12:13], v[14:15]
	v_mul_f64 v[12:13], v[16:17], v[12:13]
	global_store_b64 v[6:7], v[12:13], off
	global_store_b64 v[8:9], v[12:13], off
	global_load_b64 v[12:13], v[6:7], off
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, 8
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[10:11], v[12:13], off
	v_add_co_u32 v10, vcc_lo, v10, 8
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_cbranch_scc1 .LBB0_5
.LBB0_6:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10initializeiiddPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10initializeiiddPdS_S_S_S_S_S_, .Lfunc_end0-_Z10initializeiiddPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 704
; NumSgprs: 24
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z16collideAndStreamiidddPdS_S_S_S_S_S_ ; -- Begin function _Z16collideAndStreamiidddPdS_S_S_S_S_S_
	.globl	_Z16collideAndStreamiidddPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z16collideAndStreamiidddPdS_S_S_S_S_S_,@function
_Z16collideAndStreamiidddPdS_S_S_S_S_S_: ; @_Z16collideAndStreamiidddPdS_S_S_S_S_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x64
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, s14, s3, v[1:2]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v5
	s_cbranch_execz .LBB1_11
; %bb.1:
	s_load_b64 s[24:25], s[0:1], 0x0
	v_bfe_u32 v0, v0, 10, 10
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[6:7], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_max_i32_e32 v0, v5, v6
	v_cmp_lt_i32_e32 vcc_lo, 0, v6
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s24, -2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e64 s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_11
; %bb.2:
	s_cmp_lt_i32 s25, 1
	s_cbranch_scc1 .LBB1_11
; %bb.3:                                ; %.lr.ph
	s_load_b512 s[4:19], s[0:1], 0x8
	v_mad_u64_u32 v[1:2], null, v5, s24, v[6:7]
	s_load_b128 s[20:23], s[0:1], 0x48
	s_mov_b32 s26, s25
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ex@rel32@lo+4
	s_addc_u32 s1, s1, ex@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ey@rel32@lo+4
	s_addc_u32 s3, s3, ey@rel32@hi+12
	v_ashrrev_i32_e32 v2, 31, v1
	v_mul_lo_u32 v0, v1, s25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 3, v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s12, v7
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s14, v7
	v_lshlrev_b64 v[13:14], 3, v[0:1]
	v_add_co_ci_u32_e32 v10, vcc_lo, s15, v8, vcc_lo
	v_add_co_u32 v11, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s20, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s21, v14, vcc_lo
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, wt@rel32@lo+4
	s_addc_u32 s11, s11, wt@rel32@hi+12
.LBB1_4:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[15:16], v[9:10], off
	global_load_b64 v[17:18], v[2:3], off
	global_load_b64 v[19:20], v[11:12], off
	s_load_b64 s[28:29], s[2:3], 0x0
	s_add_i32 s26, s26, -1
	s_waitcnt vmcnt(2) lgkmcnt(0)
	v_mul_f64 v[21:22], s[28:29], v[15:16]
	s_load_b64 s[28:29], s[0:1], 0x0
	v_mul_f64 v[15:16], v[15:16], v[15:16]
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_waitcnt vmcnt(1) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], s[28:29], v[17:18], v[21:22]
	s_load_b64 s[28:29], s[10:11], 0x0
	v_fma_f64 v[15:16], v[17:18], v[17:18], v[15:16]
	s_add_u32 s10, s10, 8
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s26, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f64 v[19:20], v[19:20], s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], 0x40080000, v[21:22], 1.0
	v_mul_f64 v[25:26], 0x40120000, v[21:22]
	v_fma_f64 v[17:18], v[21:22], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], 0xbff80000, v[15:16], v[17:18]
	v_mul_f64 v[15:16], v[19:20], v[15:16]
	global_store_b64 v[13:14], v[15:16], off
	v_add_co_u32 v13, vcc_lo, v13, 8
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_cbranch_scc0 .LBB1_4
; %bb.5:                                ; %.preheader
	v_cvt_f64_i32_e32 v[1:2], s24
	s_mov_b32 s10, 0x4222de17
	s_mov_b32 s11, 0x3fbdee67
	s_mov_b32 s26, 0x3abe935a
	s_mov_b32 s27, 0x3fbe25e4
	s_mov_b32 s28, 0x47e6c9c2
	s_mov_b32 s29, 0x3fc110ef
	s_mov_b32 s30, 0xcfa74449
	s_mov_b32 s31, 0x3fc3b13b
	s_mov_b32 s34, 0x71bf3c30
	s_mov_b32 s35, 0x3fc745d1
	s_mov_b32 s36, 0x1c7792ce
	s_mov_b32 s37, 0x3fcc71c7
	s_mov_b32 s38, 0x924920da
	s_mov_b32 s39, 0x3fd24924
	s_mov_b32 s40, 0x9999999c
	s_mov_b32 s41, 0x3fd99999
	s_mov_b32 s43, 0xbfe55555
	s_mov_b32 s44, 0xd5df274d
	s_mov_b32 s45, 0x3c8543b0
	s_mov_b32 s46, 0xfefa39ef
	s_mov_b32 s47, 0x3fe62e42
	s_mov_b32 s48, 0x3b39803f
	s_mov_b32 s49, 0x3c7abc9e
	s_mov_b32 s50, 0x652b82fe
	s_mov_b32 s51, 0x3ff71547
	s_mov_b32 s53, 0xbfe62e42
	s_mov_b32 s52, s46
	s_mov_b32 s55, 0xbc7abc9e
	s_mov_b32 s54, s48
	s_mov_b32 s56, 0xfca7ab0c
	s_mov_b32 s58, 0x6a5dcb37
	s_mov_b32 s57, 0x3e928af3
	s_mov_b32 s59, 0x3e5ade15
	s_mov_b32 s60, 0x623fde64
	s_mov_b32 s61, 0x3ec71dee
	s_mov_b32 s62, 0x7c89e6b0
	s_mov_b32 s63, 0x3efa0199
	v_mul_f64 v[3:4], v[1:2], s[6:7]
	s_mov_b32 s6, 0x55555555
	s_mov_b32 s7, 0x3fe55555
	s_mov_b32 s42, s6
	s_mov_b32 s64, 0x14761f6e
	s_mov_b32 s65, 0x3f2a01a0
	s_mov_b32 s66, 0x1852b7b0
	s_mov_b32 s67, 0x3f56c16c
	s_mov_b32 s68, 0x11122322
	s_mov_b32 s69, 0x3f811111
	s_mov_b32 s70, 0x555502a1
	s_mov_b32 s71, 0x3fa55555
	s_mov_b32 s72, 0x55555511
	s_mov_b32 s73, 0x3fc55555
	s_mov_b32 s74, 11
	s_mov_b32 s75, 0x3fe00000
	v_add_co_u32 v7, s2, s16, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s2, s17, v8, s2
	s_mov_b32 s78, 0x487fcb93
	s_mov_b32 s79, 0x3fdd7dbf
	s_mov_b32 s80, 0
	v_div_scale_f64 v[9:10], null, s[8:9], s[8:9], v[3:4]
	v_div_scale_f64 v[15:16], vcc_lo, v[3:4], s[8:9], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
	v_div_fixup_f64 v[3:4], v[9:10], s[8:9], v[3:4]
	s_mov_b32 s8, 0x968915a9
	s_mov_b32 s9, 0x3fba6564
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], 0x40080000, v[3:4], 0.5
	v_frexp_mant_f64_e64 v[9:10], |v[3:4]|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[9:10]
	v_cndmask_b32_e64 v11, 0, 1, vcc_lo
	v_ldexp_f64 v[9:10], v[9:10], v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[9:10], 1.0
	v_add_f64 v[17:18], v[9:10], -1.0
	v_rcp_f64_e32 v[13:14], v[11:12]
	v_add_f64 v[19:20], v[11:12], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -v[19:20]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[15:16], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	v_fma_f64 v[13:14], v[15:16], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	v_mul_f64 v[21:22], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[15:16], v[11:12], -v[21:22]
	v_fma_f64 v[9:10], v[15:16], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[21:22], v[9:10]
	v_add_f64 v[19:20], v[17:18], -v[11:12]
	v_add_f64 v[21:22], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	v_add_f64 v[9:10], v[21:22], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[17:18], -v[11:12]
	v_add_f64 v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[19:20], v[9:10]
	v_mul_f64 v[9:10], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[15:16], v[9:10]
	v_add_f64 v[13:14], v[11:12], -v[15:16]
	v_mul_f64 v[15:16], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	v_fma_f64 v[13:14], v[11:12], v[11:12], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[9:10], v[9:10]
	v_fma_f64 v[13:14], v[11:12], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[15:16], v[13:14]
	v_fma_f64 v[19:20], v[17:18], s[10:11], s[8:9]
	v_add_f64 v[15:16], v[17:18], -v[15:16]
	v_mul_f64 v[25:26], v[11:12], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[26:27]
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[28:29]
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[34:35]
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[38:39]
	v_fma_f64 v[19:20], v[17:18], v[19:20], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[21:22], v[17:18], v[19:20]
	v_fma_f64 v[15:16], v[17:18], v[19:20], -v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[13:14], v[19:20], v[15:16]
	v_add_f64 v[19:20], v[21:22], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[19:20], s[6:7]
	v_add_f64 v[21:22], v[19:20], -v[21:22]
	v_add_f64 v[27:28], v[23:24], s[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[21:22]
	v_fma_f64 v[21:22], v[17:18], v[11:12], -v[25:26]
	v_add_f64 v[19:20], v[19:20], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], s[44:45]
	v_fma_f64 v[17:18], v[17:18], v[9:10], v[21:22]
	v_ldexp_f64 v[9:10], v[9:10], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], v[19:20]
	v_fma_f64 v[13:14], v[13:14], v[11:12], v[17:18]
	v_ldexp_f64 v[11:12], v[11:12], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[23:24], v[15:16]
	v_add_f64 v[19:20], v[25:26], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[23:24], -v[17:18]
	v_mul_f64 v[23:24], v[19:20], v[17:18]
	v_add_f64 v[25:26], v[19:20], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], v[21:22]
	v_fma_f64 v[21:22], v[19:20], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[25:26]
	v_fma_f64 v[15:16], v[19:20], v[15:16], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[15:16]
	v_frexp_exp_i32_f64_e32 v17, v[3:4]
	v_add_f64 v[15:16], v[23:24], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v17, vcc_lo
	v_cvt_f64_i32_e32 v[17:18], v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[11:12], v[15:16]
	v_add_f64 v[21:22], v[15:16], -v[23:24]
	v_mul_f64 v[23:24], v[17:18], s[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[19:20], -v[11:12]
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[17:18], s[46:47], -v[23:24]
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], v[13:14]
	v_fma_f64 v[13:14], v[17:18], s[48:49], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[11:12]
	v_add_f64 v[11:12], v[23:24], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[19:20], v[9:10]
	v_add_f64 v[23:24], v[11:12], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[11:12], v[15:16]
	v_add_f64 v[19:20], v[15:16], -v[19:20]
	v_add_f64 v[13:14], v[13:14], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[17:18], -v[11:12]
	v_add_f64 v[9:10], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[17:18], -v[21:22]
	v_add_f64 v[15:16], v[15:16], -v[21:22]
	v_add_f64 v[19:20], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[25:26]
	v_add_f64 v[11:12], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[19:20], -v[13:14]
	v_add_f64 v[11:12], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[19:20], v[19:20], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	v_add_f64 v[21:22], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	v_add_f64 v[15:16], v[21:22], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[13:14]
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], v[11:12]
	v_add_f64 v[11:12], v[21:22], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[11:12], -v[21:22]
	v_add_f64 v[15:16], v[11:12], v[11:12]
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[11:12], 2.0, -v[15:16]
	v_cmp_class_f64_e64 vcc_lo, v[15:16], 0x204
	v_fma_f64 v[9:10], v[9:10], 2.0, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[15:16], v[9:10]
	v_dual_cndmask_b32 v14, v12, v16 :: v_dual_cndmask_b32 v13, v11, v15
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[17:18], v[13:14], s[50:51]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[13:14]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[13:14]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[13:14]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	v_rndne_f64_e32 v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v10, 0, v10 :: v_dual_cndmask_b32 v9, 0, v9
	s_and_b32 vcc_lo, s1, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ex@rel32@lo+4
	s_addc_u32 s3, s3, ex@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[17:18], s[52:53], v[13:14]
	v_cvt_i32_f64_e32 v23, v[17:18]
	v_fma_f64 v[19:20], v[17:18], s[54:55], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], s[58:59], s[56:57]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[62:63]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[64:65]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[66:67]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[70:71]
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[72:73]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], v[19:20], v[21:22], s[74:75]
	v_fma_f64 v[21:22], v[19:20], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[19:20], v[21:22], 1.0
	v_mov_b32_e32 v22, 0x3ff00000
	v_ldexp_f64 v[15:16], v[17:18], v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0x7ff00000, v16, s0
	v_cndmask_b32_e32 v13, 0, v15, vcc_lo
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[3:4]|
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, v11, s1
	v_cmp_neq_f64_e64 s1, 0, v[3:4]
	v_mul_f64 v[11:12], 0x40180000, s[4:5]
	s_getpc_b64 s[4:5]
	s_add_u32 s4, s4, ey@rel32@lo+4
	s_addc_u32 s5, s5, ey@rel32@hi+12
	s_getpc_b64 s[16:17]
	s_add_u32 s16, s16, oppos@rel32@lo+4
	s_addc_u32 s17, s17, oppos@rel32@hi+12
	v_fma_f64 v[15:16], v[13:14], v[9:10], v[13:14]
	v_cmp_class_f64_e64 vcc_lo, v[13:14], 0x204
	s_getpc_b64 s[76:77]
	s_add_u32 s76, s76, wt@rel32@lo+4
	s_addc_u32 s77, s77, wt@rel32@hi+12
	s_add_i32 s24, s24, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v16, v14, vcc_lo
	v_cndmask_b32_e32 v13, v15, v13, vcc_lo
	s_and_b32 vcc_lo, s1, s0
	v_mov_b32_e32 v15, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v9, 0x7fffffff, v9
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0x7ff00000, v9, s0
	v_cvt_f64_i32_e32 v[9:10], v5
	v_cvt_f64_i32_e32 v[5:6], v6
	v_cndmask_b32_e64 v14, 0, v14, s1
.LBB1_6:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[16:17], v[7:8], off
	s_mov_b32 s81, exec_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[17:18], v[16:17], s[78:79], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f64_e64 v[19:20], |v[17:18]|
	v_cmp_class_f64_e64 s33, v[17:18], 0x204
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[19:20]
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[19:20], v[19:20], v16
	v_frexp_exp_i32_f64_e32 v16, v[17:18]
	v_add_f64 v[23:24], v[19:20], 1.0
	v_add_f64 v[29:30], v[19:20], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, 1.0, v[17:18]
	v_rcp_f64_e32 v[25:26], v[23:24]
	v_add_f64 v[31:32], v[23:24], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[27:28], -v[23:24], v[25:26], 1.0
	v_fma_f64 v[25:26], v[27:28], v[25:26], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], -v[23:24], v[25:26], 1.0
	v_fma_f64 v[25:26], v[27:28], v[25:26], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[27:28], v[29:30], v[25:26]
	v_mul_f64 v[33:34], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[27:28], v[23:24], -v[33:34]
	v_fma_f64 v[19:20], v[27:28], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[33:34], v[19:20]
	v_add_f64 v[31:32], v[29:30], -v[23:24]
	v_add_f64 v[33:34], v[23:24], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[29:30], -v[31:32]
	v_add_f64 v[19:20], v[33:34], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[29:30], -v[23:24]
	v_add_f64 v[19:20], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[31:32], v[19:20]
	v_mul_f64 v[19:20], v[25:26], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[27:28], v[19:20]
	v_add_f64 v[25:26], v[23:24], -v[27:28]
	v_mul_f64 v[27:28], v[23:24], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	v_fma_f64 v[25:26], v[23:24], v[23:24], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[29:30], v[19:20], v[19:20]
	v_fma_f64 v[25:26], v[23:24], v[29:30], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[29:30], v[27:28], v[25:26]
	v_fma_f64 v[31:32], v[29:30], s[10:11], s[8:9]
	v_add_f64 v[27:28], v[29:30], -v[27:28]
	v_mul_f64 v[37:38], v[23:24], v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[26:27]
	v_add_f64 v[25:26], v[25:26], -v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[28:29]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[34:35]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[38:39]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[33:34], v[29:30], v[31:32]
	v_fma_f64 v[27:28], v[29:30], v[31:32], -v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[27:28], v[25:26], v[31:32], v[27:28]
	v_add_f64 v[31:32], v[33:34], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[31:32], s[6:7]
	v_add_f64 v[33:34], v[31:32], -v[33:34]
	v_add_f64 v[39:40], v[35:36], s[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[27:28], -v[33:34]
	v_fma_f64 v[33:34], v[29:30], v[23:24], -v[37:38]
	v_add_f64 v[31:32], v[31:32], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[27:28], s[44:45]
	v_fma_f64 v[29:30], v[29:30], v[19:20], v[33:34]
	v_ldexp_f64 v[19:20], v[19:20], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[27:28], v[31:32]
	v_fma_f64 v[25:26], v[25:26], v[23:24], v[29:30]
	v_ldexp_f64 v[23:24], v[23:24], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[35:36], v[27:28]
	v_add_f64 v[31:32], v[37:38], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[35:36], -v[29:30]
	v_mul_f64 v[35:36], v[31:32], v[29:30]
	v_add_f64 v[37:38], v[31:32], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[27:28], v[33:34]
	v_fma_f64 v[33:34], v[31:32], v[29:30], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[25:26], v[25:26], -v[37:38]
	v_fma_f64 v[27:28], v[31:32], v[27:28], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[25:26], v[29:30], v[27:28]
	v_cvt_f64_i32_e32 v[29:30], v16
	v_cndmask_b32_e32 v16, 0x3fe00000, v22, vcc_lo
	v_add_f64 v[27:28], v[35:36], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[31:32], v[23:24], v[27:28]
	v_add_f64 v[33:34], v[27:28], -v[35:36]
	v_mul_f64 v[35:36], v[29:30], s[46:47]
	v_add_f64 v[23:24], v[31:32], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[25:26], -v[33:34]
	v_fma_f64 v[33:34], v[29:30], s[46:47], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[27:28], -v[23:24]
	v_add_f64 v[19:20], v[19:20], v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], v[29:30], s[48:49], v[33:34]
	v_add_f64 v[19:20], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[35:36], v[25:26]
	v_add_f64 v[27:28], v[31:32], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[35:36], v[23:24], -v[35:36]
	v_add_f64 v[29:30], v[23:24], v[27:28]
	v_add_f64 v[31:32], v[27:28], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[25:26], v[25:26], -v[35:36]
	v_add_nc_u32_e32 v35, s80, v0
	v_ashrrev_i32_e32 v36, 31, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[35:36], 3, v[35:36]
	v_add_f64 v[33:34], v[29:30], -v[23:24]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	v_add_f64 v[37:38], v[29:30], -v[33:34]
	v_add_f64 v[27:28], v[27:28], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[31:32], v[25:26], v[19:20]
	v_add_f64 v[23:24], v[23:24], -v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[27:28], v[23:24]
	v_add_f64 v[27:28], v[31:32], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[31:32], v[23:24]
	v_add_f64 v[31:32], v[31:32], -v[27:28]
	v_add_f64 v[19:20], v[19:20], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[29:30], v[23:24]
	v_add_f64 v[25:26], v[25:26], -v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[33:34], -v[29:30]
	v_add_f64 v[19:20], v[19:20], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[23:24], -v[27:28]
	v_add_f64 v[19:20], v[19:20], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[33:34], v[19:20]
	v_add_f64 v[25:26], v[23:24], -v[33:34]
	v_mul_f64 v[27:28], v[15:16], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[19:20], -v[25:26]
	v_fma_f64 v[23:24], v[15:16], v[23:24], -v[27:28]
	v_cmp_class_f64_e64 vcc_lo, v[27:28], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[15:16], v[19:20], v[23:24]
	v_add_f64 v[23:24], v[27:28], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v26, v24, v28 :: v_dual_cndmask_b32 v25, v23, v27
	v_add_co_u32 v37, vcc_lo, s18, v35
	v_add_co_ci_u32_e32 v38, vcc_lo, s19, v36, vcc_lo
	v_mul_f64 v[29:30], v[25:26], s[50:51]
	v_add_co_u32 v35, vcc_lo, s20, v35
	v_add_co_ci_u32_e32 v36, vcc_lo, s21, v36, vcc_lo
	global_load_b64 v[37:38], v[37:38], off
	global_load_b64 v[35:36], v[35:36], off
	v_add_f64 v[23:24], v[23:24], -v[27:28]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[25:26]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[25:26]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[25:26]
	s_load_b64 s[82:83], s[2:3], 0x0
	s_load_b64 s[84:85], s[4:5], 0x0
	v_rndne_f64_e32 v[29:30], v[29:30]
	v_add_f64 v[19:20], v[19:20], -v[23:24]
	v_trunc_f64_e32 v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[31:32], v[29:30], s[52:53], v[25:26]
	v_cvt_i32_f64_e32 v21, v[29:30]
	v_dual_cndmask_b32 v20, 0, v20 :: v_dual_cndmask_b32 v19, 0, v19
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], s[54:55], v[31:32]
	v_fma_f64 v[33:34], v[31:32], s[58:59], s[56:57]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[60:61]
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[62:63]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[64:65]
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[68:69]
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[70:71]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[72:73]
	v_fma_f64 v[33:34], v[31:32], v[33:34], s[74:75]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[33:34], v[31:32], v[33:34], 1.0
	v_fma_f64 v[29:30], v[31:32], v[33:34], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[27:28], v[29:30], v21
	v_mul_f64 v[29:30], v[15:16], 0.5
	v_cndmask_b32_e64 v21, 0x7ff00000, v28, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f64_e32 v[25:26], v[29:30]
	v_cndmask_b32_e32 v27, 0, v27, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, 0, v21, s1
	v_fma_f64 v[19:20], v[27:28], v[19:20], v[27:28]
	v_cmp_class_f64_e64 s1, v[27:28], 0x204
	v_cmp_neq_f64_e64 s0, v[25:26], v[29:30]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[29:30], s[82:83], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v20, v20, v28, s1
	v_cndmask_b32_e64 v19, v19, v27, s1
	v_cmp_eq_f64_e64 s1, 0, v[17:18]
	v_cndmask_b32_e32 v21, 0, v19, vcc_lo
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v16, 0x3ff00000, v18, s0
	v_cndmask_b32_e64 v24, 0, v18, s0
	v_bfi_b32 v16, 0x7fffffff, v20, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v20, 0x7ff80000, v16, vcc_lo
	v_cmp_gt_f64_e32 vcc_lo, 0, v[17:18]
	v_cndmask_b32_e64 v23, 0x7ff00000, 0, s1
	v_bfi_b32 v23, 0x7fffffff, v23, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v19, v19, v21 :: v_dual_cndmask_b32 v16, v16, v20
	s_or_b32 vcc_lo, s1, s33
	v_cndmask_b32_e32 v20, v16, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v19, 0, vcc_lo
	v_cmp_o_f64_e32 vcc_lo, v[17:18], v[17:18]
	s_waitcnt vmcnt(0)
	v_add_f64 v[18:19], v[37:38], -v[35:36]
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_cndmask_b32_e32 v17, 0x7ff80000, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[3:4]
	v_fma_f64 v[16:17], v[16:17], 0.5, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[20:21], null, v[16:17], v[16:17], v[18:19]
	v_rcp_f64_e32 v[23:24], v[20:21]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[20:21], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_fma_f64 v[25:26], -v[20:21], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_div_scale_f64 v[25:26], vcc_lo, v[18:19], v[16:17], v[18:19]
	v_mul_f64 v[27:28], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], -v[20:21], v[27:28], v[25:26]
	v_add_f64 v[20:21], s[84:85], v[5:6]
	v_div_fmas_f64 v[23:24], v[25:26], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], v[29:30], v[1:2], v[20:21]
	v_div_fixup_f64 v[16:17], v[23:24], v[16:17], v[18:19]
	v_cvt_i32_f64_e32 v23, v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v18, v[25:26]
                                        ; implicit-def: $vgpr19
	v_add_f64 v[16:17], v[37:38], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_eq_u32_e64 s33, 0, v23
	v_cmpx_ne_u32_e32 0, v23
; %bb.7:                                ;   in Loop: Header=BB1_6 Depth=1
	v_cvt_i32_f64_e32 v19, v[20:21]
	v_cmp_eq_u32_e32 vcc_lo, s24, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e64 s0, 0, v19
	v_cmp_eq_u32_e64 s1, s24, v19
	v_mad_u64_u32 v[19:20], null, v18, s25, s[80:81]
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_and_not1_b32 s1, s33, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s33, s1, s0
; %bb.8:                                ; %Flow
                                        ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s81
	s_and_saveexec_b32 s0, s33
	s_cbranch_execz .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_6 Depth=1
	v_ashrrev_i32_e32 v19, 31, v18
	s_load_b32 s1, s[16:17], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[18:19], 3, v[18:19]
	v_add_co_u32 v20, vcc_lo, s14, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v21, vcc_lo, s15, v19, vcc_lo
	v_add_co_u32 v18, vcc_lo, s12, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s13, v19, vcc_lo
	global_load_b64 v[20:21], v[20:21], off
	global_load_b64 v[18:19], v[18:19], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[20:21], s[84:85], v[20:21]
	s_load_b64 s[84:85], s[76:77], 0x0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], s[82:83], v[18:19], v[20:21]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[20:21], v[11:12], s[84:85]
	v_fma_f64 v[16:17], -v[20:21], v[18:19], v[16:17]
	v_add_nc_u32_e32 v19, s1, v0
.LBB1_10:                               ;   in Loop: Header=BB1_6 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v20, 31, v19
	s_add_i32 s80, s80, 1
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_add_u32 s4, s4, 8
	v_lshlrev_b64 v[18:19], 3, v[19:20]
	s_addc_u32 s5, s5, 0
	s_add_u32 s16, s16, 4
	s_addc_u32 s17, s17, 0
	s_add_u32 s76, s76, 8
	s_addc_u32 s77, s77, 0
	v_add_co_u32 v18, vcc_lo, s22, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s23, v19, vcc_lo
	s_cmp_lg_u32 s25, s80
	global_store_b64 v[18:19], v[16:17], off
	s_cbranch_scc1 .LBB1_6
.LBB1_11:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16collideAndStreamiidddPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 41
		.amdhsa_next_free_sgpr 86
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z16collideAndStreamiidddPdS_S_S_S_S_S_, .Lfunc_end1-_Z16collideAndStreamiidddPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4928
; NumSgprs: 88
; NumVgprs: 41
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 88
; NumVGPRsForWavesPerEU: 41
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z14everythingElseiidddPdS_S_S_S_S_S_ ; -- Begin function _Z14everythingElseiidddPdS_S_S_S_S_S_
	.globl	_Z14everythingElseiidddPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z14everythingElseiidddPdS_S_S_S_S_S_,@function
_Z14everythingElseiidddPdS_S_S_S_S_S_:  ; @_Z14everythingElseiidddPdS_S_S_S_S_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x64
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e32 0, v1
	s_cbranch_execz .LBB2_16
; %bb.1:
	s_load_b64 s[20:21], s[0:1], 0x0
	v_bfe_u32 v0, v0, 10, 10
	s_lshr_b32 s2, s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_max_i32_e32 v0, v1, v2
	v_cmp_lt_i32_e32 vcc_lo, 0, v2
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s20, -2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e64 s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB2_16
; %bb.2:
	v_mad_u64_u32 v[8:9], null, v1, s20, v[2:3]
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x20
	s_load_b256 s[12:19], s[0:1], 0x40
	s_cmp_gt_i32 s21, 0
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s18, s21
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s21, 1
	v_mul_lo_u32 v4, v8, s21
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_cbranch_scc1 .LBB2_5
; %bb.3:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[4:5]
	s_mov_b32 s1, s18
	v_add_co_u32 v0, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
.LBB2_4:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[0:1], off
	v_add_co_u32 v0, vcc_lo, v0, 8
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 0
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[6:7], off
	v_add_co_u32 v2, vcc_lo, v2, 8
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_cbranch_scc0 .LBB2_4
.LBB2_5:                                ; %._crit_edge
	v_ashrrev_i32_e32 v9, 31, v8
	v_mov_b32_e32 v6, 0
	v_cndmask_b32_e64 v11, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[8:9]
	v_mov_b32_e32 v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s0
	global_store_b64 v[2:3], v[6:7], off
	s_cbranch_vccnz .LBB2_8
; %bb.6:                                ; %.lr.ph128
	v_lshlrev_b64 v[9:10], 3, v[4:5]
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	s_mov_b32 s0, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s16, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s17, v10, vcc_lo
.LBB2_7:                                ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[12:13], v[9:10], off
	v_add_co_u32 v9, vcc_lo, v9, 8
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_add_i32 s0, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 0
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[12:13], v[6:7]
	global_store_b64 v[2:3], v[6:7], off
	s_cbranch_scc0 .LBB2_7
	s_branch .LBB2_9
.LBB2_8:
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
.LBB2_9:                                ; %.preheader
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	v_cmp_ne_u32_e32 vcc_lo, 1, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_cbranch_vccnz .LBB2_12
; %bb.10:                               ; %.lr.ph132
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ex@rel32@lo+4
	s_addc_u32 s1, s1, ex@rel32@hi+12
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ey@rel32@lo+4
	s_addc_u32 s3, s3, ey@rel32@hi+12
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
.LBB2_11:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[13:14], v[4:5], off
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b64 s[12:13], s[2:3], 0x0
	s_add_i32 s18, s18, -1
	v_add_co_u32 v4, vcc_lo, v4, 8
	s_add_u32 s0, s0, 8
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s18, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[11:12], v[13:14], s[4:5], v[11:12]
	v_fma_f64 v[9:10], v[13:14], s[12:13], v[9:10]
	s_cbranch_scc0 .LBB2_11
.LBB2_12:                               ; %._crit_edge133
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, v[6:7], v[6:7], v[11:12]
	v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[6:7], v[11:12]
	s_cmp_lt_i32 s21, 2
	v_rcp_f64_e32 v[13:14], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[4:5], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[4:5], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[15:16], v[17:18]
	v_div_fmas_f64 v[4:5], v[4:5], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[4:5], v[6:7], v[11:12]
	v_add_co_u32 v6, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
	global_store_b64 v[6:7], v[4:5], off
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[11:12], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[11:12], v[6:7]
	v_div_scale_f64 v[11:12], vcc_lo, v[9:10], v[2:3], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[11:12], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[13:14]
	v_add_co_u32 v11, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v1, vcc_lo
	v_div_fixup_f64 v[9:10], v[4:5], v[2:3], v[9:10]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
	global_store_b64 v[11:12], v[9:10], off
	s_cbranch_scc1 .LBB2_15
; %bb.13:                               ; %.lr.ph140
	v_mad_u64_u32 v[4:5], null, v8, s21, 1
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, ex@rel32@lo+12
	s_addc_u32 s1, s1, ex@rel32@hi+20
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, ey@rel32@lo+12
	s_addc_u32 s3, s3, ey@rel32@hi+20
	s_add_i32 s4, s21, -1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	v_add_co_u32 v8, vcc_lo, s16, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, s14, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v7, vcc_lo
	v_dual_mov_b32 v7, v3 :: v_dual_mov_b32 v6, v2
.LBB2_14:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[12:13], v[8:9], off
	global_load_b64 v[14:15], v[10:11], off
	s_load_b64 s[6:7], s[0:1], 0x0
	s_load_b64 s[8:9], s[2:3], 0x0
	v_add_co_u32 v8, vcc_lo, v8, 8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_add_i32 s4, s4, -1
	v_add_co_u32 v10, vcc_lo, v10, 8
	s_add_u32 s0, s0, 8
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_addc_u32 s1, s1, 0
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s4, 0
	s_waitcnt vmcnt(0)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[12:13], s[6:7]
	v_mul_f64 v[12:13], v[12:13], s[8:9]
	v_fma_f64 v[6:7], s[6:7], v[14:15], v[6:7]
	v_fma_f64 v[4:5], v[14:15], s[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[2:3], s[8:9], v[12:13], v[2:3]
	s_cbranch_scc0 .LBB2_14
.LBB2_15:                               ; %Flow236
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_frexp_mant_f64_e64 v[8:9], |v[6:7]|
	v_frexp_mant_f64_e64 v[10:11], |v[4:5]|
	s_mov_b32 s8, 0x55555555
	s_mov_b32 s9, 0x3fe55555
	s_mov_b32 s12, 0x968915a9
	s_mov_b32 s14, 0x4222de17
	s_mov_b32 s13, 0x3fba6564
	s_mov_b32 s15, 0x3fbdee67
	s_mov_b32 s16, 0x3abe935a
	s_mov_b32 s17, 0x3fbe25e4
	s_mov_b32 s18, 0x47e6c9c2
	s_mov_b32 s19, 0x3fc110ef
	s_mov_b32 s20, 0xcfa74449
	s_mov_b32 s21, 0x3fc3b13b
	s_mov_b32 s22, 0x71bf3c30
	s_mov_b32 s23, 0x3fc745d1
	s_mov_b32 s24, 0x1c7792ce
	s_mov_b32 s25, 0x3fcc71c7
	s_mov_b32 s26, 0x924920da
	s_mov_b32 s27, 0x3fd24924
	s_mov_b32 s28, 0x9999999c
	s_mov_b32 s29, 0x3fd99999
	s_mov_b32 s31, 0xbfe55555
	s_mov_b32 s30, s8
	s_mov_b32 s34, 0xd5df274d
	s_mov_b32 s35, 0x3c8543b0
	s_mov_b32 s36, 0xfefa39ef
	s_mov_b32 s37, 0x3fe62e42
	s_mov_b32 s38, 0x3b39803f
	s_mov_b32 s39, 0x3c7abc9e
	s_mov_b32 s40, 0x652b82fe
	s_mov_b32 s41, 0x3ff71547
	s_mov_b32 s43, 0xbfe62e42
	s_mov_b32 s42, s36
	s_mov_b32 s45, 0xbc7abc9e
	s_mov_b32 s44, s38
	s_mov_b32 s46, 0xfca7ab0c
	s_mov_b32 s48, 0x6a5dcb37
	v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[8:9]
	v_cmp_gt_f64_e64 s0, s[8:9], v[10:11]
	s_mov_b32 s47, 0x3e928af3
	s_mov_b32 s49, 0x3e5ade15
	s_mov_b32 s50, 0x623fde64
	s_mov_b32 s51, 0x3ec71dee
	s_mov_b32 s52, 0x7c89e6b0
	s_mov_b32 s53, 0x3efa0199
	s_mov_b32 s54, 0x14761f6e
	s_mov_b32 s55, 0x3f2a01a0
	s_mov_b32 s56, 0x1852b7b0
	s_mov_b32 s57, 0x3f56c16c
	s_mov_b32 s58, 0x11122322
	s_mov_b32 s59, 0x3f811111
	s_mov_b32 s60, 0x555502a1
	s_mov_b32 s61, 0x3fa55555
	s_mov_b32 s62, 0x55555511
	s_mov_b32 s63, 0x3fc55555
	s_mov_b32 s64, 11
	s_mov_b32 s65, 0x3fe00000
	v_cmp_neq_f64_e64 s5, 0, v[6:7]
	v_cmp_neq_f64_e64 s6, 0x7ff00000, |v[4:5]|
	v_cmp_neq_f64_e64 s7, 0, v[4:5]
	v_cndmask_b32_e64 v12, 0, 1, vcc_lo
	v_cndmask_b32_e64 v13, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[8:9], v[8:9], v12
	v_ldexp_f64 v[10:11], v[10:11], v13
	v_frexp_mant_f64_e64 v[12:13], |v[2:3]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[8:9], 1.0
	v_add_f64 v[16:17], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e64 s1, s[8:9], v[12:13]
	v_rcp_f64_e32 v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v18, 0, 1, s1
	v_add_f64 v[40:41], v[16:17], -1.0
	v_ldexp_f64 v[12:13], v[12:13], v18
	v_rcp_f64_e32 v[18:19], v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[26:27], -v[16:17], v[20:21], 1.0
	v_add_f64 v[22:23], v[12:13], 1.0
	v_add_f64 v[36:37], v[12:13], -1.0
	v_fma_f64 v[24:25], -v[14:15], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[20:21], v[26:27], v[20:21], v[20:21]
	v_rcp_f64_e32 v[28:29], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[24:25], v[18:19], v[18:19]
	v_fma_f64 v[30:31], -v[16:17], v[20:21], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[22:23], v[28:29], 1.0
	v_fma_f64 v[26:27], -v[14:15], v[18:19], 1.0
	v_fma_f64 v[20:21], v[30:31], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[24:25], v[28:29], v[28:29]
	v_add_f64 v[28:29], v[8:9], -1.0
	v_fma_f64 v[18:19], v[26:27], v[18:19], v[18:19]
	v_add_f64 v[26:27], v[10:11], -1.0
	v_add_f64 v[10:11], v[10:11], -v[40:41]
	v_fma_f64 v[30:31], -v[22:23], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[32:33], v[28:29], v[18:19]
	v_mul_f64 v[34:35], v[26:27], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[30:31], v[24:25], v[24:25]
	v_add_f64 v[30:31], v[14:15], -1.0
	v_mul_f64 v[38:39], v[14:15], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[42:43], v[16:17], v[34:35]
	v_mul_f64 v[44:45], v[36:37], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[8:9], v[8:9], -v[30:31]
	v_fma_f64 v[14:15], v[32:33], v[14:15], -v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[16:17], v[34:35], v[16:17], -v[42:43]
	v_add_f64 v[30:31], v[22:23], -1.0
	v_mul_f64 v[40:41], v[22:23], v[44:45]
	v_fma_f64 v[8:9], v[32:33], v[8:9], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[10:11], v[34:35], v[10:11], v[16:17]
	v_add_f64 v[12:13], v[12:13], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[44:45], v[22:23], -v[40:41]
	v_add_f64 v[16:17], v[38:39], v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[42:43], v[10:11]
	v_fma_f64 v[12:13], v[44:45], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[28:29], -v[16:17]
	v_add_f64 v[30:31], v[26:27], -v[22:23]
	v_add_f64 v[38:39], v[16:17], -v[38:39]
	v_add_f64 v[42:43], v[22:23], -v[42:43]
	v_add_f64 v[46:47], v[40:41], v[12:13]
	v_add_f64 v[28:29], v[28:29], -v[14:15]
	v_add_f64 v[26:27], v[26:27], -v[30:31]
	v_add_f64 v[8:9], v[38:39], -v[8:9]
	v_add_f64 v[10:11], v[42:43], -v[10:11]
	v_add_f64 v[48:49], v[36:37], -v[46:47]
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	v_add_f64 v[22:23], v[26:27], -v[22:23]
	v_add_f64 v[26:27], v[46:47], -v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[36:37], -v[48:49]
	v_add_f64 v[8:9], v[8:9], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], v[22:23]
	v_add_f64 v[12:13], v[26:27], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[28:29], -v[46:47]
	v_add_f64 v[8:9], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[30:31], v[10:11]
	v_add_f64 v[12:13], v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[8:9], v[18:19], v[8:9]
	v_mul_f64 v[10:11], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[48:49], v[12:13]
	v_add_f64 v[14:15], v[32:33], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[34:35], v[10:11]
	v_mul_f64 v[12:13], v[24:25], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[14:15], -v[32:33]
	v_add_f64 v[20:21], v[16:17], -v[34:35]
	v_mul_f64 v[24:25], v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[44:45], v[12:13]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	v_mul_f64 v[18:19], v[16:17], v[16:17]
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	v_fma_f64 v[26:27], v[14:15], v[14:15], -v[24:25]
	v_add_f64 v[20:21], v[22:23], -v[44:45]
	v_mul_f64 v[34:35], v[22:23], v[22:23]
	v_add_f64 v[28:29], v[8:9], v[8:9]
	v_fma_f64 v[30:31], v[16:17], v[16:17], -v[18:19]
	v_add_f64 v[32:33], v[10:11], v[10:11]
	v_add_f64 v[12:13], v[12:13], -v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[20:21], v[14:15], v[28:29], v[26:27]
	v_fma_f64 v[28:29], v[22:23], v[22:23], -v[34:35]
	v_fma_f64 v[26:27], v[16:17], v[32:33], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[12:13], v[12:13]
	v_add_f64 v[32:33], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[18:19], v[26:27]
	v_fma_f64 v[28:29], v[22:23], v[30:31], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[30:31], v[32:33], s[14:15], s[12:13]
	v_add_f64 v[24:25], v[32:33], -v[24:25]
	v_fma_f64 v[38:39], v[36:37], s[14:15], s[12:13]
	v_add_f64 v[18:19], v[36:37], -v[18:19]
	v_mul_f64 v[50:51], v[14:15], v[32:33]
	v_mul_f64 v[54:55], v[16:17], v[36:37]
	v_add_f64 v[40:41], v[34:35], v[28:29]
	v_fma_f64 v[30:31], v[32:33], v[30:31], s[16:17]
	v_add_f64 v[20:21], v[20:21], -v[24:25]
	v_fma_f64 v[38:39], v[36:37], v[38:39], s[16:17]
	v_add_f64 v[18:19], v[26:27], -v[18:19]
	v_fma_f64 v[42:43], v[40:41], s[14:15], s[12:13]
	v_add_f64 v[34:35], v[40:41], -v[34:35]
	v_fma_f64 v[30:31], v[32:33], v[30:31], s[18:19]
	v_mul_f64 v[62:63], v[22:23], v[40:41]
	v_fma_f64 v[38:39], v[36:37], v[38:39], s[18:19]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[16:17]
	v_add_f64 v[28:29], v[28:29], -v[34:35]
	v_fma_f64 v[30:31], v[32:33], v[30:31], s[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[38:39], v[36:37], v[38:39], s[20:21]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[32:33], v[30:31], s[22:23]
	v_fma_f64 v[38:39], v[36:37], v[38:39], s[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[20:21]
	v_fma_f64 v[30:31], v[32:33], v[30:31], s[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[36:37], v[38:39], s[24:25]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[32:33], v[30:31], s[26:27]
	v_fma_f64 v[38:39], v[36:37], v[38:39], s[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[24:25]
	v_fma_f64 v[30:31], v[32:33], v[30:31], s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[38:39], v[36:37], v[38:39], s[28:29]
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[44:45], v[32:33], v[30:31]
	v_mul_f64 v[46:47], v[36:37], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[40:41], v[42:43], s[28:29]
	v_fma_f64 v[24:25], v[32:33], v[30:31], -v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[36:37], v[38:39], -v[46:47]
	v_mul_f64 v[48:49], v[40:41], v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[20:21], v[30:31], v[24:25]
	v_fma_f64 v[26:27], v[18:19], v[38:39], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[40:41], v[42:43], -v[48:49]
	v_add_f64 v[34:35], v[44:45], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[38:39], v[46:47], v[26:27]
	v_fma_f64 v[30:31], v[28:29], v[42:43], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[42:43], v[34:35], s[8:9]
	v_add_f64 v[44:45], v[34:35], -v[44:45]
	v_add_f64 v[52:53], v[38:39], s[8:9]
	v_add_f64 v[46:47], v[38:39], -v[46:47]
	v_add_f64 v[56:57], v[48:49], v[30:31]
	v_add_f64 v[58:59], v[42:43], s[30:31]
	v_add_f64 v[24:25], v[24:25], -v[44:45]
	v_fma_f64 v[44:45], v[32:33], v[14:15], -v[50:51]
	v_add_f64 v[60:61], v[52:53], s[30:31]
	v_add_f64 v[26:27], v[26:27], -v[46:47]
	v_fma_f64 v[46:47], v[36:37], v[16:17], -v[54:55]
	v_add_f64 v[64:65], v[56:57], s[8:9]
	v_add_f64 v[48:49], v[56:57], -v[48:49]
	v_add_f64 v[34:35], v[34:35], -v[58:59]
	v_add_f64 v[24:25], v[24:25], s[34:35]
	v_fma_f64 v[32:33], v[32:33], v[8:9], v[44:45]
	v_add_f64 v[38:39], v[38:39], -v[60:61]
	v_add_f64 v[26:27], v[26:27], s[34:35]
	v_fma_f64 v[36:37], v[36:37], v[10:11], v[46:47]
	v_fma_f64 v[44:45], v[40:41], v[22:23], -v[62:63]
	v_ldexp_f64 v[8:9], v[8:9], 1
	v_ldexp_f64 v[10:11], v[10:11], 1
	v_add_f64 v[46:47], v[64:65], s[30:31]
	v_add_f64 v[30:31], v[30:31], -v[48:49]
	v_add_f64 v[24:25], v[24:25], v[34:35]
	v_fma_f64 v[20:21], v[20:21], v[14:15], v[32:33]
	v_ldexp_f64 v[14:15], v[14:15], 1
	v_add_f64 v[26:27], v[26:27], v[38:39]
	v_fma_f64 v[18:19], v[18:19], v[16:17], v[36:37]
	v_fma_f64 v[32:33], v[40:41], v[12:13], v[44:45]
	v_ldexp_f64 v[16:17], v[16:17], 1
	v_ldexp_f64 v[12:13], v[12:13], 1
	v_add_f64 v[34:35], v[56:57], -v[46:47]
	v_add_f64 v[30:31], v[30:31], s[34:35]
	v_add_f64 v[36:37], v[42:43], v[24:25]
	v_add_f64 v[38:39], v[50:51], v[20:21]
	v_add_f64 v[40:41], v[52:53], v[26:27]
	v_add_f64 v[44:45], v[54:55], v[18:19]
	v_fma_f64 v[28:29], v[28:29], v[22:23], v[32:33]
	v_ldexp_f64 v[22:23], v[22:23], 1
	v_add_f64 v[30:31], v[30:31], v[34:35]
	v_add_f64 v[32:33], v[42:43], -v[36:37]
	v_mul_f64 v[34:35], v[38:39], v[36:37]
	v_add_f64 v[50:51], v[38:39], -v[50:51]
	v_add_f64 v[42:43], v[52:53], -v[40:41]
	v_mul_f64 v[46:47], v[44:45], v[40:41]
	v_add_f64 v[48:49], v[62:63], v[28:29]
	v_add_f64 v[54:55], v[44:45], -v[54:55]
	v_add_f64 v[52:53], v[64:65], v[30:31]
	v_add_f64 v[24:25], v[24:25], v[32:33]
	v_fma_f64 v[32:33], v[38:39], v[36:37], -v[34:35]
	v_add_f64 v[20:21], v[20:21], -v[50:51]
	v_add_f64 v[26:27], v[26:27], v[42:43]
	v_fma_f64 v[42:43], v[44:45], v[40:41], -v[46:47]
	v_add_f64 v[18:19], v[18:19], -v[54:55]
	v_add_f64 v[56:57], v[64:65], -v[52:53]
	v_mul_f64 v[58:59], v[48:49], v[52:53]
	v_fma_f64 v[24:25], v[38:39], v[24:25], v[32:33]
	v_add_f64 v[32:33], v[48:49], -v[62:63]
	v_fma_f64 v[26:27], v[44:45], v[26:27], v[42:43]
	v_add_f64 v[30:31], v[30:31], v[56:57]
	v_fma_f64 v[38:39], v[48:49], v[52:53], -v[58:59]
	v_fma_f64 v[20:21], v[20:21], v[36:37], v[24:25]
	v_add_f64 v[24:25], v[28:29], -v[32:33]
	v_frexp_exp_i32_f64_e32 v36, v[6:7]
	v_fma_f64 v[18:19], v[18:19], v[40:41], v[26:27]
	v_frexp_exp_i32_f64_e32 v37, v[4:5]
	v_fma_f64 v[26:27], v[48:49], v[30:31], v[38:39]
	v_add_f64 v[28:29], v[34:35], v[20:21]
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v36, vcc_lo
	v_add_f64 v[30:31], v[46:47], v[18:19]
	v_subrev_co_ci_u32_e64 v36, vcc_lo, 0, v37, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[32:33], v32
	v_cvt_f64_i32_e32 v[36:37], v36
	v_fma_f64 v[24:25], v[24:25], v[52:53], v[26:27]
	v_add_f64 v[26:27], v[14:15], v[28:29]
	v_add_f64 v[34:35], v[28:29], -v[34:35]
	v_add_f64 v[40:41], v[30:31], -v[46:47]
	v_frexp_exp_i32_f64_e32 v46, v[2:3]
	v_add_f64 v[38:39], v[16:17], v[30:31]
	v_mul_f64 v[42:43], v[32:33], s[36:37]
	v_add_f64 v[44:45], v[58:59], v[24:25]
	v_add_f64 v[14:15], v[26:27], -v[14:15]
	v_add_f64 v[20:21], v[20:21], -v[34:35]
	v_mul_f64 v[34:35], v[36:37], s[36:37]
	v_add_f64 v[18:19], v[18:19], -v[40:41]
	v_subrev_co_ci_u32_e64 v40, vcc_lo, 0, v46, s1
	v_add_f64 v[16:17], v[38:39], -v[16:17]
	v_fma_f64 v[46:47], v[32:33], s[36:37], -v[42:43]
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[40:41], v40
	v_add_f64 v[48:49], v[22:23], v[44:45]
	v_add_f64 v[50:51], v[44:45], -v[58:59]
	v_add_f64 v[14:15], v[28:29], -v[14:15]
	v_add_f64 v[8:9], v[8:9], v[20:21]
	v_fma_f64 v[20:21], v[36:37], s[36:37], -v[34:35]
	v_add_f64 v[10:11], v[10:11], v[18:19]
	v_add_f64 v[16:17], v[30:31], -v[16:17]
	v_fma_f64 v[28:29], v[32:33], s[38:39], v[46:47]
	v_mul_f64 v[18:19], v[40:41], s[36:37]
	v_add_f64 v[22:23], v[48:49], -v[22:23]
	v_add_f64 v[24:25], v[24:25], -v[50:51]
	v_add_f64 v[8:9], v[8:9], v[14:15]
	v_fma_f64 v[14:15], v[36:37], s[38:39], v[20:21]
	v_add_f64 v[10:11], v[10:11], v[16:17]
	v_fma_f64 v[16:17], v[40:41], s[36:37], -v[18:19]
	v_add_f64 v[20:21], v[44:45], -v[22:23]
	v_add_f64 v[12:13], v[12:13], v[24:25]
	v_add_f64 v[22:23], v[42:43], v[28:29]
	v_add_f64 v[24:25], v[26:27], v[8:9]
	v_add_f64 v[30:31], v[34:35], v[14:15]
	v_add_f64 v[32:33], v[38:39], v[10:11]
	v_fma_f64 v[16:17], v[40:41], s[38:39], v[16:17]
	v_add_f64 v[12:13], v[12:13], v[20:21]
	v_add_f64 v[42:43], v[22:23], -v[42:43]
	v_add_f64 v[20:21], v[22:23], v[24:25]
	v_add_f64 v[26:27], v[24:25], -v[26:27]
	v_add_f64 v[34:35], v[30:31], -v[34:35]
	v_add_f64 v[36:37], v[30:31], v[32:33]
	v_add_f64 v[38:39], v[32:33], -v[38:39]
	v_add_f64 v[40:41], v[18:19], v[16:17]
	v_add_f64 v[44:45], v[48:49], v[12:13]
	v_add_f64 v[28:29], v[28:29], -v[42:43]
	v_add_f64 v[46:47], v[20:21], -v[22:23]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	v_add_f64 v[14:15], v[14:15], -v[34:35]
	v_add_f64 v[50:51], v[36:37], -v[30:31]
	v_add_f64 v[10:11], v[10:11], -v[38:39]
	v_add_f64 v[18:19], v[40:41], -v[18:19]
	v_add_f64 v[52:53], v[40:41], v[44:45]
	v_add_f64 v[34:35], v[44:45], -v[48:49]
	v_add_f64 v[54:55], v[20:21], -v[46:47]
	v_add_f64 v[24:25], v[24:25], -v[46:47]
	v_add_f64 v[38:39], v[28:29], v[8:9]
	v_add_f64 v[56:57], v[36:37], -v[50:51]
	v_add_f64 v[32:33], v[32:33], -v[50:51]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_add_f64 v[26:27], v[52:53], -v[40:41]
	v_add_f64 v[12:13], v[12:13], -v[34:35]
	v_add_f64 v[22:23], v[22:23], -v[54:55]
	v_add_f64 v[30:31], v[30:31], -v[56:57]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[42:43], v[52:53], -v[26:27]
	v_add_f64 v[18:19], v[44:45], -v[26:27]
	v_add_f64 v[22:23], v[24:25], v[22:23]
	v_add_f64 v[24:25], v[14:15], v[10:11]
	v_add_f64 v[26:27], v[38:39], -v[28:29]
	v_add_f64 v[30:31], v[32:33], v[30:31]
	v_add_f64 v[32:33], v[40:41], -v[42:43]
	v_add_f64 v[40:41], v[16:17], v[12:13]
	v_add_f64 v[22:23], v[38:39], v[22:23]
	v_add_f64 v[34:35], v[24:25], -v[14:15]
	v_add_f64 v[38:39], v[38:39], -v[26:27]
	v_add_f64 v[8:9], v[8:9], -v[26:27]
	v_add_f64 v[30:31], v[24:25], v[30:31]
	v_add_f64 v[18:19], v[18:19], v[32:33]
	v_add_f64 v[44:45], v[40:41], -v[16:17]
	v_add_f64 v[32:33], v[20:21], v[22:23]
	v_add_f64 v[24:25], v[24:25], -v[34:35]
	v_add_f64 v[26:27], v[28:29], -v[38:39]
	v_add_f64 v[10:11], v[10:11], -v[34:35]
	v_add_f64 v[42:43], v[36:37], v[30:31]
	v_add_f64 v[18:19], v[40:41], v[18:19]
	v_add_f64 v[28:29], v[40:41], -v[44:45]
	v_add_f64 v[20:21], v[32:33], -v[20:21]
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	v_add_f64 v[8:9], v[8:9], v[26:27]
	v_add_f64 v[12:13], v[12:13], -v[44:45]
	v_add_f64 v[24:25], v[42:43], -v[36:37]
	v_add_f64 v[26:27], v[52:53], v[18:19]
	v_add_f64 v[16:17], v[16:17], -v[28:29]
	v_add_f64 v[20:21], v[22:23], -v[20:21]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	v_add_f64 v[14:15], v[30:31], -v[24:25]
	v_add_f64 v[22:23], v[26:27], -v[52:53]
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_add_f64 v[8:9], v[8:9], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], v[14:15]
	v_add_f64 v[14:15], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[32:33], v[8:9]
	v_add_f64 v[18:19], v[42:43], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_add_f64 v[14:15], v[16:17], -v[32:33]
	v_add_f64 v[20:21], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[22:23], v[18:19], -v[42:43]
	v_add_f64 v[24:25], v[18:19], v[18:19]
	v_add_f64 v[28:29], v[26:27], v[12:13]
	v_add_f64 v[8:9], v[8:9], -v[14:15]
	v_fma_f64 v[14:15], v[16:17], 2.0, -v[20:21]
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	v_add_f64 v[10:11], v[10:11], -v[22:23]
	v_fma_f64 v[16:17], v[18:19], 2.0, -v[24:25]
	v_cmp_class_f64_e64 s0, v[24:25], 0x204
	v_add_f64 v[18:19], v[28:29], -v[26:27]
	v_add_f64 v[22:23], v[28:29], v[28:29]
	v_fma_f64 v[8:9], v[8:9], 2.0, v[14:15]
	v_fma_f64 v[10:11], v[10:11], 2.0, v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], -v[18:19]
	v_fma_f64 v[14:15], v[28:29], 2.0, -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[20:21], v[8:9]
	v_add_f64 v[18:19], v[24:25], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[12:13], 2.0, v[14:15]
	v_dual_cndmask_b32 v15, v17, v21 :: v_dual_cndmask_b32 v14, v16, v20
	v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x204
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_cndmask_b32_e64 v27, v19, v25, s0
	v_cndmask_b32_e64 v26, v18, v24, s0
	v_mul_f64 v[28:29], v[14:15], s[40:41]
	v_add_f64 v[18:19], v[18:19], -v[24:25]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[14:15]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[14:15]
	v_mul_f64 v[30:31], v[26:27], s[40:41]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[26:27]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[26:27]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[26:27]|
	v_add_f64 v[32:33], v[22:23], v[12:13]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_rndne_f64_e32 v[28:29], v[28:29]
	v_add_f64 v[10:11], v[10:11], -v[18:19]
	v_rndne_f64_e32 v[30:31], v[30:31]
	v_dual_cndmask_b32 v35, v33, v23 :: v_dual_cndmask_b32 v34, v32, v22
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[14:15]|
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[36:37], v[34:35], s[40:41]
	v_fma_f64 v[38:39], v[28:29], s[42:43], v[14:15]
	v_cvt_i32_f64_e32 v50, v[28:29]
	v_add_f64 v[14:15], v[32:33], -v[22:23]
	v_cndmask_b32_e64 v11, 0, v11, s0
	v_fma_f64 v[40:41], v[30:31], s[42:43], v[26:27]
	v_cndmask_b32_e64 v10, 0, v10, s0
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[34:35]
	v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v8, 0, v8
	s_and_b32 vcc_lo, s2, s1
	v_rndne_f64_e32 v[36:37], v[36:37]
	v_fma_f64 v[38:39], v[28:29], s[44:45], v[38:39]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_fma_f64 v[40:41], v[30:31], s[44:45], v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[42:43], v[36:37], s[42:43], v[34:35]
	v_cvt_i32_f64_e32 v18, v[36:37]
	v_fma_f64 v[44:45], v[38:39], s[48:49], s[46:47]
	v_fma_f64 v[46:47], v[40:41], s[48:49], s[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[36:37], s[44:45], v[42:43]
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[50:51]
	v_fma_f64 v[48:49], v[42:43], s[48:49], s[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[52:53]
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[50:51]
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[54:55]
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[56:57]
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[54:55]
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[58:59]
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[60:61]
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[58:59]
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[62:63]
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], v[38:39], v[44:45], s[64:65]
	v_fma_f64 v[46:47], v[40:41], v[46:47], s[64:65]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[62:63]
	v_fma_f64 v[44:45], v[38:39], v[44:45], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[46:47], v[40:41], v[46:47], 1.0
	v_fma_f64 v[48:49], v[42:43], v[48:49], s[64:65]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[28:29], v[38:39], v[44:45], 1.0
	v_cvt_i32_f64_e32 v38, v[30:31]
	v_fma_f64 v[30:31], v[40:41], v[46:47], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[20:21], v[42:43], v[48:49], 1.0
	v_ldexp_f64 v[24:25], v[28:29], v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[28:29], v[30:31], v38
	v_fma_f64 v[16:17], v[42:43], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v19, 0x7ff00000, v25, s1
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[34:35]
	v_cndmask_b32_e64 v20, 0x7ff00000, v29, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, 0, v19, s2
	v_cndmask_b32_e64 v21, 0, v20, s4
	v_ldexp_f64 v[16:17], v[16:17], v18
	v_cndmask_b32_e32 v18, 0, v24, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cmp_neq_f64_e64 s4, 0x7ff00000, |v[6:7]|
	v_cndmask_b32_e32 v20, 0, v28, vcc_lo
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[34:35]|
	v_fma_f64 v[8:9], v[18:19], v[8:9], v[18:19]
	v_cmp_class_f64_e64 s2, v[18:19], 0x204
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[10:11], v[20:21], v[10:11], v[20:21]
	v_cmp_class_f64_e64 s3, v[20:21], 0x204
	v_cndmask_b32_e64 v14, 0x7ff00000, v17, s0
	v_dual_cndmask_b32 v5, 0, v13 :: v_dual_cndmask_b32 v4, 0, v12
	v_cndmask_b32_e64 v9, v9, v19, s2
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v7, 0, v14, s1
	v_cndmask_b32_e64 v11, v11, v21, s3
	v_dual_cndmask_b32 v6, 0, v16 :: v_dual_and_b32 v9, 0x7fffffff, v9
	v_cndmask_b32_e64 v8, v8, v18, s2
	s_and_b32 vcc_lo, s5, s4
	s_delay_alu instid0(VALU_DEP_3)
	v_and_b32_e32 v11, 0x7fffffff, v11
	v_cndmask_b32_e64 v10, v10, v20, s3
	v_fma_f64 v[4:5], v[6:7], v[4:5], v[6:7]
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	s_and_b32 vcc_lo, s7, s6
	v_cndmask_b32_e64 v9, 0x7ff00000, v9, s4
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x204
	v_cndmask_b32_e64 v11, 0x7ff00000, v11, s6
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[2:3]|
	v_cndmask_b32_e64 v9, 0, v9, s5
	v_cmp_neq_f64_e64 s1, 0, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 0, v11, s7
	v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v5, 0x7fffffff, v5
	v_add_f64 v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cndmask_b32_e64 v5, 0x7ff00000, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v5, 0, v5, s1
	v_add_f64 v[2:3], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	v_frexp_mant_f64_e32 v[4:5], v[2:3]
	v_cmp_eq_f64_e64 s3, 0, v[2:3]
	v_cmp_eq_f64_e64 s2, 0x7ff00000, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, s[8:9], v[4:5]
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	v_ldexp_f64 v[4:5], v[4:5], v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[4:5], 1.0
	v_add_f64 v[12:13], v[4:5], -1.0
	v_rcp_f64_e32 v[8:9], v[6:7]
	v_add_f64 v[14:15], v[6:7], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	v_mul_f64 v[16:17], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
	v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[16:17], v[4:5]
	v_add_f64 v[14:15], v[12:13], -v[6:7]
	v_add_f64 v[16:17], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_add_f64 v[4:5], v[16:17], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[12:13], -v[6:7]
	v_add_f64 v[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[14:15], v[4:5]
	v_mul_f64 v[4:5], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[10:11], v[4:5]
	v_add_f64 v[8:9], v[6:7], -v[10:11]
	v_mul_f64 v[10:11], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], -v[8:9]
	v_fma_f64 v[8:9], v[6:7], v[6:7], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[4:5], v[4:5]
	v_fma_f64 v[8:9], v[6:7], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[10:11], v[8:9]
	v_fma_f64 v[14:15], v[12:13], s[14:15], s[12:13]
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	v_mul_f64 v[20:21], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[16:17]
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[18:19]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[22:23]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[26:27]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[12:13], v[14:15]
	v_fma_f64 v[10:11], v[12:13], v[14:15], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
	v_add_f64 v[14:15], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[14:15], s[8:9]
	v_add_f64 v[16:17], v[14:15], -v[16:17]
	v_add_f64 v[22:23], v[18:19], s[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_fma_f64 v[16:17], v[12:13], v[6:7], -v[20:21]
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], s[34:35]
	v_fma_f64 v[12:13], v[12:13], v[4:5], v[16:17]
	v_ldexp_f64 v[4:5], v[4:5], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], v[14:15]
	v_fma_f64 v[8:9], v[8:9], v[6:7], v[12:13]
	v_ldexp_f64 v[6:7], v[6:7], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[18:19], v[10:11]
	v_add_f64 v[14:15], v[20:21], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[18:19], -v[12:13]
	v_mul_f64 v[18:19], v[14:15], v[12:13]
	v_add_f64 v[20:21], v[14:15], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], v[16:17]
	v_fma_f64 v[16:17], v[14:15], v[12:13], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[20:21]
	v_fma_f64 v[10:11], v[14:15], v[10:11], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], v[12:13], v[10:11]
	v_frexp_exp_i32_f64_e32 v12, v[2:3]
	v_add_f64 v[10:11], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, 1.0, v[2:3]
	v_cvt_f64_i32_e32 v[12:13], v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[6:7], v[10:11]
	v_add_f64 v[16:17], v[10:11], -v[18:19]
	v_mul_f64 v[18:19], v[12:13], s[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[14:15], -v[6:7]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[12:13], s[36:37], -v[18:19]
	v_add_f64 v[6:7], v[10:11], -v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_fma_f64 v[8:9], v[12:13], s[38:39], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[18:19], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[14:15], v[4:5]
	v_add_f64 v[18:19], v[6:7], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[6:7], v[10:11]
	v_add_f64 v[14:15], v[10:11], -v[14:15]
	v_add_f64 v[8:9], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[12:13], -v[6:7]
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[12:13], -v[16:17]
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_add_f64 v[14:15], v[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[20:21]
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[14:15], -v[8:9]
	v_add_f64 v[6:7], v[14:15], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[14:15], -v[10:11]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	v_add_f64 v[16:17], v[12:13], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[14:15]
	v_add_f64 v[10:11], v[16:17], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_dual_mov_b32 v9, 0x3ff00000 :: v_dual_mov_b32 v8, 0
	v_cndmask_b32_e32 v9, 0x3fe00000, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_add_f64 v[4:5], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[16:17], v[4:5]
	v_add_f64 v[10:11], v[6:7], -v[16:17]
	v_mul_f64 v[12:13], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	v_fma_f64 v[6:7], v[8:9], v[6:7], -v[12:13]
	v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v11, v7, v13 :: v_dual_cndmask_b32 v10, v6, v12
	v_add_f64 v[6:7], v[6:7], -v[12:13]
	v_mul_f64 v[14:15], v[10:11], s[40:41]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[10:11]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[10:11]|
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[10:11]
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_trunc_f64_e32 v[6:7], v[8:9]
	v_rndne_f64_e32 v[14:15], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 0, v4
	s_and_b32 vcc_lo, s1, s0
	v_fma_f64 v[16:17], v[14:15], s[42:43], v[10:11]
	v_cvt_i32_f64_e32 v20, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], v[14:15], s[44:45], v[16:17]
	v_fma_f64 v[18:19], v[16:17], s[48:49], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[50:51]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[54:55]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[56:57]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[58:59]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[62:63]
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[64:65]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], 1.0
	v_fma_f64 v[14:15], v[16:17], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[12:13], v[14:15], v20
	v_mul_f64 v[14:15], v[8:9], 0.5
	v_cndmask_b32_e64 v13, 0x7ff00000, v13, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f64_e32 v[10:11], v[14:15]
	v_cndmask_b32_e32 v12, 0, v12, vcc_lo
	v_cmp_eq_f64_e32 vcc_lo, v[6:7], v[8:9]
	v_cndmask_b32_e64 v6, 0x7ff00000, 0, s3
	v_cndmask_b32_e64 v13, 0, v13, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13]
	v_cmp_class_f64_e64 s1, v[12:13], 0x204
	v_cmp_neq_f64_e64 s0, v[10:11], v[14:15]
	v_cndmask_b32_e64 v5, v5, v13, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, v4, v12, s1
	s_and_b32 vcc_lo, vcc_lo, s0
	v_add_co_u32 v0, s0, s10, v0
	v_cndmask_b32_e32 v7, 0x3ff00000, v3, vcc_lo
	v_cndmask_b32_e32 v8, 0, v3, vcc_lo
	s_or_b32 vcc_lo, s3, s2
	v_add_co_ci_u32_e64 v1, s0, s11, v1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfi_b32 v5, 0x7fffffff, v5, v7
	v_bfi_b32 v6, 0x7fffffff, v6, v8
	v_cndmask_b32_e64 v4, v4, 0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_o_f64_e32 vcc_lo, v[2:3], v[2:3]
	v_cndmask_b32_e32 v2, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0x7ff80000, v5, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB2_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14everythingElseiidddPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 66
		.amdhsa_next_free_sgpr 66
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z14everythingElseiidddPdS_S_S_S_S_S_, .Lfunc_end2-_Z14everythingElseiidddPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7336
; NumSgprs: 68
; NumVgprs: 66
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 68
; NumVGPRsForWavesPerEU: 66
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	ex                      ; @ex
	.type	ex,@object
	.section	.bss,"aw",@nobits
	.globl	ex
	.p2align	4, 0x0
ex:
	.zero	72
	.size	ex, 72

	.protected	ey                      ; @ey
	.type	ey,@object
	.globl	ey
	.p2align	4, 0x0
ey:
	.zero	72
	.size	ey, 72

	.protected	oppos                   ; @oppos
	.type	oppos,@object
	.globl	oppos
	.p2align	4, 0x0
oppos:
	.zero	36
	.size	oppos, 36

	.protected	wt                      ; @wt
	.type	wt,@object
	.globl	wt
	.p2align	4, 0x0
wt:
	.zero	72
	.size	wt, 72

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym ex
	.addrsig_sym ey
	.addrsig_sym oppos
	.addrsig_sym wt
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10initializeiiddPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z10initializeiiddPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16collideAndStreamiidddPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     88
    .sgpr_spill_count: 0
    .symbol:         _Z16collideAndStreamiidddPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     41
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14everythingElseiidddPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     68
    .sgpr_spill_count: 0
    .symbol:         _Z14everythingElseiidddPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     66
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
