// http://forums.nvidia.com/index.php?showtopic=52806&pid=287558&mode=threaded&start=#entry287558

#include <stdlib.h>
#include <stdio.h>

#include <cuda_runtime_api.h>


const int num_threads = 64;
const int len = 30720 * 128;//2949120;
const int stride = 16;
int nIters = 500;



#  define CUDA_SAFE_CALL( call) do {					\
	cudaError err = call;						\
	if( cudaSuccess != err) {					\
	    fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
		__FILE__, __LINE__, cudaGetErrorString( err) );		\
	    exit(EXIT_FAILURE);						\
	    } } while (0)

#ifdef NDEBUG
#define CUT_CHECK_ERROR(errorMessage)
#else
#  define CUT_CHECK_ERROR(errorMessage) do {				\
	cudaThreadSynchronize();					\
	cudaError_t err = cudaGetLastError();				\
	if( cudaSuccess != err) {					\
	    fprintf(stderr, "Cuda error: %s in file '%s' in line %i : %s.\n", \
		errorMessage, __FILE__, __LINE__, cudaGetErrorString( err) ); \
	    exit(EXIT_FAILURE);						\
	    } } while (0)
#endif



// This is a proposed new arrangement: array of structs of arrays of structs
// (ASAS.)
typedef struct {
    float4 abcd[stride];
    float4 efgh[stride];
    } states;
    
__global__ void read_and_write_states(states *y0, states *y1)
    {
    // x-axis threads are contiguous (?)
    const unsigned int modelx = threadIdx.x + blockIdx.x * blockDim.x;
    const unsigned int modely = threadIdx.y + blockIdx.y * blockDim.y;
    float4 abcd = y0[modely].abcd[modelx];
    float4 efgh = y0[modely].efgh[modelx];

    abcd.x = 1.0f * modelx;
    abcd.y = 1.0f * modely;
    efgh.z = -1.0f * modelx;
    efgh.w = -1.0f * modely;

    y1[modely].abcd[modelx] = abcd;
    y1[modely].efgh[modelx] = efgh;
    }


typedef struct {
    float2 ab[stride];
    float2 cd[stride];
    float2 ef[stride];
    float2 gh[stride];
    } states4;
    
__global__ void read_and_write_states4(states4 *y0, states4 *y1)
    {
    // x-axis threads are contiguous (?)
    const unsigned int modelx = threadIdx.x + blockIdx.x * blockDim.x;
    const unsigned int modely = threadIdx.y + blockIdx.y * blockDim.y;
    float2 ab = y0[modely].ab[modelx];
    float2 cd = y0[modely].cd[modelx];
    float2 ef = y0[modely].ef[modelx];
    float2 gh = y0[modely].gh[modelx];

    ab.x = 1.0f * modelx;
    ab.y = 1.0f * modely;
    ef.x = -1.0f * modelx;
    ef.y = -1.0f * modely;

    y1[modely].ab[modelx] = ab;
    y1[modely].cd[modelx] = cd;
    y1[modely].ef[modelx] = ef;
    y1[modely].gh[modelx] = gh;
    }


// This is the way we are arranging device memory currently.
typedef struct {
    float a[len];
    float b[len];
    float c[len];
    float d[len];
    float e[len];
    float f[len];
    float g[len];
    float h[len];
    } states2;

__global__ void read_and_write_states2(states2 *y0, states2 *y1)
    {
    const unsigned int model = threadIdx.x + blockIdx.x * blockDim.x;
    float a = y0->a[model];
    float b = y0->b[model];
    float c = y0->c[model];
    float d = y0->d[model];
    float e = y0->e[model];
    float f = y0->f[model];
    float g = y0->g[model];
    float h = y0->h[model];

    a = 1.0f * model;
    b = 1.0f * model;
    g = -1.0f * model;
    h = -1.0 * model;

    y1->a[model] = a;
    y1->b[model] = b;
    y1->c[model] = c;
    y1->d[model] = d;
    y1->e[model] = e;
    y1->f[model] = f;
    y1->g[model] = g;
    y1->h[model] = h;
    }


int main1()
    {
    CUDA_SAFE_CALL( cudaSetDevice(0) );
    int num_models = len;
    float runTime;

    states *d_idata, *d_odata;
    CUDA_SAFE_CALL( cudaMalloc((void**)&d_idata, (num_models/stride)*sizeof(states)) );
    CUDA_SAFE_CALL( cudaMalloc((void**)&d_odata, (num_models/stride)*sizeof(states)) );


    dim3  threads(stride, num_threads/stride, 1);
    dim3  grid(1, num_models/stride/threads.y, 1);

    cudaEvent_t start, end;
    CUDA_SAFE_CALL( cudaEventCreate(&start) );
    CUDA_SAFE_CALL( cudaEventCreate(&end) );
    CUDA_SAFE_CALL( cudaEventRecord(start, 0) );

    for (int i=0; i < nIters; ++i)
	{
	read_and_write_states<<< grid, threads >>>(d_idata, d_odata);
	}

    CUDA_SAFE_CALL( cudaEventRecord(end, 0) );
    CUDA_SAFE_CALL( cudaEventSynchronize(end) );

    CUDA_SAFE_CALL( cudaEventElapsedTime(&runTime, start, end) );

    runTime /= float(nIters);
    float bandwidth = (2 * (num_models/stride)*sizeof(states)) / (runTime * 1.0e-3 * (1<<30));
    printf("Average time:% 13.4f ms\n", runTime);
    printf("Bandwidth:% 16.4f GiB/s\n\n", bandwidth);

    return 0;
    }


int main4()
    {
    CUDA_SAFE_CALL( cudaSetDevice(0) );
    int num_models = len;
    float runTime;

    states4 *d_idata, *d_odata;
    CUDA_SAFE_CALL( cudaMalloc((void**)&d_idata, (num_models/stride)*sizeof(states4)) );
    CUDA_SAFE_CALL( cudaMalloc((void**)&d_odata, (num_models/stride)*sizeof(states4)) );


    dim3  threads(stride, num_threads/stride, 1);
    dim3  grid(1, num_models/stride/threads.y, 1);

    cudaEvent_t start, end;
    CUDA_SAFE_CALL( cudaEventCreate(&start) );
    CUDA_SAFE_CALL( cudaEventCreate(&end) );
    CUDA_SAFE_CALL( cudaEventRecord(start, 0) );

    for (int i=0; i < nIters; ++i)
	{
	read_and_write_states4<<< grid, threads >>>(d_idata, d_odata);
	}

    CUDA_SAFE_CALL( cudaEventRecord(end, 0) );
    CUDA_SAFE_CALL( cudaEventSynchronize(end) );

    CUDA_SAFE_CALL( cudaEventElapsedTime(&runTime, start, end) );

    runTime /= float(nIters);
    float bandwidth = (2 * (num_models/stride)*sizeof(states4)) / (runTime * 1.0e-3 * (1<<30));
    printf("Average time:% 13.4f ms\n", runTime);
    printf("Bandwidth:% 16.4f GiB/s\n\n", bandwidth);

    return 0;
    }


int main()
    {
    CUDA_SAFE_CALL( cudaSetDevice(0) );
    int num_models = len;
    float runTime;

    states2 *d_idata, *d_odata;
    CUDA_SAFE_CALL( cudaMalloc((void**)&d_idata, sizeof(states2)) );
    CUDA_SAFE_CALL( cudaMalloc((void**)&d_odata, sizeof(states2)) );


    dim3  threads(num_threads, 1, 1);
    dim3  grid(num_models/threads.x, 1, 1);

    cudaEvent_t start, end;
    CUDA_SAFE_CALL( cudaEventCreate(&start) );
    CUDA_SAFE_CALL( cudaEventCreate(&end) );
    CUDA_SAFE_CALL( cudaEventRecord(start, 0) );

    for (int i=0; i < nIters; ++i)
	{
	read_and_write_states2<<< grid, threads >>>(d_idata, d_odata);
	}

    CUDA_SAFE_CALL( cudaEventRecord(end, 0) );
    CUDA_SAFE_CALL( cudaEventSynchronize(end) );

    CUDA_SAFE_CALL( cudaEventElapsedTime(&runTime, start, end) );

    runTime /= float(nIters);
    float bandwidth = (2 * sizeof(states2)) / (runTime * 1.0e-3 * (1<<30));
    printf("Average time:% 13.4f ms\n", runTime);
    printf("Bandwidth:% 16.4f GiB/s\n\n", bandwidth);

    return 0;
    }


	.file	"tmpxft_0036838a_00000000-6_bandwidth_test.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z21read_and_write_statesP6statesS0_P6statesS0_
	.type	_Z50__device_stub__Z21read_and_write_statesP6statesS0_P6statesS0_, @function
_Z50__device_stub__Z21read_and_write_statesP6statesS0_P6statesS0_:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z21read_and_write_statesP6statesS0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z50__device_stub__Z21read_and_write_statesP6statesS0_P6statesS0_, .-_Z50__device_stub__Z21read_and_write_statesP6statesS0_P6statesS0_
	.globl	_Z21read_and_write_statesP6statesS0_
	.type	_Z21read_and_write_statesP6statesS0_, @function
_Z21read_and_write_statesP6statesS0_:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z21read_and_write_statesP6statesS0_P6statesS0_
	.cfi_endproc
.LFE2055:
	.size	_Z21read_and_write_statesP6statesS0_, .-_Z21read_and_write_statesP6statesS0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/joshuaecook/simengine/master/SIMENGINE/branches/McIntyre_gpu/share/cuda/bandwidth_test.cu"
.LC1:
	.string	"Cuda error in file '%s' in line %i : %s.\n"
.LC5:
	.string	"Average time:% 13.4f ms\n"
.LC6:
	.string	"Bandwidth:% 16.4f GiB/s\n\n"
	.text
	.globl	_Z5main1v
	.type	_Z5main1v, @function
_Z5main1v:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%edi, %edi
	subq	$96, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	testl	%eax, %eax
	je	.L9
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$135, %r8d
	movq	%rax, %r9
	jmp	.L25
.L9:
	leaq	32(%rsp), %rdi
	movl	$125829120, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L10
	call	cudaGetErrorString@PLT
	movl	$140, %r8d
	movq	%rax, %r9
.L25:
	movq	stderr(%rip), %rdi
	leaq	.LC0(%rip), %rcx
	leaq	.LC1(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L10:
	leaq	40(%rsp), %rdi
	movl	$125829120, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L11
	call	cudaGetErrorString@PLT
	movl	$141, %r8d
	movq	%rax, %r9
	jmp	.L25
.L11:
	movabsq	$263882790666241, %rax
	leaq	48(%rsp), %rdi
	movl	$16, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L12
	call	cudaGetErrorString@PLT
	movl	$148, %r8d
	movq	%rax, %r9
	jmp	.L25
.L12:
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L13
	call	cudaGetErrorString@PLT
	movl	$149, %r8d
	movq	%rax, %r9
	jmp	.L25
.L13:
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L14
	call	cudaGetErrorString@PLT
	movl	$150, %r8d
	movq	%rax, %r9
	jmp	.L25
.L16:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4, 68(%rsp)
	movl	84(%rsp), %esi
	movq	64(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z50__device_stub__Z21read_and_write_statesP6statesS0_P6statesS0_
.L15:
	incl	%ebx
.L14:
	cmpl	%ebx, nIters(%rip)
	jg	.L16
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L17
	call	cudaGetErrorString@PLT
	movl	$157, %r8d
	movq	%rax, %r9
	jmp	.L25
.L17:
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L18
	call	cudaGetErrorString@PLT
	movl	$158, %r8d
	movq	%rax, %r9
	jmp	.L25
.L18:
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L19
	call	cudaGetErrorString@PLT
	movl	$160, %r8d
	movq	%rax, %r9
	jmp	.L25
.L19:
	cvtsi2ssl	nIters(%rip), %xmm0
	movss	28(%rsp), %xmm2
	movb	$1, %al
	leaq	.LC5(%rip), %rsi
	movsd	.LC2(%rip), %xmm1
	movl	$2, %edi
	divss	%xmm0, %xmm2
	movsd	.LC4(%rip), %xmm0
	movss	%xmm2, 28(%rsp)
	cvtss2sd	%xmm2, %xmm2
	mulsd	%xmm2, %xmm1
	mulsd	.LC3(%rip), %xmm1
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm1
	movaps	%xmm2, %xmm0
	movss	%xmm1, 12(%rsp)
	call	__printf_chk@PLT
	movss	12(%rsp), %xmm1
	leaq	.LC6(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$96, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z5main1v, .-_Z5main1v
	.globl	_Z52__device_stub__Z22read_and_write_states4P7states4S0_P7states4S0_
	.type	_Z52__device_stub__Z22read_and_write_states4P7states4S0_P7states4S0_, @function
_Z52__device_stub__Z22read_and_write_states4P7states4S0_P7states4S0_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z22read_and_write_states4P7states4S0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L26:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z52__device_stub__Z22read_and_write_states4P7states4S0_P7states4S0_, .-_Z52__device_stub__Z22read_and_write_states4P7states4S0_P7states4S0_
	.globl	_Z22read_and_write_states4P7states4S0_
	.type	_Z22read_and_write_states4P7states4S0_, @function
_Z22read_and_write_states4P7states4S0_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z22read_and_write_states4P7states4S0_P7states4S0_
	.cfi_endproc
.LFE2057:
	.size	_Z22read_and_write_states4P7states4S0_, .-_Z22read_and_write_states4P7states4S0_
	.globl	_Z5main4v
	.type	_Z5main4v, @function
_Z5main4v:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%edi, %edi
	subq	$96, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	testl	%eax, %eax
	je	.L32
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$173, %r8d
	movq	%rax, %r9
	jmp	.L48
.L32:
	leaq	32(%rsp), %rdi
	movl	$125829120, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L33
	call	cudaGetErrorString@PLT
	movl	$178, %r8d
	movq	%rax, %r9
.L48:
	movq	stderr(%rip), %rdi
	leaq	.LC0(%rip), %rcx
	leaq	.LC1(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L33:
	leaq	40(%rsp), %rdi
	movl	$125829120, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L34
	call	cudaGetErrorString@PLT
	movl	$179, %r8d
	movq	%rax, %r9
	jmp	.L48
.L34:
	movabsq	$263882790666241, %rax
	leaq	48(%rsp), %rdi
	movl	$16, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L35
	call	cudaGetErrorString@PLT
	movl	$186, %r8d
	movq	%rax, %r9
	jmp	.L48
.L35:
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L36
	call	cudaGetErrorString@PLT
	movl	$187, %r8d
	movq	%rax, %r9
	jmp	.L48
.L36:
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L37
	call	cudaGetErrorString@PLT
	movl	$188, %r8d
	movq	%rax, %r9
	jmp	.L48
.L39:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4, 68(%rsp)
	movl	84(%rsp), %esi
	movq	64(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z52__device_stub__Z22read_and_write_states4P7states4S0_P7states4S0_
.L38:
	incl	%ebx
.L37:
	cmpl	%ebx, nIters(%rip)
	jg	.L39
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L40
	call	cudaGetErrorString@PLT
	movl	$195, %r8d
	movq	%rax, %r9
	jmp	.L48
.L40:
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L41
	call	cudaGetErrorString@PLT
	movl	$196, %r8d
	movq	%rax, %r9
	jmp	.L48
.L41:
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L42
	call	cudaGetErrorString@PLT
	movl	$198, %r8d
	movq	%rax, %r9
	jmp	.L48
.L42:
	cvtsi2ssl	nIters(%rip), %xmm0
	movss	28(%rsp), %xmm2
	movb	$1, %al
	leaq	.LC5(%rip), %rsi
	movsd	.LC2(%rip), %xmm1
	movl	$2, %edi
	divss	%xmm0, %xmm2
	movsd	.LC4(%rip), %xmm0
	movss	%xmm2, 28(%rsp)
	cvtss2sd	%xmm2, %xmm2
	mulsd	%xmm2, %xmm1
	mulsd	.LC3(%rip), %xmm1
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm1
	movaps	%xmm2, %xmm0
	movss	%xmm1, 12(%rsp)
	call	__printf_chk@PLT
	movss	12(%rsp), %xmm1
	leaq	.LC6(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$96, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z5main4v, .-_Z5main4v
	.globl	_Z52__device_stub__Z22read_and_write_states2P7states2S0_P7states2S0_
	.type	_Z52__device_stub__Z22read_and_write_states2P7states2S0_P7states2S0_, @function
_Z52__device_stub__Z22read_and_write_states2P7states2S0_P7states2S0_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z22read_and_write_states2P7states2S0_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L49:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z52__device_stub__Z22read_and_write_states2P7states2S0_P7states2S0_, .-_Z52__device_stub__Z22read_and_write_states2P7states2S0_P7states2S0_
	.globl	_Z22read_and_write_states2P7states2S0_
	.type	_Z22read_and_write_states2P7states2S0_, @function
_Z22read_and_write_states2P7states2S0_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z22read_and_write_states2P7states2S0_P7states2S0_
	.cfi_endproc
.LFE2059:
	.size	_Z22read_and_write_states2P7states2S0_, .-_Z22read_and_write_states2P7states2S0_
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%edi, %edi
	subq	$96, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	testl	%eax, %eax
	je	.L55
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$211, %r8d
	movq	%rax, %r9
	jmp	.L71
.L55:
	leaq	32(%rsp), %rdi
	movl	$125829120, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L56
	call	cudaGetErrorString@PLT
	movl	$216, %r8d
	movq	%rax, %r9
.L71:
	movq	stderr(%rip), %rdi
	leaq	.LC0(%rip), %rcx
	leaq	.LC1(%rip), %rdx
	xorl	%eax, %eax
	movl	$2, %esi
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L56:
	leaq	40(%rsp), %rdi
	movl	$125829120, %esi
	call	cudaMalloc@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L57
	call	cudaGetErrorString@PLT
	movl	$217, %r8d
	movq	%rax, %r9
	jmp	.L71
.L57:
	movabsq	$4294967297, %rax
	leaq	48(%rsp), %rdi
	movl	$1, 84(%rsp)
	movq	%rax, 68(%rsp)
	addq	$61439, %rax
	movq	%rax, 76(%rsp)
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L58
	call	cudaGetErrorString@PLT
	movl	$224, %r8d
	movq	%rax, %r9
	jmp	.L71
.L58:
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L59
	call	cudaGetErrorString@PLT
	movl	$225, %r8d
	movq	%rax, %r9
	jmp	.L71
.L59:
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%ebx, %ebx
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L60
	call	cudaGetErrorString@PLT
	movl	$226, %r8d
	movq	%rax, %r9
	jmp	.L71
.L62:
	movl	72(%rsp), %ecx
	movq	76(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$64, 64(%rsp)
	movl	84(%rsp), %esi
	movq	64(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z52__device_stub__Z22read_and_write_states2P7states2S0_P7states2S0_
.L61:
	incl	%ebx
.L60:
	cmpl	%ebx, nIters(%rip)
	jg	.L62
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L63
	call	cudaGetErrorString@PLT
	movl	$233, %r8d
	movq	%rax, %r9
	jmp	.L71
.L63:
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L64
	call	cudaGetErrorString@PLT
	movl	$234, %r8d
	movq	%rax, %r9
	jmp	.L71
.L64:
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	28(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L65
	call	cudaGetErrorString@PLT
	movl	$236, %r8d
	movq	%rax, %r9
	jmp	.L71
.L65:
	cvtsi2ssl	nIters(%rip), %xmm0
	movss	28(%rsp), %xmm2
	movb	$1, %al
	leaq	.LC5(%rip), %rsi
	movsd	.LC2(%rip), %xmm1
	movl	$2, %edi
	divss	%xmm0, %xmm2
	movsd	.LC4(%rip), %xmm0
	movss	%xmm2, 28(%rsp)
	cvtss2sd	%xmm2, %xmm2
	mulsd	%xmm2, %xmm1
	mulsd	.LC3(%rip), %xmm1
	divsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm1
	movaps	%xmm2, %xmm0
	movss	%xmm1, 12(%rsp)
	call	__printf_chk@PLT
	movss	12(%rsp), %xmm1
	leaq	.LC6(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm1, %xmm0
	call	__printf_chk@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$96, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z22read_and_write_states2P7states2S0_"
.LC8:
	.string	"_Z22read_and_write_states4P7states4S0_"
.LC9:
	.string	"_Z21read_and_write_statesP6statesS0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22read_and_write_states2P7states2S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22read_and_write_states4P7states4S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z21read_and_write_statesP6statesS0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	nIters
	.data
	.align 4
	.type	nIters, @object
	.size	nIters, 4
nIters:
	.long	500
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	-755914244
	.long	1062232653
	.align 8
.LC3:
	.long	0
	.long	1104150528
	.align 8
.LC4:
	.long	0
	.long	1101922304
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// http://forums.nvidia.com/index.php?showtopic=52806&pid=287558&mode=threaded&start=#entry287558


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>

#include <hip/hip_runtime_api.h>


const int num_threads = 64;
const int len = 30720 * 128;//2949120;
const int stride = 16;
int nIters = 500;



#  define CUDA_SAFE_CALL( call) do {					\
	hipError_t err = call;						\
	if( hipSuccess != err) {					\
	    fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
		__FILE__, __LINE__, hipGetErrorString( err) );		\
	    exit(EXIT_FAILURE);						\
	    } } while (0)

#ifdef NDEBUG
#define CUT_CHECK_ERROR(errorMessage)
#else
#  define CUT_CHECK_ERROR(errorMessage) do {				\
	hipDeviceSynchronize();					\
	hipError_t err = hipGetLastError();				\
	if( hipSuccess != err) {					\
	    fprintf(stderr, "Cuda error: %s in file '%s' in line %i : %s.\n", \
		errorMessage, __FILE__, __LINE__, hipGetErrorString( err) ); \
	    exit(EXIT_FAILURE);						\
	    } } while (0)
#endif



// This is a proposed new arrangement: array of structs of arrays of structs
// (ASAS.)
typedef struct {
    float4 abcd[stride];
    float4 efgh[stride];
    } states;
    
__global__ void read_and_write_states(states *y0, states *y1)
    {
    // x-axis threads are contiguous (?)
    const unsigned int modelx = threadIdx.x + blockIdx.x * blockDim.x;
    const unsigned int modely = threadIdx.y + blockIdx.y * blockDim.y;
    float4 abcd = y0[modely].abcd[modelx];
    float4 efgh = y0[modely].efgh[modelx];

    abcd.x = 1.0f * modelx;
    abcd.y = 1.0f * modely;
    efgh.z = -1.0f * modelx;
    efgh.w = -1.0f * modely;

    y1[modely].abcd[modelx] = abcd;
    y1[modely].efgh[modelx] = efgh;
    }


typedef struct {
    float2 ab[stride];
    float2 cd[stride];
    float2 ef[stride];
    float2 gh[stride];
    } states4;
    
__global__ void read_and_write_states4(states4 *y0, states4 *y1)
    {
    // x-axis threads are contiguous (?)
    const unsigned int modelx = threadIdx.x + blockIdx.x * blockDim.x;
    const unsigned int modely = threadIdx.y + blockIdx.y * blockDim.y;
    float2 ab = y0[modely].ab[modelx];
    float2 cd = y0[modely].cd[modelx];
    float2 ef = y0[modely].ef[modelx];
    float2 gh = y0[modely].gh[modelx];

    ab.x = 1.0f * modelx;
    ab.y = 1.0f * modely;
    ef.x = -1.0f * modelx;
    ef.y = -1.0f * modely;

    y1[modely].ab[modelx] = ab;
    y1[modely].cd[modelx] = cd;
    y1[modely].ef[modelx] = ef;
    y1[modely].gh[modelx] = gh;
    }


// This is the way we are arranging device memory currently.
typedef struct {
    float a[len];
    float b[len];
    float c[len];
    float d[len];
    float e[len];
    float f[len];
    float g[len];
    float h[len];
    } states2;

__global__ void read_and_write_states2(states2 *y0, states2 *y1)
    {
    const unsigned int model = threadIdx.x + blockIdx.x * blockDim.x;
    float a = y0->a[model];
    float b = y0->b[model];
    float c = y0->c[model];
    float d = y0->d[model];
    float e = y0->e[model];
    float f = y0->f[model];
    float g = y0->g[model];
    float h = y0->h[model];

    a = 1.0f * model;
    b = 1.0f * model;
    g = -1.0f * model;
    h = -1.0 * model;

    y1->a[model] = a;
    y1->b[model] = b;
    y1->c[model] = c;
    y1->d[model] = d;
    y1->e[model] = e;
    y1->f[model] = f;
    y1->g[model] = g;
    y1->h[model] = h;
    }


int main1()
    {
    CUDA_SAFE_CALL( hipSetDevice(0) );
    int num_models = len;
    float runTime;

    states *d_idata, *d_odata;
    CUDA_SAFE_CALL( hipMalloc((void**)&d_idata, (num_models/stride)*sizeof(states)) );
    CUDA_SAFE_CALL( hipMalloc((void**)&d_odata, (num_models/stride)*sizeof(states)) );


    dim3  threads(stride, num_threads/stride, 1);
    dim3  grid(1, num_models/stride/threads.y, 1);

    hipEvent_t start, end;
    CUDA_SAFE_CALL( hipEventCreate(&start) );
    CUDA_SAFE_CALL( hipEventCreate(&end) );
    CUDA_SAFE_CALL( hipEventRecord(start, 0) );

    for (int i=0; i < nIters; ++i)
	{
	read_and_write_states<<< grid, threads >>>(d_idata, d_odata);
	}

    CUDA_SAFE_CALL( hipEventRecord(end, 0) );
    CUDA_SAFE_CALL( hipEventSynchronize(end) );

    CUDA_SAFE_CALL( hipEventElapsedTime(&runTime, start, end) );

    runTime /= float(nIters);
    float bandwidth = (2 * (num_models/stride)*sizeof(states)) / (runTime * 1.0e-3 * (1<<30));
    printf("Average time:% 13.4f ms\n", runTime);
    printf("Bandwidth:% 16.4f GiB/s\n\n", bandwidth);

    return 0;
    }


int main4()
    {
    CUDA_SAFE_CALL( hipSetDevice(0) );
    int num_models = len;
    float runTime;

    states4 *d_idata, *d_odata;
    CUDA_SAFE_CALL( hipMalloc((void**)&d_idata, (num_models/stride)*sizeof(states4)) );
    CUDA_SAFE_CALL( hipMalloc((void**)&d_odata, (num_models/stride)*sizeof(states4)) );


    dim3  threads(stride, num_threads/stride, 1);
    dim3  grid(1, num_models/stride/threads.y, 1);

    hipEvent_t start, end;
    CUDA_SAFE_CALL( hipEventCreate(&start) );
    CUDA_SAFE_CALL( hipEventCreate(&end) );
    CUDA_SAFE_CALL( hipEventRecord(start, 0) );

    for (int i=0; i < nIters; ++i)
	{
	read_and_write_states4<<< grid, threads >>>(d_idata, d_odata);
	}

    CUDA_SAFE_CALL( hipEventRecord(end, 0) );
    CUDA_SAFE_CALL( hipEventSynchronize(end) );

    CUDA_SAFE_CALL( hipEventElapsedTime(&runTime, start, end) );

    runTime /= float(nIters);
    float bandwidth = (2 * (num_models/stride)*sizeof(states4)) / (runTime * 1.0e-3 * (1<<30));
    printf("Average time:% 13.4f ms\n", runTime);
    printf("Bandwidth:% 16.4f GiB/s\n\n", bandwidth);

    return 0;
    }


int main()
    {
    CUDA_SAFE_CALL( hipSetDevice(0) );
    int num_models = len;
    float runTime;

    states2 *d_idata, *d_odata;
    CUDA_SAFE_CALL( hipMalloc((void**)&d_idata, sizeof(states2)) );
    CUDA_SAFE_CALL( hipMalloc((void**)&d_odata, sizeof(states2)) );


    dim3  threads(num_threads, 1, 1);
    dim3  grid(num_models/threads.x, 1, 1);

    hipEvent_t start, end;
    CUDA_SAFE_CALL( hipEventCreate(&start) );
    CUDA_SAFE_CALL( hipEventCreate(&end) );
    CUDA_SAFE_CALL( hipEventRecord(start, 0) );

    for (int i=0; i < nIters; ++i)
	{
	read_and_write_states2<<< grid, threads >>>(d_idata, d_odata);
	}

    CUDA_SAFE_CALL( hipEventRecord(end, 0) );
    CUDA_SAFE_CALL( hipEventSynchronize(end) );

    CUDA_SAFE_CALL( hipEventElapsedTime(&runTime, start, end) );

    runTime /= float(nIters);
    float bandwidth = (2 * sizeof(states2)) / (runTime * 1.0e-3 * (1<<30));
    printf("Average time:% 13.4f ms\n", runTime);
    printf("Bandwidth:% 16.4f GiB/s\n\n", bandwidth);

    return 0;
    }


	.text
	.file	"bandwidth_test.hip"
	.globl	_Z36__device_stub__read_and_write_statesP6statesS0_ # -- Begin function _Z36__device_stub__read_and_write_statesP6statesS0_
	.type	_Z36__device_stub__read_and_write_statesP6statesS0_,@function
_Z36__device_stub__read_and_write_statesP6statesS0_: # @_Z36__device_stub__read_and_write_statesP6statesS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21read_and_write_statesP6statesS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__read_and_write_statesP6statesS0_, .Lfunc_end0-_Z36__device_stub__read_and_write_statesP6statesS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__read_and_write_states4P7states4S0_ # -- Begin function _Z37__device_stub__read_and_write_states4P7states4S0_
	.type	_Z37__device_stub__read_and_write_states4P7states4S0_,@function
_Z37__device_stub__read_and_write_states4P7states4S0_: # @_Z37__device_stub__read_and_write_states4P7states4S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22read_and_write_states4P7states4S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z37__device_stub__read_and_write_states4P7states4S0_, .Lfunc_end1-_Z37__device_stub__read_and_write_states4P7states4S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__read_and_write_states2P7states2S0_ # -- Begin function _Z37__device_stub__read_and_write_states2P7states2S0_
	.type	_Z37__device_stub__read_and_write_states2P7states2S0_,@function
_Z37__device_stub__read_and_write_states2P7states2S0_: # @_Z37__device_stub__read_and_write_states2P7states2S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22read_and_write_states2P7states2S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z37__device_stub__read_and_write_states2P7states2S0_, .Lfunc_end2-_Z37__device_stub__read_and_write_states2P7states2S0_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z5main1v
.LCPI3_0:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI3_1:
	.quad	0x41d0000000000000              # double 1073741824
.LCPI3_2:
	.quad	0x41ae000000000000              # double 251658240
	.text
	.globl	_Z5main1v
	.type	_Z5main1v,@function
_Z5main1v:                              # @_Z5main1v
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.3:
	leaq	40(%rsp), %rdi
	movl	$125829120, %esi                # imm = 0x7800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.5:
	leaq	32(%rsp), %rdi
	movl	$125829120, %esi                # imm = 0x7800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.7:
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.9:
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.11:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB3_24
# %bb.12:                               # %.preheader
	cmpl	$0, nIters(%rip)
	jle	.LBB3_17
# %bb.13:                               # %.lr.ph.preheader
	xorl	%r15d, %r15d
	movabsq	$263882790666241, %rbx          # imm = 0xF00000000001
	movabsq	$17179869200, %r14              # imm = 0x400000010
.LBB3_14:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_16
# %bb.15:                               #   in Loop: Header=BB3_14 Depth=1
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	callq	_Z36__device_stub__read_and_write_statesP6statesS0_
.LBB3_16:                               #   in Loop: Header=BB3_14 Depth=1
	incl	%r15d
	cmpl	nIters(%rip), %r15d
	jl	.LBB3_14
.LBB3_17:                               # %._crit_edge
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB3_18
# %bb.19:
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	testl	%eax, %eax
	jne	.LBB3_20
# %bb.21:
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	4(%rsp), %rdi
	callq	hipEventElapsedTime
	testl	%eax, %eax
	jne	.LBB3_22
# %bb.23:
	cvtsi2ssl	nIters(%rip), %xmm0
	movss	4(%rsp), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, 4(%rsp)
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movsd	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm0, %xmm1
	mulsd	.LCPI3_1(%rip), %xmm1
	movsd	.LCPI3_2(%rip), %xmm2           # xmm2 = mem[0],zero
	divsd	%xmm1, %xmm2
	xorps	%xmm1, %xmm1
	cvtsd2ss	%xmm2, %xmm1
	movss	%xmm1, 20(%rsp)                 # 4-byte Spill
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	20(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB3_1:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$137, %ecx
	jmp	.LBB3_2
.LBB3_4:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$142, %ecx
	jmp	.LBB3_2
.LBB3_6:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$143, %ecx
	jmp	.LBB3_2
.LBB3_8:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$150, %ecx
	jmp	.LBB3_2
.LBB3_10:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$151, %ecx
	jmp	.LBB3_2
.LBB3_24:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$152, %ecx
	jmp	.LBB3_2
.LBB3_18:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$159, %ecx
	jmp	.LBB3_2
.LBB3_20:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$160, %ecx
	jmp	.LBB3_2
.LBB3_22:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$162, %ecx
.LBB3_2:
	movq	%rax, %r8
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end3:
	.size	_Z5main1v, .Lfunc_end3-_Z5main1v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z5main4v
.LCPI4_0:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI4_1:
	.quad	0x41d0000000000000              # double 1073741824
.LCPI4_2:
	.quad	0x41ae000000000000              # double 251658240
	.text
	.globl	_Z5main4v
	.type	_Z5main4v,@function
_Z5main4v:                              # @_Z5main4v
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB4_1
# %bb.3:
	leaq	40(%rsp), %rdi
	movl	$125829120, %esi                # imm = 0x7800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_4
# %bb.5:
	leaq	32(%rsp), %rdi
	movl	$125829120, %esi                # imm = 0x7800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.7:
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.9:
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.11:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB4_24
# %bb.12:                               # %.preheader
	cmpl	$0, nIters(%rip)
	jle	.LBB4_17
# %bb.13:                               # %.lr.ph.preheader
	xorl	%r15d, %r15d
	movabsq	$263882790666241, %rbx          # imm = 0xF00000000001
	movabsq	$17179869200, %r14              # imm = 0x400000010
.LBB4_14:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_16
# %bb.15:                               #   in Loop: Header=BB4_14 Depth=1
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	callq	_Z37__device_stub__read_and_write_states4P7states4S0_
.LBB4_16:                               #   in Loop: Header=BB4_14 Depth=1
	incl	%r15d
	cmpl	nIters(%rip), %r15d
	jl	.LBB4_14
.LBB4_17:                               # %._crit_edge
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB4_18
# %bb.19:
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	testl	%eax, %eax
	jne	.LBB4_20
# %bb.21:
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	4(%rsp), %rdi
	callq	hipEventElapsedTime
	testl	%eax, %eax
	jne	.LBB4_22
# %bb.23:
	cvtsi2ssl	nIters(%rip), %xmm0
	movss	4(%rsp), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, 4(%rsp)
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movsd	.LCPI4_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm0, %xmm1
	mulsd	.LCPI4_1(%rip), %xmm1
	movsd	.LCPI4_2(%rip), %xmm2           # xmm2 = mem[0],zero
	divsd	%xmm1, %xmm2
	xorps	%xmm1, %xmm1
	cvtsd2ss	%xmm2, %xmm1
	movss	%xmm1, 20(%rsp)                 # 4-byte Spill
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	20(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB4_1:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$175, %ecx
	jmp	.LBB4_2
.LBB4_4:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$180, %ecx
	jmp	.LBB4_2
.LBB4_6:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$181, %ecx
	jmp	.LBB4_2
.LBB4_8:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$188, %ecx
	jmp	.LBB4_2
.LBB4_10:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$189, %ecx
	jmp	.LBB4_2
.LBB4_24:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$190, %ecx
	jmp	.LBB4_2
.LBB4_18:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$197, %ecx
	jmp	.LBB4_2
.LBB4_20:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$198, %ecx
	jmp	.LBB4_2
.LBB4_22:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$200, %ecx
.LBB4_2:
	movq	%rax, %r8
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end4:
	.size	_Z5main4v, .Lfunc_end4-_Z5main4v
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI5_0:
	.quad	0x3f50624dd2f1a9fc              # double 0.001
.LCPI5_1:
	.quad	0x41d0000000000000              # double 1073741824
.LCPI5_2:
	.quad	0x41ae000000000000              # double 251658240
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB5_1
# %bb.3:
	leaq	40(%rsp), %rdi
	movl	$125829120, %esi                # imm = 0x7800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.5:
	leaq	32(%rsp), %rdi
	movl	$125829120, %esi                # imm = 0x7800000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.7:
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB5_8
# %bb.9:
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.11:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB5_24
# %bb.12:                               # %.preheader
	cmpl	$0, nIters(%rip)
	jle	.LBB5_17
# %bb.13:                               # %.lr.ph.preheader
	xorl	%r15d, %r15d
	movabsq	$4294967360, %rbx               # imm = 0x100000040
	leaq	61376(%rbx), %r14
.LBB5_14:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_16
# %bb.15:                               #   in Loop: Header=BB5_14 Depth=1
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	callq	_Z37__device_stub__read_and_write_states2P7states2S0_
.LBB5_16:                               #   in Loop: Header=BB5_14 Depth=1
	incl	%r15d
	cmpl	nIters(%rip), %r15d
	jl	.LBB5_14
.LBB5_17:                               # %._crit_edge
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	testl	%eax, %eax
	jne	.LBB5_18
# %bb.19:
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	testl	%eax, %eax
	jne	.LBB5_20
# %bb.21:
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	4(%rsp), %rdi
	callq	hipEventElapsedTime
	testl	%eax, %eax
	jne	.LBB5_22
# %bb.23:
	cvtsi2ssl	nIters(%rip), %xmm0
	movss	4(%rsp), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	divss	%xmm0, %xmm1
	movss	%xmm1, 4(%rsp)
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm0
	movsd	.LCPI5_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm0, %xmm1
	mulsd	.LCPI5_1(%rip), %xmm1
	movsd	.LCPI5_2(%rip), %xmm2           # xmm2 = mem[0],zero
	divsd	%xmm1, %xmm2
	xorps	%xmm1, %xmm1
	cvtsd2ss	%xmm2, %xmm1
	movss	%xmm1, 20(%rsp)                 # 4-byte Spill
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	20(%rsp), %xmm0                 # 4-byte Folded Reload
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB5_1:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$213, %ecx
	jmp	.LBB5_2
.LBB5_4:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$218, %ecx
	jmp	.LBB5_2
.LBB5_6:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$219, %ecx
	jmp	.LBB5_2
.LBB5_8:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$226, %ecx
	jmp	.LBB5_2
.LBB5_10:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$227, %ecx
	jmp	.LBB5_2
.LBB5_24:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$228, %ecx
	jmp	.LBB5_2
.LBB5_18:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$235, %ecx
	jmp	.LBB5_2
.LBB5_20:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$236, %ecx
	jmp	.LBB5_2
.LBB5_22:
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movq	%rbx, %rdi
	movl	$238, %ecx
.LBB5_2:
	movq	%rax, %r8
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21read_and_write_statesP6statesS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22read_and_write_states4P7states4S0_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22read_and_write_states2P7states2S0_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	nIters,@object                  # @nIters
	.data
	.globl	nIters
	.p2align	2, 0x0
nIters:
	.long	500                             # 0x1f4
	.size	nIters, 4

	.type	_Z21read_and_write_statesP6statesS0_,@object # @_Z21read_and_write_statesP6statesS0_
	.section	.rodata,"a",@progbits
	.globl	_Z21read_and_write_statesP6statesS0_
	.p2align	3, 0x0
_Z21read_and_write_statesP6statesS0_:
	.quad	_Z36__device_stub__read_and_write_statesP6statesS0_
	.size	_Z21read_and_write_statesP6statesS0_, 8

	.type	_Z22read_and_write_states4P7states4S0_,@object # @_Z22read_and_write_states4P7states4S0_
	.globl	_Z22read_and_write_states4P7states4S0_
	.p2align	3, 0x0
_Z22read_and_write_states4P7states4S0_:
	.quad	_Z37__device_stub__read_and_write_states4P7states4S0_
	.size	_Z22read_and_write_states4P7states4S0_, 8

	.type	_Z22read_and_write_states2P7states2S0_,@object # @_Z22read_and_write_states2P7states2S0_
	.globl	_Z22read_and_write_states2P7states2S0_
	.p2align	3, 0x0
_Z22read_and_write_states2P7states2S0_:
	.quad	_Z37__device_stub__read_and_write_states2P7states2S0_
	.size	_Z22read_and_write_states2P7states2S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Cuda error in file '%s' in line %i : %s.\n"
	.size	.L.str, 42

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/joshuaecook/simengine/master/SIMENGINE/branches/McIntyre_gpu/share/cuda/bandwidth_test.hip"
	.size	.L.str.1, 153

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Average time:% 13.4f ms\n"
	.size	.L.str.2, 25

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Bandwidth:% 16.4f GiB/s\n\n"
	.size	.L.str.3, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z21read_and_write_statesP6statesS0_"
	.size	.L__unnamed_1, 37

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z22read_and_write_states4P7states4S0_"
	.size	.L__unnamed_2, 39

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z22read_and_write_states2P7states2S0_"
	.size	.L__unnamed_3, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__read_and_write_statesP6statesS0_
	.addrsig_sym _Z37__device_stub__read_and_write_states4P7states4S0_
	.addrsig_sym _Z37__device_stub__read_and_write_states2P7states2S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21read_and_write_statesP6statesS0_
	.addrsig_sym _Z22read_and_write_states4P7states4S0_
	.addrsig_sym _Z22read_and_write_states2P7states2S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21read_and_write_statesP6statesS0_ ; -- Begin function _Z21read_and_write_statesP6statesS0_
	.globl	_Z21read_and_write_statesP6statesS0_
	.p2align	8
	.type	_Z21read_and_write_statesP6statesS0_,@function
_Z21read_and_write_statesP6statesS0_:   ; @_Z21read_and_write_statesP6statesS0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	v_mad_u64_u32 v[6:7], null, s15, s5, v[1:2]
	v_mov_b32_e32 v7, 0
	v_mad_u64_u32 v[1:2], null, s14, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v2, v7
	v_lshlrev_b64 v[7:8], 9, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 4, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v8, vcc_lo
	v_add_co_u32 v4, vcc_lo, v0, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v2, v10, vcc_lo
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v8, vcc_lo
	s_clause 0x1
	global_load_b64 v[2:3], v[4:5], off offset:8
	global_load_b64 v[4:5], v[4:5], off offset:256
	v_cvt_f32_u32_e32 v0, v1
	v_cvt_f32_u32_e32 v1, v6
	v_add_co_u32 v8, vcc_lo, v7, v9
	v_add_co_ci_u32_e32 v9, vcc_lo, v11, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, 0x80000000, v0
	v_xor_b32_e32 v7, 0x80000000, v1
	s_waitcnt vmcnt(1)
	global_store_b128 v[8:9], v[0:3], off
	s_waitcnt vmcnt(0)
	global_store_b128 v[8:9], v[4:7], off offset:256
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21read_and_write_statesP6statesS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21read_and_write_statesP6statesS0_, .Lfunc_end0-_Z21read_and_write_statesP6statesS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22read_and_write_states4P7states4S0_ ; -- Begin function _Z22read_and_write_states4P7states4S0_
	.globl	_Z22read_and_write_states4P7states4S0_
	.p2align	8
	.type	_Z22read_and_write_states4P7states4S0_,@function
_Z22read_and_write_states4P7states4S0_: ; @_Z22read_and_write_states4P7states4S0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
	v_mov_b32_e32 v3, 0
	v_mad_u64_u32 v[4:5], null, s14, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v5, v3
	v_lshlrev_b64 v[0:1], 9, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[4:5]
	v_add_co_u32 v3, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v7, vcc_lo, v3, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_clause 0x1
	global_load_b64 v[9:10], v[7:8], off offset:128
	global_load_b64 v[7:8], v[7:8], off offset:384
	v_cvt_f32_u32_e32 v3, v4
	v_cvt_f32_u32_e32 v4, v2
	v_add_co_u32 v0, vcc_lo, v0, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, 0x80000000, v3
	v_xor_b32_e32 v6, 0x80000000, v4
	global_store_b64 v[0:1], v[3:4], off
	s_waitcnt vmcnt(1)
	s_clause 0x1
	global_store_b64 v[0:1], v[9:10], off offset:128
	global_store_b64 v[0:1], v[5:6], off offset:256
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[7:8], off offset:384
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22read_and_write_states4P7states4S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z22read_and_write_states4P7states4S0_, .Lfunc_end1-_Z22read_and_write_states4P7states4S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 260
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22read_and_write_states2P7states2S0_ ; -- Begin function _Z22read_and_write_states2P7states2S0_
	.globl	_Z22read_and_write_states2P7states2S0_
	.p2align	8
	.type	_Z22read_and_write_states2P7states2S0_,@function
_Z22read_and_write_states2P7states2S0_: ; @_Z22read_and_write_states2P7states2S0_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_mov_b32_e32 v2, 0
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_cvt_f32_u32_e32 v20, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v21, 0x80000000, v20
	v_add_co_u32 v0, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, 0x1e00000, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v6, vcc_lo, 0x2d00000, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v8, vcc_lo, 0x3c00000, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, 0x4b00000, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_clause 0x3
	global_load_b32 v16, v[4:5], off
	global_load_b32 v17, v[6:7], off
	global_load_b32 v18, v[8:9], off
	global_load_b32 v19, v[10:11], off
	v_add_co_u32 v0, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, 0xf00000, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, 0x1e00000, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, 0x2d00000, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, 0x3c00000, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, 0x4b00000, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, 0x5a00000, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v14, vcc_lo, 0x6900000, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_clause 0x1
	global_store_b32 v[0:1], v20, off
	global_store_b32 v[2:3], v20, off
	s_waitcnt vmcnt(3)
	global_store_b32 v[4:5], v16, off
	s_waitcnt vmcnt(2)
	global_store_b32 v[6:7], v17, off
	s_waitcnt vmcnt(1)
	global_store_b32 v[8:9], v18, off
	s_waitcnt vmcnt(0)
	s_clause 0x2
	global_store_b32 v[10:11], v19, off
	global_store_b32 v[12:13], v21, off
	global_store_b32 v[14:15], v21, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22read_and_write_states2P7states2S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z22read_and_write_states2P7states2S0_, .Lfunc_end2-_Z22read_and_write_states2P7states2S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 420
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21read_and_write_statesP6statesS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21read_and_write_statesP6statesS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22read_and_write_states4P7states4S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22read_and_write_states4P7states4S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22read_and_write_states2P7states2S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22read_and_write_states2P7states2S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
