#define WINSIZE 1
const int nebsize=(WINSIZE*2+1)*(WINSIZE*2+1);

__global__ void loop(double *img, int *row_inds, int *col_inds, double *vals, int w, int h, double epsilon){
    int ind=blockIdx.x*blockDim.x+threadIdx.x;
    if(ind<w*h && ind%h>=WINSIZE && ind%h<h-WINSIZE && ind/h>=WINSIZE && ind/h<w-WINSIZE){
        int win_inds[nebsize];
        double tvals[nebsize*nebsize];
        int k;
        k=0;
        for(int i=-WINSIZE; i<=WINSIZE; i++){
            for(int j=-WINSIZE; j<=WINSIZE; j++){
                win_inds[k]=ind+i*h+j;
                k++;
            }
        }
        double winI[3*nebsize];
        double winI_aux[3*nebsize];
        double pre_win_var[9];
        double win_var[9];
        double win_mu[3];
        double detwin;
        k=0;
        for(int i=-WINSIZE; i<=WINSIZE; i++){
            memcpy(&winI[3*k*(WINSIZE*2+1)],&img[3*(ind+i*h-WINSIZE)], 3*(WINSIZE*2+1)*sizeof(double));
            k++;
        }

        win_mu[0]=0;
        win_mu[1]=0;
        win_mu[2]=0;
        for(int i=0; i<nebsize; i++){
            win_mu[0]+=winI[3*i];
            win_mu[1]+=winI[3*i+1];
            win_mu[2]+=winI[3*i+2];
        }
        win_mu[0]=win_mu[0]/nebsize;
        win_mu[1]=win_mu[1]/nebsize;
        win_mu[2]=win_mu[2]/nebsize;
        for(int i=0; i<3; i++){
            for(int j=0; j<3; j++){
                pre_win_var[3*i+j]=0;
                for(int n=0; n<nebsize; n++){
                    pre_win_var[3*i+j]+=winI[3*n+i]*winI[3*n+j];
                }
                pre_win_var[3*i+j]=pre_win_var[3*i+j]/nebsize;
                pre_win_var[3*i+j]+=(i==j)*epsilon/nebsize-win_mu[j]*win_mu[i];
            }
        }

        //inversa
        detwin=pre_win_var[0]*pre_win_var[4]*pre_win_var[8]+pre_win_var[2]*pre_win_var[3]*pre_win_var[7]+pre_win_var[1]*pre_win_var[5]*pre_win_var[6];
        detwin-=pre_win_var[6]*pre_win_var[4]*pre_win_var[2]+pre_win_var[3]*pre_win_var[1]*pre_win_var[8]+pre_win_var[7]*pre_win_var[5]*pre_win_var[0];

        win_var[0]=(pre_win_var[4]*pre_win_var[8]-pre_win_var[5]*pre_win_var[7])/detwin;
        win_var[3]=-(pre_win_var[3]*pre_win_var[8]-pre_win_var[5]*pre_win_var[6])/detwin;
        win_var[6]=(pre_win_var[3]*pre_win_var[7]-pre_win_var[4]*pre_win_var[6])/detwin;
        win_var[1]=-(pre_win_var[1]*pre_win_var[8]-pre_win_var[2]*pre_win_var[7])/detwin;
        win_var[4]=(pre_win_var[0]*pre_win_var[8]-pre_win_var[2]*pre_win_var[6])/detwin;
        win_var[7]=-(pre_win_var[0]*pre_win_var[7]-pre_win_var[1]*pre_win_var[6])/detwin;
        win_var[2]=(pre_win_var[1]*pre_win_var[5]-pre_win_var[2]*pre_win_var[4])/detwin;
        win_var[5]=-(pre_win_var[0]*pre_win_var[5]-pre_win_var[2]*pre_win_var[3])/detwin;
        win_var[8]=(pre_win_var[0]*pre_win_var[4]-pre_win_var[1]*pre_win_var[3])/detwin;
        //fim da inversa


        for(int i=0; i<nebsize; i++){
                winI[3*i+0]-=win_mu[0];
                winI[3*i+1]-=win_mu[1];
                winI[3*i+2]-=win_mu[2];
        }

        for(int i=0; i<nebsize; i++){
                for(int j=0; j<3; j++){
                    winI_aux[3*i+j]=0;
                    for(int n=0; n<3; n++){
                        winI_aux[3*i+j]+=winI[3*i+n]*win_var[3*n+j];
                    }
                }
        }

        for(int i=0; i<nebsize; i++){
            for(int j=0; j<nebsize; j++){
                tvals[i*nebsize+j]=0;
                for(int n=0; n<3; n++){
                    tvals[i*nebsize+j]+=winI_aux[3*i+n]*winI[3*j+n];
                }
                tvals[i*nebsize+j]++;
                tvals[i*nebsize+j]=(i==j)-tvals[i*nebsize+j]/nebsize;
            }
        }

        k=0;
        int base=((ind/h-WINSIZE)*(h-2*WINSIZE)+(ind%h-WINSIZE))*nebsize*nebsize;
        for(int i=0; i<nebsize; i++){
            for(int j=0; j<nebsize; j++){
                row_inds[base+k]=win_inds[j];
                col_inds[base+k]=win_inds[i];
                k++;
            }
        }

        memcpy(&vals[base],tvals, nebsize*nebsize*sizeof(double));
    }
}

	.file	"tmpxft_003b4725_00000000-6_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z4loopPdPiS0_S_iidPdPiS0_S_iid
	.type	_Z33__device_stub__Z4loopPdPiS0_S_iidPdPiS0_S_iid, @function
_Z33__device_stub__Z4loopPdPiS0_S_iidPdPiS0_S_iid:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movsd	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z4loopPdPiS0_S_iid(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z33__device_stub__Z4loopPdPiS0_S_iidPdPiS0_S_iid, .-_Z33__device_stub__Z4loopPdPiS0_S_iidPdPiS0_S_iid
	.globl	_Z4loopPdPiS0_S_iid
	.type	_Z4loopPdPiS0_S_iid, @function
_Z4loopPdPiS0_S_iid:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z4loopPdPiS0_S_iidPdPiS0_S_iid
	.cfi_endproc
.LFE2033:
	.size	_Z4loopPdPiS0_S_iid, .-_Z4loopPdPiS0_S_iid
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z4loopPdPiS0_S_iid"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z4loopPdPiS0_S_iid(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define WINSIZE 1
const int nebsize=(WINSIZE*2+1)*(WINSIZE*2+1);

__global__ void loop(double *img, int *row_inds, int *col_inds, double *vals, int w, int h, double epsilon){
    int ind=blockIdx.x*blockDim.x+threadIdx.x;
    if(ind<w*h && ind%h>=WINSIZE && ind%h<h-WINSIZE && ind/h>=WINSIZE && ind/h<w-WINSIZE){
        int win_inds[nebsize];
        double tvals[nebsize*nebsize];
        int k;
        k=0;
        for(int i=-WINSIZE; i<=WINSIZE; i++){
            for(int j=-WINSIZE; j<=WINSIZE; j++){
                win_inds[k]=ind+i*h+j;
                k++;
            }
        }
        double winI[3*nebsize];
        double winI_aux[3*nebsize];
        double pre_win_var[9];
        double win_var[9];
        double win_mu[3];
        double detwin;
        k=0;
        for(int i=-WINSIZE; i<=WINSIZE; i++){
            memcpy(&winI[3*k*(WINSIZE*2+1)],&img[3*(ind+i*h-WINSIZE)], 3*(WINSIZE*2+1)*sizeof(double));
            k++;
        }

        win_mu[0]=0;
        win_mu[1]=0;
        win_mu[2]=0;
        for(int i=0; i<nebsize; i++){
            win_mu[0]+=winI[3*i];
            win_mu[1]+=winI[3*i+1];
            win_mu[2]+=winI[3*i+2];
        }
        win_mu[0]=win_mu[0]/nebsize;
        win_mu[1]=win_mu[1]/nebsize;
        win_mu[2]=win_mu[2]/nebsize;
        for(int i=0; i<3; i++){
            for(int j=0; j<3; j++){
                pre_win_var[3*i+j]=0;
                for(int n=0; n<nebsize; n++){
                    pre_win_var[3*i+j]+=winI[3*n+i]*winI[3*n+j];
                }
                pre_win_var[3*i+j]=pre_win_var[3*i+j]/nebsize;
                pre_win_var[3*i+j]+=(i==j)*epsilon/nebsize-win_mu[j]*win_mu[i];
            }
        }

        //inversa
        detwin=pre_win_var[0]*pre_win_var[4]*pre_win_var[8]+pre_win_var[2]*pre_win_var[3]*pre_win_var[7]+pre_win_var[1]*pre_win_var[5]*pre_win_var[6];
        detwin-=pre_win_var[6]*pre_win_var[4]*pre_win_var[2]+pre_win_var[3]*pre_win_var[1]*pre_win_var[8]+pre_win_var[7]*pre_win_var[5]*pre_win_var[0];

        win_var[0]=(pre_win_var[4]*pre_win_var[8]-pre_win_var[5]*pre_win_var[7])/detwin;
        win_var[3]=-(pre_win_var[3]*pre_win_var[8]-pre_win_var[5]*pre_win_var[6])/detwin;
        win_var[6]=(pre_win_var[3]*pre_win_var[7]-pre_win_var[4]*pre_win_var[6])/detwin;
        win_var[1]=-(pre_win_var[1]*pre_win_var[8]-pre_win_var[2]*pre_win_var[7])/detwin;
        win_var[4]=(pre_win_var[0]*pre_win_var[8]-pre_win_var[2]*pre_win_var[6])/detwin;
        win_var[7]=-(pre_win_var[0]*pre_win_var[7]-pre_win_var[1]*pre_win_var[6])/detwin;
        win_var[2]=(pre_win_var[1]*pre_win_var[5]-pre_win_var[2]*pre_win_var[4])/detwin;
        win_var[5]=-(pre_win_var[0]*pre_win_var[5]-pre_win_var[2]*pre_win_var[3])/detwin;
        win_var[8]=(pre_win_var[0]*pre_win_var[4]-pre_win_var[1]*pre_win_var[3])/detwin;
        //fim da inversa


        for(int i=0; i<nebsize; i++){
                winI[3*i+0]-=win_mu[0];
                winI[3*i+1]-=win_mu[1];
                winI[3*i+2]-=win_mu[2];
        }

        for(int i=0; i<nebsize; i++){
                for(int j=0; j<3; j++){
                    winI_aux[3*i+j]=0;
                    for(int n=0; n<3; n++){
                        winI_aux[3*i+j]+=winI[3*i+n]*win_var[3*n+j];
                    }
                }
        }

        for(int i=0; i<nebsize; i++){
            for(int j=0; j<nebsize; j++){
                tvals[i*nebsize+j]=0;
                for(int n=0; n<3; n++){
                    tvals[i*nebsize+j]+=winI_aux[3*i+n]*winI[3*j+n];
                }
                tvals[i*nebsize+j]++;
                tvals[i*nebsize+j]=(i==j)-tvals[i*nebsize+j]/nebsize;
            }
        }

        k=0;
        int base=((ind/h-WINSIZE)*(h-2*WINSIZE)+(ind%h-WINSIZE))*nebsize*nebsize;
        for(int i=0; i<nebsize; i++){
            for(int j=0; j<nebsize; j++){
                row_inds[base+k]=win_inds[j];
                col_inds[base+k]=win_inds[i];
                k++;
            }
        }

        memcpy(&vals[base],tvals, nebsize*nebsize*sizeof(double));
    }
}

	.text
	.file	"kernels.hip"
	.globl	_Z19__device_stub__loopPdPiS0_S_iid # -- Begin function _Z19__device_stub__loopPdPiS0_S_iid
	.type	_Z19__device_stub__loopPdPiS0_S_iid,@function
_Z19__device_stub__loopPdPiS0_S_iid:    # @_Z19__device_stub__loopPdPiS0_S_iid
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	24(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z4loopPdPiS0_S_iid, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z19__device_stub__loopPdPiS0_S_iid, .Lfunc_end0-_Z19__device_stub__loopPdPiS0_S_iid
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z4loopPdPiS0_S_iid, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z4loopPdPiS0_S_iid,@object     # @_Z4loopPdPiS0_S_iid
	.section	.rodata,"a",@progbits
	.globl	_Z4loopPdPiS0_S_iid
	.p2align	3, 0x0
_Z4loopPdPiS0_S_iid:
	.quad	_Z19__device_stub__loopPdPiS0_S_iid
	.size	_Z4loopPdPiS0_S_iid, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z4loopPdPiS0_S_iid"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z19__device_stub__loopPdPiS0_S_iid
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z4loopPdPiS0_S_iid
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z4loopPdPiS0_S_iid     ; -- Begin function _Z4loopPdPiS0_S_iid
	.globl	_Z4loopPdPiS0_S_iid
	.p2align	8
	.type	_Z4loopPdPiS0_S_iid,@function
_Z4loopPdPiS0_S_iid:                    ; @_Z4loopPdPiS0_S_iid
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b64 s[12:13], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[45:46], null, s15, s2, v[0:1]
	s_mul_i32 s2, s13, s12
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v45
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_39
; %bb.1:
	s_ashr_i32 s2, s13, 31
	v_ashrrev_i32_e32 v2, 31, v45
	s_add_i32 s3, s13, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s3, s3, s2
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	v_add_nc_u32_e32 v3, v45, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, v3, v2
	v_xor_b32_e32 v2, s2, v2
	s_add_i32 s2, s13, -1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v3, v0
	v_mul_lo_u32 v1, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v3, v1
	v_add_nc_u32_e32 v3, 1, v0
	v_subrev_nc_u32_e32 v4, s3, v1
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v0, v0, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, 1, v0
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v2
	v_sub_nc_u32_e32 v54, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v53, v54, s13
	v_sub_nc_u32_e32 v52, v45, v53
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, 0, v52
	v_cmp_gt_i32_e64 s2, s2, v52
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_39
; %bb.2:
	s_add_i32 s2, s12, -1
	v_cmp_lt_i32_e32 vcc_lo, 0, v54
	v_cmp_gt_i32_e64 s2, s2, v54
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_39
; %bb.3:
	v_xad_u32 v0, s13, -1, v45
	v_mov_b32_e32 v1, 0
	s_mov_b32 s6, -1
	s_mov_b32 s7, s13
	s_mov_b64 s[2:3], 0
                                        ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44
.LBB0_4:                                ; %.preheader179
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_mov_b64 s[4:5], 0
.LBB0_5:                                ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s4, v0
	s_add_i32 s8, s2, s4
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_mov_b32 m0, s8
	s_cmp_eq_u32 s4, 3
	v_movreld_b32_e32 v36, v2
	s_cbranch_scc0 .LBB0_5
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v0, vcc_lo, v0, s7
	s_add_i32 s6, s6, 1
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_u32 s2, s2, 3
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s6, 2
	s_cbranch_scc0 .LBB0_4
; %bb.7:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_subrev_nc_u32_e32 v2, s13, v45
	s_mul_i32 s12, s13, 3
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v2, 3, -3
.LBB0_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_mul_i32 s2, s14, 0x48
	v_add_nc_u32_e64 v3, 0x2a0, s2
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.LBB0_9:                                ; %.lr.ph.i.i
                                        ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v1, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[2:3], 0x48
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v5, 8, v4
	v_lshrrev_b32_e32 v6, 24, v4
	s_clause 0x3
	scratch_store_b8 v3, v4, off
	scratch_store_b8 v3, v5, off offset:1
	scratch_store_d16_hi_b8 v3, v4, off offset:2
	scratch_store_b8 v3, v6, off offset:3
	v_add_nc_u32_e32 v3, 4, v3
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ; %_ZL6memcpyPvPKvm.exit
                                        ;   in Loop: Header=BB0_8 Depth=1
	v_add_nc_u32_e32 v0, s12, v0
	s_add_i32 s14, s14, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s14, 3
	s_cbranch_scc1 .LBB0_8
; %bb.11:                               ; %.preheader178.preheader
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
.LBB0_12:                               ; %.preheader178
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e64 v6, 0x2a0, s2
	s_add_i32 s3, s2, 0x2a0
	s_add_i32 s2, s2, 24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmpk_eq_i32 s2, 0xd8
	v_add_nc_u32_e32 v10, 16, v6
	s_clause 0x1
	scratch_load_b128 v[6:9], off, s3
	scratch_load_b64 v[10:11], v10, off
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[0:1], v[6:7]
	v_add_f64 v[2:3], v[2:3], v[8:9]
	s_waitcnt vmcnt(0)
	v_add_f64 v[4:5], v[4:5], v[10:11]
	s_cbranch_scc0 .LBB0_12
; %bb.13:
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[6:7], null, 0x40220000, 0x40220000, v[0:1]
	v_div_scale_f64 v[8:9], null, 0x40220000, 0x40220000, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[10:11], null, 0x40220000, 0x40220000, v[4:5]
	v_div_scale_f64 v[24:25], vcc_lo, v[0:1], 0x40220000, v[0:1]
	v_mov_b32_e32 v55, 0x2a0
	s_mov_b32 s4, 0
	v_rcp_f64_e32 v[12:13], v[6:7]
	v_rcp_f64_e32 v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[16:17], v[10:11]
	v_fma_f64 v[18:19], -v[6:7], v[12:13], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
	v_fma_f64 v[22:23], -v[10:11], v[16:17], 1.0
	v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], -v[6:7], v[12:13], 1.0
	v_fma_f64 v[20:21], -v[8:9], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], -v[10:11], v[16:17], 1.0
	v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
	v_div_scale_f64 v[18:19], s2, v[2:3], 0x40220000, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
	v_div_scale_f64 v[20:21], s3, v[4:5], 0x40220000, v[4:5]
	v_fma_f64 v[16:17], v[16:17], v[22:23], v[16:17]
	v_mul_f64 v[22:23], v[24:25], v[12:13]
	v_mul_f64 v[26:27], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[28:29], v[20:21], v[16:17]
	v_fma_f64 v[6:7], -v[6:7], v[22:23], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], -v[8:9], v[26:27], v[18:19]
	v_fma_f64 v[10:11], -v[10:11], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[22:23]
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[26:27]
	s_mov_b32 vcc_lo, s3
	s_load_b64 s[2:3], s[0:1], 0x28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[10:11], v[10:11], v[16:17], v[28:29]
	s_mov_b32 s1, 0
	v_div_fixup_f64 v[32:33], v[6:7], 0x40220000, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f64 v[34:35], v[8:9], 0x40220000, v[2:3]
	v_div_fixup_f64 v[46:47], v[10:11], 0x40220000, v[4:5]
                                        ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
.LBB0_14:                               ; %.preheader177
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
                                        ;       Child Loop BB0_16 Depth 3
	s_cmp_eq_u32 s1, 1
	v_mov_b32_e32 v56, 0x2a0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s1, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v48, v33, v35, vcc_lo
	v_cndmask_b32_e32 v50, v32, v34, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_mul_i32 s12, s1, 3
	s_mov_b32 s14, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v49, v48, v47 :: v_dual_cndmask_b32 v48, v50, v46
.LBB0_15:                               ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_16 Depth 3
	s_add_i32 s5, s14, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s0, s5, 1
	s_lshl_b32 s15, s5, 1
	s_mov_b32 m0, s0
	s_mov_b32 s0, 0
	v_movreld_b32_e32 v0, 0
	v_movreld_b32_e32 v1, 0
.LBB0_16:                               ;   Parent Loop BB0_14 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v50, s0, v55
	v_add_nc_u32_e32 v57, s0, v56
	s_mov_b32 m0, s15
	s_add_i32 s0, s0, 24
	v_movrels_b32_e32 v60, v1
	scratch_load_b64 v[50:51], v50, off
	scratch_load_b64 v[57:58], v57, off
	v_movrels_b32_e32 v59, v0
	s_cmpk_eq_i32 s0, 0xd8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[50:51], v[50:51], v[57:58], v[59:60]
	v_movreld_b32_e32 v0, v50
	s_delay_alu instid0(VALU_DEP_2)
	v_movreld_b32_e32 v1, v51
	s_cbranch_scc0 .LBB0_16
; %bb.17:                               ;   in Loop: Header=BB0_15 Depth=2
	s_cmp_eq_u32 s1, s14
	v_div_scale_f64 v[59:60], null, 0x40220000, 0x40220000, v[50:51]
	s_cselect_b32 s5, 0x3ff00000, 0
	v_div_scale_f64 v[71:72], vcc_lo, v[50:51], 0x40220000, v[50:51]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[57:58], s[4:5], s[2:3]
	s_cmp_eq_u32 s14, 1
	s_mov_b32 m0, s15
	v_add_nc_u32_e32 v56, 8, v56
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[63:64], v[59:60]
	v_div_scale_f64 v[61:62], null, 0x40220000, 0x40220000, v[57:58]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[67:68], -v[59:60], v[63:64], 1.0
	v_rcp_f64_e32 v[65:66], v[61:62]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[63:64], v[63:64], v[67:68], v[63:64]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[69:70], -v[61:62], v[65:66], 1.0
	v_fma_f64 v[67:68], -v[59:60], v[63:64], 1.0
	v_fma_f64 v[65:66], v[65:66], v[69:70], v[65:66]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[63:64], v[63:64], v[67:68], v[63:64]
	v_div_scale_f64 v[67:68], s0, v[57:58], 0x40220000, v[57:58]
	v_fma_f64 v[69:70], -v[61:62], v[65:66], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[65:66], v[65:66], v[69:70], v[65:66]
	v_mul_f64 v[69:70], v[71:72], v[63:64]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[73:74], v[67:68], v[65:66]
	v_fma_f64 v[59:60], -v[59:60], v[69:70], v[71:72]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[61:62], -v[61:62], v[73:74], v[67:68]
	v_div_fmas_f64 v[59:60], v[59:60], v[63:64], v[69:70]
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[61:62], v[61:62], v[65:66], v[73:74]
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s14, 2
	v_div_fixup_f64 v[50:51], v[59:60], 0x40220000, v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[57:58], v[61:62], 0x40220000, v[57:58]
	v_cndmask_b32_e32 v61, v33, v35, vcc_lo
	v_cndmask_b32_e32 v63, v32, v34, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_i32 s14, s14, 1
	v_movreld_b32_e32 v0, v50
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v62, v61, v47 :: v_dual_cndmask_b32 v61, v63, v46
	v_movreld_b32_e32 v1, v51
	s_cmp_eq_u32 s14, 3
	v_fma_f64 v[57:58], -v[48:49], v[61:62], v[57:58]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[57:58], v[57:58], v[50:51]
	v_movreld_b32_e32 v0, v57
	s_delay_alu instid0(VALU_DEP_2)
	v_movreld_b32_e32 v1, v58
	s_cbranch_scc0 .LBB0_15
; %bb.18:                               ;   in Loop: Header=BB0_14 Depth=1
	v_add_nc_u32_e32 v55, 8, v55
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 3
	s_cbranch_scc0 .LBB0_14
; %bb.19:
	s_mov_b32 s0, 0
.LBB0_20:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v18, 0x2a0, s0
	s_add_i32 s1, s0, 0x2a0
	s_add_i32 s0, s0, 24
	s_cmpk_lg_i32 s0, 0xd8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v24, 16, v18
	s_clause 0x1
	scratch_load_b128 v[18:21], off, s1
	scratch_load_b64 v[22:23], v24, off
	s_waitcnt vmcnt(1)
	v_add_f64 v[18:19], v[18:19], -v[32:33]
	v_add_f64 v[20:21], v[20:21], -v[34:35]
	s_waitcnt vmcnt(0)
	v_add_f64 v[22:23], v[22:23], -v[46:47]
	s_clause 0x1
	scratch_store_b128 off, v[18:21], s1
	scratch_store_b64 v24, v[22:23], off
	s_cbranch_scc1 .LBB0_20
; %bb.21:                               ; %.preheader175.preheader
	v_mul_f64 v[28:29], v[4:5], v[6:7]
	v_mul_f64 v[18:19], v[0:1], v[8:9]
	v_mul_f64 v[32:33], v[6:7], v[2:3]
	v_mul_f64 v[22:23], v[2:3], v[10:11]
	v_mul_f64 v[26:27], v[14:15], v[10:11]
	s_mov_b32 s4, 0
	v_mul_f64 v[20:21], v[14:15], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[16:17], v[32:33]
	v_fma_f64 v[18:19], v[16:17], v[18:19], v[20:21]
	v_mul_f64 v[20:21], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[12:13], v[22:23], v[18:19]
	v_fma_f64 v[24:25], v[4:5], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[0:1], v[26:27], v[24:25]
	v_add_f64 v[46:47], v[18:19], -v[24:25]
	v_fma_f64 v[18:19], v[8:9], v[16:17], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[24:25], null, v[46:47], v[46:47], v[18:19]
	v_rcp_f64_e32 v[26:27], v[24:25]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[30:31], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27]
	v_fma_f64 v[30:31], -v[24:25], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27]
	v_div_scale_f64 v[30:31], vcc_lo, v[18:19], v[46:47], v[18:19]
	v_mul_f64 v[34:35], v[30:31], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], -v[24:25], v[34:35], v[30:31]
	v_div_fmas_f64 v[24:25], v[24:25], v[26:27], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[18:19], v[24:25], v[46:47], v[18:19]
	v_mul_f64 v[24:25], v[10:11], v[12:13]
	v_fma_f64 v[24:25], v[6:7], v[16:17], -v[24:25]
	v_fma_f64 v[6:7], v[6:7], v[14:15], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[26:27], null, v[46:47], v[46:47], -v[24:25]
	v_div_scale_f64 v[20:21], null, v[46:47], v[46:47], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[30:31], v[26:27]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[34:35], -v[26:27], v[30:31], 1.0
	v_fma_f64 v[30:31], v[30:31], v[34:35], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[34:35], -v[26:27], v[30:31], 1.0
	v_fma_f64 v[30:31], v[30:31], v[34:35], v[30:31]
	v_div_scale_f64 v[34:35], vcc_lo, -v[24:25], v[46:47], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[48:49], v[34:35], v[30:31]
	v_fma_f64 v[26:27], -v[26:27], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[26:27], v[26:27], v[30:31], v[48:49]
	v_div_fixup_f64 v[24:25], v[26:27], v[46:47], -v[24:25]
	v_rcp_f64_e32 v[26:27], v[20:21]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[30:31], -v[20:21], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27]
	v_fma_f64 v[30:31], -v[20:21], v[26:27], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[26:27], v[30:31], v[26:27]
	v_div_scale_f64 v[30:31], vcc_lo, v[6:7], v[46:47], v[6:7]
	v_mul_f64 v[34:35], v[30:31], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[20:21], v[34:35], v[30:31]
	v_div_fmas_f64 v[20:21], v[20:21], v[26:27], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[30:31], v[20:21], v[46:47], v[6:7]
	v_mul_f64 v[6:7], v[4:5], v[14:15]
	v_fma_f64 v[6:7], v[2:3], v[16:17], -v[6:7]
	v_mul_f64 v[2:3], v[2:3], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[20:21], null, v[46:47], v[46:47], -v[6:7]
	v_fma_f64 v[2:3], v[0:1], v[14:15], -v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[26:27], v[20:21]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[34:35], -v[20:21], v[26:27], 1.0
	v_fma_f64 v[26:27], v[26:27], v[34:35], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[34:35], -v[20:21], v[26:27], 1.0
	v_fma_f64 v[26:27], v[26:27], v[34:35], v[26:27]
	v_div_scale_f64 v[34:35], vcc_lo, -v[6:7], v[46:47], -v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[48:49], v[34:35], v[26:27]
	v_fma_f64 v[20:21], -v[20:21], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[20:21], v[20:21], v[26:27], v[48:49]
	v_div_fixup_f64 v[20:21], v[20:21], v[46:47], -v[6:7]
	v_mul_f64 v[6:7], v[4:5], v[12:13]
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[0:1], v[16:17], -v[6:7]
	v_div_scale_f64 v[16:17], null, v[46:47], v[46:47], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[26:27], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[34:35], -v[16:17], v[26:27], 1.0
	v_fma_f64 v[26:27], v[26:27], v[34:35], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[34:35], -v[16:17], v[26:27], 1.0
	v_fma_f64 v[26:27], v[26:27], v[34:35], v[26:27]
	v_div_scale_f64 v[34:35], vcc_lo, v[6:7], v[46:47], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[48:49], v[34:35], v[26:27]
	v_fma_f64 v[16:17], -v[16:17], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[16:17], v[16:17], v[26:27], v[48:49]
	v_div_fixup_f64 v[26:27], v[16:17], v[46:47], v[6:7]
	v_div_scale_f64 v[6:7], null, v[46:47], v[46:47], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[12:13], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[6:7], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[6:7], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[46:47], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[14:15], v[12:13]
	v_fma_f64 v[6:7], -v[6:7], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[12:13], v[16:17]
	v_div_fixup_f64 v[22:23], v[6:7], v[46:47], v[4:5]
	v_fma_f64 v[4:5], v[0:1], v[10:11], -v[28:29]
	v_fma_f64 v[0:1], v[0:1], v[8:9], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[6:7], null, v[46:47], v[46:47], -v[4:5]
	v_rcp_f64_e32 v[10:11], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_div_scale_f64 v[12:13], vcc_lo, -v[4:5], v[46:47], -v[4:5]
	v_mul_f64 v[14:15], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
	v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[28:29], v[6:7], v[46:47], -v[4:5]
	v_div_scale_f64 v[4:5], null, v[46:47], v[46:47], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[46:47], v[0:1]
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[34:35], v[4:5], v[46:47], v[0:1]
	v_div_scale_f64 v[0:1], null, v[46:47], v[46:47], -v[2:3]
	v_rcp_f64_e32 v[4:5], v[0:1]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[0:1], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_fma_f64 v[6:7], -v[0:1], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_div_scale_f64 v[6:7], vcc_lo, -v[2:3], v[46:47], -v[2:3]
	v_mul_f64 v[8:9], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], -v[0:1], v[8:9], v[6:7]
	v_div_fmas_f64 v[0:1], v[0:1], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[32:33], v[0:1], v[46:47], -v[2:3]
	v_mov_b32_e32 v2, 0x2a0
.LBB0_22:                               ; %.preheader175
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_23 Depth 2
                                        ;       Child Loop BB0_24 Depth 3
	s_mul_i32 s5, s4, 3
	s_mov_b64 s[0:1], 0
.LBB0_23:                               ;   Parent Loop BB0_22 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_24 Depth 3
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, v2
	v_mov_b32_e32 v1, 0
	s_mov_b64 s[2:3], 0
.LBB0_24:                               ;   Parent Loop BB0_22 Depth=1
                                        ;     Parent Loop BB0_23 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	scratch_load_b64 v[4:5], v3, off
	s_add_i32 s12, s0, s2
	v_add_nc_u32_e32 v3, 8, v3
	s_lshl_b32 s12, s12, 1
	s_add_u32 s2, s2, 3
	s_mov_b32 m0, s12
	s_addc_u32 s3, s3, 0
	v_movrels_b32_e32 v7, v19
	v_movrels_b32_e32 v6, v18
	s_cmp_eq_u32 s2, 9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[0:1], v[6:7], v[4:5], v[0:1]
	s_cbranch_scc0 .LBB0_24
; %bb.25:                               ;   in Loop: Header=BB0_23 Depth=2
	s_add_i32 s2, s0, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s2, s2, 3
	s_addk_i32 s2, 0x380
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 3
	scratch_store_b64 off, v[0:1], s2
	s_cbranch_scc0 .LBB0_23
; %bb.26:                               ;   in Loop: Header=BB0_22 Depth=1
	v_add_nc_u32_e32 v2, 24, v2
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s4, 9
	s_cbranch_scc1 .LBB0_22
; %bb.27:                               ; %.preheader173.preheader
	v_mov_b32_e32 v2, 0x380
	s_mov_b32 s0, 0
	s_mov_b32 s2, 0
.LBB0_28:                               ; %.preheader173
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_29 Depth 2
                                        ;       Child Loop BB0_30 Depth 3
	v_mov_b32_e32 v3, 0x2a0
	s_mul_i32 s3, s2, 9
	s_mov_b32 s4, s0
.LBB0_29:                               ;   Parent Loop BB0_28 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_30 Depth 3
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s1, 0
.LBB0_30:                               ;   Parent Loop BB0_28 Depth=1
                                        ;     Parent Loop BB0_29 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s1, v2
	v_add_nc_u32_e32 v6, s1, v3
	s_add_i32 s1, s1, 8
	scratch_load_b64 v[4:5], v4, off
	scratch_load_b64 v[6:7], v6, off
	s_cmp_eq_u32 s1, 24
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[4:5], v[6:7], v[0:1]
	s_cbranch_scc0 .LBB0_30
; %bb.31:                               ;   in Loop: Header=BB0_29 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_f64 v[0:1], v[0:1], 1.0
	s_add_i32 s1, s4, s3
	v_add_nc_u32_e32 v3, 24, v3
	s_lshl_b32 s1, s1, 3
	s_add_i32 s5, s1, 16
	s_cmp_eq_u32 s2, s4
	s_cselect_b32 s1, 0x3ff00000, 0
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s4, 9
	v_div_scale_f64 v[4:5], null, 0xc0220000, 0xc0220000, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[0:1], 0xc0220000, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	v_div_fixup_f64 v[0:1], v[4:5], 0xc0220000, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], s[0:1], v[0:1]
	scratch_store_b64 off, v[0:1], s5
	s_cbranch_scc0 .LBB0_29
; %bb.32:                               ;   in Loop: Header=BB0_28 Depth=1
	v_add_nc_u32_e32 v2, 24, v2
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 9
	s_cbranch_scc0 .LBB0_28
; %bb.33:
	v_add_nc_u32_e32 v0, -1, v54
	s_add_i32 s0, s13, -2
	v_mul_lo_u32 v1, 0x51, v45
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0
	v_mul_lo_u32 v0, v0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, 0x51, v0, v[1:2]
	v_mul_lo_u32 v1, 0x51, v53
	v_sub_nc_u32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v1, 0xffffffaf, v1
.LBB0_34:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_35 Depth 2
	s_mov_b32 m0, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s3, v1
	v_movrels_b32_e32 v2, v36
	s_mov_b64 s[0:1], 0
.LBB0_35:                               ;   Parent Loop BB0_34 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, s0, v3
	s_mov_b32 m0, s0
	s_add_u32 s0, s0, 1
	v_movrels_b32_e32 v8, v36
	s_addc_u32 s1, s1, 0
	v_ashrrev_i32_e32 v5, 31, v4
	s_cmp_eq_u32 s0, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v6, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_store_b32 v[6:7], v8, off
	global_store_b32 v[4:5], v2, off
	s_cbranch_scc0 .LBB0_35
; %bb.36:                               ;   in Loop: Header=BB0_34 Depth=1
	s_add_i32 s2, s2, 1
	s_add_i32 s3, s3, s0
	s_cmp_eq_u32 s2, 9
	s_cbranch_scc0 .LBB0_34
; %bb.37:
	v_add_nc_u32_e32 v2, v52, v0
	s_movk_i32 s0, 0x51
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, v2, s0, 0xffffffffffffffaf
	v_mov_b32_e32 v2, 16
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
.LBB0_38:                               ; %.lr.ph.i.i157
                                        ; =>This Inner Loop Header: Depth=1
	s_clause 0x3
	scratch_load_u8 v3, v2, off offset:1
	scratch_load_u8 v4, v2, off offset:3
	scratch_load_u8 v5, v2, off
	scratch_load_u8 v6, v2, off offset:2
	v_add_nc_u32_e32 v2, 4, v2
	s_waitcnt vmcnt(3)
	v_lshlrev_b16 v3, 8, v3
	s_waitcnt vmcnt(2)
	v_lshlrev_b16 v4, 8, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v5, v5, v3
	s_waitcnt vmcnt(0)
	v_or_b32_e32 v4, v6, v4
	v_add_co_u32 v3, vcc_lo, v0, s0
	s_add_u32 s0, s0, 4
	v_and_b32_e32 v5, 0xffff, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b32_e32 v6, 16, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v1, vcc_lo
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u64 s[0:1], 0x288
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v5, v5, v6
	global_store_b32 v[3:4], v5, off
	s_cbranch_scc1 .LBB0_38
.LBB0_39:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z4loopPdPiS0_S_iid
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 1120
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 75
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z4loopPdPiS0_S_iid, .Lfunc_end0-_Z4loopPdPiS0_S_iid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3860
; NumSgprs: 18
; NumVgprs: 75
; ScratchSize: 1120
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 75
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z4loopPdPiS0_S_iid
    .private_segment_fixed_size: 1120
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z4loopPdPiS0_S_iid.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     75
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
