#include<iostream>
#include<math.h>
#include<cuda_runtime.h>
#include"device_launch_parameters.h" 
#include<fstream>
#define MAX_NUM_LISTS 256

using namespace std;
int num_data = 1000; // the number of the data
int num_lists = 128; // the number of parallel threads

__device__ void radix_sort(float* const data_0, float* const data_1, \
    int num_lists, int num_data, int tid); 
__device__ void merge_list(const float* src_data, float* const dest_list, \
    int num_lists, int num_data, int tid); 
__device__ void preprocess_float(float* const data, int num_lists, int num_data, int tid);
__device__ void Aeprocess_float(float* const data, int num_lists, int num_data, int tid);

__global__ void GPU_radix_sort(float* const src_data, float* const dest_data, \
    int num_lists, int num_data) 
{
    // temp_data:temporarily store the data
    int tid = blockIdx.x*blockDim.x + threadIdx.x;
    // special preprocessing of IEEE floating-point numbers before applying radix sort
    preprocess_float(src_data, num_lists, num_data, tid); 
    __syncthreads();
   // no shared memory
    radix_sort(src_data, dest_data, num_lists, num_data, tid);
    __syncthreads();
    merge_list(src_data, dest_data, num_lists, num_data, tid);    
    __syncthreads();
    Aeprocess_float(dest_data, num_lists, num_data, tid);
    __syncthreads();
}

__device__ void preprocess_float(float* const src_data, int num_lists, int num_data, int tid)
{
    for(int i = tid;i<num_data;i+=num_lists)
    {
        unsigned int *data_temp = (unsigned int *)(&src_data[i]);    
        *data_temp = (*data_temp >> 31 & 0x1)? ~(*data_temp): (*data_temp) | 0x80000000; 
    }
}

__device__ void Aeprocess_float(float* const data, int num_lists, int num_data, int tid)
{
    for(int i = tid;i<num_data;i+=num_lists)
    {
        unsigned int* data_temp = (unsigned int *)(&data[i]);
        *data_temp = (*data_temp >> 31 & 0x1)? (*data_temp) & 0x7fffffff: ~(*data_temp);
    }
}


__device__ void radix_sort(float* const data_0, float* const data_1, \
    int num_lists, int num_data, int tid) 
{
    for(int bit=0;bit<32;bit++)
    {
        int bit_mask = (1 << bit);
        int count_0 = 0;
        int count_1 = 0;
        for(int i=tid; i<num_data;i+=num_lists)
        {
            unsigned int *temp =(unsigned int *) &data_0[i];
            if(*temp & bit_mask)
            {
                data_1[tid+count_1*num_lists] = data_0[i]; //bug 在这里 等于时会做强制类型转化
                count_1 += 1;
            }
            else{
                data_0[tid+count_0*num_lists] = data_0[i];
                count_0 += 1;
            }
        }
        for(int j=0;j<count_1;j++)
        {
            data_0[tid + count_0*num_lists + j*num_lists] = data_1[tid + j*num_lists]; 
        }
    }
}

__device__ void merge_list(const float* src_data, float* const dest_list, \
    int num_lists, int num_data, int tid) 
{
    int num_per_list = ceil((float)num_data/num_lists);
    __shared__ int list_index[MAX_NUM_LISTS];
    __shared__ float record_val[MAX_NUM_LISTS];
    __shared__ int record_tid[MAX_NUM_LISTS];
    list_index[tid] = 0;
    record_val[tid] = 0;
    record_tid[tid] = tid;
    __syncthreads();
    for(int i=0;i<num_data;i++)
    {
        record_val[tid] = 0;
        record_tid[tid] = tid; // bug2 每次都要进行初始化
        if(list_index[tid] < num_per_list)
        {
            int src_index = tid + list_index[tid]*num_lists;
            if(src_index < num_data)
            {
                record_val[tid] = src_data[src_index];
            }else{
                unsigned int *temp = (unsigned int *)&record_val[tid];
                *temp = 0xffffffff;
            }
        }else{
                unsigned int *temp = (unsigned int *)&record_val[tid];
                *temp = 0xffffffff;
        }
        __syncthreads();
        int tid_max = num_lists >> 1;
        while(tid_max != 0 )
        {
            if(tid < tid_max)
            {
                unsigned int* temp1 = (unsigned int*)&record_val[tid];
                unsigned int *temp2 = (unsigned int*)&record_val[tid + tid_max];
                if(*temp2 < *temp1)
                {
                    record_val[tid] = record_val[tid + tid_max];
                    record_tid[tid] = record_tid[tid + tid_max];
                }
            }
            tid_max = tid_max >> 1;
            __syncthreads();
        }
        if(tid == 0)
        {
            list_index[record_tid[0]]++;
            dest_list[i] = record_val[0];
        }
        __syncthreads();
    }
}


int main()
{
    float *data = new float[num_data];
    float  *src_data, *dest_data;
    for(int i =0;i<num_data;i++)
    {
        data[i] = (float)rand()/double(RAND_MAX);
    } 
    ofstream  outfile("./data.bin", ios::out | ios::binary);
    outfile.write((char *)data, sizeof(float)*num_data);
    outfile.close();
    ifstream infile("./data.bin",ios::in | ios::binary);
    infile.read((char *)data, sizeof(float)*num_data);
    cudaMalloc((void**)&src_data, sizeof(float)*num_data);
    cudaMalloc((void**)&dest_data, sizeof(float)*num_data);
    cudaMemcpy(src_data, data, sizeof(float)*num_data, cudaMemcpyHostToDevice);

    GPU_radix_sort<<<1,num_lists>>>(src_data, dest_data, num_lists, num_data);
    cudaMemcpy(data, dest_data, sizeof(float)*num_data, cudaMemcpyDeviceToHost);
    
    for(int i =0;i<num_data;i++)
    {
        cout<<data[i]<<" ";
    }
}

	.file	"tmpxft_0028e3db_00000000-6_radix.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3773:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3773:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z16preprocess_floatPfiii
	.type	_Z16preprocess_floatPfiii, @function
_Z16preprocess_floatPfiii:
.LFB3766:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3766:
	.size	_Z16preprocess_floatPfiii, .-_Z16preprocess_floatPfiii
	.globl	_Z15Aeprocess_floatPfiii
	.type	_Z15Aeprocess_floatPfiii, @function
_Z15Aeprocess_floatPfiii:
.LFB4492:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4492:
	.size	_Z15Aeprocess_floatPfiii, .-_Z15Aeprocess_floatPfiii
	.globl	_Z10radix_sortPfS_iii
	.type	_Z10radix_sortPfS_iii, @function
_Z10radix_sortPfS_iii:
.LFB3768:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3768:
	.size	_Z10radix_sortPfS_iii, .-_Z10radix_sortPfS_iii
	.globl	_Z10merge_listPKfPfiii
	.type	_Z10merge_listPKfPfiii, @function
_Z10merge_listPKfPfiii:
.LFB4490:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4490:
	.size	_Z10merge_listPKfPfiii, .-_Z10merge_listPKfPfiii
	.globl	_Z38__device_stub__Z14GPU_radix_sortPfS_iiPfS_ii
	.type	_Z38__device_stub__Z14GPU_radix_sortPfS_iiPfS_ii, @function
_Z38__device_stub__Z14GPU_radix_sortPfS_iiPfS_ii:
.LFB3795:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14GPU_radix_sortPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3795:
	.size	_Z38__device_stub__Z14GPU_radix_sortPfS_iiPfS_ii, .-_Z38__device_stub__Z14GPU_radix_sortPfS_iiPfS_ii
	.globl	_Z14GPU_radix_sortPfS_ii
	.type	_Z14GPU_radix_sortPfS_ii, @function
_Z14GPU_radix_sortPfS_ii:
.LFB3796:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14GPU_radix_sortPfS_iiPfS_ii
	.cfi_endproc
.LFE3796:
	.size	_Z14GPU_radix_sortPfS_ii, .-_Z14GPU_radix_sortPfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14GPU_radix_sortPfS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3798:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14GPU_radix_sortPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3798:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata.str1.1
.LC2:
	.string	"./data.bin"
.LC3:
	.string	" "
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB3770:
	.cfi_startproc
	.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
	.cfi_lsda 0x1b,.LLSDA3770
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$1088, %rsp
	.cfi_def_cfa_offset 1136
	movslq	num_data(%rip), %rdi
	movq	%fs:40, %rax
	movq	%rax, 1080(%rsp)
	xorl	%eax, %eax
	movabsq	$2305843009213693950, %rax
	cmpq	%rdi, %rax
	jb	.L19
	salq	$2, %rdi
	xorl	%ebp, %ebp
.LEHB0:
	call	_Znam@PLT
	movq	%rax, %rbx
	jmp	.L20
.L19:
	movq	1080(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L34
	call	__cxa_throw_bad_array_new_length@PLT
.L20:
	cmpl	%ebp, num_data(%rip)
	jle	.L37
	call	rand@PLT
	cvtsi2ssl	%eax, %xmm0
	cvtss2sd	%xmm0, %xmm0
	divsd	.LC1(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%rbp,4)
	incq	%rbp
	jmp	.L20
.L37:
	leaq	48(%rsp), %rbp
	leaq	.LC2(%rip), %r13
	movl	$20, %edx
	movq	%r13, %rsi
	movq	%rbp, %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
	movslq	num_data(%rip), %rdx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	salq	$2, %rdx
.LEHB1:
	call	_ZNSo5writeEPKcl@PLT
	movq	%rbp, %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
	leaq	560(%rsp), %r12
	movl	$12, %edx
	movq	%r13, %rsi
	movq	%r12, %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE1:
	movslq	num_data(%rip), %rdx
	movq	%rbx, %rsi
	movq	%r12, %rdi
	salq	$2, %rdx
.LEHB2:
	call	_ZNSi4readEPcl@PLT
	movslq	num_data(%rip), %rsi
	leaq	8(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	num_data(%rip), %rsi
	leaq	16(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	num_data(%rip), %rdx
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	num_lists(%rip), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movq	%rdi, 40(%rsp)
	movl	44(%rsp), %ecx
	movl	%eax, 36(%rsp)
	movq	36(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	movl	num_data(%rip), %ecx
	movq	16(%rsp), %rsi
	testl	%eax, %eax
	jne	.L23
	movl	num_lists(%rip), %edx
	movq	8(%rsp), %rdi
	call	_Z38__device_stub__Z14GPU_radix_sortPfS_iiPfS_ii
.L23:
	movslq	num_data(%rip), %rdx
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	xorl	%r13d, %r13d
	leaq	_ZSt4cout(%rip), %r14
.L24:
	cmpl	%r13d, num_data(%rip)
	jle	.L38
	movq	%r14, %rdi
	cvtss2sd	(%rbx,%r13,4), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	movl	$1, %edx
	leaq	.LC3(%rip), %rsi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.LEHE2:
	incq	%r13
	jmp	.L24
.L38:
	movq	%r12, %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
	movq	%rbp, %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	movq	1080(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	jmp	.L34
.L32:
	endbr64
	movq	%rax, %rbx
.L26:
	movq	%r12, %rdi
	call	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
	jmp	.L27
.L31:
	endbr64
	movq	%rax, %rbx
.L27:
	movq	%rbp, %rdi
	call	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
	movq	1080(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L34
	movq	%rbx, %rdi
.LEHB3:
	call	_Unwind_Resume@PLT
.LEHE3:
.L34:
	call	__stack_chk_fail@PLT
.L29:
	addq	$1088, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3770:
	.globl	__gxx_personality_v0
	.section	.gcc_except_table,"a",@progbits
.LLSDA3770:
	.byte	0xff
	.byte	0xff
	.byte	0x1
	.uleb128 .LLSDACSE3770-.LLSDACSB3770
.LLSDACSB3770:
	.uleb128 .LEHB0-.LFB3770
	.uleb128 .LEHE0-.LEHB0
	.uleb128 0
	.uleb128 0
	.uleb128 .LEHB1-.LFB3770
	.uleb128 .LEHE1-.LEHB1
	.uleb128 .L31-.LFB3770
	.uleb128 0
	.uleb128 .LEHB2-.LFB3770
	.uleb128 .LEHE2-.LEHB2
	.uleb128 .L32-.LFB3770
	.uleb128 0
	.uleb128 .LEHB3-.LFB3770
	.uleb128 .LEHE3-.LEHB3
	.uleb128 0
	.uleb128 0
.LLSDACSE3770:
	.section	.text.startup
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	num_lists
	.data
	.align 4
	.type	num_lists, @object
	.size	num_lists, 4
num_lists:
	.long	128
	.globl	num_data
	.align 4
	.type	num_data, @object
	.size	num_data, 4
num_data:
	.long	1000
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	-4194304
	.long	1105199103
	.hidden	DW.ref.__gxx_personality_v0
	.weak	DW.ref.__gxx_personality_v0
	.section	.data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
	.align 8
	.type	DW.ref.__gxx_personality_v0, @object
	.size	DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
	.quad	__gxx_personality_v0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include<iostream>
#include<math.h>
#include<hip/hip_runtime.h>
 
#include<fstream>
#define MAX_NUM_LISTS 256

using namespace std;
int num_data = 1000; // the number of the data
int num_lists = 128; // the number of parallel threads

__device__ void radix_sort(float* const data_0, float* const data_1, \
    int num_lists, int num_data, int tid); 
__device__ void merge_list(const float* src_data, float* const dest_list, \
    int num_lists, int num_data, int tid); 
__device__ void preprocess_float(float* const data, int num_lists, int num_data, int tid);
__device__ void Aeprocess_float(float* const data, int num_lists, int num_data, int tid);

__global__ void GPU_radix_sort(float* const src_data, float* const dest_data, \
    int num_lists, int num_data) 
{
    // temp_data:temporarily store the data
    int tid = blockIdx.x*blockDim.x + threadIdx.x;
    // special preprocessing of IEEE floating-point numbers before applying radix sort
    preprocess_float(src_data, num_lists, num_data, tid); 
    __syncthreads();
   // no shared memory
    radix_sort(src_data, dest_data, num_lists, num_data, tid);
    __syncthreads();
    merge_list(src_data, dest_data, num_lists, num_data, tid);    
    __syncthreads();
    Aeprocess_float(dest_data, num_lists, num_data, tid);
    __syncthreads();
}

__device__ void preprocess_float(float* const src_data, int num_lists, int num_data, int tid)
{
    for(int i = tid;i<num_data;i+=num_lists)
    {
        unsigned int *data_temp = (unsigned int *)(&src_data[i]);    
        *data_temp = (*data_temp >> 31 & 0x1)? ~(*data_temp): (*data_temp) | 0x80000000; 
    }
}

__device__ void Aeprocess_float(float* const data, int num_lists, int num_data, int tid)
{
    for(int i = tid;i<num_data;i+=num_lists)
    {
        unsigned int* data_temp = (unsigned int *)(&data[i]);
        *data_temp = (*data_temp >> 31 & 0x1)? (*data_temp) & 0x7fffffff: ~(*data_temp);
    }
}


__device__ void radix_sort(float* const data_0, float* const data_1, \
    int num_lists, int num_data, int tid) 
{
    for(int bit=0;bit<32;bit++)
    {
        int bit_mask = (1 << bit);
        int count_0 = 0;
        int count_1 = 0;
        for(int i=tid; i<num_data;i+=num_lists)
        {
            unsigned int *temp =(unsigned int *) &data_0[i];
            if(*temp & bit_mask)
            {
                data_1[tid+count_1*num_lists] = data_0[i]; //bug 在这里 等于时会做强制类型转化
                count_1 += 1;
            }
            else{
                data_0[tid+count_0*num_lists] = data_0[i];
                count_0 += 1;
            }
        }
        for(int j=0;j<count_1;j++)
        {
            data_0[tid + count_0*num_lists + j*num_lists] = data_1[tid + j*num_lists]; 
        }
    }
}

__device__ void merge_list(const float* src_data, float* const dest_list, \
    int num_lists, int num_data, int tid) 
{
    int num_per_list = ceil((float)num_data/num_lists);
    __shared__ int list_index[MAX_NUM_LISTS];
    __shared__ float record_val[MAX_NUM_LISTS];
    __shared__ int record_tid[MAX_NUM_LISTS];
    list_index[tid] = 0;
    record_val[tid] = 0;
    record_tid[tid] = tid;
    __syncthreads();
    for(int i=0;i<num_data;i++)
    {
        record_val[tid] = 0;
        record_tid[tid] = tid; // bug2 每次都要进行初始化
        if(list_index[tid] < num_per_list)
        {
            int src_index = tid + list_index[tid]*num_lists;
            if(src_index < num_data)
            {
                record_val[tid] = src_data[src_index];
            }else{
                unsigned int *temp = (unsigned int *)&record_val[tid];
                *temp = 0xffffffff;
            }
        }else{
                unsigned int *temp = (unsigned int *)&record_val[tid];
                *temp = 0xffffffff;
        }
        __syncthreads();
        int tid_max = num_lists >> 1;
        while(tid_max != 0 )
        {
            if(tid < tid_max)
            {
                unsigned int* temp1 = (unsigned int*)&record_val[tid];
                unsigned int *temp2 = (unsigned int*)&record_val[tid + tid_max];
                if(*temp2 < *temp1)
                {
                    record_val[tid] = record_val[tid + tid_max];
                    record_tid[tid] = record_tid[tid + tid_max];
                }
            }
            tid_max = tid_max >> 1;
            __syncthreads();
        }
        if(tid == 0)
        {
            list_index[record_tid[0]]++;
            dest_list[i] = record_val[0];
        }
        __syncthreads();
    }
}


int main()
{
    float *data = new float[num_data];
    float  *src_data, *dest_data;
    for(int i =0;i<num_data;i++)
    {
        data[i] = (float)rand()/double(RAND_MAX);
    } 
    ofstream  outfile("./data.bin", ios::out | ios::binary);
    outfile.write((char *)data, sizeof(float)*num_data);
    outfile.close();
    ifstream infile("./data.bin",ios::in | ios::binary);
    infile.read((char *)data, sizeof(float)*num_data);
    hipMalloc((void**)&src_data, sizeof(float)*num_data);
    hipMalloc((void**)&dest_data, sizeof(float)*num_data);
    hipMemcpy(src_data, data, sizeof(float)*num_data, hipMemcpyHostToDevice);

    GPU_radix_sort<<<1,num_lists>>>(src_data, dest_data, num_lists, num_data);
    hipMemcpy(data, dest_data, sizeof(float)*num_data, hipMemcpyDeviceToHost);
    
    for(int i =0;i<num_data;i++)
    {
        cout<<data[i]<<" ";
    }
}

	.text
	.file	"radix.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z29__device_stub__GPU_radix_sortPfS_ii # -- Begin function _Z29__device_stub__GPU_radix_sortPfS_ii
	.type	_Z29__device_stub__GPU_radix_sortPfS_ii,@function
_Z29__device_stub__GPU_radix_sortPfS_ii: # @_Z29__device_stub__GPU_radix_sortPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14GPU_radix_sortPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__GPU_radix_sortPfS_ii, .Lfunc_end0-_Z29__device_stub__GPU_radix_sortPfS_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x41dfffffffc00000              # double 2147483647
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
.Lfunc_begin0:
	.cfi_startproc
	.cfi_personality 3, __gxx_personality_v0
	.cfi_lsda 3, .Lexception0
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$1048, %rsp                     # imm = 0x418
	.cfi_def_cfa_offset 1072
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movslq	num_data(%rip), %r14
	leaq	(,%r14,4), %rax
	testq	%r14, %r14
	movq	$-1, %rdi
	cmovnsq	%rax, %rdi
	callq	_Znam
	movq	%rax, %rbx
	testq	%r14, %r14
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%r14d, %r14d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	cvtss2sd	%xmm0, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%r14,4)
	incq	%r14
	movslq	num_data(%rip), %rax
	cmpq	%rax, %r14
	jl	.LBB1_2
.LBB1_3:                                # %._crit_edge
	leaq	16(%rsp), %r14
	movl	$.L.str, %esi
	movq	%r14, %rdi
	movl	$20, %edx
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
	movslq	num_data(%rip), %rdx
	shlq	$2, %rdx
.Ltmp0:
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_ZNSo5writeEPKcl
.Ltmp1:
# %bb.4:
.Ltmp2:
	leaq	16(%rsp), %rdi
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv
.Ltmp3:
# %bb.5:
.Ltmp5:
	leaq	528(%rsp), %rdi
	movl	$.L.str, %esi
	movl	$12, %edx
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp6:
# %bb.6:
	movslq	num_data(%rip), %rdx
	shlq	$2, %rdx
.Ltmp8:
	leaq	528(%rsp), %rdi
	movq	%rbx, %rsi
	callq	_ZNSi4readEPcl
.Ltmp9:
# %bb.7:
	movslq	num_data(%rip), %rsi
	shlq	$2, %rsi
.Ltmp10:
	leaq	8(%rsp), %rdi
	callq	hipMalloc
.Ltmp11:
# %bb.8:
	movslq	num_data(%rip), %rsi
	shlq	$2, %rsi
.Ltmp12:
	movq	%rsp, %rdi
	callq	hipMalloc
.Ltmp13:
# %bb.9:
	movq	8(%rsp), %rdi
	movslq	num_data(%rip), %rdx
	shlq	$2, %rdx
.Ltmp14:
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
.Ltmp15:
# %bb.10:
	movl	num_lists(%rip), %edx
	btsq	$32, %rdx
.Ltmp16:
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
.Ltmp17:
# %bb.11:
	testl	%eax, %eax
	jne	.LBB1_13
# %bb.12:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	num_lists(%rip), %edx
	movl	num_data(%rip), %ecx
.Ltmp18:
	callq	_Z29__device_stub__GPU_radix_sortPfS_ii
.Ltmp19:
.LBB1_13:
	movq	(%rsp), %rsi
	movslq	num_data(%rip), %rdx
	shlq	$2, %rdx
.Ltmp20:
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
.Ltmp21:
# %bb.14:                               # %.preheader
	cmpl	$0, num_data(%rip)
	jle	.LBB1_19
# %bb.15:                               # %.lr.ph29.preheader
	xorl	%r14d, %r14d
.LBB1_16:                               # %.lr.ph29
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r14,4), %xmm0
.Ltmp23:
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
.Ltmp24:
# %bb.17:                               # %_ZNSolsEf.exit
                                        #   in Loop: Header=BB1_16 Depth=1
.Ltmp25:
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp26:
# %bb.18:                               # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
                                        #   in Loop: Header=BB1_16 Depth=1
	incq	%r14
	movslq	num_data(%rip), %rax
	cmpq	%rax, %r14
	jl	.LBB1_16
.LBB1_19:                               # %._crit_edge30
	leaq	528(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
	leaq	24(%rsp), %rdi
	movq	%rax, -8(%rdi)
	movq	_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE+24(%rip), %rcx
	movq	-24(%rax), %rax
	movq	%rcx, 16(%rsp,%rax)
	callq	_ZNSt13basic_filebufIcSt11char_traitsIcEED2Ev
	leaq	264(%rsp), %rdi
	callq	_ZNSt8ios_baseD2Ev
	xorl	%eax, %eax
	addq	$1048, %rsp                     # imm = 0x418
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_20:
	.cfi_def_cfa_offset 1072
.Ltmp7:
	jmp	.LBB1_22
.LBB1_21:
.Ltmp4:
.LBB1_22:
	movq	%rax, %rbx
	jmp	.LBB1_26
.LBB1_23:
.Ltmp22:
	jmp	.LBB1_25
.LBB1_24:
.Ltmp27:
.LBB1_25:
	movq	%rax, %rbx
	leaq	528(%rsp), %rdi
	callq	_ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev
.LBB1_26:
	leaq	16(%rsp), %rdi
	callq	_ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
	movq	%rbx, %rdi
	callq	_Unwind_Resume@PLT
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
	.section	.gcc_except_table,"a",@progbits
	.p2align	2, 0x0
GCC_except_table1:
.Lexception0:
	.byte	255                             # @LPStart Encoding = omit
	.byte	255                             # @TType Encoding = omit
	.byte	1                               # Call site Encoding = uleb128
	.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
	.uleb128 .Lfunc_begin0-.Lfunc_begin0    # >> Call Site 1 <<
	.uleb128 .Ltmp0-.Lfunc_begin0           #   Call between .Lfunc_begin0 and .Ltmp0
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp0-.Lfunc_begin0           # >> Call Site 2 <<
	.uleb128 .Ltmp3-.Ltmp0                  #   Call between .Ltmp0 and .Ltmp3
	.uleb128 .Ltmp4-.Lfunc_begin0           #     jumps to .Ltmp4
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp5-.Lfunc_begin0           # >> Call Site 3 <<
	.uleb128 .Ltmp6-.Ltmp5                  #   Call between .Ltmp5 and .Ltmp6
	.uleb128 .Ltmp7-.Lfunc_begin0           #     jumps to .Ltmp7
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp8-.Lfunc_begin0           # >> Call Site 4 <<
	.uleb128 .Ltmp21-.Ltmp8                 #   Call between .Ltmp8 and .Ltmp21
	.uleb128 .Ltmp22-.Lfunc_begin0          #     jumps to .Ltmp22
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp23-.Lfunc_begin0          # >> Call Site 5 <<
	.uleb128 .Ltmp26-.Ltmp23                #   Call between .Ltmp23 and .Ltmp26
	.uleb128 .Ltmp27-.Lfunc_begin0          #     jumps to .Ltmp27
	.byte	0                               #   On action: cleanup
	.uleb128 .Ltmp26-.Lfunc_begin0          # >> Call Site 6 <<
	.uleb128 .Lfunc_end1-.Ltmp26            #   Call between .Ltmp26 and .Lfunc_end1
	.byte	0                               #     has no landing pad
	.byte	0                               #   On action: cleanup
.Lcst_end0:
	.p2align	2, 0x0
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14GPU_radix_sortPfS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	num_data,@object                # @num_data
	.data
	.globl	num_data
	.p2align	2, 0x0
num_data:
	.long	1000                            # 0x3e8
	.size	num_data, 4

	.type	num_lists,@object               # @num_lists
	.globl	num_lists
	.p2align	2, 0x0
num_lists:
	.long	128                             # 0x80
	.size	num_lists, 4

	.type	_Z14GPU_radix_sortPfS_ii,@object # @_Z14GPU_radix_sortPfS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z14GPU_radix_sortPfS_ii
	.p2align	3, 0x0
_Z14GPU_radix_sortPfS_ii:
	.quad	_Z29__device_stub__GPU_radix_sortPfS_ii
	.size	_Z14GPU_radix_sortPfS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"./data.bin"
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14GPU_radix_sortPfS_ii"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__GPU_radix_sortPfS_ii
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Unwind_Resume
	.addrsig_sym _Z14GPU_radix_sortPfS_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14GPU_radix_sortPfS_ii ; -- Begin function _Z14GPU_radix_sortPfS_ii
	.globl	_Z14GPU_radix_sortPfS_ii
	.p2align	8
	.type	_Z14GPU_radix_sortPfS_ii,@function
_Z14GPU_radix_sortPfS_ii:               ; @_Z14GPU_radix_sortPfS_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	v_cmp_gt_i32_e64 s0, s3, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2)
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph.i.preheader
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_mov_b32_e32 v0, v1
	s_ashr_i32 s9, s2, 31
	s_mov_b32 s8, s2
	s_mov_b32 s11, 0
	s_lshl_b64 s[8:9], s[8:9], 2
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_2:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[3:4], off
	s_waitcnt vmcnt(0)
	v_not_b32_e32 v6, v5
	v_or_b32_e32 v7, 0x80000000, v5
	v_cmp_gt_i32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v5, v7, v6 :: v_dual_add_nc_u32 v0, s2, v0
	v_cmp_le_i32_e32 vcc_lo, s3, v0
	global_store_b32 v[3:4], v5, off
	v_add_co_u32 v3, s1, v3, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v4, s1, s9, v4, s1
	s_or_b32 s11, vcc_lo, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_2
.LBB0_3:                                ; %Flow62
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_ashr_i32 s9, s2, 31
	s_mov_b32 s8, s2
	s_mov_b32 s10, 0
	s_lshl_b64 s[8:9], s[8:9], 2
	s_waitcnt_vscnt null, 0x0
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_barrier
	buffer_gl0_inv
.LBB0_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;     Child Loop BB0_14 Depth 2
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v8, 0
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_12
; %bb.5:                                ; %.lr.ph.i19.preheader
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v7, v5
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v9, v1
	v_mov_b32_e32 v8, 0
	s_lshl_b32 s13, 1, s10
	s_mov_b32 s12, 0
.LBB0_6:                                ; %.lr.ph.i19
                                        ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v10, v[6:7], off
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v11, s13, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v11
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=2
	v_mad_u64_u32 v[11:12], null, v0, s2, v[1:2]
	v_add_nc_u32_e32 v0, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_store_b32 v[11:12], v10, off
                                        ; implicit-def: $vgpr10
.LBB0_8:                                ; %Flow58
                                        ;   in Loop: Header=BB0_6 Depth=2
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=2
	v_mad_u64_u32 v[11:12], null, v8, s2, v[1:2]
	v_add_nc_u32_e32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s4, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
	global_store_b32 v[11:12], v10, off
.LBB0_10:                               ;   in Loop: Header=BB0_6 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v9, s2, v9
	v_add_co_u32 v6, s1, v6, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s1, s9, v7, s1
	v_cmp_le_i32_e32 vcc_lo, s3, v9
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_6
; %bb.11:                               ; %Flow59
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_12:                               ; %Flow60
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s11, exec_lo
	v_cmpx_lt_i32_e32 0, v0
	s_cbranch_execz .LBB0_15
; %bb.13:                               ; %.lr.ph48.i
                                        ;   in Loop: Header=BB0_4 Depth=1
	v_mul_lo_u32 v8, v8, s2
	v_mov_b32_e32 v6, v1
	s_mov_b32 s12, 0
.LBB0_14:                               ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v6
	v_add_nc_u32_e32 v0, -1, v0
	v_lshlrev_b64 v[9:10], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	global_load_b32 v7, v[9:10], off
	v_add_nc_u32_e32 v9, v8, v6
	v_add_nc_u32_e32 v6, s2, v6
	s_or_b32 s12, vcc_lo, s12
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	v_add_co_u32 v9, s1, s4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s1, s5, v10, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v[9:10], v7, off
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_14
.LBB0_15:                               ; %Flow57
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_add_i32 s10, s10, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, 32
	s_cbranch_scc0 .LBB0_4
; %bb.16:                               ; %_Z10radix_sortPfS_iii.exit
	v_cvt_f32_i32_e32 v4, s3
	v_cvt_f32_i32_e32 v5, s2
	v_mov_b32_e32 v6, 0
	s_cmp_lt_i32 s3, 1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	v_div_scale_f32 v7, null, v5, v5, v4
	v_div_scale_f32 v9, vcc_lo, v4, v5, v4
	buffer_gl0_inv
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v0, -v7, v8, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v0, v8
	v_mul_f32_e32 v10, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, -v7, v10, v9
	v_fmac_f32_e32 v10, v0, v8
	v_lshlrev_b32_e32 v0, 2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v7, -v7, v10, v9
	ds_store_b32 v0, v6 offset:2048
	ds_store_2addr_stride64_b32 v0, v6, v1 offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_div_fmas_f32 v7, v7, v8, v10
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_30
; %bb.17:                               ; %.lr.ph55.i
	v_div_fixup_f32 v4, v7, v5, v4
	v_add_nc_u32_e32 v7, 0x800, v0
	v_add_nc_u32_e32 v8, 0x400, v0
	v_cmp_eq_u32_e64 s1, 0, v1
	s_cmp_gt_u32 s2, 1
	v_ceil_f32_e32 v4, v4
	s_mov_b32 s11, 0
	s_cselect_b32 s12, -1, 0
	s_mov_b32 s10, s11
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_i32_f32_e32 v9, v4
.LBB0_18:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_23 Depth 2
	ds_load_b32 v10, v0
	v_mov_b32_e32 v5, -1
	s_mov_b32 s13, exec_lo
	ds_store_b32 v8, v1
	s_waitcnt lgkmcnt(1)
	v_cmpx_lt_i32_e64 v10, v9
	s_cbranch_execz .LBB0_22
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=1
	v_mad_u64_u32 v[4:5], null, v10, s2, v[1:2]
	v_mov_b32_e32 v5, -1
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e64 s3, v4
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_18 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
.LBB0_21:                               ; %Flow53
                                        ;   in Loop: Header=BB0_18 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_22:                               ;   in Loop: Header=BB0_18 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s13
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_mov_b32 s13, s2
	s_waitcnt vmcnt(0)
	ds_store_b32 v7, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_27
.LBB0_23:                               ; %.lr.ph.i20
                                        ;   Parent Loop BB0_18 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ashr_i32 s13, s13, 1
	s_mov_b32 s14, exec_lo
	v_cmpx_gt_i32_e64 s13, v1
	s_cbranch_execz .LBB0_26
; %bb.24:                               ;   in Loop: Header=BB0_23 Depth=2
	v_lshl_add_u32 v4, s13, 2, v7
	ds_load_b32 v4, v4
	ds_load_b32 v5, v7
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v4, v5
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_23 Depth=2
	v_lshl_add_u32 v5, s13, 2, v8
	ds_load_b32 v5, v5
	ds_store_b32 v7, v4
	s_waitcnt lgkmcnt(1)
	ds_store_b32 v8, v5
.LBB0_26:                               ;   in Loop: Header=BB0_23 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_cmp_gt_u32 s13, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_23
.LBB0_27:                               ; %._crit_edge.i22
                                        ;   in Loop: Header=BB0_18 Depth=1
	s_and_saveexec_b32 s13, s1
	s_cbranch_execz .LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_18 Depth=1
	ds_load_2addr_stride64_b32 v[4:5], v6 offset0:4 offset1:8
	s_lshl_b64 s[14:15], s[10:11], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s14, s6, s14
	s_addc_u32 s15, s7, s15
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v4, 2, v4
	global_store_b32 v6, v5, s[14:15]
	ds_load_b32 v10, v4
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, 1, v10
	ds_store_b32 v4, v10
.LBB0_29:                               ;   in Loop: Header=BB0_18 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s10, s10, 1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_cmp_lg_u32 s10, s3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_18
.LBB0_30:                               ; %_Z10merge_listPKfPfiii.exit
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_33
; %bb.31:                               ; %.lr.ph.i25.preheader
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s4, 0
.LBB0_32:                               ; %.lr.ph.i25
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0x7fffffff, v0
	v_not_b32_e32 v5, v0
	v_cmp_gt_i32_e32 vcc_lo, 0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v5, v4 :: v_dual_add_nc_u32 v1, s2, v1
	v_cmp_le_i32_e32 vcc_lo, s3, v1
	global_store_b32 v[2:3], v0, off
	v_add_co_u32 v2, s0, v2, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_or_b32 s4, vcc_lo, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_32
.LBB0_33:                               ; %Flow49
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14GPU_radix_sortPfS_ii
		.amdhsa_group_segment_fixed_size 3072
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14GPU_radix_sortPfS_ii, .Lfunc_end0-_Z14GPU_radix_sortPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1436
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 3072 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 3072
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14GPU_radix_sortPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14GPU_radix_sortPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
