/**
 * Copyright 1993-2014 NVIDIA Corporation.  All rights reserved.
 *
 * Please refer to the NVIDIA end user license agreement (EULA) associated
 * with this source code for terms and conditions that govern your use of
 * this software. Any use, reproduction, disclosure, or distribution of
 * this software and related documentation outside the terms of the EULA
 * is strictly prohibited.
 *
 */

/**
 * Matrix multiplication: C = A * B.
 * Host code.
 *
 * This sample implements matrix multiplication as described in Chapter 3
 * of the programming guide.
 * It has been written for clarity of exposition to illustrate various CUDA
 * programming principles, not with the goal of providing the most
 * performant generic kernel for matrix multiplication.
 *
 * See also:
 * V. Volkov and J. Demmel, "Benchmarking GPUs to tune dense linear algebra,"
 * in Proc. 2008 ACM/IEEE Conf. on Supercomputing (SC '08),
 * Piscataway, NJ: IEEE Press, 2008, pp. Art. 31:1-11.
 */

// System includes
#include <stdio.h>
#include <assert.h>

// CUDA runtime
#include <cuda_runtime.h>

// Helper functions and utilities to work with CUDA
//#include <helper_functions.h>

#define TOTAL_SHARED 25600
#define BLOCK_SIZE_WIDTH 16
#define EXTRA_SHARED_MEM_USAGE ((TOTAL_SHARED - BLOCK_SIZE_WIDTH*BLOCK_SIZE_WIDTH*8) / 4)

// assuming all gpus are the same
float occupancyCalc(const void* func, int block_size) {
	struct cudaFuncAttributes attr;
	cudaError_t error;
	error = cudaFuncGetAttributes(&attr, func);
	if (error != cudaSuccess)
		printf("cudaFuncGetAttributes returned error code %d, line(%d)\n", error, __LINE__);

	cudaSetDevice(0);
	cudaDeviceProp deviceProp;
	error = cudaGetDeviceProperties(&deviceProp, 0);
	if (error != cudaSuccess)
		printf("cudaGetDeviceProperties returned error code %d, line(%d)\n", error, __LINE__);

	/* prepare some configuration variables */
	int maxWarpsPerSM = deviceProp.maxThreadsPerMultiProcessor / deviceProp.warpSize;
	//printf("max warps per sm: %d\n", maxWarpsPerSM);
	/* variable starting by b means related to block size */
	//printf("block_size: %d\n", block_size);
	int b_warpsPerBlock = block_size / deviceProp.warpSize + ((block_size % deviceProp.warpSize > 0) ? 1 : 0);
	//printf("warps per block: %d, block_size/deviceProp.warpSize: %d\n", b_warpsPerBlock, block_size/deviceProp.warpSize);
	int b_blocksPerSM = maxWarpsPerSM / b_warpsPerBlock;

	/* variable starting by r means related to register file */
	int r_warpsPerBlock = b_warpsPerBlock;
	if (attr.numRegs > deviceProp.regsPerBlock) {
		printf("Register usage is larger than %d limit per block.", deviceProp.regsPerBlock);
		return 0;
	}

	int r_warpsPerSM = deviceProp.regsPerMultiprocessor / (deviceProp.warpSize * attr.numRegs);
	int r_blocksPerSM = r_warpsPerSM / r_warpsPerBlock;

	/* variable starting by s means related to shared memory */
	int s_blocksPerSM = deviceProp.sharedMemPerMultiprocessor / attr.sharedSizeBytes;

	int numBlocks = (b_blocksPerSM < r_blocksPerSM) ? b_blocksPerSM : r_blocksPerSM;
	numBlocks = (numBlocks < s_blocksPerSM) ? numBlocks : s_blocksPerSM;

	//printf("b: %d, r: %d, s: %d\n", b_blocksPerSM, r_blocksPerSM, s_blocksPerSM);
	int numWarps = numBlocks * b_warpsPerBlock;
	printf("%d,%d,%d,%d,", attr.numRegs, attr.sharedSizeBytes, numBlocks, numWarps);
	float occupancy = (float)numWarps / maxWarpsPerSM;

	return occupancy;
}

/**
 * Matrix multiplication (CUDA Kernel) on the device: C = A * B
 * wA is A's width and wB is B's width
 */
#define BLOCK_SIZE 32
extern "C" __global__ void
matrixMulCUDA(float *C, float *A, float *B, int wA, int wB)
{
	// Block index
	int bx = blockIdx.x;
	int by = blockIdx.y;

	// Thread index
	int tx = threadIdx.x;
	int ty = threadIdx.y;

	// Index of the first sub-matrix of A processed by the block
	int aBegin = wA * BLOCK_SIZE * by;

	// Index of the last sub-matrix of A processed by the block
	int aEnd   = aBegin + wA - 1;

	// Step size used to iterate through the sub-matrices of A
	int aStep  = BLOCK_SIZE;

	// Index of the first sub-matrix of B processed by the block
	int bBegin = BLOCK_SIZE * bx;

	// Step size used to iterate through the sub-matrices of B
	int bStep  = BLOCK_SIZE * wB;

	// Csub is used to store the element of the block sub-matrix
	// that is computed by the thread
	float Csub = 0;

	// Loop over all the sub-matrices of A and B
	// required to compute the block sub-matrix
	for (int a = aBegin, b = bBegin;
	     a <= aEnd;
	     a += aStep, b += bStep)
	{

		// Declaration of the shared memory array As used to
		// store the sub-matrix of A
		__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];

		// Declaration of the shared memory array Bs used to
		// store the sub-matrix of B
		__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];

		// Load the matrices from device memory
		// to shared memory; each thread loads
		// one element of each matrix
		As[ty][tx] = A[a + wA * ty + tx];
		Bs[ty][tx] = B[b + wB * ty + tx];

		// Synchronize to make sure the matrices are loaded
		__syncthreads();

		// Multiply the two matrices together;
		// each thread computes one element
		// of the block sub-matrix
#pragma unroll

		for (int k = 0; k < BLOCK_SIZE; ++k)
		{
			Csub += As[ty][k] * Bs[k][tx];
		}

		// Synchronize to make sure that the preceding
		// computation is done before loading two new
		// sub-matrices of A and B in the next iteration
		__syncthreads();
	}

	// Write the block sub-matrix to device memory;
	// each thread writes one element
	int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
	C[c + wB * ty + tx] = Csub;
}

	.file	"tmpxft_00298db0_00000000-6_matrixMul.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"cudaFuncGetAttributes returned error code %d, line(%d)\n"
.LC2:
	.string	"cudaGetDeviceProperties returned error code %d, line(%d)\n"
.LC3:
	.string	"Register usage is larger than %d limit per block."
.LC4:
	.string	"%d,%d,%d,%d,"
	.text
	.globl	_Z13occupancyCalcPKvi
	.type	_Z13occupancyCalcPKvi, @function
_Z13occupancyCalcPKvi:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%esi, %ebp
	movq	%rdi, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$1208, %rsp
	.cfi_def_cfa_offset 1232
	movq	%fs:40, %rax
	movq	%rax, 1192(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rax, %rdi
	call	cudaFuncGetAttributes@PLT
	testl	%eax, %eax
	je	.L3
	movl	%eax, %edx
	movl	$48, %ecx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
.L3:
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	leaq	160(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaGetDeviceProperties_v2@PLT
	movl	%eax, %edx
	testl	%eax, %eax
	je	.L4
	movl	$54, %ecx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L4:
	movl	44(%rsp), %edi
	movl	464(%rsp), %edx
	movl	784(%rsp), %eax
	movl	468(%rsp), %esi
	cmpl	%edx, %edi
	jle	.L5
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorps	%xmm0, %xmm0
	jmp	.L2
.L5:
	cltd
	xorl	%r9d, %r9d
	movq	16(%rsp), %rcx
	idivl	%esi
	movl	%eax, %ebx
	movl	%ebp, %eax
	cltd
	idivl	%esi
	testl	%edx, %edx
	setg	%r9b
	imull	%edi, %esi
	addl	%eax, %r9d
	movl	808(%rsp), %eax
	cltd
	idivl	%esi
	leaq	.LC4(%rip), %rsi
	cltd
	idivl	%r9d
	movl	%eax, %r8d
	movl	%ebx, %eax
	cltd
	idivl	%r9d
	cmpl	%eax, %r8d
	cmovg	%eax, %r8d
	movq	800(%rsp), %rax
	xorl	%edx, %edx
	divq	%rcx
	movl	%edi, %edx
	movl	$2, %edi
	cmpl	%eax, %r8d
	cmovg	%eax, %r8d
	xorl	%eax, %eax
	imull	%r8d, %r9d
	movl	%r9d, 12(%rsp)
	call	__printf_chk@PLT
	movl	12(%rsp), %r9d
	cvtsi2ssl	%ebx, %xmm1
	cvtsi2ssl	%r9d, %xmm0
	divss	%xmm1, %xmm0
.L2:
	movq	1192(%rsp), %rax
	subq	%fs:40, %rax
	je	.L7
	call	__stack_chk_fail@PLT
.L7:
	addq	$1208, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z13occupancyCalcPKvi, .-_Z13occupancyCalcPKvi
	.globl	_Z39__device_stub__Z13matrixMulCUDAPfS_S_iiPfS_S_ii
	.type	_Z39__device_stub__Z13matrixMulCUDAPfS_S_iiPfS_S_ii, @function
_Z39__device_stub__Z13matrixMulCUDAPfS_S_iiPfS_S_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	matrixMulCUDA(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L16:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z39__device_stub__Z13matrixMulCUDAPfS_S_iiPfS_S_ii, .-_Z39__device_stub__Z13matrixMulCUDAPfS_S_iiPfS_S_ii
	.globl	matrixMulCUDA
	.type	matrixMulCUDA, @function
matrixMulCUDA:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z13matrixMulCUDAPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2053:
	.size	matrixMulCUDA, .-matrixMulCUDA
	.section	.rodata.str1.1
.LC5:
	.string	"matrixMulCUDA"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	matrixMulCUDA(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/**
 * Copyright 1993-2014 NVIDIA Corporation.  All rights reserved.
 *
 * Please refer to the NVIDIA end user license agreement (EULA) associated
 * with this source code for terms and conditions that govern your use of
 * this software. Any use, reproduction, disclosure, or distribution of
 * this software and related documentation outside the terms of the EULA
 * is strictly prohibited.
 *
 */

/**
 * Matrix multiplication: C = A * B.
 * Host code.
 *
 * This sample implements matrix multiplication as described in Chapter 3
 * of the programming guide.
 * It has been written for clarity of exposition to illustrate various CUDA
 * programming principles, not with the goal of providing the most
 * performant generic kernel for matrix multiplication.
 *
 * See also:
 * V. Volkov and J. Demmel, "Benchmarking GPUs to tune dense linear algebra,"
 * in Proc. 2008 ACM/IEEE Conf. on Supercomputing (SC '08),
 * Piscataway, NJ: IEEE Press, 2008, pp. Art. 31:1-11.
 */

// System includes
#include <stdio.h>
#include <assert.h>

// CUDA runtime
#include <hip/hip_runtime.h>

// Helper functions and utilities to work with CUDA
//#include <helper_functions.h>

#define TOTAL_SHARED 25600
#define BLOCK_SIZE_WIDTH 16
#define EXTRA_SHARED_MEM_USAGE ((TOTAL_SHARED - BLOCK_SIZE_WIDTH*BLOCK_SIZE_WIDTH*8) / 4)

// assuming all gpus are the same
float occupancyCalc(const void* func, int block_size) {
	struct hipFuncAttributes attr;
	hipError_t error;
	error = hipFuncGetAttributes(&attr, reinterpret_cast<const void*>(func));
	if (error != hipSuccess)
		printf("hipFuncGetAttributes returned error code %d, line(%d)\n", error, __LINE__);

	hipSetDevice(0);
	hipDeviceProp_t deviceProp;
	error = hipGetDeviceProperties(&deviceProp, 0);
	if (error != hipSuccess)
		printf("hipGetDeviceProperties returned error code %d, line(%d)\n", error, __LINE__);

	/* prepare some configuration variables */
	int maxWarpsPerSM = deviceProp.maxThreadsPerMultiProcessor / deviceProp.warpSize;
	//printf("max warps per sm: %d\n", maxWarpsPerSM);
	/* variable starting by b means related to block size */
	//printf("block_size: %d\n", block_size);
	int b_warpsPerBlock = block_size / deviceProp.warpSize + ((block_size % deviceProp.warpSize > 0) ? 1 : 0);
	//printf("warps per block: %d, block_size/deviceProp.warpSize: %d\n", b_warpsPerBlock, block_size/deviceProp.warpSize);
	int b_blocksPerSM = maxWarpsPerSM / b_warpsPerBlock;

	/* variable starting by r means related to register file */
	int r_warpsPerBlock = b_warpsPerBlock;
	if (attr.numRegs > deviceProp.regsPerBlock) {
		printf("Register usage is larger than %d limit per block.", deviceProp.regsPerBlock);
		return 0;
	}

	int r_warpsPerSM = deviceProp.regsPerMultiprocessor / (deviceProp.warpSize * attr.numRegs);
	int r_blocksPerSM = r_warpsPerSM / r_warpsPerBlock;

	/* variable starting by s means related to shared memory */
	int s_blocksPerSM = deviceProp.sharedMemPerMultiprocessor / attr.sharedSizeBytes;

	int numBlocks = (b_blocksPerSM < r_blocksPerSM) ? b_blocksPerSM : r_blocksPerSM;
	numBlocks = (numBlocks < s_blocksPerSM) ? numBlocks : s_blocksPerSM;

	//printf("b: %d, r: %d, s: %d\n", b_blocksPerSM, r_blocksPerSM, s_blocksPerSM);
	int numWarps = numBlocks * b_warpsPerBlock;
	printf("%d,%d,%d,%d,", attr.numRegs, attr.sharedSizeBytes, numBlocks, numWarps);
	float occupancy = (float)numWarps / maxWarpsPerSM;

	return occupancy;
}

/**
 * Matrix multiplication (CUDA Kernel) on the device: C = A * B
 * wA is A's width and wB is B's width
 */
#define BLOCK_SIZE 32
extern "C" __global__ void
matrixMulCUDA(float *C, float *A, float *B, int wA, int wB)
{
	// Block index
	int bx = blockIdx.x;
	int by = blockIdx.y;

	// Thread index
	int tx = threadIdx.x;
	int ty = threadIdx.y;

	// Index of the first sub-matrix of A processed by the block
	int aBegin = wA * BLOCK_SIZE * by;

	// Index of the last sub-matrix of A processed by the block
	int aEnd   = aBegin + wA - 1;

	// Step size used to iterate through the sub-matrices of A
	int aStep  = BLOCK_SIZE;

	// Index of the first sub-matrix of B processed by the block
	int bBegin = BLOCK_SIZE * bx;

	// Step size used to iterate through the sub-matrices of B
	int bStep  = BLOCK_SIZE * wB;

	// Csub is used to store the element of the block sub-matrix
	// that is computed by the thread
	float Csub = 0;

	// Loop over all the sub-matrices of A and B
	// required to compute the block sub-matrix
	for (int a = aBegin, b = bBegin;
	     a <= aEnd;
	     a += aStep, b += bStep)
	{

		// Declaration of the shared memory array As used to
		// store the sub-matrix of A
		__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];

		// Declaration of the shared memory array Bs used to
		// store the sub-matrix of B
		__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];

		// Load the matrices from device memory
		// to shared memory; each thread loads
		// one element of each matrix
		As[ty][tx] = A[a + wA * ty + tx];
		Bs[ty][tx] = B[b + wB * ty + tx];

		// Synchronize to make sure the matrices are loaded
		__syncthreads();

		// Multiply the two matrices together;
		// each thread computes one element
		// of the block sub-matrix
#pragma unroll

		for (int k = 0; k < BLOCK_SIZE; ++k)
		{
			Csub += As[ty][k] * Bs[k][tx];
		}

		// Synchronize to make sure that the preceding
		// computation is done before loading two new
		// sub-matrices of A and B in the next iteration
		__syncthreads();
	}

	// Write the block sub-matrix to device memory;
	// each thread writes one element
	int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
	C[c + wB * ty + tx] = Csub;
}

	.text
	.file	"matrixMul.hip"
	.globl	_Z13occupancyCalcPKvi           # -- Begin function _Z13occupancyCalcPKvi
	.type	_Z13occupancyCalcPKvi,@function
_Z13occupancyCalcPKvi:                  # @_Z13occupancyCalcPKvi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$1528, %rsp                     # imm = 0x5F8
	.cfi_def_cfa_offset 1552
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rsi
	movq	%rsp, %rdi
	callq	hipFuncGetAttributes
	testl	%eax, %eax
	je	.LBB0_2
# %bb.1:
	movl	$.L.str, %edi
	movl	%eax, %esi
	movl	$48, %edx
	xorl	%eax, %eax
	callq	printf
.LBB0_2:
	xorl	%edi, %edi
	callq	hipSetDevice
	leaq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	testl	%eax, %eax
	je	.LBB0_4
# %bb.3:
	movl	$.L.str.1, %edi
	movl	%eax, %esi
	movl	$54, %edx
	xorl	%eax, %eax
	callq	printf
.LBB0_4:
	movl	32(%rsp), %esi
	movl	360(%rsp), %eax
	cmpl	%eax, %esi
	jle	.LBB0_6
# %bb.5:
	movl	$.L.str.2, %edi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	printf
	xorps	%xmm0, %xmm0
	jmp	.LBB0_7
.LBB0_6:
	movl	364(%rsp), %edi
	movl	680(%rsp), %eax
	cltd
	idivl	%edi
	movl	%eax, %ebx
	movl	%ebp, %eax
	cltd
	idivl	%edi
	xorl	%ebp, %ebp
	testl	%edx, %edx
	setg	%bpl
	addl	%eax, %ebp
	movl	%ebx, %eax
	cltd
	idivl	%ebp
	movl	%eax, %ecx
	movl	704(%rsp), %eax
	imull	%esi, %edi
	cltd
	idivl	%edi
	cltd
	idivl	%ebp
	movl	%eax, %r8d
	movq	696(%rsp), %rax
	movq	48(%rsp), %r9
	xorl	%edx, %edx
	divq	%r9
	cmpl	%r8d, %ecx
	cmovll	%ecx, %r8d
	cmpl	%eax, %r8d
	cmovgel	%eax, %r8d
	imull	%r8d, %ebp
	movl	$.L.str.3, %edi
	movq	%r9, %rdx
	movl	%r8d, %ecx
	movl	%ebp, %r8d
	xorl	%eax, %eax
	callq	printf
	cvtsi2ss	%ebp, %xmm0
	cvtsi2ss	%ebx, %xmm1
	divss	%xmm1, %xmm0
.LBB0_7:
	addq	$1528, %rsp                     # imm = 0x5F8
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z13occupancyCalcPKvi, .Lfunc_end0-_Z13occupancyCalcPKvi
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__matrixMulCUDA    # -- Begin function __device_stub__matrixMulCUDA
	.type	__device_stub__matrixMulCUDA,@function
__device_stub__matrixMulCUDA:           # @__device_stub__matrixMulCUDA
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$matrixMulCUDA, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__matrixMulCUDA, .Lfunc_end1-__device_stub__matrixMulCUDA
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$matrixMulCUDA, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"hipFuncGetAttributes returned error code %d, line(%d)\n"
	.size	.L.str, 55

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"hipGetDeviceProperties returned error code %d, line(%d)\n"
	.size	.L.str.1, 57

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Register usage is larger than %d limit per block."
	.size	.L.str.2, 50

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%d,%d,%d,%d,"
	.size	.L.str.3, 13

	.type	matrixMulCUDA,@object           # @matrixMulCUDA
	.section	.rodata,"a",@progbits
	.globl	matrixMulCUDA
	.p2align	3, 0x0
matrixMulCUDA:
	.quad	__device_stub__matrixMulCUDA
	.size	matrixMulCUDA, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"matrixMulCUDA"
	.size	.L__unnamed_1, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__matrixMulCUDA
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym matrixMulCUDA
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	matrixMulCUDA           ; -- Begin function matrixMulCUDA
	.globl	matrixMulCUDA
	.p2align	8
	.type	matrixMulCUDA,@function
matrixMulCUDA:                          ; @matrixMulCUDA
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v5, v2, s7
	s_cmp_gt_i32 s6, 0
	s_cbranch_scc1 .LBB0_2
; %bb.1:                                ; %.._crit_edge_crit_edge
	v_mul_lo_u32 v1, v2, s7
	s_mov_b32 s10, 0
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s9, -1
                                        ; implicit-def: $sgpr10
                                        ; implicit-def: $vgpr1
.LBB0_3:                                ; %Flow132
	v_and_b32_e32 v0, 0x3ff, v0
	s_lshl_b32 s8, s14, 5
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_lshl_b32 s7, s7, 5
	s_cbranch_vccnz .LBB0_7
; %bb.4:                                ; %.lr.ph
	v_dual_mov_b32 v6, 0 :: v_dual_lshlrev_b32 v3, 2, v0
	v_lshlrev_b32_e32 v7, 7, v2
	v_add3_u32 v1, v0, v5, s8
	v_lshl_add_u32 v2, s15, 5, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_or_b32_e32 v8, 0x1000, v3
	s_mul_i32 s9, s6, s15
	v_add_nc_u32_e32 v9, v7, v3
	s_lshl_b32 s9, s9, 5
	v_mad_u64_u32 v[3:4], null, s6, v2, v[0:1]
	v_add_nc_u32_e32 v10, v8, v7
	v_add_nc_u32_e32 v11, 0x400, v8
	v_add_nc_u32_e32 v12, 0x800, v8
	v_add_nc_u32_e32 v13, 0xc00, v8
	s_add_i32 s6, s9, s6
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s9, s9, 32
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_ge_i32 s9, s6
	v_lshlrev_b64 v[14:15], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[16:17], 2, v[1:2]
	v_add_nc_u32_e32 v1, s7, v1
	v_add_nc_u32_e32 v3, 32, v3
	v_add_co_u32 v14, vcc_lo, s2, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v15, vcc_lo
	v_add_co_u32 v16, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v17, vcc_lo
	global_load_b32 v2, v[14:15], off
	global_load_b32 v4, v[16:17], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v9, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b32 v[22:23], v8 offset1:32
	ds_load_b128 v[14:17], v7
	ds_load_2addr_b32 v[24:25], v8 offset0:64 offset1:96
	ds_load_b128 v[18:21], v7 offset:16
	ds_load_2addr_b32 v[26:27], v8 offset0:128 offset1:160
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v14, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v15, v23
	ds_load_2addr_b32 v[22:23], v8 offset0:192 offset1:224
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v16, v24
	v_fmac_f32_e32 v6, v17, v25
	ds_load_2addr_b32 v[24:25], v11 offset1:32
	ds_load_b128 v[14:17], v7 offset:32
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v18, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v19, v27
	ds_load_2addr_b32 v[26:27], v11 offset0:64 offset1:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v20, v22
	v_fmac_f32_e32 v6, v21, v23
	ds_load_b128 v[18:21], v7 offset:48
	ds_load_2addr_b32 v[22:23], v11 offset0:128 offset1:160
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v14, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v15, v25
	ds_load_2addr_b32 v[24:25], v11 offset0:192 offset1:224
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v16, v26
	v_fmac_f32_e32 v6, v17, v27
	ds_load_2addr_b32 v[26:27], v12 offset1:32
	ds_load_b128 v[14:17], v7 offset:64
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v18, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v19, v23
	ds_load_2addr_b32 v[22:23], v12 offset0:64 offset1:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v20, v24
	v_fmac_f32_e32 v6, v21, v25
	ds_load_b128 v[18:21], v7 offset:80
	ds_load_2addr_b32 v[24:25], v12 offset0:128 offset1:160
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v14, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v15, v27
	ds_load_2addr_b32 v[26:27], v12 offset0:192 offset1:224
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v16, v22
	v_fmac_f32_e32 v6, v17, v23
	ds_load_2addr_b32 v[22:23], v13 offset1:32
	ds_load_b128 v[14:17], v7 offset:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v18, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v19, v25
	ds_load_2addr_b32 v[24:25], v13 offset0:64 offset1:96
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v20, v26
	v_fmac_f32_e32 v6, v21, v27
	ds_load_b128 v[18:21], v7 offset:112
	ds_load_2addr_b32 v[26:27], v13 offset0:128 offset1:160
	s_waitcnt lgkmcnt(3)
	v_fmac_f32_e32 v6, v14, v22
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, v15, v23
	ds_load_2addr_b32 v[14:15], v13 offset0:192 offset1:224
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v6, v16, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v17, v25
	v_fmac_f32_e32 v6, v18, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v19, v27
	v_fmac_f32_e32 v6, v20, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v6, v21, v15
	s_cbranch_scc0 .LBB0_5
; %bb.6:                                ; %Flow
	v_mov_b32_e32 v1, v5
	s_branch .LBB0_8
.LBB0_7:
	v_mov_b32_e32 v6, s10
.LBB0_8:                                ; %Flow133
	v_add_nc_u32_e32 v0, s8, v0
	s_mul_i32 s7, s7, s15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, v0, v1, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v6, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel matrixMulCUDA
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 28
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	matrixMulCUDA, .Lfunc_end0-matrixMulCUDA
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 824
; NumSgprs: 18
; NumVgprs: 28
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 28
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           matrixMulCUDA
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         matrixMulCUDA.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     28
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
