#include "distance_transformation_gpu.cuh"

__global__ void distTransformation_GPU (int scheme,
			unsigned char *raw_vol,
		       	float sp2_0, float sp2_1, float sp2_2,	
			int height, int width, int depth, 
			double *ed_out)
{
	int size_of_vol = height * width * depth;

	int slice_stride = height * width;

	int tid = threadIdx.x + blockDim.x * blockIdx.x;

	while (tid < size_of_vol)
	{
		int cfv = int(ed_out[tid]); 

		// Coordinates of CFV
		int cfv_k = cfv / slice_stride;
		int cfv_i = cfv % slice_stride / width;
               	int cfv_j = cfv % slice_stride % width;	
	
		// Coordinates of me
		int k = tid / slice_stride;
		int i = tid % slice_stride / width;
		int j = tid % slice_stride % width;

		// Am myself the CFV?
		bool is_cfv = (tid == cfv) ? 1 : 0;

		// Distance translation
		if (scheme == 0)
		{
			// center-to-center
			ed_out[tid] = calcDist_GPU( sp2_0, sp2_1, sp2_2,
                                                i, j, k,
                                                cfv_i, cfv_j, cfv_k);
		}
		else if (scheme == 1)
		{
			// center-to-face
			ed_out[tid] = distToClosetFacePointOfCFV_GPU(
					 	is_cfv,
                                                sp2_0, sp2_1, sp2_2,
                                                i, j, k,
                                                cfv_i, cfv_j, cfv_k,
                                                raw_vol[cfv]);
		}	

		tid += blockDim.x * gridDim.x;
	}	
}

__device__ double distToClosetFacePointOfCFV_GPU(
				bool is_cfv,
				float sp2_0, float sp2_1, float sp2_2,
				int i, int j, int k,
				int cfv_i, int cfv_j, int cfv_k,
		       		unsigned char cfv_val)
{
	
	double closet_dist = (is_cfv == 1) ? 0.0 : DBL_MAX;

	double calculated_dists[6];

	// Negative i face
	calculated_dists[0] = (isKthBitSet_GPU(cfv_val, 1) == 0) ? DBL_MAX :
					distToFacePoint_I_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j-0.5, (double)cfv_k);
	
	// Negative j face
	calculated_dists[1] = (isKthBitSet_GPU(cfv_val, 2) == 0) ? DBL_MAX :
					distToFacePoint_J_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i-0.5, (double)cfv_j, (double)cfv_k);
	
	// Negative k face
	calculated_dists[2] = (isKthBitSet_GPU(cfv_val, 3) == 0) ? DBL_MAX :
					distToFacePoint_K_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j, (double)cfv_k-0.5);
	
	// Positive i face
	calculated_dists[3] = (isKthBitSet_GPU(cfv_val, 4) == 0) ? DBL_MAX :
					distToFacePoint_I_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j+0.5, (double)cfv_k);

	// Positive j face
	calculated_dists[4] = (isKthBitSet_GPU(cfv_val, 5) == 0) ? DBL_MAX :
					distToFacePoint_J_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i+0.5, (double)cfv_j, (double)cfv_k);

	// Positive k face
	calculated_dists[5] = (isKthBitSet_GPU(cfv_val, 6) == 0) ? DBL_MAX :
					distToFacePoint_K_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j, (double)cfv_k+0.5);
	
	for (int i = 0; i < 6; i++)
	{
		if (calculated_dists[i] < closet_dist)
		{
			closet_dist = calculated_dists[i];
		}
	}

	
	return closet_dist;
}

__device__ double distToFacePoint_I_GPU(
			float sp2_0, float sp2_1, float sp2_2,
                        double i, double j, double k,
                        double cfv_i, double cfv_j, double cfv_k)
{	
	double dist = DBL_MAX;

	double temp_i = cfv_i - 0.5;

	int add_i;
	for (add_i = 0; add_i < 3; add_i++)
	{
			
		double temp_k = cfv_k - 0.5;

		int add_k;
		for (add_k = 0; add_k < 3; add_k++)
		{
			double temp_dist = calcDist_GPU(
						sp2_0, sp2_1, sp2_2,
						i, j, k,
						temp_i + 0.5 * add_i,
						cfv_j,
						temp_k + 0.5 * add_k);
			if(temp_dist < dist)
			{
				dist = temp_dist;
			}
		}
	}

	return dist;
}

__device__ double distToFacePoint_J_GPU(
			float sp2_0, float sp2_1, float sp2_2,
                        double i, double j, double k,
                        double cfv_i, double cfv_j, double cfv_k)
{
	double dist = DBL_MAX;

	double temp_j = cfv_j - 0.5;

	int add_j;
	for (add_j = 0; add_j < 3; add_j++)
	{
		double temp_k = cfv_k - 0.5;

		int add_k;
		for (add_k = 0; add_k < 3; add_k++)
		{
			double temp_dist = calcDist_GPU(
						sp2_0, sp2_1, sp2_2,
						i, j, k,
						cfv_i,
						temp_j + 0.5 * add_j,
						temp_k + 0.5 * add_k);
				
			if(temp_dist < dist)
			{
				dist = temp_dist;
			}

		}
	}
	
	return dist;
}

__device__ double distToFacePoint_K_GPU(
			float sp2_0, float sp2_1, float sp2_2,
                        double i, double j, double k,
                        double cfv_i, double cfv_j, double cfv_k)
{
	double dist = DBL_MAX;

	double temp_i = cfv_i - 0.5;

	int add_i;
	for (add_i = 0; add_i < 3; add_i++)
	{
			
		double temp_j = cfv_j - 0.5;

		int add_j;
		for (add_j = 0; add_j < 3; add_j++)
		{
			double temp_dist = calcDist_GPU(
						sp2_0, sp2_1, sp2_2,
						i, j, k,
						temp_i + 0.5 * add_i,
						temp_j + 0.5 * add_j,
						cfv_k);
				
			if(temp_dist < dist)
			{
				dist = temp_dist;
			}
		}
	}

	return dist;
}

__device__ double calcDist_GPU(float sp2_0, float sp2_1, float sp2_2,
		double i, double j, double k,
		double target_i, double target_j, double target_k)
{
	double result = (i - target_i) * (i - target_i) * sp2_0 +
			(j - target_j) * (j - target_j) * sp2_1 +
			(k - target_k) * (k - target_k) * sp2_2;

	return sqrt(result);
}

__device__ bool isKthBitSet_GPU(int n, int k)
{
    if (n & (1 << (k - 1)))
        return 1;
    else
        return 0;
}


	.file	"tmpxft_002f6ec7_00000000-6_distance_transformation_gpu.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2016:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2016:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30distToClosetFacePointOfCFV_GPUbfffiiiiiih
	.type	_Z30distToClosetFacePointOfCFV_GPUbfffiiiiiih, @function
_Z30distToClosetFacePointOfCFV_GPUbfffiiiiiih:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z30distToClosetFacePointOfCFV_GPUbfffiiiiiih, .-_Z30distToClosetFacePointOfCFV_GPUbfffiiiiiih
	.globl	_Z21distToFacePoint_I_GPUfffdddddd
	.type	_Z21distToFacePoint_I_GPUfffdddddd, @function
_Z21distToFacePoint_I_GPUfffdddddd:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z21distToFacePoint_I_GPUfffdddddd, .-_Z21distToFacePoint_I_GPUfffdddddd
	.globl	_Z21distToFacePoint_J_GPUfffdddddd
	.type	_Z21distToFacePoint_J_GPUfffdddddd, @function
_Z21distToFacePoint_J_GPUfffdddddd:
.LFB2158:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2158:
	.size	_Z21distToFacePoint_J_GPUfffdddddd, .-_Z21distToFacePoint_J_GPUfffdddddd
	.globl	_Z21distToFacePoint_K_GPUfffdddddd
	.type	_Z21distToFacePoint_K_GPUfffdddddd, @function
_Z21distToFacePoint_K_GPUfffdddddd:
.LFB2160:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2160:
	.size	_Z21distToFacePoint_K_GPUfffdddddd, .-_Z21distToFacePoint_K_GPUfffdddddd
	.globl	_Z12calcDist_GPUfffdddddd
	.type	_Z12calcDist_GPUfffdddddd, @function
_Z12calcDist_GPUfffdddddd:
.LFB2162:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2162:
	.size	_Z12calcDist_GPUfffdddddd, .-_Z12calcDist_GPUfffdddddd
	.globl	_Z15isKthBitSet_GPUii
	.type	_Z15isKthBitSet_GPUii, @function
_Z15isKthBitSet_GPUii:
.LFB2013:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2013:
	.size	_Z15isKthBitSet_GPUii, .-_Z15isKthBitSet_GPUii
	.globl	_Z51__device_stub__Z22distTransformation_GPUiPhfffiiiPdiPhfffiiiPd
	.type	_Z51__device_stub__Z22distTransformation_GPUiPhfffiiiPdiPhfffiiiPd, @function
_Z51__device_stub__Z22distTransformation_GPUiPhfffiiiPdiPhfffiiiPd:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%r9, (%rsp)
	movss	%xmm0, 40(%rsp)
	movss	%xmm1, 28(%rsp)
	movss	%xmm2, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	%rsp, %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z22distTransformation_GPUiPhfffiiiPd(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L14:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z51__device_stub__Z22distTransformation_GPUiPhfffiiiPdiPhfffiiiPd, .-_Z51__device_stub__Z22distTransformation_GPUiPhfffiiiPdiPhfffiiiPd
	.globl	_Z22distTransformation_GPUiPhfffiiiPd
	.type	_Z22distTransformation_GPUiPhfffiiiPd, @function
_Z22distTransformation_GPUiPhfffiiiPd:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z22distTransformation_GPUiPhfffiiiPdiPhfffiiiPd
	.cfi_endproc
.LFE2039:
	.size	_Z22distTransformation_GPUiPhfffiiiPd, .-_Z22distTransformation_GPUiPhfffiiiPd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z22distTransformation_GPUiPhfffiiiPd"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z22distTransformation_GPUiPhfffiiiPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2041:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "distance_transformation_gpu.cuh"

__global__ void distTransformation_GPU (int scheme,
			unsigned char *raw_vol,
		       	float sp2_0, float sp2_1, float sp2_2,	
			int height, int width, int depth, 
			double *ed_out)
{
	int size_of_vol = height * width * depth;

	int slice_stride = height * width;

	int tid = threadIdx.x + blockDim.x * blockIdx.x;

	while (tid < size_of_vol)
	{
		int cfv = int(ed_out[tid]); 

		// Coordinates of CFV
		int cfv_k = cfv / slice_stride;
		int cfv_i = cfv % slice_stride / width;
               	int cfv_j = cfv % slice_stride % width;	
	
		// Coordinates of me
		int k = tid / slice_stride;
		int i = tid % slice_stride / width;
		int j = tid % slice_stride % width;

		// Am myself the CFV?
		bool is_cfv = (tid == cfv) ? 1 : 0;

		// Distance translation
		if (scheme == 0)
		{
			// center-to-center
			ed_out[tid] = calcDist_GPU( sp2_0, sp2_1, sp2_2,
                                                i, j, k,
                                                cfv_i, cfv_j, cfv_k);
		}
		else if (scheme == 1)
		{
			// center-to-face
			ed_out[tid] = distToClosetFacePointOfCFV_GPU(
					 	is_cfv,
                                                sp2_0, sp2_1, sp2_2,
                                                i, j, k,
                                                cfv_i, cfv_j, cfv_k,
                                                raw_vol[cfv]);
		}	

		tid += blockDim.x * gridDim.x;
	}	
}

__device__ double distToClosetFacePointOfCFV_GPU(
				bool is_cfv,
				float sp2_0, float sp2_1, float sp2_2,
				int i, int j, int k,
				int cfv_i, int cfv_j, int cfv_k,
		       		unsigned char cfv_val)
{
	
	double closet_dist = (is_cfv == 1) ? 0.0 : DBL_MAX;

	double calculated_dists[6];

	// Negative i face
	calculated_dists[0] = (isKthBitSet_GPU(cfv_val, 1) == 0) ? DBL_MAX :
					distToFacePoint_I_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j-0.5, (double)cfv_k);
	
	// Negative j face
	calculated_dists[1] = (isKthBitSet_GPU(cfv_val, 2) == 0) ? DBL_MAX :
					distToFacePoint_J_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i-0.5, (double)cfv_j, (double)cfv_k);
	
	// Negative k face
	calculated_dists[2] = (isKthBitSet_GPU(cfv_val, 3) == 0) ? DBL_MAX :
					distToFacePoint_K_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j, (double)cfv_k-0.5);
	
	// Positive i face
	calculated_dists[3] = (isKthBitSet_GPU(cfv_val, 4) == 0) ? DBL_MAX :
					distToFacePoint_I_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j+0.5, (double)cfv_k);

	// Positive j face
	calculated_dists[4] = (isKthBitSet_GPU(cfv_val, 5) == 0) ? DBL_MAX :
					distToFacePoint_J_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i+0.5, (double)cfv_j, (double)cfv_k);

	// Positive k face
	calculated_dists[5] = (isKthBitSet_GPU(cfv_val, 6) == 0) ? DBL_MAX :
					distToFacePoint_K_GPU(
                                        sp2_0, sp2_1, sp2_2,
                                        (double)i, (double)j, (double)k,
                                        (double)cfv_i, (double)cfv_j, (double)cfv_k+0.5);
	
	for (int i = 0; i < 6; i++)
	{
		if (calculated_dists[i] < closet_dist)
		{
			closet_dist = calculated_dists[i];
		}
	}

	
	return closet_dist;
}

__device__ double distToFacePoint_I_GPU(
			float sp2_0, float sp2_1, float sp2_2,
                        double i, double j, double k,
                        double cfv_i, double cfv_j, double cfv_k)
{	
	double dist = DBL_MAX;

	double temp_i = cfv_i - 0.5;

	int add_i;
	for (add_i = 0; add_i < 3; add_i++)
	{
			
		double temp_k = cfv_k - 0.5;

		int add_k;
		for (add_k = 0; add_k < 3; add_k++)
		{
			double temp_dist = calcDist_GPU(
						sp2_0, sp2_1, sp2_2,
						i, j, k,
						temp_i + 0.5 * add_i,
						cfv_j,
						temp_k + 0.5 * add_k);
			if(temp_dist < dist)
			{
				dist = temp_dist;
			}
		}
	}

	return dist;
}

__device__ double distToFacePoint_J_GPU(
			float sp2_0, float sp2_1, float sp2_2,
                        double i, double j, double k,
                        double cfv_i, double cfv_j, double cfv_k)
{
	double dist = DBL_MAX;

	double temp_j = cfv_j - 0.5;

	int add_j;
	for (add_j = 0; add_j < 3; add_j++)
	{
		double temp_k = cfv_k - 0.5;

		int add_k;
		for (add_k = 0; add_k < 3; add_k++)
		{
			double temp_dist = calcDist_GPU(
						sp2_0, sp2_1, sp2_2,
						i, j, k,
						cfv_i,
						temp_j + 0.5 * add_j,
						temp_k + 0.5 * add_k);
				
			if(temp_dist < dist)
			{
				dist = temp_dist;
			}

		}
	}
	
	return dist;
}

__device__ double distToFacePoint_K_GPU(
			float sp2_0, float sp2_1, float sp2_2,
                        double i, double j, double k,
                        double cfv_i, double cfv_j, double cfv_k)
{
	double dist = DBL_MAX;

	double temp_i = cfv_i - 0.5;

	int add_i;
	for (add_i = 0; add_i < 3; add_i++)
	{
			
		double temp_j = cfv_j - 0.5;

		int add_j;
		for (add_j = 0; add_j < 3; add_j++)
		{
			double temp_dist = calcDist_GPU(
						sp2_0, sp2_1, sp2_2,
						i, j, k,
						temp_i + 0.5 * add_i,
						temp_j + 0.5 * add_j,
						cfv_k);
				
			if(temp_dist < dist)
			{
				dist = temp_dist;
			}
		}
	}

	return dist;
}

__device__ double calcDist_GPU(float sp2_0, float sp2_1, float sp2_2,
		double i, double j, double k,
		double target_i, double target_j, double target_k)
{
	double result = (i - target_i) * (i - target_i) * sp2_0 +
			(j - target_j) * (j - target_j) * sp2_1 +
			(k - target_k) * (k - target_k) * sp2_2;

	return sqrt(result);
}

__device__ bool isKthBitSet_GPU(int n, int k)
{
    if (n & (1 << (k - 1)))
        return 1;
    else
        return 0;
}


	.text
	.file	"distance_transformation_gpu.hip"
	.globl	_Z37__device_stub__distTransformation_GPUiPhfffiiiPd # -- Begin function _Z37__device_stub__distTransformation_GPUiPhfffiiiPd
	.type	_Z37__device_stub__distTransformation_GPUiPhfffiiiPd,@function
_Z37__device_stub__distTransformation_GPUiPhfffiiiPd: # @_Z37__device_stub__distTransformation_GPUiPhfffiiiPd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	20(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	16(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	12(%rsp), %r14
	movl	%edx, (%r14)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%rdx, 48(%rbx)
	movq	%rcx, 56(%rbx)
	movq	%r8, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22distTransformation_GPUiPhfffiiiPd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__distTransformation_GPUiPhfffiiiPd, .Lfunc_end0-_Z37__device_stub__distTransformation_GPUiPhfffiiiPd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22distTransformation_GPUiPhfffiiiPd, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22distTransformation_GPUiPhfffiiiPd,@object # @_Z22distTransformation_GPUiPhfffiiiPd
	.section	.rodata,"a",@progbits
	.globl	_Z22distTransformation_GPUiPhfffiiiPd
	.p2align	3, 0x0
_Z22distTransformation_GPUiPhfffiiiPd:
	.quad	_Z37__device_stub__distTransformation_GPUiPhfffiiiPd
	.size	_Z22distTransformation_GPUiPhfffiiiPd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z22distTransformation_GPUiPhfffiiiPd"
	.size	.L__unnamed_1, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__distTransformation_GPUiPhfffiiiPd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22distTransformation_GPUiPhfffiiiPd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22distTransformation_GPUiPhfffiiiPd ; -- Begin function _Z22distTransformation_GPUiPhfffiiiPd
	.globl	_Z22distTransformation_GPUiPhfffiiiPd
	.p2align	8
	.type	_Z22distTransformation_GPUiPhfffiiiPd,@function
_Z22distTransformation_GPUiPhfffiiiPd:  ; @_Z22distTransformation_GPUiPhfffiiiPd
; %bb.0:
	s_clause 0x2
	s_load_b32 s10, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x10
	s_load_b64 s[2:3], s[0:1], 0x20
	s_add_u32 s8, s0, 48
	s_addc_u32 s9, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s10, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[12:13], null, s15, s16, v[0:1]
	s_mul_i32 s10, s2, s7
	s_mov_b32 s7, exec_lo
	s_mul_i32 s3, s10, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_i32_e64 s3, v12
	s_cbranch_execz .LBB0_44
; %bb.1:                                ; %.lr.ph
	s_ashr_i32 s11, s10, 31
	s_ashr_i32 s12, s2, 31
	s_add_i32 s7, s10, s11
	s_add_i32 s14, s2, s12
	s_xor_b32 s13, s7, s11
	s_xor_b32 s14, s14, s12
	v_cvt_f32_u32_e32 v0, s13
	v_cvt_f32_u32_e32 v1, s14
	v_cvt_f64_f32_e32 v[14:15], s4
	v_cvt_f64_f32_e32 v[16:17], s5
	v_cvt_f64_f32_e32 v[18:19], s6
	v_rcp_iflag_f32_e32 v0, v0
	v_rcp_iflag_f32_e32 v1, v1
	s_sub_i32 s4, 0, s13
	s_sub_i32 s5, 0, s14
	s_load_b32 s17, s[8:9], 0x0
	s_mov_b32 s8, -1
	s_mov_b32 s9, 0x7fefffff
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v0, v0
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s4, v0
	v_mul_lo_u32 v3, s5, v1
	s_clause 0x2
	s_load_b32 s15, s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x8
	s_load_b64 s[6:7], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s17, s16
	s_mov_b32 s16, 0
	v_mul_hi_u32 v2, v0, v2
	v_mul_hi_u32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v40, v0, v2
	v_add_nc_u32_e32 v41, v1, v3
.LBB0_2:                                ; %NodeBlock
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
                                        ;     Child Loop BB0_11 Depth 2
                                        ;       Child Loop BB0_12 Depth 3
                                        ;     Child Loop BB0_16 Depth 2
                                        ;       Child Loop BB0_17 Depth 3
                                        ;     Child Loop BB0_21 Depth 2
                                        ;       Child Loop BB0_22 Depth 3
                                        ;     Child Loop BB0_26 Depth 2
                                        ;       Child Loop BB0_27 Depth 3
                                        ;     Child Loop BB0_31 Depth 2
                                        ;       Child Loop BB0_32 Depth 3
                                        ;     Child Loop BB0_35 Depth 2
	v_ashrrev_i32_e32 v13, 31, v12
	s_cmp_lt_i32 s15, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[12:13]
	v_add_co_u32 v20, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v21, vcc_lo, s7, v1, vcc_lo
	global_load_b64 v[0:1], v[20:21], off
	s_waitcnt vmcnt(0)
	v_cvt_i32_f64_e32 v43, v[0:1]
	v_add_nc_u32_e32 v1, v12, v13
	v_xor_b32_e32 v1, v1, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v1, v40
	v_mul_lo_u32 v5, v3, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v1, v5
	v_add_nc_u32_e32 v5, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s13, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_ashrrev_i32_e32 v0, 31, v43
	v_add_nc_u32_e32 v2, v43, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v0
	v_mul_hi_u32 v4, v2, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v6, v4, s13
	v_sub_nc_u32_e32 v2, v2, v6
	v_subrev_nc_u32_e32 v6, s13, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s13, v2
	v_cndmask_b32_e32 v1, v1, v6, vcc_lo
	v_cmp_le_u32_e64 s0, s13, v2
	v_add_nc_u32_e32 v6, 1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s13, v1
	v_cndmask_b32_e64 v2, v2, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v3, v6, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s13, v2
	v_add_nc_u32_e32 v7, 1, v4
	v_xor_b32_e32 v3, s11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v4, v7, s0
	v_xor_b32_e32 v7, s11, v13
	v_add_nc_u32_e32 v5, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v1, v7
	v_cndmask_b32_e32 v2, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v42, v1, v7
	v_xor_b32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v42, s10
	v_sub_nc_u32_e32 v13, v2, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v12, v1
	v_mul_lo_u32 v2, v13, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v1
	v_sub_nc_u32_e32 v2, v43, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v1, v3
	v_ashrrev_i32_e32 v4, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v3
	v_xor_b32_e32 v3, s12, v3
	v_add_nc_u32_e32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v7, v5, v41
	v_xor_b32_e32 v6, v6, v4
	v_xor_b32_e32 v4, s12, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, v7, s14
	v_mul_hi_u32 v8, v6, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v9
	v_mul_lo_u32 v10, v8, s14
	v_add_nc_u32_e32 v9, 1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v11, s14, v5
	v_cmp_le_u32_e64 s0, s14, v5
	v_sub_nc_u32_e32 v6, v6, v10
	v_add_nc_u32_e32 v10, 1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v5, v11, s0
	v_subrev_nc_u32_e32 v22, s14, v6
	v_cmp_le_u32_e32 vcc_lo, s14, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v7, v10, s0
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_cndmask_b32_e32 v6, v6, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, 1, v7
	v_add_nc_u32_e32 v9, 1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s14, v6
	v_cndmask_b32_e32 v6, v8, v9, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v6, v4
	v_cndmask_b32_e32 v5, v7, v10, vcc_lo
	v_sub_nc_u32_e32 v44, v6, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v5, v3
	v_sub_nc_u32_e32 v45, v5, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v44, s2
	v_mul_lo_u32 v4, v45, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v46, v2, v3
	v_sub_nc_u32_e32 v47, v1, v4
	s_cbranch_scc1 .LBB0_37
; %bb.3:                                ; %LeafBlock127
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
	s_cmp_eq_u32 s15, 1
	s_mov_b32 s17, 0
                                        ; implicit-def: $vgpr22_vgpr23
	s_cbranch_scc0 .LBB0_38
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_co_u32 v1, vcc_lo, s4, v43
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v0, vcc_lo
	global_load_u8 v30, v[1:2], off
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 1, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v0
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB0_9
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[0:1], v46
	v_cvt_f64_i32_e32 v[2:3], v47
	v_cvt_f64_i32_e32 v[6:7], v44
	v_cvt_f64_i32_e32 v[8:9], v13
	v_cvt_f64_i32_e32 v[4:5], v42
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_mov_b32 s18, 0
	v_add_f64 v[0:1], v[0:1], -0.5
	v_add_f64 v[6:7], v[6:7], -0.5
	v_add_f64 v[8:9], v[8:9], -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[2:3], -v[0:1]
	v_cvt_f64_i32_e32 v[2:3], v45
	v_mul_f64 v[0:1], v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[10:11], v[0:1], v[16:17]
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	v_dual_mov_b32 v25, v23 :: v_dual_mov_b32 v24, v22
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[24:25], 0.5, v[6:7]
	v_dual_mov_b32 v29, v23 :: v_dual_mov_b32 v28, v22
	s_mov_b32 s19, 3
	v_add_f64 v[26:27], v[2:3], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[26:27], v[26:27], v[26:27]
	v_fma_f64 v[26:27], v[26:27], v[14:15], v[10:11]
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_6 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_fma_f64 v[31:32], v[28:29], 0.5, v[8:9]
	v_add_f64 v[28:29], v[28:29], 1.0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s19, 0
	v_add_f64 v[31:32], v[4:5], -v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[31:32], v[31:32], v[31:32]
	v_fma_f64 v[31:32], v[31:32], v[18:19], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[31:32]
	v_cndmask_b32_e64 v33, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v33, 8, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[31:32], v[31:32], v33
	v_rsq_f64_e32 v[33:34], v[31:32]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[35:36], v[31:32], v[33:34]
	v_mul_f64 v[33:34], v[33:34], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[37:38], -v[33:34], v[35:36], 0.5
	v_fma_f64 v[35:36], v[35:36], v[37:38], v[35:36]
	v_fma_f64 v[33:34], v[33:34], v[37:38], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[37:38], -v[35:36], v[35:36], v[31:32]
	v_fma_f64 v[35:36], v[37:38], v[33:34], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[37:38], -v[35:36], v[35:36], v[31:32]
	v_fma_f64 v[33:34], v[37:38], v[33:34], v[35:36]
	v_cndmask_b32_e64 v35, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[31:32], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[33:34], v[33:34], v35
	v_dual_cndmask_b32 v32, v34, v32 :: v_dual_cndmask_b32 v31, v33, v31
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[31:32], v[0:1]
	v_dual_cndmask_b32 v1, v1, v32 :: v_dual_cndmask_b32 v0, v0, v31
	s_cbranch_scc1 .LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=2
	v_add_f64 v[24:25], v[24:25], 1.0
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 3
	s_cbranch_scc1 .LBB0_6
.LBB0_9:                                ; %Flow140
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_and_b32_e32 v38, 0xff, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 2, v38
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[2:3], v44
	v_cvt_f64_i32_e32 v[4:5], v45
	v_cvt_f64_i32_e32 v[8:9], v46
	v_cvt_f64_i32_e32 v[10:11], v13
	v_cvt_f64_i32_e32 v[6:7], v42
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_mov_b32 s18, 0
	v_add_f64 v[2:3], v[2:3], -0.5
	v_add_f64 v[8:9], v[8:9], -0.5
	v_add_f64 v[10:11], v[10:11], -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[4:5], -v[2:3]
	v_cvt_f64_i32_e32 v[4:5], v47
	v_mul_f64 v[2:3], v[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[22:23], v[2:3], v[14:15]
	v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
	v_dual_mov_b32 v27, v25 :: v_dual_mov_b32 v26, v24
.LBB0_11:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_12 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[26:27], 0.5, v[8:9]
	v_dual_mov_b32 v31, v25 :: v_dual_mov_b32 v30, v24
	s_mov_b32 s19, 3
	v_add_f64 v[28:29], v[4:5], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[28:29], v[28:29], v[28:29]
	v_fma_f64 v[28:29], v[28:29], v[16:17], v[22:23]
.LBB0_12:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_11 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_fma_f64 v[32:33], v[30:31], 0.5, v[10:11]
	v_add_f64 v[30:31], v[30:31], 1.0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s19, 0
	v_add_f64 v[32:33], v[6:7], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[32:33], v[32:33], v[32:33]
	v_fma_f64 v[32:33], v[32:33], v[18:19], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[32:33]
	v_cndmask_b32_e64 v34, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v34, 8, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[32:33], v[32:33], v34
	v_rsq_f64_e32 v[34:35], v[32:33]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[36:37], v[32:33], v[34:35]
	v_mul_f64 v[34:35], v[34:35], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[48:49], -v[34:35], v[36:37], 0.5
	v_fma_f64 v[36:37], v[36:37], v[48:49], v[36:37]
	v_fma_f64 v[34:35], v[34:35], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[48:49], -v[36:37], v[36:37], v[32:33]
	v_fma_f64 v[36:37], v[48:49], v[34:35], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[48:49], -v[36:37], v[36:37], v[32:33]
	v_fma_f64 v[34:35], v[48:49], v[34:35], v[36:37]
	v_cndmask_b32_e64 v36, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[32:33], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[34:35], v[34:35], v36
	v_dual_cndmask_b32 v33, v35, v33 :: v_dual_cndmask_b32 v32, v34, v32
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[32:33], v[2:3]
	v_dual_cndmask_b32 v3, v3, v33 :: v_dual_cndmask_b32 v2, v2, v32
	s_cbranch_scc1 .LBB0_12
; %bb.13:                               ;   in Loop: Header=BB0_11 Depth=2
	v_add_f64 v[26:27], v[26:27], 1.0
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 3
	s_cbranch_scc1 .LBB0_11
.LBB0_14:                               ; %Flow138
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_and_b32_e32 v4, 4, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB0_19
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[4:5], v13
	v_cvt_f64_i32_e32 v[6:7], v42
	v_cvt_f64_i32_e32 v[10:11], v44
	v_cvt_f64_i32_e32 v[22:23], v46
	v_cvt_f64_i32_e32 v[8:9], v47
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_mov_b32 s18, 0
	v_add_f64 v[4:5], v[4:5], -0.5
	v_add_f64 v[10:11], v[10:11], -0.5
	v_add_f64 v[22:23], v[22:23], -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[6:7], -v[4:5]
	v_cvt_f64_i32_e32 v[6:7], v45
	v_mul_f64 v[4:5], v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[24:25], v[4:5], v[18:19]
	v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
	v_dual_mov_b32 v29, v27 :: v_dual_mov_b32 v28, v26
.LBB0_16:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_17 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[28:29], 0.5, v[10:11]
	v_dual_mov_b32 v33, v27 :: v_dual_mov_b32 v32, v26
	s_mov_b32 s19, 3
	v_add_f64 v[30:31], v[6:7], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[30:31], v[30:31], v[30:31]
	v_mul_f64 v[30:31], v[30:31], v[14:15]
.LBB0_17:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_16 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_fma_f64 v[34:35], v[32:33], 0.5, v[22:23]
	v_add_f64 v[32:33], v[32:33], 1.0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s19, 0
	v_add_f64 v[34:35], v[8:9], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[34:35], v[34:35], v[34:35]
	v_fma_f64 v[34:35], v[34:35], v[16:17], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[34:35], v[24:25], v[34:35]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[34:35]
	v_cndmask_b32_e64 v36, 0, 1, vcc_lo
	v_cndmask_b32_e64 v39, 0, 0xffffff80, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v36, 8, v36
	v_ldexp_f64 v[34:35], v[34:35], v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[36:37], v[34:35]
	v_cmp_class_f64_e64 vcc_lo, v[34:35], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[48:49], v[34:35], v[36:37]
	v_mul_f64 v[36:37], v[36:37], 0.5
	v_fma_f64 v[50:51], -v[36:37], v[48:49], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[48:49], v[48:49], v[50:51], v[48:49]
	v_fma_f64 v[36:37], v[36:37], v[50:51], v[36:37]
	v_fma_f64 v[50:51], -v[48:49], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[48:49], v[50:51], v[36:37], v[48:49]
	v_fma_f64 v[50:51], -v[48:49], v[48:49], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[36:37], v[50:51], v[36:37], v[48:49]
	v_ldexp_f64 v[36:37], v[36:37], v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v35, v37, v35 :: v_dual_cndmask_b32 v34, v36, v34
	v_cmp_lt_f64_e32 vcc_lo, v[34:35], v[4:5]
	v_dual_cndmask_b32 v5, v5, v35 :: v_dual_cndmask_b32 v4, v4, v34
	s_cbranch_scc1 .LBB0_17
; %bb.18:                               ;   in Loop: Header=BB0_16 Depth=2
	v_add_f64 v[28:29], v[28:29], 1.0
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 3
	s_cbranch_scc1 .LBB0_16
.LBB0_19:                               ; %Flow136
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_and_b32_e32 v6, 8, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB0_24
; %bb.20:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[6:7], v46
	v_cvt_f64_i32_e32 v[8:9], v47
	v_cvt_f64_i32_e32 v[22:23], v44
	v_cvt_f64_i32_e32 v[24:25], v13
	v_cvt_f64_i32_e32 v[10:11], v42
	v_mov_b32_e32 v28, 0
	v_mov_b32_e32 v29, 0
	s_mov_b32 s18, 0
	v_add_f64 v[6:7], v[6:7], 0.5
	v_add_f64 v[22:23], v[22:23], -0.5
	v_add_f64 v[24:25], v[24:25], -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[8:9], -v[6:7]
	v_cvt_f64_i32_e32 v[8:9], v45
	v_mul_f64 v[6:7], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[26:27], v[6:7], v[16:17]
	v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
	v_dual_mov_b32 v31, v29 :: v_dual_mov_b32 v30, v28
.LBB0_21:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_22 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[30:31], 0.5, v[22:23]
	v_dual_mov_b32 v35, v29 :: v_dual_mov_b32 v34, v28
	s_mov_b32 s19, 3
	v_add_f64 v[32:33], v[8:9], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[32:33], v[32:33], v[32:33]
	v_fma_f64 v[32:33], v[32:33], v[14:15], v[26:27]
.LBB0_22:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_21 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_fma_f64 v[36:37], v[34:35], 0.5, v[24:25]
	v_add_f64 v[34:35], v[34:35], 1.0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s19, 0
	v_add_f64 v[36:37], v[10:11], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[36:37], v[36:37], v[36:37]
	v_fma_f64 v[36:37], v[36:37], v[18:19], v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[36:37]
	v_cndmask_b32_e64 v39, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v39, 8, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[36:37], v[36:37], v39
	v_cndmask_b32_e64 v39, 0, 0xffffff80, vcc_lo
	v_rsq_f64_e32 v[48:49], v[36:37]
	v_cmp_class_f64_e64 vcc_lo, v[36:37], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[50:51], v[36:37], v[48:49]
	v_mul_f64 v[48:49], v[48:49], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], -v[48:49], v[50:51], 0.5
	v_fma_f64 v[50:51], v[50:51], v[52:53], v[50:51]
	v_fma_f64 v[48:49], v[48:49], v[52:53], v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], -v[50:51], v[50:51], v[36:37]
	v_fma_f64 v[50:51], v[52:53], v[48:49], v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], -v[50:51], v[50:51], v[36:37]
	v_fma_f64 v[48:49], v[52:53], v[48:49], v[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[48:49], v[48:49], v39
	v_dual_cndmask_b32 v36, v48, v36 :: v_dual_cndmask_b32 v37, v49, v37
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[36:37], v[6:7]
	v_dual_cndmask_b32 v6, v6, v36 :: v_dual_cndmask_b32 v7, v7, v37
	s_cbranch_scc1 .LBB0_22
; %bb.23:                               ;   in Loop: Header=BB0_21 Depth=2
	v_add_f64 v[30:31], v[30:31], 1.0
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 3
	s_cbranch_scc1 .LBB0_21
.LBB0_24:                               ; %Flow134
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_and_b32_e32 v8, 16, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v8
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB0_29
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[8:9], v44
	v_cvt_f64_i32_e32 v[10:11], v45
	v_cvt_f64_i32_e32 v[24:25], v46
	v_cvt_f64_i32_e32 v[26:27], v13
	v_cvt_f64_i32_e32 v[22:23], v42
	v_mov_b32_e32 v30, 0
	v_mov_b32_e32 v31, 0
	s_mov_b32 s18, 0
	v_add_f64 v[8:9], v[8:9], 0.5
	v_add_f64 v[24:25], v[24:25], -0.5
	v_add_f64 v[26:27], v[26:27], -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[10:11], -v[8:9]
	v_cvt_f64_i32_e32 v[10:11], v47
	v_mul_f64 v[8:9], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[28:29], v[8:9], v[14:15]
	v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
	v_dual_mov_b32 v33, v31 :: v_dual_mov_b32 v32, v30
.LBB0_26:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_27 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[32:33], 0.5, v[24:25]
	v_dual_mov_b32 v37, v31 :: v_dual_mov_b32 v36, v30
	s_mov_b32 s19, 3
	v_add_f64 v[34:35], v[10:11], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[34:35], v[34:35], v[34:35]
	v_fma_f64 v[34:35], v[34:35], v[16:17], v[28:29]
.LBB0_27:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_26 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_fma_f64 v[48:49], v[36:37], 0.5, v[26:27]
	v_add_f64 v[36:37], v[36:37], 1.0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s19, 0
	v_add_f64 v[48:49], v[22:23], -v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[48:49], v[48:49], v[48:49]
	v_fma_f64 v[48:49], v[48:49], v[18:19], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[48:49]
	v_cndmask_b32_e64 v39, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v39, 8, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[48:49], v[48:49], v39
	v_cndmask_b32_e64 v39, 0, 0xffffff80, vcc_lo
	v_rsq_f64_e32 v[50:51], v[48:49]
	v_cmp_class_f64_e64 vcc_lo, v[48:49], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[52:53], v[48:49], v[50:51]
	v_mul_f64 v[50:51], v[50:51], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[54:55], -v[50:51], v[52:53], 0.5
	v_fma_f64 v[52:53], v[52:53], v[54:55], v[52:53]
	v_fma_f64 v[50:51], v[50:51], v[54:55], v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[54:55], -v[52:53], v[52:53], v[48:49]
	v_fma_f64 v[52:53], v[54:55], v[50:51], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[54:55], -v[52:53], v[52:53], v[48:49]
	v_fma_f64 v[50:51], v[54:55], v[50:51], v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[50:51], v[50:51], v39
	v_dual_cndmask_b32 v48, v50, v48 :: v_dual_cndmask_b32 v49, v51, v49
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[48:49], v[8:9]
	v_dual_cndmask_b32 v8, v8, v48 :: v_dual_cndmask_b32 v9, v9, v49
	s_cbranch_scc1 .LBB0_27
; %bb.28:                               ;   in Loop: Header=BB0_26 Depth=2
	v_add_f64 v[32:33], v[32:33], 1.0
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 3
	s_cbranch_scc1 .LBB0_26
.LBB0_29:                               ; %Flow132
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_and_b32_e32 v10, 32, v38
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
	s_and_saveexec_b32 s17, vcc_lo
	s_cbranch_execz .LBB0_34
; %bb.30:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[10:11], v13
	v_cvt_f64_i32_e32 v[22:23], v42
	v_cvt_f64_i32_e32 v[26:27], v44
	v_cvt_f64_i32_e32 v[28:29], v46
	v_cvt_f64_i32_e32 v[24:25], v47
	v_mov_b32_e32 v32, 0
	v_mov_b32_e32 v33, 0
	s_mov_b32 s18, 0
	v_add_f64 v[10:11], v[10:11], 0.5
	v_add_f64 v[26:27], v[26:27], -0.5
	v_add_f64 v[28:29], v[28:29], -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[22:23], -v[10:11]
	v_cvt_f64_i32_e32 v[22:23], v45
	v_mul_f64 v[10:11], v[10:11], v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[30:31], v[10:11], v[18:19]
	v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
	v_dual_mov_b32 v35, v33 :: v_dual_mov_b32 v34, v32
.LBB0_31:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_32 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[36:37], v[34:35], 0.5, v[26:27]
	v_dual_mov_b32 v39, v33 :: v_dual_mov_b32 v38, v32
	s_mov_b32 s19, 3
	v_add_f64 v[36:37], v[22:23], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[36:37], v[36:37], v[36:37]
	v_mul_f64 v[36:37], v[36:37], v[14:15]
.LBB0_32:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_31 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_fma_f64 v[48:49], v[38:39], 0.5, v[28:29]
	v_add_f64 v[38:39], v[38:39], 1.0
	s_add_i32 s19, s19, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s19, 0
	v_add_f64 v[48:49], v[24:25], -v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[48:49], v[48:49], v[48:49]
	v_fma_f64 v[48:49], v[48:49], v[16:17], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[48:49], v[30:31], v[48:49]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[48:49]
	v_cndmask_b32_e64 v50, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v50, 8, v50
	v_ldexp_f64 v[48:49], v[48:49], v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[50:51], v[48:49]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[52:53], v[48:49], v[50:51]
	v_mul_f64 v[50:51], v[50:51], 0.5
	v_fma_f64 v[54:55], -v[50:51], v[52:53], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[52:53], v[52:53], v[54:55], v[52:53]
	v_fma_f64 v[50:51], v[50:51], v[54:55], v[50:51]
	v_fma_f64 v[54:55], -v[52:53], v[52:53], v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[52:53], v[54:55], v[50:51], v[52:53]
	v_fma_f64 v[54:55], -v[52:53], v[52:53], v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[50:51], v[54:55], v[50:51], v[52:53]
	v_cndmask_b32_e64 v52, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[48:49], 0x260
	v_ldexp_f64 v[50:51], v[50:51], v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v49, v51, v49 :: v_dual_cndmask_b32 v48, v50, v48
	v_cmp_lt_f64_e32 vcc_lo, v[48:49], v[10:11]
	v_dual_cndmask_b32 v11, v11, v49 :: v_dual_cndmask_b32 v10, v10, v48
	s_cbranch_scc1 .LBB0_32
; %bb.33:                               ;   in Loop: Header=BB0_31 Depth=2
	v_add_f64 v[34:35], v[34:35], 1.0
	s_add_i32 s18, s18, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, 3
	s_cbranch_scc1 .LBB0_31
.LBB0_34:                               ; %Flow130
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_cmp_eq_u32_e32 vcc_lo, v12, v43
	s_mov_b32 s17, 0
	v_cndmask_b32_e64 v23, 0x7fefffff, 0, vcc_lo
	v_cndmask_b32_e64 v22, -1, 0, vcc_lo
.LBB0_35:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b32 s18, s17, 1
	s_add_i32 s17, s17, 1
	s_mov_b32 m0, s18
	s_cmp_lg_u32 s17, 6
	v_movrels_b32_e32 v25, v1
	v_movrels_b32_e32 v24, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_f64_e32 vcc_lo, v[24:25], v[22:23]
	v_dual_cndmask_b32 v23, v23, v25 :: v_dual_cndmask_b32 v22, v22, v24
	s_cbranch_scc1 .LBB0_35
; %bb.36:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s17, -1
	s_branch .LBB0_38
.LBB0_37:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
	s_mov_b32 s17, 0
                                        ; implicit-def: $vgpr22_vgpr23
.LBB0_38:                               ; %Flow141
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_41
; %bb.39:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_cmp_eq_u32 s15, 0
                                        ; implicit-def: $vgpr22_vgpr23
	s_cbranch_scc0 .LBB0_41
; %bb.40:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cvt_f64_i32_e32 v[0:1], v47
	v_cvt_f64_i32_e32 v[2:3], v46
	v_cvt_f64_i32_e32 v[4:5], v45
	v_cvt_f64_i32_e32 v[6:7], v44
	v_cvt_f64_i32_e32 v[8:9], v13
	s_mov_b32 s17, -1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	v_cvt_f64_i32_e32 v[2:3], v42
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[0:1], v[0:1], v[0:1]
	v_add_f64 v[2:3], v[2:3], -v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], v[4:5], v[4:5]
	v_mul_f64 v[0:1], v[0:1], v[16:17]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[2:3], v[2:3]
	v_fma_f64 v[0:1], v[4:5], v[14:15], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[2:3], v[18:19], v[0:1]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v2, 8, v2
	v_ldexp_f64 v[0:1], v[0:1], v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[2:3], v[0:1]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[4:5], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
	v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
	v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
	v_ldexp_f64 v[2:3], v[2:3], v4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_cndmask_b32 v23, v3, v1 :: v_dual_cndmask_b32 v22, v2, v0
.LBB0_41:                               ; %Flow143
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 vcc_lo, exec_lo, s17
	s_cbranch_vccz .LBB0_43
; %bb.42:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_2 Depth=1
	global_store_b64 v[20:21], v[22:23], off
.LBB0_43:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v12, s1, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s3, v12
	s_or_b32 s16, vcc_lo, s16
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_2
.LBB0_44:                               ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22distTransformation_GPUiPhfffiiiPd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 56
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22distTransformation_GPUiPhfffiiiPd, .Lfunc_end0-_Z22distTransformation_GPUiPhfffiiiPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4120
; NumSgprs: 22
; NumVgprs: 56
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 56
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22distTransformation_GPUiPhfffiiiPd
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z22distTransformation_GPUiPhfffiiiPd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     56
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
