#include "checkers.cuh"

int *initial_state();
int4 selected_move(int*, int4*);

int main() {
  int *A = initial_state();
  my_rep_class *my_rep;
  int *n_moves;
  int4 *moves;
  cudaMalloc(&my_rep, sizeof(my_rep_class));
  cudaMalloc(&n_moves, sizeof(int));
  cudaMalloc(&moves, 1024*2048*4*sizeof(int4));
  my_representation<<<my_representation_blocks,
    my_representation_threads>>>(A, my_rep);
  for (int i = 0; i < 100; i++){
    cudaMemset(n_moves, 0, sizeof(int));
    possible_moves<<<possible_moves_blocks,
      possible_moves_threads>>>(my_rep, 1, n_moves, moves);
    update<<<update_blocks, update_threads>>>(my_rep,
      selected_move(n_moves, moves));
    cudaMemset(n_moves, 0, sizeof(int));
    possible_moves<<<possible_moves_blocks,
      possible_moves_threads>>>(my_rep, 2, n_moves, moves);
    update<<<update_blocks, update_threads>>>(my_rep,
      selected_move(n_moves, moves));
  }
  // ...
  return 0;
}

	.file	"tmpxft_002d9565_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z52__device_stub__Z17my_representationPiP12my_rep_classPiP12my_rep_class
	.type	_Z52__device_stub__Z17my_representationPiP12my_rep_classPiP12my_rep_class, @function
_Z52__device_stub__Z17my_representationPiP12my_rep_classPiP12my_rep_class:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z17my_representationPiP12my_rep_class(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z52__device_stub__Z17my_representationPiP12my_rep_classPiP12my_rep_class, .-_Z52__device_stub__Z17my_representationPiP12my_rep_classPiP12my_rep_class
	.globl	_Z17my_representationPiP12my_rep_class
	.type	_Z17my_representationPiP12my_rep_class, @function
_Z17my_representationPiP12my_rep_class:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z17my_representationPiP12my_rep_classPiP12my_rep_class
	.cfi_endproc
.LFE2034:
	.size	_Z17my_representationPiP12my_rep_class, .-_Z17my_representationPiP12my_rep_class
	.globl	_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4
	.type	_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4, @function
_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14possible_movesP12my_rep_classiPiP4int4(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4, .-_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4
	.globl	_Z14possible_movesP12my_rep_classiPiP4int4
	.type	_Z14possible_movesP12my_rep_classiPiP4int4, @function
_Z14possible_movesP12my_rep_classiPiP4int4:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4
	.cfi_endproc
.LFE2036:
	.size	_Z14possible_movesP12my_rep_classiPiP4int4, .-_Z14possible_movesP12my_rep_classiPiP4int4
	.globl	_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4
	.type	_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4, @function
_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rsi, 96(%rsp)
	leaq	52(%rsp), %rsi
	movq	%rax, 88(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z6updateP12my_rep_class4int4(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4, .-_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4
	.globl	_Z6updateP12my_rep_class4int4
	.type	_Z6updateP12my_rep_class4int4, @function
_Z6updateP12my_rep_class4int4:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, (%rsp)
	movq	%rsp, %rsi
	movq	%rdx, 8(%rsp)
	call	_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z6updateP12my_rep_class4int4, .-_Z6updateP12my_rep_class4int4
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	_Z13initial_statev@PLT
	movq	%rsp, %rdi
	movl	$16810004, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$134217728, %esi
	call	cudaMalloc@PLT
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$16777217, %edi
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$8, %rdi
	movq	%rdx, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rdi, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	(%rsp), %rsi
	movq	%rbx, %rdi
	call	_Z52__device_stub__Z17my_representationPiP12my_rep_classPiP12my_rep_class
.L20:
	movl	$33554433, %ebp
	movl	$16777217, %ebx
	movl	$100, %r13d
	movabsq	$4294967808, %r12
	salq	$7, %rbp
	salq	$8, %rbx
.L25:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	call	cudaMemset@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rbx, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	movl	$1, %esi
	movq	(%rsp), %rdi
	call	_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4
.L21:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rbx, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z13selected_movePiP4int4@PLT
	movq	(%rsp), %rdi
	leaq	48(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	%rdx, 56(%rsp)
	call	_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4
.L22:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	call	cudaMemset@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rbp, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%rbp, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rbx, 36(%rsp)
	movl	$1, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	16(%rsp), %rcx
	movq	8(%rsp), %rdx
	movl	$2, %esi
	movq	(%rsp), %rdi
	call	_Z56__device_stub__Z14possible_movesP12my_rep_classiPiP4int4P12my_rep_classiPiP4int4
.L23:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r12, %rdx
	movl	$1, %ecx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r12, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rbx, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z13selected_movePiP4int4@PLT
	movq	(%rsp), %rdi
	leaq	48(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	%rdx, 56(%rsp)
	call	_Z43__device_stub__Z6updateP12my_rep_class4int4P12my_rep_classR4int4
.L24:
	decl	%r13d
	jne	.L25
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6updateP12my_rep_class4int4"
.LC1:
	.string	"_Z14possible_movesP12my_rep_classiPiP4int4"
.LC2:
	.string	"_Z17my_representationPiP12my_rep_class"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6updateP12my_rep_class4int4(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z14possible_movesP12my_rep_classiPiP4int4(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17my_representationPiP12my_rep_class(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "checkers.cuh"

int *initial_state();
int4 selected_move(int*, int4*);

int main() {
  int *A = initial_state();
  my_rep_class *my_rep;
  int *n_moves;
  int4 *moves;
  hipMalloc(&my_rep, sizeof(my_rep_class));
  hipMalloc(&n_moves, sizeof(int));
  hipMalloc(&moves, 1024*2048*4*sizeof(int4));
  my_representation<<<my_representation_blocks,
    my_representation_threads>>>(A, my_rep);
  for (int i = 0; i < 100; i++){
    hipMemset(n_moves, 0, sizeof(int));
    possible_moves<<<possible_moves_blocks,
      possible_moves_threads>>>(my_rep, 1, n_moves, moves);
    update<<<update_blocks, update_threads>>>(my_rep,
      selected_move(n_moves, moves));
    hipMemset(n_moves, 0, sizeof(int));
    possible_moves<<<possible_moves_blocks,
      possible_moves_threads>>>(my_rep, 2, n_moves, moves);
    update<<<update_blocks, update_threads>>>(my_rep,
      selected_move(n_moves, moves));
  }
  // ...
  return 0;
}

	.text
	.file	"main.hip"
	.globl	_Z32__device_stub__my_representationPiP12my_rep_class # -- Begin function _Z32__device_stub__my_representationPiP12my_rep_class
	.type	_Z32__device_stub__my_representationPiP12my_rep_class,@function
_Z32__device_stub__my_representationPiP12my_rep_class: # @_Z32__device_stub__my_representationPiP12my_rep_class
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17my_representationPiP12my_rep_class, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__my_representationPiP12my_rep_class, .Lfunc_end0-_Z32__device_stub__my_representationPiP12my_rep_class
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE # -- Begin function _Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.type	_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE,@function
_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE: # @_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE, .Lfunc_end1-_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE # -- Begin function _Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.type	_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE,@function
_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE: # @_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rsi, (%rax)
	movq	%rdx, 8(%rax)
	leaq	24(%rsp), %rcx
	movq	%rdi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rax, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE, .Lfunc_end2-_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movabsq	$4294967552, %rbx               # imm = 0x100000100
	callq	_Z13initial_statev
	movq	%rax, %r15
	leaq	16(%rsp), %rdi
	movl	$16810004, %esi                 # imm = 0x1008014
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$134217728, %esi                # imm = 0x8000000
	callq	hipMalloc
	leaq	256(%rbx), %r14
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_1
# %bb.12:
	movq	16(%rsp), %rsi
	movq	%r15, %rdi
	callq	_Z32__device_stub__my_representationPiP12my_rep_class
.LBB3_1:                                # %.preheader
	movl	$100, %ebp
	leaq	-128(%rbx), %r15
.LBB3_2:                                # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:                                #   in Loop: Header=BB3_2 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	$1, %esi
	callq	_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
.LBB3_4:                                #   in Loop: Header=BB3_2 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_2 Depth=1
	movq	16(%rsp), %r12
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z13selected_movePiP15HIP_vector_typeIiLj4EE
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE
.LBB3_6:                                #   in Loop: Header=BB3_2 Depth=1
	movq	8(%rsp), %rdi
	movl	$4, %edx
	xorl	%esi, %esi
	callq	hipMemset
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:                                #   in Loop: Header=BB3_2 Depth=1
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rdx
	movq	24(%rsp), %rcx
	movl	$2, %esi
	callq	_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
.LBB3_8:                                #   in Loop: Header=BB3_2 Depth=1
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:                                #   in Loop: Header=BB3_2 Depth=1
	movq	16(%rsp), %r12
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z13selected_movePiP15HIP_vector_typeIiLj4EE
	movq	%r12, %rdi
	movq	%rax, %rsi
	callq	_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE
.LBB3_10:                               #   in Loop: Header=BB3_2 Depth=1
	decl	%ebp
	jne	.LBB3_2
# %bb.11:
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17my_representationPiP12my_rep_class, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17my_representationPiP12my_rep_class,@object # @_Z17my_representationPiP12my_rep_class
	.section	.rodata,"a",@progbits
	.globl	_Z17my_representationPiP12my_rep_class
	.p2align	3, 0x0
_Z17my_representationPiP12my_rep_class:
	.quad	_Z32__device_stub__my_representationPiP12my_rep_class
	.size	_Z17my_representationPiP12my_rep_class, 8

	.type	_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE,@object # @_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.globl	_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.p2align	3, 0x0
_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE:
	.quad	_Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.size	_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE, 8

	.type	_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE,@object # @_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.globl	_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.p2align	3, 0x0
_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE:
	.quad	_Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.size	_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17my_representationPiP12my_rep_class"
	.size	.L__unnamed_1, 39

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE"
	.size	.L__unnamed_2, 62

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE"
	.size	.L__unnamed_3, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__my_representationPiP12my_rep_class
	.addrsig_sym _Z29__device_stub__possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.addrsig_sym _Z21__device_stub__updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17my_representationPiP12my_rep_class
	.addrsig_sym _Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.addrsig_sym _Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17my_representationPiP12my_rep_class ; -- Begin function _Z17my_representationPiP12my_rep_class
	.globl	_Z17my_representationPiP12my_rep_class
	.p2align	8
	.type	_Z17my_representationPiP12my_rep_class,@function
_Z17my_representationPiP12my_rep_class: ; @_Z17my_representationPiP12my_rep_class
; %bb.0:
	s_load_b32 s4, s[0:1], 0x1c
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x400000, v1
	s_cbranch_execz .LBB0_37
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s2, s[2:3], 0x0
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s2, s8
	s_add_u32 s2, s6, 8
	s_addc_u32 s3, s7, 0
	s_mov_b32 s8, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_mov_b32 s9, 0
	s_mov_b32 s12, 0
	s_mov_b32 s10, 0
	s_mov_b32 s11, exec_lo
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_lshrrev_b32_e32 v2, 21, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v2, v1, v2
	v_add_co_u32 v4, vcc_lo, s4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	v_ashrrev_i32_e32 v4, 11, v2
	v_mul_i32_i24_e32 v2, 0x800, v4
	v_mul_i32_i24_e32 v6, 0x802, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v6, v2
	v_sub_nc_u32_e32 v2, v1, v2
	v_add_nc_u32_e32 v4, v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 0x803, v4
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[7:8], v5, off
	v_add_nc_u32_e32 v5, 0x7ff, v1
                                        ; implicit-def: $vgpr7_vgpr8
	v_cmp_lt_u32_e32 vcc_lo, 0xffe, v5
	v_cmpx_lt_i32_e32 0x7fe, v2
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB0_14
; %bb.3:                                ; %LeafBlock98
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s13, -1
	s_mov_b32 s10, exec_lo
                                        ; implicit-def: $vgpr7_vgpr8
	v_cmpx_eq_u32_e32 0x7ff, v2
	s_cbranch_execz .LBB0_13
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
                                        ; implicit-def: $vgpr7_vgpr8
	s_and_saveexec_b32 s0, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s0
	s_cbranch_execz .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v2, 0xfffff800, v1
	s_mov_b32 s14, exec_lo
                                        ; implicit-def: $vgpr7_vgpr8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0x3ff800, v2
	s_xor_b32 s14, exec_lo, s14
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v8, v3 :: v_dual_add_nc_u32 v7, 0x1006, v4
	v_add_nc_u32_e32 v2, 0x1005, v4
	s_mov_b32 s12, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	v_add_co_u32 v9, s0, s6, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, s7, v8, s0
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	global_store_b32 v[9:10], v0, off
.LBB0_7:                                ; %Flow100
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s12, s12, exec_lo
.LBB0_8:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s13, s13
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_nc_u32_e32 v7, 1, v4
	s_or_b32 s12, s12, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	v_add_co_u32 v10, s0, s2, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s0, s3, v9, s0
	v_ashrrev_i32_e32 v8, 31, v7
	global_store_b32 v[10:11], v0, off
.LBB0_10:                               ; %Flow101
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_saveexec_b32 s13, s12
	s_cbranch_execz .LBB0_12
; %bb.11:                               ; %.sink.split86
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s6, v7
	v_add_co_ci_u32_e64 v8, s0, s7, v8, s0
	global_store_b32 v[7:8], v0, off
.LBB0_12:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v7, 0x804, v4
	s_mov_b32 s12, exec_lo
	s_xor_b32 s13, exec_lo, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
.LBB0_13:                               ; %Flow106
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s10, s12, exec_lo
	s_and_b32 s12, s13, exec_lo
                                        ; implicit-def: $vgpr2
.LBB0_14:                               ; %Flow105
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s11, s11
; %bb.15:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_ne_u32_e64 s0, 0, v2
	s_and_not1_b32 s12, s12, exec_lo
	s_mov_b32 s9, exec_lo
                                        ; implicit-def: $vgpr7_vgpr8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s12, s12, s0
; %bb.16:                               ; %Flow107
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s11, s12
	s_cbranch_execz .LBB0_24
; %bb.17:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, s10
                                        ; implicit-def: $vgpr7_vgpr8
	s_and_saveexec_b32 s12, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_21
; %bb.18:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v2, 0xfffff800, v1
	s_mov_b32 s13, s10
                                        ; implicit-def: $vgpr7_vgpr8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, 0x3ff800, v2
	s_and_saveexec_b32 s14, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s14
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v2, 0x1005, v4
	v_mov_b32_e32 v8, v3
	s_or_b32 s13, s10, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v7, v2
; %bb.20:                               ; %Flow110
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s10, exec_lo
	s_and_b32 s13, s13, exec_lo
	s_or_b32 s0, s0, s13
.LBB0_21:                               ; %Flow109
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s12, s12
; %bb.22:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v7, 1, v4
	s_or_b32 s0, s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
; %bb.23:                               ; %Flow111
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s10, s10, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_and_not1_b32 s9, s9, exec_lo
	s_or_b32 s10, s10, s0
.LBB0_24:                               ; %Flow108
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s0, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_34
; %bb.25:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s9, 0
                                        ; implicit-def: $vgpr7_vgpr8
	s_and_saveexec_b32 s11, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s11, exec_lo, s11
	s_cbranch_execz .LBB0_29
; %bb.26:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v2, 0xfffff800, v1
	s_mov_b32 s12, exec_lo
                                        ; implicit-def: $vgpr7_vgpr8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0x3ff800, v2
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 0x1004, v4
	v_add_nc_u32_e32 v2, 0x1005, v4
	s_mov_b32 s9, exec_lo
	v_mov_b32_e32 v8, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_mov_b32_e32 v7, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_store_b32 v[5:6], v0, off
.LBB0_28:                               ; %Flow103
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s9, s9, exec_lo
                                        ; implicit-def: $vgpr6
.LBB0_29:                               ; %Flow102
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s11, s11
	s_cbranch_execz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v7, 31, v6
	s_or_b32 s9, s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[6:7]
	v_or_b32_e32 v7, 1, v6
	v_add_co_u32 v5, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v9, vcc_lo
	v_ashrrev_i32_e32 v8, 31, v7
	global_store_b32 v[5:6], v0, off
.LBB0_31:                               ; %Flow104
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s11, s9
	s_cbranch_execz .LBB0_33
; %bb.32:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[5:6], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_store_b32 v[5:6], v0, off
.LBB0_33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_nc_u32_e32 v7, 0x802, v4
	s_or_b32 s10, s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
.LBB0_34:                               ; %Flow112
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s10
	s_cbranch_execz .LBB0_36
; %bb.35:                               ; %.sink.split88
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[7:8]
	v_add_co_u32 v4, vcc_lo, s6, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	global_store_b32 v[4:5], v0, off
.LBB0_36:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v1, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x3fffff, v1
	s_or_b32 s8, vcc_lo, s8
	s_and_not1_b32 exec_lo, exec_lo, s8
	s_cbranch_execnz .LBB0_2
.LBB0_37:                               ; %Flow114
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17my_representationPiP12my_rep_class
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17my_representationPiP12my_rep_class, .Lfunc_end0-_Z17my_representationPiP12my_rep_class
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1160
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE ; -- Begin function _Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.globl	_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
	.p2align	8
	.type	_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE,@function
_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE: ; @_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
; %bb.0:
	s_clause 0x2
	s_load_b64 s[4:5], s[0:1], 0x0
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b32 s9, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s4, 0x1008010
	s_addc_u32 s7, s5, 0
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[7:8], null, s15, s8, v[0:1]
	v_dual_mov_b32 v0, 0x1008000 :: v_dual_mov_b32 v1, s9
	s_mov_b32 s9, exec_lo
	global_store_b32 v0, v1, s[4:5] offset:16
	v_cmpx_gt_i32_e32 0x400000, v7
	s_cbranch_execz .LBB1_20
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s9, s[2:3], 0x0
	s_load_b128 s[0:3], s[0:1], 0x10
	v_mov_b32_e32 v10, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s9, s8
	s_mov_b32 s9, 0
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v0, 31, v7
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v0, 21, v0
	v_add_nc_u32_e32 v0, v7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 11, v0
	v_add_nc_u32_e32 v6, 1, v1
	v_mul_i32_i24_e32 v0, 0x800, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_i32_i24_e32 v2, 0x802, v6
	v_sub_nc_u32_e32 v0, v7, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v4, 31, v0
	v_add_co_u32 v2, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[4:5], off offset:4
	global_load_b32 v3, v10, s[6:7]
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e64 v2, v3
	s_cbranch_execz .LBB1_19
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_add_co_u32 v8, vcc_lo, 0xffffe000, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, -1, v5, vcc_lo
	s_mov_b32 s11, exec_lo
	global_load_b32 v2, v[8:9], off offset:-8
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_7
; %bb.4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s13, exec_lo
	s_mov_b32 s12, exec_lo
	v_mbcnt_lo_u32_b32 v2, s13, 0
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v3, s13
	global_atomic_add_u32 v3, v10, v3, s[0:1] glc
.LBB1_6:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s12, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[11:12], 4, v[2:3]
	v_add_nc_u32_e32 v2, -1, v0
	v_add_nc_u32_e32 v3, -1, v1
	v_add_co_u32 v11, vcc_lo, s2, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	global_store_b128 v[11:12], v[0:3], off
.LBB1_7:                                ; %Flow77
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b32 v3, v[8:9], off
	v_add_nc_u32_e32 v2, 1, v0
	s_mov_b32 s11, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_11
; %bb.8:                                ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s13, exec_lo
	s_mov_b32 s12, exec_lo
	v_mbcnt_lo_u32_b32 v3, s13, 0
                                        ; implicit-def: $vgpr8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_2 Depth=1
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v8, s13
	global_atomic_add_u32 v8, v10, v8, s[0:1] glc
.LBB1_10:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, s12, v3
	v_add_nc_u32_e32 v3, -1, v1
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 4, v[8:9]
	v_add_co_u32 v8, vcc_lo, s2, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_store_b128 v[8:9], v[0:3], off
.LBB1_11:                               ; %Flow76
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_add_co_u32 v8, vcc_lo, 0x2000, v4
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v5, vcc_lo
	s_mov_b32 s11, exec_lo
	global_load_b32 v3, v[8:9], off offset:8
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_15
; %bb.12:                               ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s13, exec_lo
	s_mov_b32 s12, exec_lo
	v_mbcnt_lo_u32_b32 v3, s13, 0
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_14
; %bb.13:                               ;   in Loop: Header=BB1_2 Depth=1
	s_bcnt1_i32_b32 s13, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s13
	global_atomic_add_u32 v4, v10, v4, s[0:1] glc
.LBB1_14:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v4
	v_add_nc_u32_e32 v5, -1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s12, v3
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 4, v[3:4]
	v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
	v_add_co_u32 v11, vcc_lo, s2, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	global_store_b128 v[11:12], v[3:6], off
.LBB1_15:                               ; %Flow75
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	global_load_b32 v3, v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_19
; %bb.16:                               ;   in Loop: Header=BB1_2 Depth=1
	s_mov_b32 s12, exec_lo
	s_mov_b32 s11, exec_lo
	v_mbcnt_lo_u32_b32 v3, s12, 0
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v3
	s_cbranch_execz .LBB1_18
; %bb.17:                               ;   in Loop: Header=BB1_2 Depth=1
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s12
	global_atomic_add_u32 v4, v10, v4, s[0:1] glc
.LBB1_18:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, s11, v3
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 4, v[3:4]
	v_mov_b32_e32 v3, v6
	v_add_co_u32 v4, vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
.LBB1_19:                               ; %Flow78
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v7, s8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x3fffff, v7
	s_or_b32 s9, vcc_lo, s9
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB1_2
.LBB1_20:                               ; %Flow80
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE, .Lfunc_end1-_Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 932
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE ; -- Begin function _Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.globl	_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
	.p2align	8
	.type	_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE,@function
_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE: ; @_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
; %bb.0:
	s_load_b32 s4, s[0:1], 0x2c
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x402003, v1
	s_cbranch_execz .LBB2_7
; %bb.1:                                ; %.lr.ph
	s_load_b32 s9, s[2:3], 0x0
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b128 s[4:7], s[0:1], 0x10
	v_mov_b32_e32 v0, 0
	s_mov_b32 s10, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s9, s8
	s_add_u32 s8, s2, 0x1008010
	s_addc_u32 s9, s3, 0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 21, v2
	v_add_nc_u32_e32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 11, v2
	v_mul_i32_i24_e32 v5, 0x800, v4
	v_mul_i32_i24_e32 v2, 0x802, v4
	v_mad_i32_i24 v3, 0x800, v4, s4
	v_cmp_eq_u32_e64 s0, s5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v2, v2, v5
	v_cmp_eq_u32_e32 vcc_lo, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v2, v1, v2, 0x803
	s_and_b32 s11, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_and_saveexec_b32 s0, s11
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_add_co_u32 v6, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	global_store_b32 v[6:7], v0, off
.LBB2_4:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v5, s6, v5
	v_cmp_eq_u32_e64 s0, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, v5, v1
	s_and_b32 s11, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s11
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_2 Depth=1
	global_load_b32 v4, v0, s[8:9]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v4, off
.LBB2_6:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v1, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i32_e32 vcc_lo, 0x402002, v1
	s_or_b32 s10, vcc_lo, s10
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB2_2
.LBB2_7:                                ; %Flow31
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE, .Lfunc_end2-_Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17my_representationPiP12my_rep_class
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17my_representationPiP12my_rep_class.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14possible_movesP12my_rep_classiPiP15HIP_vector_typeIiLj4EE.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           16
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 16
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6updateP12my_rep_class15HIP_vector_typeIiLj4EE.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
