#include <math.h>

#define DEG2RAD 0.0174532925
#define RAD2DEG 57.2957795
#define FT_PER_MIN_TO_M_PER_SEC 0.00508

// nvcc -Xcompiler -fPIC -shared propagator_cuda.cu -o propagator_cuda.so


__device__
inline size_t idx(size_t i, size_t y, size_t vec_len=3){

    /* The numpy vectors are flattened for some reason. This fcn gives the correct index. */

    return i*vec_len + y;
}


__global__
void propagate(int n, float *position, float *velocity, float dt,
               float *turn_rate, float *climb_rate, float *heading){
    
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
        
    for (int i = index; i < n; i += stride){
        float horizontal_speed = sqrt(velocity[idx(i,0)]*velocity[idx(i,0)] + 
                                    velocity[idx(i,1)]*velocity[idx(i,1)]);
        heading[i] = atan2(velocity[idx(i,1)], velocity[idx(i,0)])
                                    + turn_rate[i] * dt * DEG2RAD;

        velocity[idx(i, 0)] = cos(heading[i]) * horizontal_speed;
        velocity[idx(i, 1)] = sin(heading[i]) * horizontal_speed;
        velocity[idx(i, 2)] = climb_rate[i] * FT_PER_MIN_TO_M_PER_SEC;

        position[idx(i, 0)] += velocity[idx(i, 0)] * dt;
        position[idx(i, 1)] += velocity[idx(i, 1)] * dt;
        position[idx(i, 2)] += velocity[idx(i, 2)] * dt;
    }
}


extern "C" void propagate_cuda(float *position,
                               float *velocity,
                               float dt,
                               float *turn_rate,
                               float *climb_rate,
                               float *heading,
                               int fleet_size){
    
    float *d_position, *d_velocity, *d_turn_rate, *d_climb_rate, *d_heading;
    
    cudaMalloc(&d_position, fleet_size*3*sizeof(float));
    cudaMalloc(&d_velocity, fleet_size*3*sizeof(float));
    cudaMalloc(&d_turn_rate, fleet_size*sizeof(float));
    cudaMalloc(&d_climb_rate, fleet_size*sizeof(float));
    cudaMalloc(&d_heading, fleet_size*sizeof(float));
    
    cudaMemcpy(d_position, position, fleet_size*3*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_velocity, velocity, fleet_size*3*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_turn_rate, turn_rate, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_climb_rate, climb_rate, fleet_size*sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(d_heading, heading, fleet_size*sizeof(float), cudaMemcpyHostToDevice);


    propagate<<<1, 1>>>(fleet_size, d_position, d_velocity, dt, d_turn_rate,
                        d_climb_rate, d_heading); 

    cudaDeviceSynchronize();
        
    cudaMemcpy(position, d_position, fleet_size*3*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(velocity, d_velocity, fleet_size*3*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(turn_rate, d_turn_rate, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(climb_rate, d_climb_rate, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
    cudaMemcpy(heading, d_heading, fleet_size*sizeof(float), cudaMemcpyDeviceToHost);
    
    cudaFree(position);
    cudaFree(velocity);
    cudaFree(turn_rate);
    cudaFree(climb_rate);
    cudaFree(heading); 
    return;
}

	.file	"tmpxft_00336ff5_00000000-6_propagator_cuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
	.type	_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_, @function
_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movss	%xmm0, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9propagateiPfS_fS_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_, .-_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
	.globl	_Z9propagateiPfS_fS_S_S_
	.type	_Z9propagateiPfS_fS_S_S_, @function
_Z9propagateiPfS_fS_S_S_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
	.cfi_endproc
.LFE2035:
	.size	_Z9propagateiPfS_fS_S_S_, .-_Z9propagateiPfS_fS_S_S_
	.globl	propagate_cuda
	.type	propagate_cuda, @function
propagate_cuda:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r9d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rcx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%r8, %rbx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movss	%xmm0, 28(%rsp)
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leal	(%r9,%r9,2), %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	movslq	%r15d, %rax
	leaq	56(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdx
	movq	40(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rdi
	movq	%rbx, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movq	%rdi, %rdx
	call	__cudaPushCallConfiguration@PLT
	movss	28(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L9
	movq	72(%rsp), %r9
	movq	64(%rsp), %r8
	movl	%r15d, %edi
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movq	40(%rsp), %rsi
	call	_Z38__device_stub__Z9propagateiPfS_fS_S_S_iPfS_fS_S_S_
.L9:
	call	cudaDeviceSynchronize@PLT
	movq	16(%rsp), %rdx
	movq	40(%rsp), %rsi
	movq	%r14, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	56(%rsp), %rsi
	movq	%r12, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	%rbp, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	%rbx, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	%r14, %rdi
	call	cudaFree@PLT
	movq	%r13, %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	propagate_cuda, .-propagate_cuda
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9propagateiPfS_fS_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9propagateiPfS_fS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <math.h>

#define DEG2RAD 0.0174532925
#define RAD2DEG 57.2957795
#define FT_PER_MIN_TO_M_PER_SEC 0.00508

// nvcc -Xcompiler -fPIC -shared propagator_cuda.cu -o propagator_cuda.so


__device__
inline size_t idx(size_t i, size_t y, size_t vec_len=3){

    /* The numpy vectors are flattened for some reason. This fcn gives the correct index. */

    return i*vec_len + y;
}


__global__
void propagate(int n, float *position, float *velocity, float dt,
               float *turn_rate, float *climb_rate, float *heading){
    
    int index = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;
        
    for (int i = index; i < n; i += stride){
        float horizontal_speed = sqrt(velocity[idx(i,0)]*velocity[idx(i,0)] + 
                                    velocity[idx(i,1)]*velocity[idx(i,1)]);
        heading[i] = atan2(velocity[idx(i,1)], velocity[idx(i,0)])
                                    + turn_rate[i] * dt * DEG2RAD;

        velocity[idx(i, 0)] = cos(heading[i]) * horizontal_speed;
        velocity[idx(i, 1)] = sin(heading[i]) * horizontal_speed;
        velocity[idx(i, 2)] = climb_rate[i] * FT_PER_MIN_TO_M_PER_SEC;

        position[idx(i, 0)] += velocity[idx(i, 0)] * dt;
        position[idx(i, 1)] += velocity[idx(i, 1)] * dt;
        position[idx(i, 2)] += velocity[idx(i, 2)] * dt;
    }
}


extern "C" void propagate_cuda(float *position,
                               float *velocity,
                               float dt,
                               float *turn_rate,
                               float *climb_rate,
                               float *heading,
                               int fleet_size){
    
    float *d_position, *d_velocity, *d_turn_rate, *d_climb_rate, *d_heading;
    
    hipMalloc(&d_position, fleet_size*3*sizeof(float));
    hipMalloc(&d_velocity, fleet_size*3*sizeof(float));
    hipMalloc(&d_turn_rate, fleet_size*sizeof(float));
    hipMalloc(&d_climb_rate, fleet_size*sizeof(float));
    hipMalloc(&d_heading, fleet_size*sizeof(float));
    
    hipMemcpy(d_position, position, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_velocity, velocity, fleet_size*3*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_turn_rate, turn_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_climb_rate, climb_rate, fleet_size*sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(d_heading, heading, fleet_size*sizeof(float), hipMemcpyHostToDevice);


    propagate<<<1, 1>>>(fleet_size, d_position, d_velocity, dt, d_turn_rate,
                        d_climb_rate, d_heading); 

    hipDeviceSynchronize();
        
    hipMemcpy(position, d_position, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(velocity, d_velocity, fleet_size*3*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(turn_rate, d_turn_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(climb_rate, d_climb_rate, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
    hipMemcpy(heading, d_heading, fleet_size*sizeof(float), hipMemcpyDeviceToHost);
    
    hipFree(position);
    hipFree(velocity);
    hipFree(turn_rate);
    hipFree(climb_rate);
    hipFree(heading); 
    return;
}

	.text
	.file	"propagator_cuda.hip"
	.globl	_Z24__device_stub__propagateiPfS_fS_S_S_ # -- Begin function _Z24__device_stub__propagateiPfS_fS_S_S_
	.type	_Z24__device_stub__propagateiPfS_fS_S_S_,@function
_Z24__device_stub__propagateiPfS_fS_S_S_: # @_Z24__device_stub__propagateiPfS_fS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	movq	%rsp, %rdx
	movss	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movq	%rcx, (%r10)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	24(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9propagateiPfS_fS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__propagateiPfS_fS_S_S_, .Lfunc_end0-_Z24__device_stub__propagateiPfS_fS_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	propagate_cuda                  # -- Begin function propagate_cuda
	.type	propagate_cuda,@function
propagate_cuda:                         # @propagate_cuda
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebp
	movq	%r8, 64(%rsp)                   # 8-byte Spill
	movq	%rcx, %r12
	movq	%rdx, %r13
	movss	%xmm0, 52(%rsp)                 # 4-byte Spill
	movq	%rsi, %r14
	movq	%rdi, %r15
	leal	(%rbp,%rbp,2), %eax
	movslq	%eax, %rbx
	shlq	$2, %rbx
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%rbp, 56(%rsp)                  # 8-byte Spill
	movslq	%ebp, %rbp
	shlq	$2, %rbp
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r15, 80(%rsp)                  # 8-byte Spill
	movq	%r15, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %r15                  # 8-byte Reload
	movq	%r13, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r12, 72(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r15, %rsi
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rcx
	movq	16(%rsp), %r8
	movq	8(%rsp), %r9
	movq	56(%rsp), %rdi                  # 8-byte Reload
                                        # kill: def $edi killed $edi killed $rdi
	movss	52(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z24__device_stub__propagateiPfS_fS_S_S_
.LBB1_2:
	callq	hipDeviceSynchronize
	movq	40(%rsp), %rsi
	movq	80(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	movq	%r13, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	72(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	%r15, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%r12, %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	hipFree
	movq	%r13, %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	hipFree
	movq	%r15, %rdi
	callq	hipFree
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	propagate_cuda, .Lfunc_end1-propagate_cuda
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9propagateiPfS_fS_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9propagateiPfS_fS_S_S_,@object # @_Z9propagateiPfS_fS_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z9propagateiPfS_fS_S_S_
	.p2align	3, 0x0
_Z9propagateiPfS_fS_S_S_:
	.quad	_Z24__device_stub__propagateiPfS_fS_S_S_
	.size	_Z9propagateiPfS_fS_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9propagateiPfS_fS_S_S_"
	.size	.L__unnamed_1, 25

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__propagateiPfS_fS_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9propagateiPfS_fS_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9propagateiPfS_fS_S_S_ ; -- Begin function _Z9propagateiPfS_fS_S_S_
	.globl	_Z9propagateiPfS_fS_S_S_
	.p2align	8
	.type	_Z9propagateiPfS_fS_S_S_,@function
_Z9propagateiPfS_fS_S_S_:               ; @_Z9propagateiPfS_fS_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x44
	s_load_b32 s20, s[0:1], 0x0
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s16, s4, 0xffff
	s_mov_b32 s4, exec_lo
	v_mad_u64_u32 v[1:2], null, s15, s16, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s20, v1
	s_cbranch_execz .LBB0_11
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s17, s[2:3], 0x0
	s_clause 0x3
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s21, s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b64 s[2:3], s[0:1], 0x30
	v_ashrrev_i32_e32 v2, 31, v1
	v_mad_i64_i32 v[3:4], null, v1, 12, 0
	v_mov_b32_e32 v0, 0x4016cbe4
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[7:8], 2, v[1:2]
	s_mov_b32 s12, 0xa1fae711
	s_mov_b32 s14, 0x1dd1a21f
	s_mov_b32 s22, 0
	s_mov_b32 s23, 0x3b2d2a58
	s_mov_b32 s13, 0x3f91df46
	s_mov_b32 s24, 0x7fffff
	s_mov_b32 s25, 0xb94c1982
	s_mov_b32 s15, 0x3f74cec4
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s16, s17, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s17, s16, 31
	s_mul_hi_i32 s26, s16, 12
	s_mul_i32 s27, s16, 12
	s_lshl_b64 s[18:19], s[16:17], 2
	s_mov_b32 s17, 0x37d75334
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v9, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v13, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v8, vcc_lo
	global_load_b64 v[11:12], v[9:10], off
	global_load_b32 v2, v[13:14], off
	s_waitcnt vmcnt(1)
	v_max_f32_e64 v5, |v12|, |v12|
	v_max_f32_e64 v13, |v11|, |v11|
	v_cmp_gt_f32_e64 vcc_lo, |v12|, |v11|
	v_cmp_gt_i32_e64 s0, 0, v11
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, s21, v2
	v_cmp_class_f32_e64 s1, v12, 0x204
	v_max_f32_e32 v14, v13, v5
	v_min_f32_e32 v5, v13, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e32 v15, v14
	v_frexp_exp_i32_f32_e32 v14, v14
	v_rcp_f32_e32 v13, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_frexp_exp_i32_f32_e32 v15, v5
	v_frexp_mant_f32_e32 v5, v5
	v_sub_nc_u32_e32 v14, v15, v14
	v_cvt_f64_f32_e32 v[15:16], v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, v5, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v5, v5, v14
	v_mul_f32_e32 v13, v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v14, s23, v13, 0xbc7a590c
	v_fmaak_f32 v14, v13, v14, 0x3d29fb3f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v14, v13, v14, 0xbd97d4d7
	v_fmaak_f32 v14, v13, v14, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v14, v13, v14, 0xbe1160e6
	v_fmaak_f32 v14, v13, v14, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v14, v13, v14, 0xbeaaaa62
	v_mul_f32_e32 v13, v13, v14
	v_cndmask_b32_e64 v14, 0, 0x40490fdb, s0
	v_cmp_class_f32_e64 s0, v11, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v5, v13
	v_sub_f32_e32 v13, 0x3fc90fdb, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v13, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v11
	v_sub_f32_e32 v13, 0x40490fdb, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v5, v5, v13, vcc_lo
	v_cndmask_b32_e32 v13, 0x3f490fdb, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v12
	v_cndmask_b32_e32 v5, v5, v14, vcc_lo
	s_and_b32 vcc_lo, s0, s1
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v13, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v11, v12
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v5, 0x7fffffff, v5, v12
	v_cvt_f64_f32_e32 v[13:14], v5
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[15:16], s[12:13], v[13:14]
                                        ; implicit-def: $vgpr15
	v_cvt_f32_f64_e32 v2, v[13:14]
	v_add_co_u32 v13, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v8, vcc_lo
	global_store_b32 v[13:14], v2, off
	v_cmpx_ngt_f32_e64 0x48000000, |v2|
	s_xor_b32 s28, exec_lo, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v20, 0x7fffffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v23, v20, s24, 0x800000
	v_mad_u64_u32 v[15:16], null, 0xfe5163ab, v23, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v5, v16
	v_lshrrev_b32_e32 v20, 23, v20
	v_mad_u64_u32 v[16:17], null, 0x3c439041, v23, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v21, 0xffffff88, v20
	v_cmp_lt_u32_e32 vcc_lo, 63, v21
	v_cndmask_b32_e64 v22, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v17 :: v_dual_add_nc_u32 v22, v22, v21
	v_mad_u64_u32 v[17:18], null, 0xdb629599, v23, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v22
	v_cndmask_b32_e32 v15, v17, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, 0, 0xffffffe0, s0
	v_dual_mov_b32 v5, v18 :: v_dual_add_nc_u32 v24, v24, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[18:19], null, 0xf534ddc0, v23, v[5:6]
	v_cmp_lt_u32_e64 s1, 31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v5, v19 :: v_dual_cndmask_b32 v16, v18, v16
	v_mad_u64_u32 v[19:20], null, 0xfc2757d1, v23, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v16, v15, s0
	v_mov_b32_e32 v5, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[20:21], null, 0x4e441529, v23, v[5:6]
	v_mov_b32_e32 v5, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[21:22], null, 0xa2f9836e, v23, v[5:6]
	v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v23, v20, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v5, v5, v24
	v_dual_cndmask_b32 v21, v21, v19 :: v_dual_cndmask_b32 v20, v22, v20
	v_cndmask_b32_e32 v19, v19, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v22, 32, v5
	v_cndmask_b32_e64 v18, v21, v23, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v20, v21, s0
	v_cndmask_b32_e64 v21, v23, v19, s0
	v_cndmask_b32_e64 v19, v19, v16, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v18, v18, v21, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, v21, v19, s1
	v_cndmask_b32_e64 v15, v19, v15, s1
	v_alignbit_b32 v23, v20, v18, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v17, v18, v21, v22
	v_dual_cndmask_b32 v5, v23, v20 :: v_dual_cndmask_b32 v16, v17, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v21, v15, v22
	v_bfe_u32 v17, v5, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v5, v16, 30
	v_cndmask_b32_e32 v20, v20, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, 0, v17
	v_alignbit_b32 v16, v16, v20, 30
	v_alignbit_b32 v15, v20, v15, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v18, v18, v19
	v_xor_b32_e32 v16, v16, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v15, v19
	v_lshrrev_b32_e32 v19, 29, v5
	v_clz_i32_u32_e32 v21, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v19, 31, v19
	v_min_u32_e32 v21, 32, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v22, 0.5, v19
	v_sub_nc_u32_e32 v20, 31, v21
	v_lshlrev_b32_e32 v23, 23, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v18, v16, v20
	v_alignbit_b32 v15, v16, v15, v20
	v_sub_nc_u32_e32 v22, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v18, v15, 9
	v_lshrrev_b32_e32 v18, 9, v18
	v_clz_i32_u32_e32 v20, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v20, 32, v20
	v_sub_nc_u32_e32 v24, 31, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v16, v15, v24
	v_or_b32_e32 v16, v18, v22
	v_add_lshl_u32 v18, v20, v21, 23
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v20, 0x3fc90fda, v16
	v_sub_nc_u32_e32 v15, v15, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v18, 0x3fc90fda, v16, -v20
	v_add_nc_u32_e32 v15, 0x33000000, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, 0x33a22168, v16
	v_or_b32_e32 v15, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, 0x3fc90fda, v15
	v_lshrrev_b32_e32 v15, 30, v5
	v_add_f32_e32 v5, v20, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v15, v17, v15
.LBB0_4:                                ; %Flow100
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s28
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v5, 0x3f22f983, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v15, v5
	v_fma_f32 v5, 0xbfc90fda, v15, |v2|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v15
	v_fmac_f32_e32 v5, 0xa7c234c4, v15
	v_cvt_i32_f32_e32 v15, v15
; %bb.6:                                ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f32_e32 v12, v12, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v16, v5, v5
	v_and_b32_e32 v22, 1, v15
	v_lshlrev_b32_e32 v15, 30, v15
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v12, v11, v11 :: v_dual_fmaak_f32 v17, s25, v16, 0x3c0881c4
	v_mul_f32_e32 v11, 0x4f800000, v12
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v11, v12, v11, vcc_lo
	v_sqrt_f32_e32 v12, v11
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v20, 1, v12
	v_add_nc_u32_e32 v19, -1, v12
	v_fmaak_f32 v17, v16, v17, 0xbe2aaa9d
	v_fmaak_f32 v18, s17, v16, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v23, -v20, v12, v11
	v_fma_f32 v21, -v19, v12, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v17, v16, v17
	v_fmaak_f32 v18, v16, v18, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s0, 0, v21
	v_dual_fmac_f32 v5, v5, v17 :: v_dual_fmaak_f32 v18, v16, v18, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v12, v19, s0
	v_cmp_lt_f32_e64 s0, 0, v23
	v_fma_f32 v16, v16, v18, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v20, s0
	v_cmp_eq_u32_e64 s0, 0, v22
	v_cndmask_b32_e64 v5, -v5, v16, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v16, 0x37800000, v12
	v_dual_cndmask_b32 v12, v12, v16 :: v_dual_and_b32 v15, 0x80000000, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v15, v5
	v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
	v_cndmask_b32_e32 v2, 0x7fc00000, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v11, 0x260
                                        ; implicit-def: $vgpr5
	v_cndmask_b32_e32 v11, v12, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, v11, v2
	global_store_b32 v[9:10], v2, off
	global_load_b32 v12, v[13:14], off
                                        ; implicit-def: $vgpr14
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v13, 0x7fffffff, v12
	v_cmpx_ngt_f32_e64 0x48000000, |v12|
	s_xor_b32 s28, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v22, v13, s24, 0x800000
	v_lshrrev_b32_e32 v19, 23, v13
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v22, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v20, 0xffffff88, v19
	v_cmp_lt_u32_e32 vcc_lo, 63, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v5, v15
	v_cndmask_b32_e64 v21, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[15:16], null, 0x3c439041, v22, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v21, v21, v20
	v_mov_b32_e32 v5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v21
	v_mad_u64_u32 v[16:17], null, 0xdb629599, v22, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v23, v23, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v5, v17 :: v_dual_cndmask_b32 v14, v16, v14
	v_cmp_lt_u32_e64 s1, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0xf534ddc0, v22, v[5:6]
	v_mov_b32_e32 v5, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v17, v15, vcc_lo
	v_mad_u64_u32 v[18:19], null, 0xfc2757d1, v22, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v15, v14, s0
	v_mov_b32_e32 v5, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[19:20], null, 0x4e441529, v22, v[5:6]
	v_mov_b32_e32 v5, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[20:21], null, 0xa2f9836e, v22, v[5:6]
	v_cndmask_b32_e64 v5, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v22, v19, v17 :: v_dual_add_nc_u32 v5, v5, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v20, v20, v18 :: v_dual_cndmask_b32 v19, v21, v19
	v_cndmask_b32_e32 v18, v18, v16, vcc_lo
	v_sub_nc_u32_e32 v21, 32, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v20, v22, s0
	v_cndmask_b32_e64 v19, v19, v20, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v20, v22, v18, s0
	v_cndmask_b32_e64 v18, v18, v15, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e64 v19, v19, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v20, s1
	v_cndmask_b32_e64 v20, v20, v18, s1
	v_cndmask_b32_e64 v14, v18, v14, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v19, v17, v21
	v_alignbit_b32 v16, v17, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v22, v19, vcc_lo
	v_cndmask_b32_e32 v15, v16, v17, vcc_lo
	v_alignbit_b32 v19, v20, v14, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v16, v5, 29, 1
	v_alignbit_b32 v17, v5, v15, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v19, v19, v20, vcc_lo
	v_sub_nc_u32_e32 v18, 0, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v15, v19, 30
	v_alignbit_b32 v14, v19, v14, 30
	v_xor_b32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v15, v18
	v_xor_b32_e32 v14, v14, v18
	v_lshrrev_b32_e32 v18, 29, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v20, v17
	v_lshlrev_b32_e32 v18, 31, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v20, 32, v20
	v_or_b32_e32 v21, 0.5, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, 31, v20
	v_lshlrev_b32_e32 v22, 23, v20
	v_alignbit_b32 v17, v17, v15, v19
	v_alignbit_b32 v14, v15, v14, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v21, v21, v22
	v_alignbit_b32 v15, v17, v14, 9
	v_lshrrev_b32_e32 v17, 9, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v19, v15
	v_min_u32_e32 v19, 32, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v23, 31, v19
	v_alignbit_b32 v14, v15, v14, v23
	v_or_b32_e32 v15, v17, v21
	v_add_lshl_u32 v17, v19, v20, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v14, 9, v14
	v_mul_f32_e32 v19, 0x3fc90fda, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, v14, v17
	v_fma_f32 v17, 0x3fc90fda, v15, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0x33000000, v14
	v_fmac_f32_e32 v17, 0x33a22168, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v14, v14, v18
	v_fmac_f32_e32 v17, 0x3fc90fda, v14
	v_lshrrev_b32_e32 v14, 30, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v5, v19, v17 :: v_dual_add_nc_u32 v14, v16, v14
.LBB0_8:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s28
; %bb.9:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v5, 0x3f22f983, |v12|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v14, v5
	v_fma_f32 v5, 0xbfc90fda, v14, |v12|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v14
	v_fmac_f32_e32 v5, 0xa7c234c4, v14
	v_cvt_i32_f32_e32 v14, v14
; %bb.10:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v15, v5, v5 :: v_dual_and_b32 v18, 1, v14
	v_xor_b32_e32 v13, v13, v12
	v_add_nc_u32_e32 v1, s16, v1
	v_lshlrev_b32_e32 v14, 30, v14
	v_fmaak_f32 v16, s25, v15, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v14, 0x80000000, v14
	v_fmaak_f32 v16, v15, v16, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v17, s17, v15, 0xbab64f3b :: v_dual_mul_f32 v16, v15, v16
	v_fmaak_f32 v17, v15, v17, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, v5, v16
	v_fmaak_f32 v17, v15, v17, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, v15, v17, 1.0
	v_cndmask_b32_e32 v5, v15, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v12, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor3_b32 v5, v13, v14, v5
	v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v5, v11, v5
	v_add_co_u32 v11, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v8, vcc_lo
	global_store_b32 v[9:10], v5, off offset:4
	v_add_co_u32 v14, vcc_lo, s4, v3
	global_load_b32 v5, v[11:12], off
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, v7, s18
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v8, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s20, v1
	s_add_u32 s4, s4, s27
	s_addc_u32 s5, s5, s26
	s_add_u32 s6, s6, s27
	s_addc_u32 s7, s7, s26
	s_or_b32 s22, vcc_lo, s22
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[11:12], v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[11:12], s[14:15]
	v_cvt_f32_f64_e32 v5, v[11:12]
	global_store_b32 v[9:10], v5, off offset:8
	global_load_b96 v[11:13], v[14:15], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v2, s21, v2, v11
	global_store_b32 v[14:15], v2, off
	global_load_b32 v2, v[9:10], off offset:4
	s_waitcnt vmcnt(0)
	v_fma_f32 v2, s21, v2, v12
	global_store_b32 v[14:15], v2, off offset:4
	global_load_b32 v2, v[9:10], off offset:8
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v13, s21, v2
	global_store_b32 v[14:15], v13, off offset:8
	s_and_not1_b32 exec_lo, exec_lo, s22
	s_cbranch_execnz .LBB0_2
.LBB0_11:                               ; %Flow102
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9propagateiPfS_fS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 29
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9propagateiPfS_fS_S_S_, .Lfunc_end0-_Z9propagateiPfS_fS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2864
; NumSgprs: 31
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 31
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9propagateiPfS_fS_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     31
    .sgpr_spill_count: 0
    .symbol:         _Z9propagateiPfS_fS_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     25
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
