/* 
 * Copyright (C) 2010, Florian Kummer, Technische Universitaet Darmstadt, Fachgebiet fuer Stroemungsmechanik
 *
 * Use, modification and distribution is subject to the Boost Software
 * License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at
 * http://www.boost.org/LICENSE_1_0.txt)
 *  
 * Authors: Christoph Busold
 * 
 */

extern __shared__ char smem[];

extern "C" __global__ void sparseMultiply(double* values, int* colIdx, int* rowStart, double* result, double* x, double alpha, double beta, int size) {
	// Dynamically allocated shared memory, should be BlockDim.x + 1 ints (see cuFuncSetSharedSize host code)
	int* sharedRowStart = (int*)smem;
	
	// Indices
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	
	double rowacc = 0.0;
	
	// Each thread loads one element of rowStart
	if(idx < size) {
		sharedRowStart[tid] = rowStart[idx];
	}
	// The first thread loads additionally the next element, needed by the last thread
	if(tid == 0) {
		int loadIdx = min((blockIdx.x + 1) * blockDim.x, size);
		int storIdx = size % blockDim.x > 0 && idx + blockDim.x >= size ? size % blockDim.x : blockDim.x;
		sharedRowStart[storIdx] = rowStart[loadIdx];
	}
	__syncthreads();
	
	if(idx < size) {
		// Multiply and sum up data of this row
		for(int i = sharedRowStart[tid]; i < sharedRowStart[tid + 1]; i++) {
			rowacc += values[i] * x[colIdx[i]];
		}
		
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

extern "C" __global__ void accumulateExternal(double* data, int* indices, double* rcvBuffer, double alpha, int size) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	
	if(idx < size) {
		data[indices[idx]] += rcvBuffer[idx] * alpha;
	}
}

// In this kernel each block computes multiple cell rows 
// IMPORTANT: All cell rows must have the same number of cells!
//            Otherwise sync in kernel might fail, causing crash or incorrect behaviour!
extern "C" __global__ void blockMultiply2(double* cellData, double* xData, int* cellColIdx, double* result, double alpha, double beta, int cellsize, int cellrowsperblock, int cellsperrow, int stride, int size) {
	// Dynamically allocated shared memory, should be blockDim.x doubles for xData
	double* sharedData = (double*)smem;
	// Start cell index of this thread
	int* start = (int*)&sharedData[blockDim.x];
	// Column of this thread's cell
	int* colIdx = (int*)&start[cellrowsperblock];
	
	// Global index
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	// Number of the cell this thread is in
	int cellid = tid / cellsize;
	// Thread index inside this cell
	int cid = tid % cellsize;
	
	double rowacc = 0.0;
	double value;
	
	// Load start index for every cell row in this block
	if(tid < cellrowsperblock) {
		start[tid] = (cellrowsperblock * blockIdx.x + tid) * cellsperrow;
	}
	__syncthreads();
	
	// Loop over all cells, discard overlapping threads inside because of sync
	for(int i = 0; i < cellsperrow; i++) {
		// Load column index for every cell
		if(tid < cellrowsperblock) {
			colIdx[tid] = cellColIdx[start[tid] + i];
		}
		__syncthreads();
		
		// No overlapping threads
		if(idx < size) {
			// Load x at colIdx location into shared memory
			// colIdx * cellsize is the start index at this column
			// cid is the row index of this thread
			sharedData[tid] = xData[colIdx[cellid] * cellsize + cid];
		}
		__syncthreads();
		
		// No overlapping threads
		if(idx < size) {
			// Loop over all columns of this cell
			for(int col = 0; col < cellsize; col++) {
				// Load value of this column
				// cell * cellsize * cellsize is the start index of the current cell
				// col * cellsize is the start index of the current column
				// cid is the row index of this thread
				value = cellData[(start[cellid] + i) * stride + col * cellsize + cid];
				// Multiply value with x from sharedMemory
				// cellid * cellsize is the offset for the cell this thread is in
				// col is the column index of this loop cycle
				rowacc += value * sharedData[cellid * cellsize + col];
			}
		}
		
		__syncthreads();
	}
	
	// No overlapping threads
	if(idx < size) {
		// Write back result 
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

// In this kernel each block computes one cell row (block size equals cell size)
extern "C" __global__ void blockMultiply(double* cellData, double* xData, int* cellColIdx, int* cellRowStart, double* result, double dia, int cellsize, int size) {
	double* sharedData = (double*)smem;
	__shared__ int colIdx;
	__shared__ int start;
	__shared__ int end;
	
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	
	double rowacc = 0.0;
	double value;
	
	if(tid == 0) {
		start = cellRowStart[blockIdx.x    ];
		end   = cellRowStart[blockIdx.x + 1];
	}
	__syncthreads();
	
	for(int cell = start; cell < end; cell++) {
		if(tid == 0) {
			colIdx = cellColIdx[cell];
		}
		__syncthreads();
		
		if(idx < size) {
			sharedData[tid] = xData[colIdx * cellsize + tid];
		}
		__syncthreads();
		
		if(idx < size) {
			for(int col = 0; col < cellsize; col++) {
				value = cellData[cell * cellsize * cellsize + col * cellsize + tid];
				rowacc += value * sharedData[col];
			}
		}
	}
	
	if(idx < size) {
		rowacc += dia * xData[idx];
		result[idx] += rowacc;
	}
}

// ELLPACKmod format
extern "C" __global__ void ellMultiply(double* valData, int* colIdxData, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	// Add offsets to the start of this block's value and column data pointers
	valData    += blockIdx.x * colCount * valStride;
	colIdxData += blockIdx.x * colCount * colStride;
	
	int valIdx;
	int colIdx;
	
	// No sync in this kernel, therefore overlapping threads are discarded here
	if(idx < size) {
		double rowacc = 0.0;
		
		// Loop over all columns
		for(int col = 0; col < colCount; col++) {
			// Index of the value and column index to load
			valIdx = col * valStride + threadIdx.x;
			colIdx = col * colStride + threadIdx.x;
			// Load value and multiply with x at column of this value
			rowacc += valData[valIdx] * xData[colIdxData[colIdx]];
		}
		
		// Write result back
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

// ManualCacheELLPACK format
extern "C" __global__ void mcellMultiply(double* valData, unsigned short* colIdxData, int* xSubStart, int* blockSubVector, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	// Add offsets to the start of this block's value and column data pointers
	valData    += blockIdx.x * colCount * valStride;
	colIdxData += blockIdx.x * colCount * colStride;
	
	double* xSub = (double*)smem;
	__shared__ int xStart;
	__shared__ int xLength;
	
	int valIdx;
	unsigned short colIdx;
	
	if(tid == 0) {
		xStart  = xSubStart[blockIdx.x    ];
		xLength = xSubStart[blockIdx.x + 1] - xStart;
	}
	
	__syncthreads();
	
	blockSubVector += xStart;
	int ldIdx = tid;
	
	while(ldIdx < xLength) {
		xSub[ldIdx] = xData[blockSubVector[ldIdx]];
		ldIdx += blockDim.x;
	}
	
	__syncthreads();
	
	// No sync inside this loop, therefore overlapping threads are discarded here
	if(idx < size) {
		double rowacc = 0.0;
		
		// Loop over all columns
		for(int col = 0; col < colCount; col++) {
			// Index of the value and column index to load
			valIdx = col * valStride + tid;
			colIdx = col * colStride + tid;
			// Load value and multiply with x at column of this value
			rowacc += valData[valIdx] * xSub[colIdxData[colIdx]];
		}
		
		// Write result back
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

	.file	"tmpxft_002ead17_00000000-6_CudaMatrixKernelDP.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
	.type	_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi, @function
_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 4(%rsp)
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	sparseMultiply(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi, .-_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
	.globl	sparseMultiply
	.type	sparseMultiply, @function
sparseMultiply:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z14sparseMultiplyPdPiS0_S_S_ddiPdPiS0_S_S_ddi
	.cfi_endproc
.LFE2033:
	.size	sparseMultiply, .-sparseMultiply
	.globl	_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
	.type	_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di, @function
_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	accumulateExternal(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L8:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di, .-_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
	.globl	accumulateExternal
	.type	accumulateExternal, @function
accumulateExternal:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z18accumulateExternalPdPiS_diPdPiS_di
	.cfi_endproc
.LFE2035:
	.size	accumulateExternal, .-accumulateExternal
	.globl	_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
	.type	_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii, @function
_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	64(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	72(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	72(%rsp)
	.cfi_def_cfa_offset 248
	leaq	blockMultiply2(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 256
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L13:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii, .-_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
	.globl	blockMultiply2
	.type	blockMultiply2, @function
blockMultiply2:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z14blockMultiply2PdS_PiS_ddiiiiiPdS_PiS_ddiiiii
	.cfi_endproc
.LFE2037:
	.size	blockMultiply2, .-blockMultiply2
	.globl	_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
	.type	_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii, @function
_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movl	%r9d, 12(%rsp)
	movsd	%xmm0, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	80(%rsp)
	.cfi_def_cfa_offset 232
	leaq	blockMultiply(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 240
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L18:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii, .-_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
	.globl	blockMultiply
	.type	blockMultiply, @function
blockMultiply:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z13blockMultiplyPdS_PiS0_S_diiPdS_PiS0_S_dii
	.cfi_endproc
.LFE2039:
	.size	blockMultiply, .-blockMultiply
	.globl	_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
	.type	_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii, @function
_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	ellMultiply(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L23:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii, .-_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
	.globl	ellMultiply
	.type	ellMultiply, @function
ellMultiply:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z11ellMultiplyPdPiS_S_ddiiiiPdPiS_S_ddiiii
	.cfi_endproc
.LFE2041:
	.size	ellMultiply, .-ellMultiply
	.globl	_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
	.type	_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii, @function
_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movsd	%xmm0, 8(%rsp)
	movsd	%xmm1, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	80(%rsp)
	.cfi_def_cfa_offset 264
	leaq	mcellMultiply(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 272
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L28:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii, .-_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
	.globl	mcellMultiply
	.type	mcellMultiply, @function
mcellMultiply:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z13mcellMultiplyPdPtPiS1_S_S_ddiiiiPdPtPiS1_S_S_ddiiii
	.cfi_endproc
.LFE2043:
	.size	mcellMultiply, .-mcellMultiply
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"mcellMultiply"
.LC1:
	.string	"ellMultiply"
.LC2:
	.string	"blockMultiply"
.LC3:
	.string	"blockMultiply2"
.LC4:
	.string	"accumulateExternal"
.LC5:
	.string	"sparseMultiply"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2045:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	mcellMultiply(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	ellMultiply(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	blockMultiply(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	blockMultiply2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	accumulateExternal(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	sparseMultiply(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2045:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/* 
 * Copyright (C) 2010, Florian Kummer, Technische Universitaet Darmstadt, Fachgebiet fuer Stroemungsmechanik
 *
 * Use, modification and distribution is subject to the Boost Software
 * License, Version 1.0. (See accompanying file LICENSE_1_0.txt or copy at
 * http://www.boost.org/LICENSE_1_0.txt)
 *  
 * Authors: Christoph Busold
 * 
 */

extern __shared__ char smem[];

extern "C" __global__ void sparseMultiply(double* values, int* colIdx, int* rowStart, double* result, double* x, double alpha, double beta, int size) {
	// Dynamically allocated shared memory, should be BlockDim.x + 1 ints (see cuFuncSetSharedSize host code)
	int* sharedRowStart = (int*)smem;
	
	// Indices
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	
	double rowacc = 0.0;
	
	// Each thread loads one element of rowStart
	if(idx < size) {
		sharedRowStart[tid] = rowStart[idx];
	}
	// The first thread loads additionally the next element, needed by the last thread
	if(tid == 0) {
		int loadIdx = min((blockIdx.x + 1) * blockDim.x, size);
		int storIdx = size % blockDim.x > 0 && idx + blockDim.x >= size ? size % blockDim.x : blockDim.x;
		sharedRowStart[storIdx] = rowStart[loadIdx];
	}
	__syncthreads();
	
	if(idx < size) {
		// Multiply and sum up data of this row
		for(int i = sharedRowStart[tid]; i < sharedRowStart[tid + 1]; i++) {
			rowacc += values[i] * x[colIdx[i]];
		}
		
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

extern "C" __global__ void accumulateExternal(double* data, int* indices, double* rcvBuffer, double alpha, int size) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	
	if(idx < size) {
		data[indices[idx]] += rcvBuffer[idx] * alpha;
	}
}

// In this kernel each block computes multiple cell rows 
// IMPORTANT: All cell rows must have the same number of cells!
//            Otherwise sync in kernel might fail, causing crash or incorrect behaviour!
extern "C" __global__ void blockMultiply2(double* cellData, double* xData, int* cellColIdx, double* result, double alpha, double beta, int cellsize, int cellrowsperblock, int cellsperrow, int stride, int size) {
	// Dynamically allocated shared memory, should be blockDim.x doubles for xData
	double* sharedData = (double*)smem;
	// Start cell index of this thread
	int* start = (int*)&sharedData[blockDim.x];
	// Column of this thread's cell
	int* colIdx = (int*)&start[cellrowsperblock];
	
	// Global index
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	// Number of the cell this thread is in
	int cellid = tid / cellsize;
	// Thread index inside this cell
	int cid = tid % cellsize;
	
	double rowacc = 0.0;
	double value;
	
	// Load start index for every cell row in this block
	if(tid < cellrowsperblock) {
		start[tid] = (cellrowsperblock * blockIdx.x + tid) * cellsperrow;
	}
	__syncthreads();
	
	// Loop over all cells, discard overlapping threads inside because of sync
	for(int i = 0; i < cellsperrow; i++) {
		// Load column index for every cell
		if(tid < cellrowsperblock) {
			colIdx[tid] = cellColIdx[start[tid] + i];
		}
		__syncthreads();
		
		// No overlapping threads
		if(idx < size) {
			// Load x at colIdx location into shared memory
			// colIdx * cellsize is the start index at this column
			// cid is the row index of this thread
			sharedData[tid] = xData[colIdx[cellid] * cellsize + cid];
		}
		__syncthreads();
		
		// No overlapping threads
		if(idx < size) {
			// Loop over all columns of this cell
			for(int col = 0; col < cellsize; col++) {
				// Load value of this column
				// cell * cellsize * cellsize is the start index of the current cell
				// col * cellsize is the start index of the current column
				// cid is the row index of this thread
				value = cellData[(start[cellid] + i) * stride + col * cellsize + cid];
				// Multiply value with x from sharedMemory
				// cellid * cellsize is the offset for the cell this thread is in
				// col is the column index of this loop cycle
				rowacc += value * sharedData[cellid * cellsize + col];
			}
		}
		
		__syncthreads();
	}
	
	// No overlapping threads
	if(idx < size) {
		// Write back result 
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

// In this kernel each block computes one cell row (block size equals cell size)
extern "C" __global__ void blockMultiply(double* cellData, double* xData, int* cellColIdx, int* cellRowStart, double* result, double dia, int cellsize, int size) {
	double* sharedData = (double*)smem;
	__shared__ int colIdx;
	__shared__ int start;
	__shared__ int end;
	
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	
	double rowacc = 0.0;
	double value;
	
	if(tid == 0) {
		start = cellRowStart[blockIdx.x    ];
		end   = cellRowStart[blockIdx.x + 1];
	}
	__syncthreads();
	
	for(int cell = start; cell < end; cell++) {
		if(tid == 0) {
			colIdx = cellColIdx[cell];
		}
		__syncthreads();
		
		if(idx < size) {
			sharedData[tid] = xData[colIdx * cellsize + tid];
		}
		__syncthreads();
		
		if(idx < size) {
			for(int col = 0; col < cellsize; col++) {
				value = cellData[cell * cellsize * cellsize + col * cellsize + tid];
				rowacc += value * sharedData[col];
			}
		}
	}
	
	if(idx < size) {
		rowacc += dia * xData[idx];
		result[idx] += rowacc;
	}
}

// ELLPACKmod format
extern "C" __global__ void ellMultiply(double* valData, int* colIdxData, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	// Add offsets to the start of this block's value and column data pointers
	valData    += blockIdx.x * colCount * valStride;
	colIdxData += blockIdx.x * colCount * colStride;
	
	int valIdx;
	int colIdx;
	
	// No sync in this kernel, therefore overlapping threads are discarded here
	if(idx < size) {
		double rowacc = 0.0;
		
		// Loop over all columns
		for(int col = 0; col < colCount; col++) {
			// Index of the value and column index to load
			valIdx = col * valStride + threadIdx.x;
			colIdx = col * colStride + threadIdx.x;
			// Load value and multiply with x at column of this value
			rowacc += valData[valIdx] * xData[colIdxData[colIdx]];
		}
		
		// Write result back
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

// ManualCacheELLPACK format
extern "C" __global__ void mcellMultiply(double* valData, unsigned short* colIdxData, int* xSubStart, int* blockSubVector, double* xData, double* result, double alpha, double beta, int size, int colCount, int valStride, int colStride) {
	int idx = blockIdx.x * blockDim.x + threadIdx.x;
	int tid = threadIdx.x;
	// Add offsets to the start of this block's value and column data pointers
	valData    += blockIdx.x * colCount * valStride;
	colIdxData += blockIdx.x * colCount * colStride;
	
	double* xSub = (double*)smem;
	__shared__ int xStart;
	__shared__ int xLength;
	
	int valIdx;
	unsigned short colIdx;
	
	if(tid == 0) {
		xStart  = xSubStart[blockIdx.x    ];
		xLength = xSubStart[blockIdx.x + 1] - xStart;
	}
	
	__syncthreads();
	
	blockSubVector += xStart;
	int ldIdx = tid;
	
	while(ldIdx < xLength) {
		xSub[ldIdx] = xData[blockSubVector[ldIdx]];
		ldIdx += blockDim.x;
	}
	
	__syncthreads();
	
	// No sync inside this loop, therefore overlapping threads are discarded here
	if(idx < size) {
		double rowacc = 0.0;
		
		// Loop over all columns
		for(int col = 0; col < colCount; col++) {
			// Index of the value and column index to load
			valIdx = col * valStride + tid;
			colIdx = col * colStride + tid;
			// Load value and multiply with x at column of this value
			rowacc += valData[valIdx] * xSub[colIdxData[colIdx]];
		}
		
		// Write result back
		result[idx] = result[idx] * beta + rowacc * alpha;
	}
}

	.text
	.file	"CudaMatrixKernelDP.hip"
	.globl	__device_stub__sparseMultiply   # -- Begin function __device_stub__sparseMultiply
	.type	__device_stub__sparseMultiply,@function
__device_stub__sparseMultiply:          # @__device_stub__sparseMultiply
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	24(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movl	%r9d, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	movq	%r11, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sparseMultiply, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__sparseMultiply, .Lfunc_end0-__device_stub__sparseMultiply
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__accumulateExternal # -- Begin function __device_stub__accumulateExternal
	.type	__device_stub__accumulateExternal,@function
__device_stub__accumulateExternal:      # @__device_stub__accumulateExternal
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	12(%rsp), %r8
	movl	%ecx, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r8, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$accumulateExternal, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__accumulateExternal, .Lfunc_end1-__device_stub__accumulateExternal
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__blockMultiply2   # -- Begin function __device_stub__blockMultiply2
	.type	__device_stub__blockMultiply2,@function
__device_stub__blockMultiply2:          # @__device_stub__blockMultiply2
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movl	%r8d, (%r11)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$blockMultiply2, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__blockMultiply2, .Lfunc_end2-__device_stub__blockMultiply2
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__blockMultiply    # -- Begin function __device_stub__blockMultiply
	.type	__device_stub__blockMultiply,@function
__device_stub__blockMultiply:           # @__device_stub__blockMultiply
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	12(%rsp), %r10
	movl	%r9d, (%r10)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$blockMultiply, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__blockMultiply, .Lfunc_end3-__device_stub__blockMultiply
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__ellMultiply      # -- Begin function __device_stub__ellMultiply
	.type	__device_stub__ellMultiply,@function
__device_stub__ellMultiply:             # @__device_stub__ellMultiply
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	12(%rsp), %r11
	movl	%r8d, (%r11)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$ellMultiply, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	__device_stub__ellMultiply, .Lfunc_end4-__device_stub__ellMultiply
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__mcellMultiply    # -- Begin function __device_stub__mcellMultiply
	.type	__device_stub__mcellMultiply,@function
__device_stub__mcellMultiply:           # @__device_stub__mcellMultiply
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	24(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	16(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r9, 48(%rbx)
	movq	%r10, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$mcellMultiply, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	__device_stub__mcellMultiply, .Lfunc_end5-__device_stub__mcellMultiply
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sparseMultiply, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$accumulateExternal, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$blockMultiply2, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$blockMultiply, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$ellMultiply, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$mcellMultiply, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	sparseMultiply,@object          # @sparseMultiply
	.section	.rodata,"a",@progbits
	.globl	sparseMultiply
	.p2align	3, 0x0
sparseMultiply:
	.quad	__device_stub__sparseMultiply
	.size	sparseMultiply, 8

	.type	accumulateExternal,@object      # @accumulateExternal
	.globl	accumulateExternal
	.p2align	3, 0x0
accumulateExternal:
	.quad	__device_stub__accumulateExternal
	.size	accumulateExternal, 8

	.type	blockMultiply2,@object          # @blockMultiply2
	.globl	blockMultiply2
	.p2align	3, 0x0
blockMultiply2:
	.quad	__device_stub__blockMultiply2
	.size	blockMultiply2, 8

	.type	blockMultiply,@object           # @blockMultiply
	.globl	blockMultiply
	.p2align	3, 0x0
blockMultiply:
	.quad	__device_stub__blockMultiply
	.size	blockMultiply, 8

	.type	ellMultiply,@object             # @ellMultiply
	.globl	ellMultiply
	.p2align	3, 0x0
ellMultiply:
	.quad	__device_stub__ellMultiply
	.size	ellMultiply, 8

	.type	mcellMultiply,@object           # @mcellMultiply
	.globl	mcellMultiply
	.p2align	3, 0x0
mcellMultiply:
	.quad	__device_stub__mcellMultiply
	.size	mcellMultiply, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"sparseMultiply"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"accumulateExternal"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"blockMultiply2"
	.size	.L__unnamed_3, 15

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"blockMultiply"
	.size	.L__unnamed_4, 14

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"ellMultiply"
	.size	.L__unnamed_5, 12

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"mcellMultiply"
	.size	.L__unnamed_6, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__sparseMultiply
	.addrsig_sym __device_stub__accumulateExternal
	.addrsig_sym __device_stub__blockMultiply2
	.addrsig_sym __device_stub__blockMultiply
	.addrsig_sym __device_stub__ellMultiply
	.addrsig_sym __device_stub__mcellMultiply
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym sparseMultiply
	.addrsig_sym accumulateExternal
	.addrsig_sym blockMultiply2
	.addrsig_sym blockMultiply
	.addrsig_sym ellMultiply
	.addrsig_sym mcellMultiply
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	sparseMultiply          ; -- Begin function sparseMultiply
	.globl	sparseMultiply
	.p2align	8
	.type	sparseMultiply,@function
sparseMultiply:                         ; @sparseMultiply
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b32 s3, s[0:1], 0x38
	s_load_b256 s[4:11], s[0:1], 0x0
	v_lshl_add_u32 v3, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s14, s15, s12
	v_add_nc_u32_e32 v1, s14, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, s2, s8, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s2, s9, v5, s2
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v3, v4
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s13, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_add_i32 s14, s14, s12
	v_cvt_f64_i32_e32 v[4:5], s3
	v_cvt_f64_u32_e32 v[6:7], s14
	v_cvt_f32_u32_e32 v0, s12
	s_sub_i32 s14, 0, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s2, v0
	s_mul_i32 s14, s14, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s14, s2, s14
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_hi_u32 s14, s3, s2
	v_min_f64 v[4:5], v[6:7], v[4:5]
	s_mul_i32 s14, s14, s12
	v_cvt_i32_f64_e32 v4, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s2, s8, v4
	v_add_co_ci_u32_e64 v4, s2, s9, v5, s2
	s_sub_i32 s2, s3, s14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s8, v0
	s_sub_i32 s14, s2, s12
	v_readfirstlane_b32 s9, v4
	s_cmp_ge_u32 s2, s12
	v_add_nc_u32_e32 v0, s12, v1
	s_cselect_b32 s2, s14, s2
	s_load_b32 s8, s[8:9], 0x0
	s_sub_i32 s9, s2, s12
	s_cmp_ge_u32 s2, s12
	s_cselect_b32 s9, s9, s2
	v_cmp_gt_u32_e64 s2, s3, v0
	s_cmp_eq_u32 s9, 0
	v_mov_b32_e32 v0, s12
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v0, s9, v0, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v0, v0, 2, 0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v4, s8
	ds_store_b32 v0, v4
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.5:
	ds_load_2addr_b32 v[5:6], v3 offset1:1
	s_load_b256 s[12:19], s[0:1], 0x20
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_mov_b32 s2, 0
	s_mov_b32 s1, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e64 v5, v6
	s_cbranch_execz .LBB0_9
; %bb.6:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v8, 31, v5
	v_mov_b32_e32 v7, v5
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[9:10], 3, v[7:8]
	v_lshlrev_b64 v[11:12], 2, v[7:8]
	v_add_co_u32 v7, vcc_lo, s4, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v12, vcc_lo
.LBB0_7:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v11, v[9:10], off
	v_add_nc_u32_e32 v5, 1, v5
	v_add_co_u32 v9, s0, v9, 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s12, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v12, vcc_lo
	global_load_b64 v[13:14], v[7:8], off
	global_load_b64 v[11:12], v[11:12], off
	v_add_co_u32 v7, vcc_lo, v7, 8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v5, v6
	s_or_b32 s2, vcc_lo, s2
	s_waitcnt vmcnt(0)
	v_fma_f64 v[3:4], v[13:14], v[11:12], v[3:4]
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_7
; %bb.8:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_9:                                ; %Flow73
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b64 v[5:6], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[5:6], v[5:6], s[16:17]
	v_fma_f64 v[2:3], v[3:4], s[14:15], v[5:6]
	global_store_b64 v[0:1], v[2:3], off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sparseMultiply
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	sparseMultiply, .Lfunc_end0-sparseMultiply
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 748
; NumSgprs: 22
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	accumulateExternal      ; -- Begin function accumulateExternal
	.globl	accumulateExternal
	.p2align	8
	.type	accumulateExternal,@function
accumulateExternal:                     ; @accumulateExternal
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s3, s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[2:3], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[4:5], v[2:3], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[6:7], v[4:5]
	global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel accumulateExternal
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	accumulateExternal, .Lfunc_end1-accumulateExternal
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 216
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	blockMultiply2          ; -- Begin function blockMultiply2
	.globl	blockMultiply2
	.p2align	8
	.type	blockMultiply2,@function
blockMultiply2:                         ; @blockMultiply2
; %bb.0:
	s_clause 0x2
	s_load_b32 s3, s[0:1], 0x54
	s_load_b128 s[20:23], s[0:1], 0x30
	s_load_b32 s2, s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s12, s3, 0xffff
	v_cmp_gt_i32_e32 vcc_lo, s21, v0
	s_lshl_b32 s3, s12, 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s3, s3, 0
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	v_mad_u64_u32 v[1:2], null, s15, s21, v[0:1]
	v_lshl_add_u32 v2, v0, 2, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, s22
	ds_store_b32 v2, v1
.LBB2_2:
	s_or_b32 exec_lo, exec_lo, s4
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
	s_cmp_lt_i32 s22, 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e64 s0, s2, v1
	s_cbranch_scc1 .LBB2_12
; %bb.3:                                ; %.lr.ph77
	s_ashr_i32 s12, s20, 31
	v_lshlrev_b32_e32 v6, 2, v0
	s_add_i32 s1, s20, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s13, s1, s12
	v_add_nc_u32_e32 v7, s3, v6
	v_cvt_f32_u32_e32 v2, s13
	s_sub_i32 s1, 0, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s1, v2
	v_mul_hi_u32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_hi_u32 v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v2, s13
	v_add_nc_u32_e32 v4, 1, v2
	v_sub_nc_u32_e32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v5, s13, v3
	v_cmp_le_u32_e64 s1, s13, v3
	v_cndmask_b32_e64 v2, v2, v4, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v3, v5, s1
	v_add_nc_u32_e32 v4, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s1, s13, v3
	v_cndmask_b32_e64 v2, v2, v4, s1
	v_mov_b32_e32 v3, 0
	s_lshl_b32 s1, s21, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s1, s3, s1
	v_xor_b32_e32 v2, s12, v2
	s_cmp_gt_i32 s20, 0
	v_add_nc_u32_e32 v8, s1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v5, s12, v2
	v_mov_b32_e32 v4, 0
	v_lshl_add_u32 v2, v0, 3, 0
	v_mul_lo_u32 v11, v5, s20
	v_lshlrev_b32_e32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v9, s1, v5
	v_add_nc_u32_e32 v10, s3, v5
	v_sub_nc_u32_e32 v0, v0, v11
	v_lshl_add_u32 v11, v11, 3, 0
	s_cselect_b32 s1, -1, 0
	s_mov_b32 s3, 0
	s_and_b32 s12, s0, s1
.LBB2_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_10 Depth 2
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=1
	ds_load_b32 v5, v7
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v5, s3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s8, v5
	v_add_co_ci_u32_e64 v6, s1, s9, v6, s1
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v5
.LBB2_6:                                ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_4 Depth=1
	ds_load_b32 v12, v9
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[5:6], null, v12, s20, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s1, s6, v5
	v_add_co_ci_u32_e64 v6, s1, s7, v6, s1
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v2, v[5:6]
.LBB2_8:                                ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s13, s12
	s_cbranch_execz .LBB2_11
; %bb.9:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_4 Depth=1
	ds_load_b32 v5, v10
	s_mov_b32 s14, s20
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, s3, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s23, v12, v[0:1]
	v_mov_b32_e32 v12, v11
.LBB2_10:                               ;   Parent Loop BB2_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v6, 31, v5
	ds_load_b64 v[15:16], v12
	v_add_nc_u32_e32 v12, 8, v12
	s_add_i32 s14, s14, -1
	s_cmp_lg_u32 s14, 0
	v_lshlrev_b64 v[13:14], 3, v[5:6]
	v_add_nc_u32_e32 v5, s20, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v13, s1, s4, v13
	v_add_co_ci_u32_e64 v14, s1, s5, v14, s1
	global_load_b64 v[13:14], v[13:14], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[3:4], v[13:14], v[15:16], v[3:4]
	s_cbranch_scc1 .LBB2_10
.LBB2_11:                               ; %Flow116
                                        ;   in Loop: Header=BB2_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s3, s22
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB2_4
	s_branch .LBB2_13
.LBB2_12:
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
.LBB2_13:                               ; %Flow118
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB2_15
; %bb.14:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b64 v[5:6], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[5:6], v[5:6], s[18:19]
	v_fma_f64 v[2:3], v[3:4], s[16:17], v[5:6]
	global_store_b64 v[0:1], v[2:3], off
.LBB2_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel blockMultiply2
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	blockMultiply2, .Lfunc_end2-blockMultiply2
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 904
; NumSgprs: 26
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	blockMultiply           ; -- Begin function blockMultiply
	.globl	blockMultiply
	.p2align	8
	.type	blockMultiply,@function
blockMultiply:                          ; @blockMultiply
; %bb.0:
	s_mov_b32 s16, s15
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[12:15], s[0:1], 0x20
	s_load_b32 s3, s[0:1], 0x44
	v_cmp_eq_u32_e64 s2, 0, v0
	s_mov_b32 s19, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s20, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_add_i32 s18, s16, 1
	s_mov_b32 s17, s19
	s_lshl_b64 s[22:23], s[18:19], 2
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s18, s10, s22
	s_addc_u32 s19, s11, s23
	s_lshl_b64 s[22:23], s[16:17], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s10, s10, s22
	s_addc_u32 s11, s11, s23
	s_clause 0x1
	s_load_b32 s17, s[18:19], 0x0
	s_load_b32 s10, s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	v_dual_mov_b32 v1, s17 :: v_dual_mov_b32 v2, s10
	ds_store_b64 v3, v[1:2]
.LBB3_2:
	s_or_b32 exec_lo, exec_lo, s20
	v_mov_b32_e32 v8, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_load_b64 s[10:11], s[0:1], 0x30
	ds_load_b64 v[4:5], v8
	s_and_b32 s0, 0xffff, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s16, s0, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s0, s11, v1
	v_cmp_ge_i32_e32 vcc_lo, v5, v4
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_cbranch_vccnz .LBB3_12
; %bb.3:                                ; %.lr.ph53
	s_mul_i32 s1, s10, s10
	s_cmp_gt_i32 s10, 0
	v_mad_u64_u32 v[2:3], null, v5, s1, v[0:1]
	v_mov_b32_e32 v3, 0
	v_lshl_add_u32 v9, v0, 3, 12
	v_mov_b32_e32 v4, 0
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s0, s3
.LBB3_4:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_10 Depth 2
	s_and_saveexec_b32 s16, s2
	s_cbranch_execz .LBB3_6
; %bb.5:                                ;   in Loop: Header=BB3_4 Depth=1
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	v_readfirstlane_b32 s18, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_readfirstlane_b32 s19, v7
	s_load_b32 s17, s[18:19], 0x0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v6, s17
	ds_store_b32 v8, v6 offset:8
.LBB3_6:                                ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB3_8
; %bb.7:                                ;   in Loop: Header=BB3_4 Depth=1
	ds_load_b32 v10, v8 offset:8
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[6:7], null, v10, s10, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v9, v[6:7]
.LBB3_8:                                ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s16, s3
	s_cbranch_execz .LBB3_11
; %bb.9:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_4 Depth=1
	v_mov_b32_e32 v6, v2
	s_mov_b32 s17, 12
	s_mov_b32 s18, s10
.LBB3_10:                               ;   Parent Loop BB3_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	s_add_i32 s18, s18, -1
	v_lshlrev_b64 v[10:11], 3, v[6:7]
	v_dual_mov_b32 v7, s17 :: v_dual_add_nc_u32 v6, s10, v6
	s_add_i32 s17, s17, 8
	s_cmp_lg_u32 s18, 0
	ds_load_b64 v[12:13], v7
	v_add_co_u32 v10, vcc_lo, s4, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[3:4], v[10:11], v[12:13], v[3:4]
	s_cbranch_scc1 .LBB3_10
.LBB3_11:                               ; %Flow84
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	ds_load_b32 v6, v8
	v_add_nc_u32_e32 v5, 1, v5
	v_add_nc_u32_e32 v2, s1, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_ge_i32_e32 vcc_lo, v5, v6
	s_cbranch_vccz .LBB3_4
.LBB3_12:                               ; %Flow87
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s11, v1
	s_cbranch_execz .LBB3_14
; %bb.13:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v5, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	global_load_b64 v[7:8], v[0:1], off
	s_waitcnt vmcnt(1)
	v_fma_f64 v[2:3], v[5:6], s[14:15], v[3:4]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[7:8], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB3_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel blockMultiply
		.amdhsa_group_segment_fixed_size 12
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	blockMultiply, .Lfunc_end3-blockMultiply
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 728
; NumSgprs: 26
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 12 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	ellMultiply             ; -- Begin function ellMultiply
	.globl	ellMultiply
	.p2align	8
	.type	ellMultiply,@function
ellMultiply:                            ; @ellMultiply
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[16:19], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s16, v2
	s_cbranch_execz .LBB4_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b128 s[0:3], s[0:1], 0x20
	s_cmp_lt_i32 s17, 1
	s_cbranch_scc1 .LBB4_4
; %bb.2:                                ; %.lr.ph.preheader
	s_mul_i32 s16, s15, s17
	s_mov_b32 s13, 0
	s_mul_i32 s12, s16, s18
	v_mov_b32_e32 v4, 0
	s_lshl_b64 s[14:15], s[12:13], 3
	s_mul_i32 s12, s16, s19
	s_waitcnt lgkmcnt(0)
	s_add_u32 s4, s4, s14
	s_addc_u32 s5, s5, s15
	s_lshl_b64 s[12:13], s[12:13], 2
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v0
	s_add_u32 s6, s6, s12
	s_addc_u32 s7, s7, s13
.LBB4_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s17, s17, -1
	s_cmp_eq_u32 s17, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[6:7]
	v_lshlrev_b64 v[9:10], 3, v[0:1]
	v_add_nc_u32_e32 v6, s19, v6
	v_add_nc_u32_e32 v0, s18, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s6, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	global_load_b64 v[9:10], v[9:10], off
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[4:5], v[9:10], v[7:8], v[4:5]
	s_cbranch_scc0 .LBB4_3
	s_branch .LBB4_5
.LBB4_4:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
.LBB4_5:                                ; %Flow68
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[2:3], v[2:3], s[2:3]
	v_fma_f64 v[2:3], v[4:5], s[0:1], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB4_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel ellMultiply
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	ellMultiply, .Lfunc_end4-ellMultiply
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 392
; NumSgprs: 22
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	mcellMultiply           ; -- Begin function mcellMultiply
	.globl	mcellMultiply
	.p2align	8
	.type	mcellMultiply,@function
mcellMultiply:                          ; @mcellMultiply
; %bb.0:
	s_mov_b32 s20, s15
	s_clause 0x1
	s_load_b512 s[4:19], s[0:1], 0x0
	s_load_b32 s2, s[0:1], 0x5c
	s_mov_b32 s21, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_2
; %bb.1:
	s_lshl_b64 s[22:23], s[20:21], 2
	s_mov_b32 s25, s21
	s_waitcnt lgkmcnt(0)
	s_add_u32 s22, s8, s22
	s_addc_u32 s23, s9, s23
	s_add_i32 s24, s20, 1
	v_mov_b32_e32 v3, 0
	s_lshl_b64 s[24:25], s[24:25], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s8, s24
	s_addc_u32 s9, s9, s25
	s_clause 0x1
	s_load_b32 s21, s[22:23], 0x0
	s_load_b32 s8, s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s8, s8, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, s21 :: v_dual_mov_b32 v2, s8
	ds_store_b64 v3, v[1:2]
.LBB5_2:
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s8, 0xffff, s2
	ds_load_b64 v[1:2], v1
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_lt_i32_e64 v0, v2
	s_cbranch_execz .LBB5_5
; %bb.3:                                ; %.lr.ph.preheader
	v_ashrrev_i32_e32 v4, 31, v1
	v_mov_b32_e32 v3, v1
	v_lshl_add_u32 v1, v0, 3, 8
	s_lshl_b32 s3, s8, 3
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v5, vcc_lo, s10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
	v_mov_b32_e32 v3, v0
.LBB5_4:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_nc_u32_e32 v3, s8, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v5, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, v6, v8, vcc_lo
	global_load_b32 v7, v[7:8], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v7, vcc_lo, s12, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s13, v8, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v3, v2
	global_load_b64 v[7:8], v[7:8], off
	s_or_b32 s9, vcc_lo, s9
	s_waitcnt vmcnt(0)
	ds_store_b64 v1, v[7:8]
	v_add_nc_u32_e32 v1, s3, v1
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB5_4
.LBB5_5:                                ; %Flow100
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b128 s[0:3], s[0:1], 0x40
	v_mad_u64_u32 v[1:2], null, s20, s8, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmp_gt_i32_e32 vcc_lo, s0, v1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB5_11
; %bb.6:                                ; %.preheader
	s_cmp_lt_i32 s1, 1
	s_cbranch_scc1 .LBB5_9
; %bb.7:                                ; %.lr.ph53.preheader
	s_mul_i32 s0, s20, s1
	s_mov_b32 s9, 0
	s_mul_i32 s10, s0, s3
	s_mov_b32 s11, s9
	s_mul_i32 s8, s0, s2
	s_lshl_b64 s[10:11], s[10:11], 1
	v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 3, v0
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_lshl_b64 s[8:9], s[8:9], 3
	v_mov_b32_e32 v4, 0
	s_add_u32 s0, s4, s8
	s_addc_u32 s4, s5, s9
	v_add_co_u32 v5, s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v6, null, s4, 0, s0
	s_ashr_i32 s5, s2, 31
	s_mov_b32 s4, s2
	s_lshl_b64 s[4:5], s[4:5], 3
.LBB5_8:                                ; %.lr.ph53
                                        ; =>This Inner Loop Header: Depth=1
	v_and_b32_e32 v2, 0xffff, v0
	v_add_nc_u32_e32 v0, s3, v0
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_eq_u32 s1, 0
	v_lshlrev_b32_e32 v2, 1, v2
	global_load_u16 v2, v2, s[6:7]
	global_load_b64 v[7:8], v[5:6], off
	v_add_co_u32 v5, vcc_lo, v5, s4
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_waitcnt vmcnt(1)
	v_lshl_add_u32 v2, v2, 3, 8
	ds_load_b64 v[9:10], v2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[3:4], v[7:8], v[9:10], v[3:4]
	s_cbranch_scc0 .LBB5_8
	s_branch .LBB5_10
.LBB5_9:
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
.LBB5_10:                               ; %Flow97
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v0, vcc_lo, s14, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_load_b64 v[5:6], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[5:6], v[5:6], s[18:19]
	v_fma_f64 v[2:3], v[3:4], s[16:17], v[5:6]
	global_store_b64 v[0:1], v[2:3], off
.LBB5_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel mcellMultiply
		.amdhsa_group_segment_fixed_size 8
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	mcellMultiply, .Lfunc_end5-mcellMultiply
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 696
; NumSgprs: 28
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         184
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sparseMultiply
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         sparseMultiply.kd
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amdhsa.version:
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...

	.end_amdgpu_metadata
