
#include "cuda_runtime.h"
#include "device_launch_parameters.h"

#include <stdio.h>

#define __u32 unsigned int 
#define __u8 unsigned char

cudaError_t addWithCuda(__u32 SHA1Sum[], __u8 SHA1Data[], int *retVal);


#define	FETCH_32(p)							\
	(((__u32)*((const __u8 *)(p) + 3)) |			\
	(((__u32)*((const __u8 *)(p) + 2)) << 8) |		\
	(((__u32)*((const __u8 *)(p) + 1)) << 16) |		\
	(((__u32)*((const __u8 *)(p))) << 24))

/* Constants from FIPS 180-1 */
#define	K_00_19		0x5a827999UL
#define	K_20_39		0x6ed9eba1UL
#define	K_40_59		0x8f1bbcdcUL
#define	K_60_79		0xca62c1d6UL

/* F, G, H and I are basic SHA1 functions. */
#define	F(b, c, d)	((((c) ^ (d)) & (b)) ^ (d))
#define	G(b, c, d)	((b) ^ (c) ^ (d))
#define	H(b, c, d)	(((b) & (c)) | (((b) | (c)) & (d)))

/* ROTATE_LEFT rotates x left n bits. */
#define	ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32 - (n))))

/* R, R1-R4 are macros used during each transformation round. */
#define R(f, k, v, w, x, y, z, i) {				\
	(v) = ROTATE_LEFT(w, 5) + f(x, y, z) + (v) + (i) + (k);	\
	(x) = ROTATE_LEFT(x, 30);				\
}

#define	R1(v, w, x, y, z, i)	R(F, K_00_19, v, w, x, y, z, i)
#define	R2(v, w, x, y, z, i)	R(G, K_20_39, v, w, x, y, z, i)
#define	R3(v, w, x, y, z, i)	R(H, K_40_59, v, w, x, y, z, i)
#define	R4(v, w, x, y, z, i)	R(G, K_60_79, v, w, x, y, z, i)

#define	WUPDATE(p, q, r, s) {		\
	(p) = ((q) ^ (r) ^ (s) ^ (p));	\
	(p) = ROTATE_LEFT(p, 1);	\
}

void SHA1Init(__u32 mass[]) {
	mass[0] = 0x67452301UL;
	mass[1] = 0xefcdab89UL;
	mass[2] = 0x98badcfeUL;
	mass[3] = 0x10325476UL;
	mass[4] = 0xc3d2e1f0UL;
}

void
sha_transformINIT(__u32 mass[], __u8 block[])
{
	__u32 a = mass[0];
	__u32 b = mass[1];
	__u32 c = mass[2];
	__u32 d = mass[3];
	__u32 e = mass[4];

	/* Register (instead of array) is a win in most cases */
	__u32 w0, w1, w2, w3, w4, w5, w6, w7;
	__u32 w8, w9, w10, w11, w12, w13, w14, w15;

	w15 = FETCH_32(block + 60);
	w14 = FETCH_32(block + 56);
	w13 = FETCH_32(block + 52);
	w12 = FETCH_32(block + 48);
	w11 = FETCH_32(block + 44);
	w10 = FETCH_32(block + 40);
	w9 = FETCH_32(block + 36);
	w8 = FETCH_32(block + 32);
	w7 = FETCH_32(block + 28);
	w6 = FETCH_32(block + 24);
	w5 = FETCH_32(block + 20);
	w4 = FETCH_32(block + 16);
	w3 = FETCH_32(block + 12);
	w2 = FETCH_32(block + 8);
	w1 = FETCH_32(block + 4);
	w0 = FETCH_32(block + 0);

	/* Round 1 */
	R1(e, a, b, c, d, w0);		/*  0 */
	R1(d, e, a, b, c, w1);		/*  1 */
	R1(c, d, e, a, b, w2);		/*  2 */
	R1(b, c, d, e, a, w3);		/*  3 */
	R1(a, b, c, d, e, w4);		/*  4 */
	R1(e, a, b, c, d, w5);		/*  5 */
	R1(d, e, a, b, c, w6);		/*  6 */
	R1(c, d, e, a, b, w7);		/*  7 */
	R1(b, c, d, e, a, w8);		/*  8 */
	R1(a, b, c, d, e, w9);		/*  9 */
	R1(e, a, b, c, d, w10);		/* 10 */
	R1(d, e, a, b, c, w11);		/* 11 */
	R1(c, d, e, a, b, w12);		/* 12 */
	R1(b, c, d, e, a, w13);		/* 13 */
	R1(a, b, c, d, e, w14);		/* 14 */
	R1(e, a, b, c, d, w15);		/* 15 */
	WUPDATE(w0, w13, w8, w2);	R1(d, e, a, b, c, w0);		/* 16 */
	WUPDATE(w1, w14, w9, w3);	R1(c, d, e, a, b, w1);		/* 17 */
	WUPDATE(w2, w15, w10, w4);	R1(b, c, d, e, a, w2);		/* 18 */
	WUPDATE(w3, w0, w11, w5);	R1(a, b, c, d, e, w3);		/* 19 */

	/* Round 2 */
	WUPDATE(w4, w1, w12, w6);	R2(e, a, b, c, d, w4);		/* 20 */
	WUPDATE(w5, w2, w13, w7);	R2(d, e, a, b, c, w5);		/* 21 */
	WUPDATE(w6, w3, w14, w8);	R2(c, d, e, a, b, w6);		/* 22 */
	WUPDATE(w7, w4, w15, w9);	R2(b, c, d, e, a, w7);		/* 23 */
	WUPDATE(w8, w5, w0, w10);	R2(a, b, c, d, e, w8);		/* 24 */
	WUPDATE(w9, w6, w1, w11);	R2(e, a, b, c, d, w9);		/* 25 */
	WUPDATE(w10, w7, w2, w12);	R2(d, e, a, b, c, w10);		/* 26 */
	WUPDATE(w11, w8, w3, w13);	R2(c, d, e, a, b, w11);		/* 27 */
	WUPDATE(w12, w9, w4, w14);	R2(b, c, d, e, a, w12);		/* 28 */
	WUPDATE(w13, w10, w5, w15);	R2(a, b, c, d, e, w13);		/* 29 */
	WUPDATE(w14, w11, w6, w0);	R2(e, a, b, c, d, w14);		/* 30 */
	WUPDATE(w15, w12, w7, w1);	R2(d, e, a, b, c, w15);		/* 31 */
	WUPDATE(w0, w13, w8, w2);	R2(c, d, e, a, b, w0);		/* 32 */
	WUPDATE(w1, w14, w9, w3);	R2(b, c, d, e, a, w1);		/* 33 */
	WUPDATE(w2, w15, w10, w4);	R2(a, b, c, d, e, w2);		/* 34 */
	WUPDATE(w3, w0, w11, w5);	R2(e, a, b, c, d, w3);		/* 35 */
	WUPDATE(w4, w1, w12, w6);	R2(d, e, a, b, c, w4);		/* 36 */
	WUPDATE(w5, w2, w13, w7);	R2(c, d, e, a, b, w5);		/* 37 */
	WUPDATE(w6, w3, w14, w8);	R2(b, c, d, e, a, w6);		/* 38 */
	WUPDATE(w7, w4, w15, w9);	R2(a, b, c, d, e, w7);		/* 39 */

	/* Round 3 */
	WUPDATE(w8, w5, w0, w10);	R3(e, a, b, c, d, w8);		/* 40 */
	WUPDATE(w9, w6, w1, w11);	R3(d, e, a, b, c, w9);		/* 41 */
	WUPDATE(w10, w7, w2, w12);	R3(c, d, e, a, b, w10);		/* 42 */
	WUPDATE(w11, w8, w3, w13);	R3(b, c, d, e, a, w11);		/* 43 */
	WUPDATE(w12, w9, w4, w14);	R3(a, b, c, d, e, w12);		/* 44 */
	WUPDATE(w13, w10, w5, w15);	R3(e, a, b, c, d, w13);		/* 45 */
	WUPDATE(w14, w11, w6, w0);	R3(d, e, a, b, c, w14);		/* 46 */
	WUPDATE(w15, w12, w7, w1);	R3(c, d, e, a, b, w15);		/* 47 */
	WUPDATE(w0, w13, w8, w2);	R3(b, c, d, e, a, w0);		/* 48 */
	WUPDATE(w1, w14, w9, w3);	R3(a, b, c, d, e, w1);		/* 49 */
	WUPDATE(w2, w15, w10, w4);	R3(e, a, b, c, d, w2);		/* 50 */
	WUPDATE(w3, w0, w11, w5);	R3(d, e, a, b, c, w3);		/* 51 */
	WUPDATE(w4, w1, w12, w6);	R3(c, d, e, a, b, w4);		/* 52 */
	WUPDATE(w5, w2, w13, w7);	R3(b, c, d, e, a, w5);		/* 53 */
	WUPDATE(w6, w3, w14, w8);	R3(a, b, c, d, e, w6);		/* 54 */
	WUPDATE(w7, w4, w15, w9);	R3(e, a, b, c, d, w7);		/* 55 */
	WUPDATE(w8, w5, w0, w10);	R3(d, e, a, b, c, w8);		/* 56 */
	WUPDATE(w9, w6, w1, w11);	R3(c, d, e, a, b, w9);		/* 57 */
	WUPDATE(w10, w7, w2, w12);	R3(b, c, d, e, a, w10);		/* 58 */
	WUPDATE(w11, w8, w3, w13);	R3(a, b, c, d, e, w11);		/* 59 */

	WUPDATE(w12, w9, w4, w14);	R4(e, a, b, c, d, w12);		/* 60 */
	WUPDATE(w13, w10, w5, w15);	R4(d, e, a, b, c, w13);		/* 61 */
	WUPDATE(w14, w11, w6, w0);	R4(c, d, e, a, b, w14);		/* 62 */
	WUPDATE(w15, w12, w7, w1);	R4(b, c, d, e, a, w15);		/* 63 */
	WUPDATE(w0, w13, w8, w2);	R4(a, b, c, d, e, w0);		/* 64 */
	WUPDATE(w1, w14, w9, w3);	R4(e, a, b, c, d, w1);		/* 65 */
	WUPDATE(w2, w15, w10, w4);	R4(d, e, a, b, c, w2);		/* 66 */
	WUPDATE(w3, w0, w11, w5);	R4(c, d, e, a, b, w3);		/* 67 */
	WUPDATE(w4, w1, w12, w6);	R4(b, c, d, e, a, w4);		/* 68 */
	WUPDATE(w5, w2, w13, w7);	R4(a, b, c, d, e, w5);		/* 69 */
	WUPDATE(w6, w3, w14, w8);	R4(e, a, b, c, d, w6);		/* 70 */
	WUPDATE(w7, w4, w15, w9);	R4(d, e, a, b, c, w7);		/* 71 */
	WUPDATE(w8, w5, w0, w10);	R4(c, d, e, a, b, w8);		/* 72 */
	WUPDATE(w9, w6, w1, w11);	R4(b, c, d, e, a, w9);		/* 73 */
	WUPDATE(w10, w7, w2, w12);	R4(a, b, c, d, e, w10);		/* 74 */
	WUPDATE(w11, w8, w3, w13);	R4(e, a, b, c, d, w11);		/* 75 */
	WUPDATE(w12, w9, w4, w14);	R4(d, e, a, b, c, w12);		/* 76 */
	WUPDATE(w13, w10, w5, w15);	R4(c, d, e, a, b, w13);		/* 77 */
	WUPDATE(w14, w11, w6, w0);	R4(b, c, d, e, a, w14);		/* 78 */
	WUPDATE(w15, w12, w7, w1);	R4(a, b, c, d, e, w15);		/* 79 */

	mass[0] += a;
	mass[1] += b;
	mass[2] += c;
	mass[3] += d;
	mass[4] += e;
}

__constant__ __u32 g_cSHA1baseCode[5];

__global__ void
sha_transform(int *ret_block, __u32 *in_block)
{
	__u32 *block = in_block + ((blockIdx.x << 6) + threadIdx.x) * 16;
	__u8 *pos_cur;

	__u32 a, b, c, d, e;
	/* Register (instead of array) is a win in most cases */
	__u32 w0, w1, w2, w3, w4, w5, w6, w7;
	__u32 w8, w9, w10, w11, w12, w13, w14, w15;
	__u32 wi[16];
	wi[0] = block[0];
	wi[1] = block[1];
	wi[2] = block[2];
	wi[3] = block[3];
	wi[4] = block[4];
	wi[5] = block[5];
	wi[6] = block[6];
	wi[7] = block[7];
	wi[8] = block[8];
	wi[9] = block[9];
	wi[10] = block[10];
	wi[11] = block[11];
	wi[12] = block[12];
	wi[13] = block[13];
	wi[14] = block[14];
	wi[15] = block[15];



	while (true) {
		pos_cur = (__u8*)wi;
		while (true) {
			if ((*pos_cur) == 126) {
				(*pos_cur) = 33;
				pos_cur++;
				continue;
			}
			(*pos_cur)++;

			a = g_cSHA1baseCode[0];
			b = g_cSHA1baseCode[1];
			c = g_cSHA1baseCode[2];
			d = g_cSHA1baseCode[3];
			e = g_cSHA1baseCode[4];

/*			w15 = FETCH_32((__u8 *)(block + 15));
			w14 = FETCH_32((__u8 *)(block + 14));
			w13 = FETCH_32((__u8 *)(block + 13));
			w12 = FETCH_32((__u8 *)(block + 12));
			w11 = FETCH_32((__u8 *)(block + 11));
			w10 = FETCH_32((__u8 *)(block + 10));
			w9 = FETCH_32((__u8 *)(block + 9));
			w8 = FETCH_32((__u8 *)(block + 8));
			w7 = FETCH_32((__u8 *)(block + 7));
			w6 = FETCH_32((__u8 *)(block + 6));
			w5 = FETCH_32((__u8 *)(block + 5));
			w4 = FETCH_32((__u8 *)(block + 4));
			w3 = FETCH_32((__u8 *)(block + 3));
			w2 = FETCH_32((__u8 *)(block + 2));
			w1 = FETCH_32((__u8 *)(block + 1));
			w0 = FETCH_32((__u8 *)(block + 0));
			*/
			w15 = wi[15];
			w14 = wi[14];
			w13 = wi[13];
			w12 = wi[12];
			w11 = wi[11];
			w10 = wi[10];
			w9 = wi[9];
			w8 = wi[8];
			w7 = wi[7];
			w6 = wi[6];
			w5 = wi[5];
			w4 = wi[4];
			w3 = wi[3];
			w2 = wi[2];
			w1 = wi[1];
			w0 = wi[0];

			/* Round 1 */
			R1(e, a, b, c, d, w0);		/*  0 */
			R1(d, e, a, b, c, w1);		/*  1 */
			R1(c, d, e, a, b, w2);		/*  2 */
			R1(b, c, d, e, a, w3);		/*  3 */
			R1(a, b, c, d, e, w4);		/*  4 */
			R1(e, a, b, c, d, w5);		/*  5 */
			R1(d, e, a, b, c, w6);		/*  6 */
			R1(c, d, e, a, b, w7);		/*  7 */
			R1(b, c, d, e, a, w8);		/*  8 */
			R1(a, b, c, d, e, w9);		/*  9 */
			R1(e, a, b, c, d, w10);		/* 10 */
			R1(d, e, a, b, c, w11);		/* 11 */
			R1(c, d, e, a, b, w12);		/* 12 */
			R1(b, c, d, e, a, w13);		/* 13 */
			R1(a, b, c, d, e, w14);		/* 14 */
			R1(e, a, b, c, d, w15);		/* 15 */
			WUPDATE(w0, w13, w8, w2);	R1(d, e, a, b, c, w0);		/* 16 */
			WUPDATE(w1, w14, w9, w3);	R1(c, d, e, a, b, w1);		/* 17 */
			WUPDATE(w2, w15, w10, w4);	R1(b, c, d, e, a, w2);		/* 18 */
			WUPDATE(w3, w0, w11, w5);	R1(a, b, c, d, e, w3);		/* 19 */

			/* Round 2 */
			WUPDATE(w4, w1, w12, w6);	R2(e, a, b, c, d, w4);		/* 20 */
			WUPDATE(w5, w2, w13, w7);	R2(d, e, a, b, c, w5);		/* 21 */
			WUPDATE(w6, w3, w14, w8);	R2(c, d, e, a, b, w6);		/* 22 */
			WUPDATE(w7, w4, w15, w9);	R2(b, c, d, e, a, w7);		/* 23 */
			WUPDATE(w8, w5, w0, w10);	R2(a, b, c, d, e, w8);		/* 24 */
			WUPDATE(w9, w6, w1, w11);	R2(e, a, b, c, d, w9);		/* 25 */
			WUPDATE(w10, w7, w2, w12);	R2(d, e, a, b, c, w10);		/* 26 */
			WUPDATE(w11, w8, w3, w13);	R2(c, d, e, a, b, w11);		/* 27 */
			WUPDATE(w12, w9, w4, w14);	R2(b, c, d, e, a, w12);		/* 28 */
			WUPDATE(w13, w10, w5, w15);	R2(a, b, c, d, e, w13);		/* 29 */
			WUPDATE(w14, w11, w6, w0);	R2(e, a, b, c, d, w14);		/* 30 */
			WUPDATE(w15, w12, w7, w1);	R2(d, e, a, b, c, w15);		/* 31 */
			WUPDATE(w0, w13, w8, w2);	R2(c, d, e, a, b, w0);		/* 32 */
			WUPDATE(w1, w14, w9, w3);	R2(b, c, d, e, a, w1);		/* 33 */
			WUPDATE(w2, w15, w10, w4);	R2(a, b, c, d, e, w2);		/* 34 */
			WUPDATE(w3, w0, w11, w5);	R2(e, a, b, c, d, w3);		/* 35 */
			WUPDATE(w4, w1, w12, w6);	R2(d, e, a, b, c, w4);		/* 36 */
			WUPDATE(w5, w2, w13, w7);	R2(c, d, e, a, b, w5);		/* 37 */
			WUPDATE(w6, w3, w14, w8);	R2(b, c, d, e, a, w6);		/* 38 */
			WUPDATE(w7, w4, w15, w9);	R2(a, b, c, d, e, w7);		/* 39 */

			/* Round 3 */
			WUPDATE(w8, w5, w0, w10);	R3(e, a, b, c, d, w8);		/* 40 */
			WUPDATE(w9, w6, w1, w11);	R3(d, e, a, b, c, w9);		/* 41 */
			WUPDATE(w10, w7, w2, w12);	R3(c, d, e, a, b, w10);		/* 42 */
			WUPDATE(w11, w8, w3, w13);	R3(b, c, d, e, a, w11);		/* 43 */
			WUPDATE(w12, w9, w4, w14);	R3(a, b, c, d, e, w12);		/* 44 */
			WUPDATE(w13, w10, w5, w15);	R3(e, a, b, c, d, w13);		/* 45 */
			WUPDATE(w14, w11, w6, w0);	R3(d, e, a, b, c, w14);		/* 46 */
			WUPDATE(w15, w12, w7, w1);	R3(c, d, e, a, b, w15);		/* 47 */
			WUPDATE(w0, w13, w8, w2);	R3(b, c, d, e, a, w0);		/* 48 */
			WUPDATE(w1, w14, w9, w3);	R3(a, b, c, d, e, w1);		/* 49 */
			WUPDATE(w2, w15, w10, w4);	R3(e, a, b, c, d, w2);		/* 50 */
			WUPDATE(w3, w0, w11, w5);	R3(d, e, a, b, c, w3);		/* 51 */
			WUPDATE(w4, w1, w12, w6);	R3(c, d, e, a, b, w4);		/* 52 */
			WUPDATE(w5, w2, w13, w7);	R3(b, c, d, e, a, w5);		/* 53 */
			WUPDATE(w6, w3, w14, w8);	R3(a, b, c, d, e, w6);		/* 54 */
			WUPDATE(w7, w4, w15, w9);	R3(e, a, b, c, d, w7);		/* 55 */
			WUPDATE(w8, w5, w0, w10);	R3(d, e, a, b, c, w8);		/* 56 */
			WUPDATE(w9, w6, w1, w11);	R3(c, d, e, a, b, w9);		/* 57 */
			WUPDATE(w10, w7, w2, w12);	R3(b, c, d, e, a, w10);		/* 58 */
			WUPDATE(w11, w8, w3, w13);	R3(a, b, c, d, e, w11);		/* 59 */

			WUPDATE(w12, w9, w4, w14);	R4(e, a, b, c, d, w12);		/* 60 */
			WUPDATE(w13, w10, w5, w15);	R4(d, e, a, b, c, w13);		/* 61 */
			WUPDATE(w14, w11, w6, w0);	R4(c, d, e, a, b, w14);		/* 62 */
			WUPDATE(w15, w12, w7, w1);	R4(b, c, d, e, a, w15);		/* 63 */
			WUPDATE(w0, w13, w8, w2);	R4(a, b, c, d, e, w0);		/* 64 */
			WUPDATE(w1, w14, w9, w3);	R4(e, a, b, c, d, w1);		/* 65 */
			WUPDATE(w2, w15, w10, w4);	R4(d, e, a, b, c, w2);		/* 66 */
			WUPDATE(w3, w0, w11, w5);	R4(c, d, e, a, b, w3);		/* 67 */
			WUPDATE(w4, w1, w12, w6);	R4(b, c, d, e, a, w4);		/* 68 */
			WUPDATE(w5, w2, w13, w7);	R4(a, b, c, d, e, w5);		/* 69 */
			WUPDATE(w6, w3, w14, w8);	R4(e, a, b, c, d, w6);		/* 70 */
			WUPDATE(w7, w4, w15, w9);	R4(d, e, a, b, c, w7);		/* 71 */
			WUPDATE(w8, w5, w0, w10);	R4(c, d, e, a, b, w8);		/* 72 */
			WUPDATE(w9, w6, w1, w11);	R4(b, c, d, e, a, w9);		/* 73 */
			WUPDATE(w10, w7, w2, w12);	R4(a, b, c, d, e, w10);		/* 74 */
			WUPDATE(w11, w8, w3, w13);	R4(e, a, b, c, d, w11);		/* 75 */
			WUPDATE(w12, w9, w4, w14);	R4(d, e, a, b, c, w12);		/* 76 */
			WUPDATE(w13, w10, w5, w15);	R4(c, d, e, a, b, w13);		/* 77 */
			WUPDATE(w14, w11, w6, w0);	R4(b, c, d, e, a, w14);		/* 78 */
			WUPDATE(w15, w12, w7, w1);	R4(a, b, c, d, e, w15);		/* 79 */
			a += g_cSHA1baseCode[0];
			
			if (((a) == 0)) {
				b += g_cSHA1baseCode[1];
				if ((b & 0xfff00000) == 0) {
					block[0] = wi[0];
					block[1] = wi[1];
					block[2] = wi[2];
					block[3] = wi[3];
					block[4] = wi[4];
					block[5] = wi[5];
					block[6] = wi[6];
					block[7] = wi[7];
					block[8] = wi[8];
					block[9] = wi[9];
					block[10] = wi[10];
					block[11] = wi[11];
					block[12] = wi[12];
					block[13] = wi[13];
					block[14] = wi[14];
					block[15] = wi[15];

					(*ret_block) = (blockIdx.x << 6) + threadIdx.x;
					return;
				}
			}
			if ((*ret_block) != -1)
				return;

			break;
		}
	}
}
#include <random>
#include <chrono>

int main(int argc, char **argv)
{
	__u32 buf[5];
	SHA1Init(buf);
	sha_transformINIT(buf, (unsigned char*)argv[1]);
	
	std::default_random_engine generator(std::chrono::system_clock::now().time_since_epoch().count());
	std::uniform_int_distribution<int> distribution(33, 126);

	unsigned char data[2048 * 64];
	//memset(data, 33, 2048 * 64);
	for (int j = 0; j < 2048; j++) {
		for (int i = 0; i < 56; i++)
			data[j*64 + i] = distribution(generator);
		//data[j * 64] = 33 + (j % 94);
		//data[j * 64 + 1] = 33 + int(j / 94);

		data[j * 64 + 52] = 0x80;
		memset(j * 64 + data + 56, 0, 8);
		data[j * 64 + 61] = 0x03;
		data[j * 64 + 60] = 0xb8;
	}

	int iRetVal = -1;
    // Add vectors in parallel.
    cudaError_t cudaStatus = addWithCuda(buf, data, &iRetVal);
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "addWithCuda failed!");
        return 1;
    }
	for (int i = 0; i < 13; i++)
		for (int j = 3; j >= 0; j--)
			printf("%x ", data[iRetVal * 64 + (i << 2) + j]);
	printf("%x %x %x", data[iRetVal * 64 + 55], data[iRetVal * 64 + 54], data[iRetVal * 64 + 53]);

    // cudaDeviceReset must be called before exiting in order for profiling and
    // tracing tools such as Nsight and Visual Profiler to show complete traces.
    cudaStatus = cudaDeviceReset();
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaDeviceReset failed!");
        return 1;
    }

    return 0;
}

// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(__u32 SHA1Sum[], __u8 SHA1Data[], int *retVal)
{
	__u32 *dev_SHA1Data = 0;
	int *dev_retVal = 0;
    cudaError_t cudaStatus;

    // Choose which GPU to run on, change this on a multi-GPU system.
    cudaStatus = cudaSetDevice(0);
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?");
        goto Error;
    }

    cudaStatus = cudaMalloc((void**)&dev_SHA1Data, 2048 * 64 * sizeof(__u8));
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaMalloc failed!");
        goto Error;
    }

	cudaStatus = cudaMalloc((void**)&dev_retVal, sizeof(int));
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMalloc failed!");
		goto Error;
	}

	cudaStatus = cudaMemcpyToSymbol(g_cSHA1baseCode, SHA1Sum, 5 * sizeof(__u32));
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaMemcpyToSymbol failed!");
        goto Error;
    }

    cudaStatus = cudaMemcpy(dev_SHA1Data, SHA1Data, 2048 * 64 * sizeof(__u8), cudaMemcpyHostToDevice);
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaMemcpy failed!");
        goto Error;
    }

	cudaStatus = cudaMemcpy(dev_retVal, retVal, sizeof(int), cudaMemcpyHostToDevice);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy failed!");
		goto Error;
	}

    // Launch a kernel on the GPU with one thread for each element.
	sha_transform <<<32, 64>>>(dev_retVal, dev_SHA1Data);

    // Check for any errors launching the kernel
    cudaStatus = cudaGetLastError();
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
        goto Error;
    }
    
    // cudaDeviceSynchronize waits for the kernel to finish, and returns
    // any errors encountered during the launch.
    cudaStatus = cudaDeviceSynchronize();
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
        goto Error;
    }

    // Copy output vector from GPU buffer to host memory.
    cudaStatus = cudaMemcpy(SHA1Data, dev_SHA1Data, 2048 * 64 * sizeof(__u8), cudaMemcpyDeviceToHost);
    if (cudaStatus != cudaSuccess) {
        fprintf(stderr, "cudaMemcpy failed!");
        goto Error;
    }

	// Copy output vector from GPU buffer to host memory.
	cudaStatus = cudaMemcpy(retVal, dev_retVal, sizeof(int), cudaMemcpyDeviceToHost);
	if (cudaStatus != cudaSuccess) {
		fprintf(stderr, "cudaMemcpy failed!");
		goto Error;
	}

Error:
    cudaFree(dev_SHA1Data);
	cudaFree(dev_retVal);

    return cudaStatus;
}

	.file	"tmpxft_0026d807_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4213:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4213:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE.isra.0, @function
_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE.isra.0:
.LFB4949:
	.cfi_startproc
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movslq	%esi, %rax
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rax, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movslq	%edx, %rbp
	subq	%rax, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	cmpq	$2147483644, %rbp
	ja	.L3
	incq	%rbp
	movl	$2147483645, %eax
	xorl	%edx, %edx
	movl	$2147483647, %esi
	divq	%rbp
	movq	(%rdi), %rdx
	imulq	%rax, %rbp
	movq	%rax, %rcx
.L4:
	imulq	$16807, %rdx, %rax
	xorl	%edx, %edx
	divq	%rsi
	leaq	-1(%rdx), %rax
	cmpq	%rbp, %rax
	jnb	.L4
	movq	%rdx, 0(%r13)
	xorl	%edx, %edx
	divq	%rcx
	jmp	.L5
.L3:
	cmpq	$2147483645, %rbp
	je	.L6
	movl	$2147483646, %ecx
	movq	%rbp, %rax
	xorl	%edx, %edx
	movl	$2147483647, %ebx
	divq	%rcx
	movq	%rax, %r14
.L11:
	movl	%r14d, %edx
	xorl	%esi, %esi
	movq	%r13, %rdi
	call	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE.isra.0
	xorl	%edx, %edx
	movl	%eax, %ecx
	imulq	$16807, 0(%r13), %rax
	divq	%rbx
	movslq	%ecx, %rax
	imulq	$2147483646, %rax, %rax
	movq	%rdx, 0(%r13)
	decq	%rdx
	addq	%rdx, %rax
	setc	%dl
	movzbl	%dl, %edx
	cmpq	%rax, %rbp
	jb	.L11
	testq	%rdx, %rdx
	jne	.L11
	jmp	.L5
.L6:
	imulq	$16807, (%rdi), %rax
	movl	$2147483647, %ecx
	xorl	%edx, %edx
	divq	%rcx
	movq	%rdx, (%rdi)
	leaq	-1(%rdx), %rax
.L5:
	popq	%rbx
	.cfi_def_cfa_offset 40
	addl	%r12d, %eax
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4949:
	.size	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE.isra.0, .-_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE.isra.0
	.globl	_Z8SHA1InitPj
	.type	_Z8SHA1InitPj, @function
_Z8SHA1InitPj:
.LFB2027:
	.cfi_startproc
	endbr64
	movabsq	$-1167088121787636991, %rax
	movl	$-1009589776, 16(%rdi)
	movq	%rax, (%rdi)
	movabsq	$1167088121787636990, %rax
	movq	%rax, 8(%rdi)
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z8SHA1InitPj, .-_Z8SHA1InitPj
	.globl	_Z17sha_transformINITPjPh
	.type	_Z17sha_transformINITPjPh, @function
_Z17sha_transformINITPjPh:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %rax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	60(%rax), %edx
	movl	(%rdi), %esi
	movl	16(%rdi), %ebx
	bswap	%edx
	movl	%edx, -64(%rsp)
	movl	56(%rax), %edx
	movl	%esi, -16(%rsp)
	movl	4(%rdi), %esi
	bswap	%edx
	movl	%edx, -60(%rsp)
	movl	52(%rax), %edx
	movl	%esi, -8(%rsp)
	movl	8(%rdi), %esi
	bswap	%edx
	movl	%edx, -56(%rsp)
	movl	48(%rax), %edx
	movl	%esi, -68(%rsp)
	movl	12(%rdi), %esi
	bswap	%edx
	movl	%edx, -36(%rsp)
	movl	44(%rax), %edx
	movq	%rdi, -80(%rsp)
	movl	%esi, -12(%rsp)
	bswap	%edx
	movl	%ebx, -4(%rsp)
	movl	%edx, -40(%rsp)
	movl	40(%rax), %edx
	movl	-12(%rsp), %ebx
	movl	20(%rax), %ecx
	bswap	%edx
	movl	16(%rax), %esi
	movl	12(%rax), %edi
	movl	%edx, -44(%rsp)
	movl	36(%rax), %edx
	movl	8(%rax), %r8d
	bswap	%ecx
	movl	(%rax), %r10d
	movl	-16(%rsp), %r9d
	bswap	%edi
	bswap	%esi
	bswap	%edx
	movl	%edx, -48(%rsp)
	movl	32(%rax), %edx
	bswap	%r8d
	roll	$5, %r9d
	movl	-16(%rsp), %r11d
	bswap	%r10d
	movl	-68(%rsp), %r13d
	bswap	%edx
	movl	%edx, %r15d
	movl	28(%rax), %edx
	leal	1518500249(%r13,%r8), %r12d
	bswap	%edx
	movl	%edx, -52(%rsp)
	movl	24(%rax), %edx
	movl	-52(%rsp), %r13d
	bswap	%edx
	movl	%edx, %r14d
	movl	4(%rax), %edx
	movl	-68(%rsp), %eax
	xorl	%ebx, %eax
	movl	-8(%rsp), %ebx
	bswap	%edx
	andl	%ebx, %eax
	movl	-12(%rsp), %ebx
	xorl	%ebx, %eax
	movl	-4(%rsp), %ebx
	leal	1518500249(%rbx,%r9), %r9d
	movl	-8(%rsp), %ebx
	addl	%r9d, %eax
	movl	-68(%rsp), %r9d
	rorl	$2, %ebx
	addl	%r10d, %eax
	xorl	%ebx, %r9d
	movl	%eax, %ebp
	andl	%r11d, %r9d
	movl	-68(%rsp), %r11d
	roll	$5, %ebp
	xorl	%r11d, %r9d
	movl	-12(%rsp), %r11d
	leal	1518500249(%r11,%r9), %r9d
	movl	-16(%rsp), %r11d
	addl	%edx, %r9d
	addl	%r9d, %ebp
	rorl	$2, %r11d
	movl	%ebx, %r9d
	xorl	%r11d, %r9d
	andl	%eax, %r9d
	rorl	$2, %eax
	xorl	%ebx, %r9d
	leal	1518500249(%rdi,%rbx), %ebx
	addl	%r9d, %r12d
	movl	%ebp, %r9d
	roll	$5, %r9d
	addl	%r12d, %r9d
	movl	%r11d, %r12d
	xorl	%eax, %r12d
	andl	%ebp, %r12d
	rorl	$2, %ebp
	xorl	%r11d, %r12d
	leal	1518500249(%rsi,%r11), %r11d
	addl	%r12d, %ebx
	movl	%r9d, %r12d
	roll	$5, %r12d
	addl	%ebx, %r12d
	movl	%eax, %ebx
	xorl	%ebp, %ebx
	andl	%r9d, %ebx
	xorl	%eax, %ebx
	leal	1518500249(%rcx,%rax), %eax
	addl	%ebx, %r11d
	movl	%r12d, %ebx
	roll	$5, %ebx
	rorl	$2, %r9d
	addl	%r11d, %ebx
	movl	%ebp, %r11d
	xorl	%r9d, %r11d
	andl	%r12d, %r11d
	xorl	%ebp, %r11d
	leal	1518500249(%r14,%rbp), %ebp
	addl	%r11d, %eax
	movl	%ebx, %r11d
	roll	$5, %r11d
	addl	%eax, %r11d
	movl	%r12d, %eax
	movl	%r9d, %r12d
	rorl	$2, %eax
	xorl	%eax, %r12d
	andl	%ebx, %r12d
	rorl	$2, %ebx
	xorl	%r9d, %r12d
	leal	1518500249(%r13,%r9), %r9d
	movl	-48(%rsp), %r13d
	addl	%ebp, %r12d
	movl	%r11d, %ebp
	roll	$5, %ebp
	addl	%r12d, %ebp
	movl	%eax, %r12d
	xorl	%ebx, %r12d
	andl	%r11d, %r12d
	rorl	$2, %r11d
	xorl	%eax, %r12d
	leal	1518500249(%r15,%rax), %eax
	addl	%r9d, %r12d
	movl	%ebp, %r9d
	roll	$5, %r9d
	addl	%r12d, %r9d
	movl	%ebx, %r12d
	xorl	%r11d, %r12d
	andl	%ebp, %r12d
	rorl	$2, %ebp
	xorl	%ebx, %r12d
	leal	1518500249(%r13,%rbx), %ebx
	movl	-44(%rsp), %r13d
	addl	%eax, %r12d
	movl	%r9d, %eax
	roll	$5, %eax
	addl	%r12d, %eax
	movl	%r11d, %r12d
	xorl	%ebp, %r12d
	andl	%r9d, %r12d
	rorl	$2, %r9d
	xorl	%r11d, %r12d
	leal	1518500249(%r13,%r11), %r11d
	movl	-40(%rsp), %r13d
	addl	%ebx, %r12d
	movl	%eax, %ebx
	roll	$5, %ebx
	addl	%r12d, %ebx
	movl	%ebp, %r12d
	xorl	%r9d, %r12d
	andl	%eax, %r12d
	rorl	$2, %eax
	xorl	%ebp, %r12d
	leal	1518500249(%r13,%rbp), %ebp
	movl	-36(%rsp), %r13d
	addl	%r11d, %r12d
	movl	%ebx, %r11d
	roll	$5, %r11d
	addl	%r12d, %r11d
	movl	%r9d, %r12d
	xorl	%eax, %r12d
	andl	%ebx, %r12d
	rorl	$2, %ebx
	xorl	%r9d, %r12d
	leal	1518500249(%r13,%r9), %r9d
	movl	-56(%rsp), %r13d
	addl	%ebp, %r12d
	movl	%r11d, %ebp
	roll	$5, %ebp
	addl	%r12d, %ebp
	movl	%eax, %r12d
	xorl	%ebx, %r12d
	andl	%r11d, %r12d
	rorl	$2, %r11d
	xorl	%eax, %r12d
	leal	1518500249(%r13,%rax), %eax
	movl	-60(%rsp), %r13d
	addl	%r9d, %r12d
	movl	%ebp, %r9d
	roll	$5, %r9d
	addl	%r12d, %r9d
	movl	%ebx, %r12d
	xorl	%r11d, %r12d
	andl	%ebp, %r12d
	xorl	%ebx, %r12d
	leal	1518500249(%r13,%rbx), %ebx
	movl	-64(%rsp), %r13d
	addl	%eax, %r12d
	movl	%r9d, %eax
	roll	$5, %eax
	addl	%r12d, %eax
	rorl	$2, %ebp
	movl	%r11d, %r12d
	xorl	%ebp, %r12d
	andl	%r9d, %r12d
	rorl	$2, %r9d
	xorl	%r11d, %r12d
	leal	1518500249(%r13,%r11), %r11d
	movl	-60(%rsp), %r13d
	addl	%r12d, %ebx
	movl	%eax, %r12d
	roll	$5, %r12d
	addl	%ebx, %r12d
	movl	%ebp, %ebx
	xorl	%r9d, %ebx
	andl	%eax, %ebx
	rorl	$2, %eax
	xorl	%ebp, %ebx
	addl	%ebx, %r11d
	movl	%r12d, %ebx
	roll	$5, %ebx
	addl	%r11d, %ebx
	movl	-56(%rsp), %r11d
	xorl	%r15d, %r11d
	xorl	%r8d, %r11d
	xorl	%r10d, %r11d
	movl	%r9d, %r10d
	xorl	%eax, %r10d
	roll	%r11d
	andl	%r12d, %r10d
	leal	1518500249(%rbp,%r11), %ebp
	rorl	$2, %r12d
	xorl	%r9d, %r10d
	addl	%ebp, %r10d
	movl	%ebx, %ebp
	roll	$5, %ebp
	addl	%r10d, %ebp
	movl	-48(%rsp), %r10d
	xorl	%r13d, %r10d
	movl	-64(%rsp), %r13d
	xorl	%edi, %r10d
	xorl	%edx, %r10d
	movl	%eax, %edx
	xorl	%r12d, %edx
	roll	%r10d
	andl	%ebx, %edx
	leal	1518500249(%r9,%r10), %r9d
	rorl	$2, %ebx
	xorl	%eax, %edx
	addl	%edx, %r9d
	movl	%ebp, %edx
	roll	$5, %edx
	addl	%r9d, %edx
	movl	-44(%rsp), %r9d
	xorl	%r13d, %r9d
	xorl	%esi, %r9d
	xorl	%r8d, %r9d
	movl	%r12d, %r8d
	xorl	%ebx, %r8d
	roll	%r9d
	andl	%ebp, %r8d
	leal	1518500249(%rax,%r9), %eax
	rorl	$2, %ebp
	xorl	%r12d, %r8d
	movl	%ebp, %r13d
	addl	%eax, %r8d
	movl	%edx, %eax
	roll	$5, %eax
	addl	%r8d, %eax
	movl	-40(%rsp), %r8d
	xorl	%ecx, %r8d
	xorl	%edi, %r8d
	movl	%ebx, %edi
	xorl	%r11d, %r8d
	xorl	%ebp, %edi
	roll	%r8d
	andl	%edx, %edi
	rorl	$2, %edx
	xorl	%ebx, %edi
	leal	1518500249(%r12,%r8), %r12d
	addl	%r12d, %edi
	movl	%eax, %r12d
	roll	$5, %r12d
	addl	%edi, %r12d
	movl	-36(%rsp), %edi
	xorl	%r14d, %edi
	xorl	%esi, %edi
	xorl	%r10d, %edi
	roll	%edi
	xorl	%edx, %r13d
	xorl	%eax, %r13d
	leal	1859775393(%rbx,%rdi), %esi
	movl	%r12d, %ebx
	rorl	$2, %eax
	addl	%r13d, %esi
	roll	$5, %ebx
	movl	-56(%rsp), %r13d
	addl	%esi, %ebx
	movl	-52(%rsp), %esi
	xorl	%r13d, %esi
	movl	%edx, %r13d
	xorl	%ecx, %esi
	xorl	%eax, %r13d
	xorl	%r9d, %esi
	xorl	%r12d, %r13d
	rorl	$2, %r12d
	roll	%esi
	leal	1859775393(%rbp,%rsi), %ecx
	movl	%ebx, %ebp
	addl	%r13d, %ecx
	roll	$5, %ebp
	movl	%eax, %r13d
	addl	%ecx, %ebp
	movl	-60(%rsp), %ecx
	xorl	%r12d, %r13d
	xorl	%ebx, %r13d
	rorl	$2, %ebx
	xorl	%r15d, %ecx
	xorl	%r14d, %ecx
	movl	%ebp, %r14d
	xorl	%r8d, %ecx
	roll	$5, %r14d
	roll	%ecx
	leal	1859775393(%rdx,%rcx), %edx
	addl	%r13d, %edx
	movl	-64(%rsp), %r13d
	addl	%edx, %r14d
	movl	-48(%rsp), %edx
	xorl	%r13d, %edx
	movl	-52(%rsp), %r13d
	xorl	%r13d, %edx
	movl	%r12d, %r13d
	xorl	%edi, %edx
	xorl	%ebx, %r13d
	roll	%edx
	xorl	%ebp, %r13d
	leal	1859775393(%rax,%rdx), %eax
	addl	%r13d, %eax
	movl	%r14d, %r13d
	rorl	$2, %ebp
	roll	$5, %r13d
	addl	%eax, %r13d
	movl	-44(%rsp), %eax
	xorl	%r15d, %eax
	movl	%ebx, %r15d
	xorl	%r11d, %eax
	xorl	%ebp, %r15d
	xorl	%esi, %eax
	xorl	%r14d, %r15d
	rorl	$2, %r14d
	roll	%eax
	leal	1859775393(%r12,%rax), %r12d
	movl	%eax, -52(%rsp)
	movl	-40(%rsp), %eax
	addl	%r12d, %r15d
	movl	%r13d, %r12d
	roll	$5, %r12d
	addl	%r15d, %r12d
	movl	-48(%rsp), %r15d
	xorl	%eax, %r15d
	xorl	%r10d, %r15d
	xorl	%ecx, %r15d
	roll	%r15d
	movl	%r15d, -48(%rsp)
	movl	%ebp, %r15d
	movl	-48(%rsp), %eax
	xorl	%r14d, %r15d
	xorl	%r13d, %r15d
	leal	1859775393(%rbx,%rax), %ebx
	movl	-36(%rsp), %eax
	rorl	$2, %r13d
	addl	%r15d, %ebx
	movl	%r12d, %r15d
	roll	$5, %r15d
	addl	%ebx, %r15d
	movl	-44(%rsp), %ebx
	xorl	%eax, %ebx
	xorl	%r9d, %ebx
	xorl	%edx, %ebx
	roll	%ebx
	movl	%ebx, -44(%rsp)
	movl	%r14d, %ebx
	movl	-44(%rsp), %eax
	xorl	%r13d, %ebx
	xorl	%r12d, %ebx
	leal	1859775393(%rbp,%rax), %ebp
	movl	-56(%rsp), %eax
	addl	%ebx, %ebp
	movl	%r15d, %ebx
	roll	$5, %ebx
	addl	%ebp, %ebx
	movl	-40(%rsp), %ebp
	rorl	$2, %r12d
	xorl	%eax, %ebp
	movl	-52(%rsp), %eax
	xorl	%r8d, %ebp
	xorl	%eax, %ebp
	roll	%ebp
	movl	%ebp, -40(%rsp)
	movl	%r13d, %ebp
	movl	-40(%rsp), %eax
	xorl	%r12d, %ebp
	xorl	%r15d, %ebp
	leal	1859775393(%r14,%rax), %r14d
	rorl	$2, %r15d
	addl	%r14d, %ebp
	movl	%ebx, %r14d
	roll	$5, %r14d
	addl	%ebp, %r14d
	movl	-36(%rsp), %ebp
	movl	-60(%rsp), %eax
	xorl	%eax, %ebp
	movl	-48(%rsp), %eax
	xorl	%edi, %ebp
	xorl	%eax, %ebp
	roll	%ebp
	movl	%ebp, -36(%rsp)
	movl	%r12d, %ebp
	movl	-36(%rsp), %eax
	xorl	%r15d, %ebp
	xorl	%ebx, %ebp
	leal	1859775393(%r13,%rax), %r13d
	movl	-64(%rsp), %eax
	rorl	$2, %ebx
	addl	%r13d, %ebp
	movl	%r14d, %r13d
	roll	$5, %r13d
	addl	%ebp, %r13d
	movl	-56(%rsp), %ebp
	xorl	%eax, %ebp
	movl	-44(%rsp), %eax
	xorl	%esi, %ebp
	xorl	%eax, %ebp
	roll	%ebp
	movl	%ebp, -56(%rsp)
	movl	%r15d, %ebp
	movl	-56(%rsp), %eax
	xorl	%ebx, %ebp
	xorl	%r14d, %ebp
	leal	1859775393(%r12,%rax), %r12d
	rorl	$2, %r14d
	movl	-40(%rsp), %eax
	addl	%r12d, %ebp
	movl	%r13d, %r12d
	roll	$5, %r12d
	addl	%ebp, %r12d
	movl	-60(%rsp), %ebp
	xorl	%r11d, %ebp
	xorl	%r9d, %r11d
	xorl	%ecx, %ebp
	xorl	%eax, %ebp
	roll	%ebp
	movl	%ebp, -60(%rsp)
	movl	%ebx, %ebp
	movl	-60(%rsp), %eax
	xorl	%r14d, %ebp
	xorl	%r13d, %ebp
	leal	1859775393(%r15,%rax), %r15d
	movl	-36(%rsp), %eax
	rorl	$2, %r13d
	addl	%ebp, %r15d
	movl	%r12d, %ebp
	roll	$5, %ebp
	addl	%r15d, %ebp
	movl	-64(%rsp), %r15d
	xorl	%r10d, %r15d
	xorl	%r8d, %r10d
	xorl	%edx, %r15d
	xorl	%eax, %r15d
	roll	%r15d
	movl	%r15d, -64(%rsp)
	movl	-64(%rsp), %eax
	movl	%r14d, %r15d
	xorl	%r13d, %r15d
	leal	1859775393(%rbx,%rax), %ebx
	movl	-52(%rsp), %eax
	xorl	%r12d, %r15d
	rorl	$2, %r12d
	addl	%r15d, %ebx
	movl	%ebp, %r15d
	xorl	%eax, %r11d
	movl	-56(%rsp), %eax
	roll	$5, %r15d
	addl	%r15d, %ebx
	movl	%r13d, %r15d
	xorl	%eax, %r11d
	movl	-48(%rsp), %eax
	xorl	%r12d, %r15d
	roll	%r11d
	xorl	%ebp, %r15d
	rorl	$2, %ebp
	movl	%r11d, -32(%rsp)
	xorl	%eax, %r10d
	leal	1859775393(%r14,%r11), %r11d
	movl	-60(%rsp), %eax
	movl	%ebx, %r14d
	addl	%r15d, %r11d
	roll	$5, %r14d
	addl	%r14d, %r11d
	xorl	%eax, %r10d
	movl	-44(%rsp), %eax
	xorl	%edi, %r9d
	movl	%r12d, %r14d
	roll	%r10d
	xorl	%esi, %r8d
	xorl	%ecx, %edi
	xorl	%ebp, %r14d
	xorl	%eax, %r9d
	movl	-64(%rsp), %eax
	movl	%r10d, %r15d
	xorl	%ebx, %r14d
	leal	1859775393(%r13,%r10), %r10d
	movl	%r11d, %r13d
	rorl	$2, %ebx
	xorl	%eax, %r9d
	addl	%r14d, %r10d
	roll	$5, %r13d
	movl	-40(%rsp), %eax
	addl	%r13d, %r10d
	movl	%r9d, %r14d
	movl	%ebp, %r13d
	roll	%r14d
	xorl	%ebx, %r13d
	xorl	%eax, %r8d
	movl	-32(%rsp), %eax
	xorl	%r11d, %r13d
	leal	1859775393(%r12,%r14), %r9d
	movl	%r10d, %r12d
	rorl	$2, %r11d
	addl	%r13d, %r9d
	roll	$5, %r12d
	xorl	%eax, %r8d
	movl	-36(%rsp), %eax
	addl	%r12d, %r9d
	movl	%ebx, %r12d
	roll	%r8d
	xorl	%r11d, %r12d
	movl	%r8d, %r13d
	leal	1859775393(%rbp,%r8), %r8d
	xorl	%eax, %edi
	xorl	%r10d, %r12d
	movl	%r9d, %ebp
	movl	-56(%rsp), %eax
	rorl	$2, %r10d
	addl	%r12d, %r8d
	roll	$5, %ebp
	xorl	%r15d, %edi
	addl	%ebp, %r8d
	movl	%r11d, %ebp
	roll	%edi
	xorl	%r10d, %ebp
	xorl	%edx, %esi
	movl	%edi, %r12d
	xorl	%eax, %esi
	movl	-52(%rsp), %eax
	xorl	%r9d, %ebp
	leal	1859775393(%rbx,%rdi), %edi
	xorl	%r14d, %esi
	movl	%r8d, %ebx
	addl	%ebp, %edi
	rorl	$2, %r9d
	roll	%esi
	xorl	%eax, %ecx
	movl	-60(%rsp), %eax
	roll	$5, %ebx
	movl	%esi, -28(%rsp)
	addl	%ebx, %edi
	movl	%r10d, %ebx
	leal	1859775393(%r11,%rsi), %esi
	xorl	%eax, %ecx
	xorl	%r9d, %ebx
	movl	%edi, %r11d
	xorl	%r13d, %ecx
	xorl	%r8d, %ebx
	roll	$5, %r11d
	roll	%ecx
	addl	%ebx, %esi
	rorl	$2, %r8d
	movl	%ecx, -24(%rsp)
	movl	-48(%rsp), %eax
	addl	%r11d, %esi
	movl	%r9d, %r11d
	xorl	%r8d, %r11d
	movl	-52(%rsp), %ebx
	leal	1859775393(%r10,%rcx), %ecx
	movl	%esi, %r10d
	xorl	%eax, %edx
	movl	-64(%rsp), %eax
	xorl	%edi, %r11d
	rorl	$2, %edi
	addl	%r11d, %ecx
	roll	$5, %r10d
	xorl	%eax, %edx
	addl	%r10d, %ecx
	xorl	%r12d, %edx
	roll	%edx
	movl	%edx, -20(%rsp)
	movl	-20(%rsp), %eax
	movl	%r8d, %edx
	xorl	%edi, %edx
	leal	1859775393(%r9,%rax), %r9d
	movl	-44(%rsp), %eax
	xorl	%esi, %edx
	addl	%edx, %r9d
	movl	%ecx, %edx
	rorl	$2, %esi
	xorl	%eax, %ebx
	roll	$5, %edx
	movl	%ebx, %eax
	movl	-32(%rsp), %ebx
	addl	%r9d, %edx
	movl	%ecx, %r9d
	andl	%esi, %r9d
	xorl	%ebx, %eax
	movl	-28(%rsp), %ebx
	xorl	%ebx, %eax
	movl	-40(%rsp), %ebx
	roll	%eax
	movl	%eax, -52(%rsp)
	leal	-1894007588(%r8,%rax), %r8d
	movl	%edx, %eax
	roll	$5, %eax
	addl	%eax, %r8d
	movl	%ecx, %eax
	rorl	$2, %ecx
	orl	%esi, %eax
	andl	%edi, %eax
	orl	%r9d, %eax
	movl	%edx, %r9d
	addl	%r8d, %eax
	movl	-48(%rsp), %r8d
	orl	%ecx, %r9d
	andl	%esi, %r9d
	xorl	%ebx, %r8d
	movl	-24(%rsp), %ebx
	xorl	%r15d, %r8d
	xorl	%ebx, %r8d
	roll	%r8d
	movl	%r8d, -48(%rsp)
	movl	%edx, %r8d
	movl	-48(%rsp), %ebx
	rorl	$2, %edx
	andl	%ecx, %r8d
	orl	%r9d, %r8d
	leal	-1894007588(%rdi,%rbx), %edi
	movl	-36(%rsp), %ebx
	movl	%eax, %r9d
	addl	%r8d, %edi
	movl	%eax, %r8d
	roll	$5, %r8d
	addl	%edi, %r8d
	movl	-44(%rsp), %edi
	xorl	%ebx, %edi
	movl	-20(%rsp), %ebx
	xorl	%r14d, %edi
	xorl	%ebx, %edi
	movl	-56(%rsp), %ebx
	roll	%edi
	movl	%edi, -44(%rsp)
	leal	-1894007588(%rsi,%rdi), %edi
	movl	%r8d, %esi
	roll	$5, %esi
	andl	%edx, %r9d
	addl	%esi, %edi
	movl	%eax, %esi
	rorl	$2, %eax
	orl	%edx, %esi
	andl	%ecx, %esi
	orl	%r9d, %esi
	movl	%r8d, %r9d
	addl	%edi, %esi
	movl	-40(%rsp), %edi
	orl	%eax, %r9d
	andl	%edx, %r9d
	xorl	%ebx, %edi
	movl	-52(%rsp), %ebx
	xorl	%r13d, %edi
	xorl	%ebx, %edi
	roll	%edi
	movl	%edi, -40(%rsp)
	movl	%r8d, %edi
	movl	-40(%rsp), %ebx
	rorl	$2, %r8d
	andl	%eax, %edi
	orl	%r9d, %edi
	leal	-1894007588(%rcx,%rbx), %ecx
	movl	-60(%rsp), %ebx
	movl	%esi, %r9d
	addl	%edi, %ecx
	movl	%esi, %edi
	andl	%r8d, %r9d
	roll	$5, %edi
	addl	%ecx, %edi
	movl	-36(%rsp), %ecx
	xorl	%ebx, %ecx
	movl	-48(%rsp), %ebx
	xorl	%r12d, %ecx
	xorl	%ebx, %ecx
	movl	-64(%rsp), %ebx
	roll	%ecx
	movl	%ecx, -36(%rsp)
	leal	-1894007588(%rdx,%rcx), %ecx
	movl	%edi, %edx
	roll	$5, %edx
	addl	%edx, %ecx
	movl	%esi, %edx
	rorl	$2, %esi
	orl	%r8d, %edx
	andl	%eax, %edx
	orl	%r9d, %edx
	movl	%edi, %r9d
	addl	%ecx, %edx
	movl	-56(%rsp), %ecx
	xorl	%ebx, %ecx
	movl	-28(%rsp), %ebx
	orl	%esi, %r9d
	andl	%r8d, %r9d
	xorl	%ebx, %ecx
	movl	-44(%rsp), %ebx
	xorl	%ebx, %ecx
	roll	%ecx
	movl	%ecx, -56(%rsp)
	movl	%edi, %ecx
	movl	-56(%rsp), %ebx
	rorl	$2, %edi
	andl	%esi, %ecx
	orl	%r9d, %ecx
	leal	-1894007588(%rax,%rbx), %eax
	movl	-32(%rsp), %ebx
	movl	%edi, %r9d
	addl	%ecx, %eax
	movl	%edx, %ecx
	roll	$5, %ecx
	addl	%eax, %ecx
	movl	-60(%rsp), %eax
	xorl	%ebx, %eax
	movl	-24(%rsp), %ebx
	xorl	%ebx, %eax
	movl	-40(%rsp), %ebx
	xorl	%ebx, %eax
	movl	-20(%rsp), %ebx
	roll	%eax
	movl	%eax, -60(%rsp)
	leal	-1894007588(%r8,%rax), %edi
	movl	%ecx, %eax
	movl	%edx, %r8d
	roll	$5, %eax
	andl	%r9d, %r8d
	addl	%eax, %edi
	movl	%edx, %eax
	rorl	$2, %edx
	orl	%r9d, %eax
	andl	%esi, %eax
	orl	%r8d, %eax
	movl	%ecx, %r8d
	addl	%edi, %eax
	movl	-64(%rsp), %edi
	orl	%edx, %r8d
	andl	%r9d, %r8d
	xorl	%r15d, %edi
	xorl	%ebx, %edi
	movl	-36(%rsp), %ebx
	xorl	%ebx, %edi
	movl	-44(%rsp), %ebx
	roll	%edi
	movl	%edi, %r10d
	movl	%ecx, %edi
	andl	%edx, %edi
	leal	-1894007588(%rsi,%r10), %esi
	orl	%r8d, %edi
	addl	%edi, %esi
	rorl	$2, %ecx
	movl	%eax, %edi
	xorl	%r13d, %r15d
	movl	%ecx, %r8d
	roll	$5, %edi
	movl	-32(%rsp), %ecx
	addl	%esi, %edi
	movl	-52(%rsp), %esi
	xorl	%r14d, %ecx
	xorl	%r12d, %r14d
	xorl	%esi, %ecx
	movl	-56(%rsp), %esi
	xorl	%ebx, %r14d
	movl	-28(%rsp), %ebx
	xorl	%r10d, %r14d
	xorl	%esi, %ecx
	roll	%r14d
	roll	%ecx
	movl	%ecx, %r11d
	leal	-1894007588(%r9,%rcx), %esi
	movl	%edi, %ecx
	movl	%eax, %r9d
	roll	$5, %ecx
	andl	%r8d, %r9d
	addl	%ecx, %esi
	movl	%eax, %ecx
	rorl	$2, %eax
	orl	%r8d, %ecx
	andl	%edx, %ecx
	orl	%r9d, %ecx
	movl	%edi, %r9d
	addl	%esi, %ecx
	movl	-48(%rsp), %esi
	orl	%eax, %r9d
	andl	%r8d, %r9d
	leal	-1894007588(%r8,%r14), %r8d
	xorl	%esi, %r15d
	movl	-60(%rsp), %esi
	xorl	%esi, %r15d
	movl	%edi, %esi
	rorl	$2, %edi
	roll	%r15d
	andl	%eax, %esi
	orl	%r9d, %esi
	leal	-1894007588(%rdx,%r15), %edx
	movl	%ecx, %r9d
	addl	%esi, %edx
	movl	%ecx, %esi
	roll	$5, %esi
	addl	%edx, %esi
	movl	%esi, %edx
	roll	$5, %edx
	xorl	%ebx, %r13d
	movl	-40(%rsp), %ebx
	andl	%edi, %r9d
	addl	%edx, %r8d
	movl	%ecx, %edx
	rorl	$2, %ecx
	orl	%edi, %edx
	xorl	%ebx, %r13d
	andl	%eax, %edx
	xorl	%r11d, %r13d
	orl	%r9d, %edx
	movl	%esi, %r9d
	movl	%r13d, %ebx
	addl	%r8d, %edx
	orl	%ecx, %r9d
	movl	%esi, %r8d
	roll	%ebx
	andl	%edi, %r9d
	andl	%ecx, %r8d
	leal	-1894007588(%rax,%rbx), %eax
	rorl	$2, %esi
	orl	%r9d, %r8d
	movl	%edx, %r9d
	addl	%r8d, %eax
	movl	%edx, %r8d
	andl	%esi, %r9d
	roll	$5, %r8d
	addl	%eax, %r8d
	movl	-24(%rsp), %eax
	xorl	%eax, %r12d
	movl	-36(%rsp), %eax
	xorl	%eax, %r12d
	movl	%r8d, %eax
	xorl	%r15d, %r12d
	roll	$5, %eax
	movl	%r12d, %ebp
	roll	%ebp
	leal	-1894007588(%rdi,%rbp), %edi
	addl	%eax, %edi
	movl	%edx, %eax
	rorl	$2, %edx
	orl	%esi, %eax
	andl	%ecx, %eax
	orl	%r9d, %eax
	movl	-20(%rsp), %r9d
	addl	%edi, %eax
	movl	-28(%rsp), %edi
	xorl	%r9d, %edi
	movl	-56(%rsp), %r9d
	xorl	%r9d, %edi
	movl	%r8d, %r9d
	xorl	%r14d, %edi
	orl	%edx, %r9d
	roll	%edi
	andl	%esi, %r9d
	movl	%edi, %r13d
	movl	%r8d, %edi
	rorl	$2, %r8d
	andl	%edx, %edi
	leal	-1894007588(%rcx,%r13), %ecx
	orl	%r9d, %edi
	movl	-52(%rsp), %r9d
	addl	%edi, %ecx
	movl	%eax, %edi
	roll	$5, %edi
	addl	%ecx, %edi
	movl	-24(%rsp), %ecx
	xorl	%r9d, %ecx
	movl	-60(%rsp), %r9d
	xorl	%r9d, %ecx
	movl	%eax, %r9d
	xorl	%ebx, %ecx
	andl	%r8d, %r9d
	roll	%ecx
	movl	%ecx, -64(%rsp)
	leal	-1894007588(%rsi,%rcx), %esi
	movl	%edi, %ecx
	roll	$5, %ecx
	addl	%ecx, %esi
	movl	%eax, %ecx
	rorl	$2, %eax
	orl	%r8d, %ecx
	andl	%edx, %ecx
	orl	%r9d, %ecx
	movl	-48(%rsp), %r9d
	addl	%esi, %ecx
	movl	-20(%rsp), %esi
	xorl	%r9d, %esi
	movl	%edi, %r9d
	xorl	%r10d, %esi
	orl	%eax, %r9d
	xorl	%ebp, %esi
	andl	%r8d, %r9d
	roll	%esi
	movl	%esi, %r12d
	movl	%edi, %esi
	andl	%eax, %esi
	leal	-1894007588(%rdx,%r12), %edx
	orl	%r9d, %esi
	movl	-44(%rsp), %r9d
	addl	%esi, %edx
	movl	%ecx, %esi
	rorl	$2, %edi
	roll	$5, %esi
	addl	%edx, %esi
	movl	-52(%rsp), %edx
	xorl	%r9d, %edx
	movl	%ecx, %r9d
	xorl	%r11d, %edx
	andl	%edi, %r9d
	xorl	%r13d, %edx
	roll	%edx
	movl	%edx, -52(%rsp)
	leal	-1894007588(%r8,%rdx), %r8d
	movl	%esi, %edx
	roll	$5, %edx
	addl	%edx, %r8d
	movl	%ecx, %edx
	rorl	$2, %ecx
	orl	%edi, %edx
	andl	%eax, %edx
	orl	%r9d, %edx
	addl	%r8d, %edx
	movl	-48(%rsp), %r8d
	movl	-40(%rsp), %r9d
	xorl	%r9d, %r8d
	movl	-64(%rsp), %r9d
	xorl	%r15d, %r8d
	xorl	%r9d, %r8d
	movl	%esi, %r9d
	roll	%r8d
	orl	%ecx, %r9d
	movl	%r8d, -48(%rsp)
	movl	%esi, %r8d
	andl	%edi, %r9d
	rorl	$2, %esi
	andl	%ecx, %r8d
	orl	%r9d, %r8d
	movl	-48(%rsp), %r9d
	leal	-1894007588(%rax,%r9), %eax
	movl	-36(%rsp), %r9d
	addl	%eax, %r8d
	movl	%edx, %eax
	roll	$5, %eax
	addl	%r8d, %eax
	movl	-44(%rsp), %r8d
	xorl	%r9d, %r8d
	movl	%edx, %r9d
	xorl	%r14d, %r8d
	xorl	%r12d, %r8d
	roll	%r8d
	movl	%r8d, -44(%rsp)
	leal	-1894007588(%rdi,%r8), %r8d
	movl	%eax, %edi
	roll	$5, %edi
	andl	%esi, %r9d
	addl	%edi, %r8d
	movl	%edx, %edi
	rorl	$2, %edx
	orl	%esi, %edi
	andl	%ecx, %edi
	orl	%r9d, %edi
	movl	-56(%rsp), %r9d
	addl	%r8d, %edi
	movl	-40(%rsp), %r8d
	xorl	%r9d, %r8d
	movl	-52(%rsp), %r9d
	xorl	%ebx, %r8d
	xorl	%r9d, %r8d
	movl	%eax, %r9d
	roll	%r8d
	orl	%edx, %r9d
	movl	%r8d, -40(%rsp)
	movl	%eax, %r8d
	andl	%esi, %r9d
	rorl	$2, %eax
	andl	%edx, %r8d
	orl	%r9d, %r8d
	movl	-40(%rsp), %r9d
	leal	-1894007588(%rcx,%r9), %ecx
	movl	%edi, %r9d
	addl	%ecx, %r8d
	roll	$5, %r9d
	movl	-36(%rsp), %ecx
	addl	%r8d, %r9d
	movl	-60(%rsp), %r8d
	xorl	%r8d, %ecx
	movl	-48(%rsp), %r8d
	xorl	%ebp, %ecx
	xorl	%r8d, %ecx
	movl	%edx, %r8d
	roll	%ecx
	xorl	%eax, %r8d
	movl	%ecx, -36(%rsp)
	xorl	%edi, %r8d
	leal	-899497514(%rsi,%rcx), %ecx
	movl	%r9d, %esi
	roll	$5, %esi
	addl	%r8d, %ecx
	movl	-44(%rsp), %r8d
	rorl	$2, %edi
	addl	%ecx, %esi
	movl	-56(%rsp), %ecx
	xorl	%r10d, %ecx
	xorl	%r13d, %ecx
	xorl	%r8d, %ecx
	movl	%eax, %r8d
	roll	%ecx
	xorl	%edi, %r8d
	movl	%ecx, -56(%rsp)
	xorl	%r9d, %r8d
	leal	-899497514(%rdx,%rcx), %ecx
	movl	%esi, %edx
	roll	$5, %edx
	addl	%r8d, %ecx
	movl	-64(%rsp), %r8d
	rorl	$2, %r9d
	addl	%ecx, %edx
	movl	-60(%rsp), %ecx
	xorl	%r11d, %ecx
	xorl	%r8d, %ecx
	movl	-40(%rsp), %r8d
	xorl	%r8d, %ecx
	movl	%edi, %r8d
	roll	%ecx
	xorl	%r9d, %r8d
	movl	%ecx, -60(%rsp)
	xorl	%esi, %r8d
	leal	-899497514(%rax,%rcx), %ecx
	movl	%edx, %eax
	roll	$5, %eax
	addl	%r8d, %ecx
	rorl	$2, %esi
	movl	%r9d, %r8d
	addl	%ecx, %eax
	movl	%r10d, %ecx
	movl	-36(%rsp), %r10d
	xorl	%esi, %r8d
	xorl	%r15d, %ecx
	xorl	%edx, %r8d
	rorl	$2, %edx
	xorl	%r12d, %ecx
	xorl	%r10d, %ecx
	movl	-52(%rsp), %r10d
	roll	%ecx
	leal	-899497514(%rdi,%rcx), %edi
	addl	%r8d, %edi
	movl	%eax, %r8d
	roll	$5, %r8d
	addl	%edi, %r8d
	movl	%r11d, %edi
	xorl	%r14d, %edi
	xorl	%r10d, %edi
	movl	-56(%rsp), %r10d
	xorl	%r10d, %edi
	roll	%edi
	movl	%edi, -32(%rsp)
	movl	%esi, %edi
	movl	-32(%rsp), %r10d
	xorl	%edx, %edi
	xorl	%ebx, %r15d
	xorl	%ebp, %r14d
	xorl	%r13d, %ebx
	xorl	%eax, %edi
	leal	-899497514(%r9,%r10), %r9d
	rorl	$2, %eax
	movl	%r14d, %r11d
	addl	%edi, %r9d
	movl	%r8d, %edi
	movl	-48(%rsp), %r10d
	movl	-44(%rsp), %r14d
	roll	$5, %edi
	addl	%r9d, %edi
	movl	%r15d, %r9d
	xorl	%r14d, %r11d
	xorl	%r10d, %r9d
	movl	-60(%rsp), %r10d
	xorl	%ecx, %r11d
	roll	%r11d
	xorl	%r10d, %r9d
	movl	%edx, %r10d
	roll	%r9d
	xorl	%eax, %r10d
	xorl	%r8d, %r10d
	movl	%r9d, -28(%rsp)
	movl	%r9d, %r15d
	rorl	$2, %r8d
	leal	-899497514(%rsi,%r9), %r9d
	movl	%edi, %esi
	addl	%r10d, %r9d
	movl	%eax, %r10d
	roll	$5, %esi
	xorl	%r8d, %r10d
	addl	%r9d, %esi
	leal	-899497514(%rdx,%r11), %r9d
	xorl	%edi, %r10d
	movl	%esi, %edx
	rorl	$2, %edi
	addl	%r10d, %r9d
	movl	%ebx, %r10d
	movl	-40(%rsp), %ebx
	roll	$5, %edx
	addl	%r9d, %edx
	movl	-56(%rsp), %r14d
	xorl	%ebx, %r10d
	movl	-32(%rsp), %ebx
	xorl	%ebx, %r10d
	movl	%r8d, %ebx
	roll	%r10d
	xorl	%edi, %ebx
	xorl	%esi, %ebx
	leal	-899497514(%rax,%r10), %r9d
	movl	%edx, %eax
	addl	%ebx, %r9d
	roll	$5, %eax
	movl	-36(%rsp), %ebx
	addl	%r9d, %eax
	movl	-64(%rsp), %r9d
	rorl	$2, %esi
	xorl	%ebp, %r9d
	movl	%esi, %ebp
	xorl	%ebx, %r9d
	movl	%edi, %ebx
	xorl	%r15d, %r9d
	xorl	%esi, %ebx
	movl	-52(%rsp), %r15d
	roll	%r9d
	xorl	%edx, %ebx
	rorl	$2, %edx
	leal	-899497514(%r8,%r9), %r8d
	xorl	%edx, %ebp
	addl	%ebx, %r8d
	movl	%eax, %ebx
	xorl	%eax, %ebp
	rorl	$2, %eax
	roll	$5, %ebx
	addl	%r8d, %ebx
	movl	%r13d, %r8d
	xorl	%r12d, %r8d
	xorl	%r14d, %r8d
	movl	%ebx, %r14d
	xorl	%r11d, %r8d
	roll	$5, %r14d
	roll	%r8d
	leal	-899497514(%rdi,%r8), %edi
	addl	%ebp, %edi
	movl	%edx, %ebp
	addl	%edi, %r14d
	movl	-64(%rsp), %edi
	xorl	%eax, %ebp
	xorl	%ebx, %ebp
	movl	%r14d, %r13d
	xorl	%r15d, %edi
	movl	-60(%rsp), %r15d
	roll	$5, %r13d
	xorl	%r15d, %edi
	movl	-44(%rsp), %r15d
	xorl	%r10d, %edi
	roll	%edi
	leal	-899497514(%rsi,%rdi), %esi
	addl	%ebp, %esi
	movl	%eax, %ebp
	addl	%esi, %r13d
	movl	-48(%rsp), %esi
	rorl	$2, %ebx
	xorl	%ebx, %ebp
	xorl	%r12d, %esi
	xorl	%r14d, %ebp
	movl	%r13d, %r12d
	rorl	$2, %r14d
	xorl	%ecx, %esi
	roll	$5, %r12d
	xorl	%r9d, %esi
	roll	%esi
	leal	-899497514(%rdx,%rsi), %edx
	addl	%ebp, %edx
	movl	%ebx, %ebp
	addl	%edx, %r12d
	movl	-52(%rsp), %edx
	xorl	%r14d, %ebp
	xorl	%r13d, %ebp
	rorl	$2, %r13d
	xorl	%r15d, %edx
	movl	-32(%rsp), %r15d
	xorl	%r15d, %edx
	movl	-40(%rsp), %r15d
	xorl	%r8d, %edx
	roll	%edx
	leal	-899497514(%rax,%rdx), %eax
	addl	%ebp, %eax
	movl	%r12d, %ebp
	roll	$5, %ebp
	addl	%eax, %ebp
	movl	-48(%rsp), %eax
	xorl	%r15d, %eax
	movl	-28(%rsp), %r15d
	xorl	%r15d, %eax
	movl	%r14d, %r15d
	xorl	%edi, %eax
	xorl	%r13d, %r15d
	roll	%eax
	xorl	%r12d, %r15d
	rorl	$2, %r12d
	leal	-899497514(%rbx,%rax), %ebx
	movl	%eax, -64(%rsp)
	movl	-36(%rsp), %eax
	addl	%r15d, %ebx
	movl	%ebp, %r15d
	roll	$5, %r15d
	addl	%r15d, %ebx
	movl	-44(%rsp), %r15d
	xorl	%eax, %r15d
	movl	-56(%rsp), %eax
	xorl	%r15d, %r11d
	movl	%r13d, %r15d
	xorl	%esi, %r11d
	xorl	%r12d, %r15d
	roll	%r11d
	xorl	%ebp, %r15d
	rorl	$2, %ebp
	leal	-899497514(%r14,%r11), %r14d
	addl	%r15d, %r14d
	movl	%ebx, %r15d
	roll	$5, %r15d
	addl	%r15d, %r14d
	movl	-40(%rsp), %r15d
	xorl	%eax, %r15d
	movl	-60(%rsp), %eax
	xorl	%r10d, %r15d
	xorl	%r15d, %edx
	movl	%r12d, %r15d
	roll	%edx
	xorl	%ebp, %r15d
	xorl	%ebx, %r15d
	leal	-899497514(%r13,%rdx), %r10d
	movl	%r14d, %r13d
	rorl	$2, %ebx
	addl	%r15d, %r10d
	roll	$5, %r13d
	movl	-60(%rsp), %r15d
	addl	%r13d, %r10d
	movl	-36(%rsp), %r13d
	xorl	%eax, %r13d
	movl	-64(%rsp), %eax
	xorl	%r9d, %r13d
	xorl	%r13d, %eax
	movl	%ebp, %r13d
	roll	%eax
	xorl	%ebx, %r13d
	xorl	%r14d, %r13d
	leal	-899497514(%r12,%rax), %r9d
	movl	%r10d, %r12d
	rorl	$2, %r14d
	addl	%r13d, %r9d
	roll	$5, %r12d
	addl	%r12d, %r9d
	movl	-56(%rsp), %r12d
	xorl	%ecx, %r12d
	xorl	%r8d, %r12d
	movl	%ebx, %r8d
	xorl	%r12d, %r11d
	xorl	%r14d, %r8d
	roll	%r11d
	xorl	%r10d, %r8d
	rorl	$2, %r10d
	leal	-899497514(%rbp,%r11), %r11d
	addl	%r11d, %r8d
	movl	%r9d, %r11d
	roll	$5, %r11d
	addl	%r11d, %r8d
	movl	-32(%rsp), %r11d
	xorl	%r15d, %r11d
	xorl	%edi, %r11d
	xorl	%r11d, %edx
	roll	%edx
	leal	-899497514(%rbx,%rdx), %edi
	movl	%r14d, %edx
	xorl	%r10d, %edx
	xorl	%r9d, %edx
	rorl	$2, %r9d
	addl	%edi, %edx
	movl	%r8d, %edi
	roll	$5, %edi
	addl	%edi, %edx
	movl	-28(%rsp), %edi
	xorl	%edi, %ecx
	xorl	%esi, %ecx
	movl	-16(%rsp), %esi
	xorl	%ecx, %eax
	movl	%r10d, %ecx
	roll	%eax
	xorl	%r9d, %ecx
	leal	-899497514(%rsi,%rax), %eax
	xorl	%r8d, %ecx
	movq	-80(%rsp), %rsi
	rorl	$2, %r8d
	addl	%r14d, %eax
	addl	%ecx, %eax
	movl	%edx, %ecx
	roll	$5, %ecx
	addl	%ecx, %eax
	movl	%eax, (%rsi)
	movl	-8(%rsp), %eax
	addl	%edx, %eax
	movl	%eax, 4(%rsi)
	movl	-68(%rsp), %eax
	addl	%eax, %r8d
	movl	-12(%rsp), %eax
	movl	%r8d, 8(%rsi)
	addl	%r9d, %eax
	movl	%eax, 12(%rsi)
	movl	-4(%rsp), %eax
	addl	%r10d, %eax
	movl	%eax, 16(%rsi)
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z17sha_transformINITPjPh, .-_Z17sha_transformINITPjPh
	.globl	_Z35__device_stub__Z13sha_transformPiPjPiPj
	.type	_Z35__device_stub__Z13sha_transformPiPjPiPj, @function
_Z35__device_stub__Z13sha_transformPiPjPiPj:
.LFB4235:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13sha_transformPiPj(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L17:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4235:
	.size	_Z35__device_stub__Z13sha_transformPiPjPiPj, .-_Z35__device_stub__Z13sha_transformPiPjPiPj
	.globl	_Z13sha_transformPiPj
	.type	_Z13sha_transformPiPj, @function
_Z13sha_transformPiPj:
.LFB4236:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z13sha_transformPiPjPiPj
	.cfi_endproc
.LFE4236:
	.size	_Z13sha_transformPiPj, .-_Z13sha_transformPiPj
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"cudaSetDevice failed!  Do you have a CUDA-capable GPU installed?"
.LC1:
	.string	"cudaMalloc failed!"
.LC2:
	.string	"cudaMemcpyToSymbol failed!"
.LC3:
	.string	"cudaMemcpy failed!"
.LC4:
	.string	"addKernel launch failed: %s\n"
.LC5:
	.string	"cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
	.text
	.globl	_Z11addWithCudaPjPhPi
	.type	_Z11addWithCudaPjPhPi, @function
_Z11addWithCudaPjPhPi:
.LFB4210:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	xorl	%edi, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	xorl	%eax, %eax
	movq	%rax, (%rsp)
	movq	%rax, 8(%rsp)
	call	cudaSetDevice@PLT
	leaq	.LC0(%rip), %rdx
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L38
	movq	%rsp, %rdi
	movl	$131072, %esi
	call	cudaMalloc@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L40
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L26
.L40:
	leaq	.LC1(%rip), %rdx
	jmp	.L38
.L26:
	movl	$20, %edx
	movl	$1, %r8d
	xorl	%ecx, %ecx
	movq	%r13, %rsi
	leaq	_ZL15g_cSHA1baseCode(%rip), %rdi
	call	cudaMemcpyToSymbol@PLT
	leaq	.LC2(%rip), %rdx
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L38
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movl	$131072, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L39
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$4, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L39
	movl	$67108865, %edx
	movl	$134217729, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$6, %rdx
	salq	$5, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z35__device_stub__Z13sha_transformPiPjPiPj
.L30:
	call	cudaGetLastError@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L31
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L24
.L31:
	call	cudaDeviceSynchronize@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L32
	movq	stderr(%rip), %rdi
	movl	%eax, %ecx
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC5(%rip), %rdx
	call	__fprintf_chk@PLT
	jmp	.L24
.L32:
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movl	$131072, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	.L39
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L24
.L39:
	leaq	.LC3(%rip), %rdx
.L38:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L24:
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	movl	%ebx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4210:
	.size	_Z11addWithCudaPjPhPi, .-_Z11addWithCudaPjPhPi
	.section	.rodata.str1.1
.LC6:
	.string	"addWithCuda failed!"
.LC7:
	.string	"%x "
.LC8:
	.string	"%x %x %x"
.LC9:
	.string	"cudaDeviceReset failed!"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB4209:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	-131072(%rsp), %r11
	.cfi_def_cfa 11, 131104
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$48, %rsp
	.cfi_def_cfa_offset 131152
	movq	%fs:40, %rax
	movq	%rax, 131112(%rsp)
	xorl	%eax, %eax
	leaq	20(%rsp), %rbx
	leaq	8(%rsp), %rbp
	movq	%rbx, %rdi
	call	_Z8SHA1InitPj
	movq	8(%rsi), %rsi
	call	_Z17sha_transformINITPjPh
	call	_ZNSt6chrono3_V212system_clock3nowEv@PLT
	xorl	%edx, %edx
	movl	$2147483647, %ecx
	leaq	40(%rsp), %r8
	divq	%rcx
	movl	$1, %eax
	movq	%r8, %r11
	testq	%rdx, %rdx
	cmove	%rax, %rdx
	xorl	%r10d, %r10d
	movq	%rdx, 8(%rsp)
.L42:
	xorl	%r9d, %r9d
.L43:
	movl	$126, %edx
	movl	$33, %esi
	movq	%rbp, %rdi
	call	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE.isra.0
	movb	%al, (%r8,%r9)
	incq	%r9
	cmpq	$56, %r9
	jne	.L43
	xorl	%eax, %eax
	addl	$64, %r10d
	movb	$-128, 52(%r8)
	addq	$64, %r8
	movq	%rax, -8(%r8)
	movb	$3, -3(%r8)
	movb	$-72, -4(%r8)
	cmpl	$131072, %r10d
	jne	.L42
	movq	%rbx, %rdi
	leaq	4(%rsp), %rdx
	movq	%r11, %rsi
	movl	$-1, 4(%rsp)
	call	_Z11addWithCudaPjPhPi
	leaq	.LC7(%rip), %rbp
	movl	%eax, %ebx
	testl	%eax, %eax
	je	.L45
	movq	stderr(%rip), %rdi
	leaq	.LC6(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	jmp	.L58
.L47:
	movl	4(%rsp), %edx
	xorl	%eax, %eax
	movq	%rbp, %rsi
	movl	$2, %edi
	sall	$6, %edx
	addl	%ebx, %edx
	addl	%r12d, %edx
	movslq	%edx, %rdx
	movzbl	40(%rsp,%rdx), %edx
	call	__printf_chk@PLT
	subl	$1, %r12d
	jnb	.L47
	addl	$4, %ebx
	cmpl	$52, %ebx
	je	.L48
.L45:
	movl	$3, %r12d
	jmp	.L47
.L48:
	movl	4(%rsp), %eax
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	sall	$6, %eax
	leal	53(%rax), %edx
	leal	54(%rax), %ecx
	addl	$55, %eax
	cltq
	movslq	%edx, %rdx
	movslq	%ecx, %rcx
	movzbl	40(%rsp,%rax), %eax
	movzbl	40(%rsp,%rdx), %r8d
	movzbl	40(%rsp,%rcx), %ecx
	movl	%eax, %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	call	cudaDeviceReset@PLT
	movl	%eax, %edx
	xorl	%eax, %eax
	testl	%edx, %edx
	je	.L41
	movq	stderr(%rip), %rdi
	leaq	.LC9(%rip), %rdx
	movl	$2, %esi
.L58:
	call	__fprintf_chk@PLT
	movl	$1, %eax
.L41:
	movq	131112(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$131120, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4209:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z13sha_transformPiPj"
.LC11:
	.string	"g_cSHA1baseCode"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4238:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z13sha_transformPiPj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movl	$20, %r9d
	leaq	_ZL15g_cSHA1baseCode(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4238:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL15g_cSHA1baseCode
	.comm	_ZL15g_cSHA1baseCode,20,16
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"


#include <stdio.h>

#define __u32 unsigned int 
#define __u8 unsigned char

hipError_t addWithCuda(__u32 SHA1Sum[], __u8 SHA1Data[], int *retVal);


#define	FETCH_32(p)							\
	(((__u32)*((const __u8 *)(p) + 3)) |			\
	(((__u32)*((const __u8 *)(p) + 2)) << 8) |		\
	(((__u32)*((const __u8 *)(p) + 1)) << 16) |		\
	(((__u32)*((const __u8 *)(p))) << 24))

/* Constants from FIPS 180-1 */
#define	K_00_19		0x5a827999UL
#define	K_20_39		0x6ed9eba1UL
#define	K_40_59		0x8f1bbcdcUL
#define	K_60_79		0xca62c1d6UL

/* F, G, H and I are basic SHA1 functions. */
#define	F(b, c, d)	((((c) ^ (d)) & (b)) ^ (d))
#define	G(b, c, d)	((b) ^ (c) ^ (d))
#define	H(b, c, d)	(((b) & (c)) | (((b) | (c)) & (d)))

/* ROTATE_LEFT rotates x left n bits. */
#define	ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32 - (n))))

/* R, R1-R4 are macros used during each transformation round. */
#define R(f, k, v, w, x, y, z, i) {				\
	(v) = ROTATE_LEFT(w, 5) + f(x, y, z) + (v) + (i) + (k);	\
	(x) = ROTATE_LEFT(x, 30);				\
}

#define	R1(v, w, x, y, z, i)	R(F, K_00_19, v, w, x, y, z, i)
#define	R2(v, w, x, y, z, i)	R(G, K_20_39, v, w, x, y, z, i)
#define	R3(v, w, x, y, z, i)	R(H, K_40_59, v, w, x, y, z, i)
#define	R4(v, w, x, y, z, i)	R(G, K_60_79, v, w, x, y, z, i)

#define	WUPDATE(p, q, r, s) {		\
	(p) = ((q) ^ (r) ^ (s) ^ (p));	\
	(p) = ROTATE_LEFT(p, 1);	\
}

void SHA1Init(__u32 mass[]) {
	mass[0] = 0x67452301UL;
	mass[1] = 0xefcdab89UL;
	mass[2] = 0x98badcfeUL;
	mass[3] = 0x10325476UL;
	mass[4] = 0xc3d2e1f0UL;
}

void
sha_transformINIT(__u32 mass[], __u8 block[])
{
	__u32 a = mass[0];
	__u32 b = mass[1];
	__u32 c = mass[2];
	__u32 d = mass[3];
	__u32 e = mass[4];

	/* Register (instead of array) is a win in most cases */
	__u32 w0, w1, w2, w3, w4, w5, w6, w7;
	__u32 w8, w9, w10, w11, w12, w13, w14, w15;

	w15 = FETCH_32(block + 60);
	w14 = FETCH_32(block + 56);
	w13 = FETCH_32(block + 52);
	w12 = FETCH_32(block + 48);
	w11 = FETCH_32(block + 44);
	w10 = FETCH_32(block + 40);
	w9 = FETCH_32(block + 36);
	w8 = FETCH_32(block + 32);
	w7 = FETCH_32(block + 28);
	w6 = FETCH_32(block + 24);
	w5 = FETCH_32(block + 20);
	w4 = FETCH_32(block + 16);
	w3 = FETCH_32(block + 12);
	w2 = FETCH_32(block + 8);
	w1 = FETCH_32(block + 4);
	w0 = FETCH_32(block + 0);

	/* Round 1 */
	R1(e, a, b, c, d, w0);		/*  0 */
	R1(d, e, a, b, c, w1);		/*  1 */
	R1(c, d, e, a, b, w2);		/*  2 */
	R1(b, c, d, e, a, w3);		/*  3 */
	R1(a, b, c, d, e, w4);		/*  4 */
	R1(e, a, b, c, d, w5);		/*  5 */
	R1(d, e, a, b, c, w6);		/*  6 */
	R1(c, d, e, a, b, w7);		/*  7 */
	R1(b, c, d, e, a, w8);		/*  8 */
	R1(a, b, c, d, e, w9);		/*  9 */
	R1(e, a, b, c, d, w10);		/* 10 */
	R1(d, e, a, b, c, w11);		/* 11 */
	R1(c, d, e, a, b, w12);		/* 12 */
	R1(b, c, d, e, a, w13);		/* 13 */
	R1(a, b, c, d, e, w14);		/* 14 */
	R1(e, a, b, c, d, w15);		/* 15 */
	WUPDATE(w0, w13, w8, w2);	R1(d, e, a, b, c, w0);		/* 16 */
	WUPDATE(w1, w14, w9, w3);	R1(c, d, e, a, b, w1);		/* 17 */
	WUPDATE(w2, w15, w10, w4);	R1(b, c, d, e, a, w2);		/* 18 */
	WUPDATE(w3, w0, w11, w5);	R1(a, b, c, d, e, w3);		/* 19 */

	/* Round 2 */
	WUPDATE(w4, w1, w12, w6);	R2(e, a, b, c, d, w4);		/* 20 */
	WUPDATE(w5, w2, w13, w7);	R2(d, e, a, b, c, w5);		/* 21 */
	WUPDATE(w6, w3, w14, w8);	R2(c, d, e, a, b, w6);		/* 22 */
	WUPDATE(w7, w4, w15, w9);	R2(b, c, d, e, a, w7);		/* 23 */
	WUPDATE(w8, w5, w0, w10);	R2(a, b, c, d, e, w8);		/* 24 */
	WUPDATE(w9, w6, w1, w11);	R2(e, a, b, c, d, w9);		/* 25 */
	WUPDATE(w10, w7, w2, w12);	R2(d, e, a, b, c, w10);		/* 26 */
	WUPDATE(w11, w8, w3, w13);	R2(c, d, e, a, b, w11);		/* 27 */
	WUPDATE(w12, w9, w4, w14);	R2(b, c, d, e, a, w12);		/* 28 */
	WUPDATE(w13, w10, w5, w15);	R2(a, b, c, d, e, w13);		/* 29 */
	WUPDATE(w14, w11, w6, w0);	R2(e, a, b, c, d, w14);		/* 30 */
	WUPDATE(w15, w12, w7, w1);	R2(d, e, a, b, c, w15);		/* 31 */
	WUPDATE(w0, w13, w8, w2);	R2(c, d, e, a, b, w0);		/* 32 */
	WUPDATE(w1, w14, w9, w3);	R2(b, c, d, e, a, w1);		/* 33 */
	WUPDATE(w2, w15, w10, w4);	R2(a, b, c, d, e, w2);		/* 34 */
	WUPDATE(w3, w0, w11, w5);	R2(e, a, b, c, d, w3);		/* 35 */
	WUPDATE(w4, w1, w12, w6);	R2(d, e, a, b, c, w4);		/* 36 */
	WUPDATE(w5, w2, w13, w7);	R2(c, d, e, a, b, w5);		/* 37 */
	WUPDATE(w6, w3, w14, w8);	R2(b, c, d, e, a, w6);		/* 38 */
	WUPDATE(w7, w4, w15, w9);	R2(a, b, c, d, e, w7);		/* 39 */

	/* Round 3 */
	WUPDATE(w8, w5, w0, w10);	R3(e, a, b, c, d, w8);		/* 40 */
	WUPDATE(w9, w6, w1, w11);	R3(d, e, a, b, c, w9);		/* 41 */
	WUPDATE(w10, w7, w2, w12);	R3(c, d, e, a, b, w10);		/* 42 */
	WUPDATE(w11, w8, w3, w13);	R3(b, c, d, e, a, w11);		/* 43 */
	WUPDATE(w12, w9, w4, w14);	R3(a, b, c, d, e, w12);		/* 44 */
	WUPDATE(w13, w10, w5, w15);	R3(e, a, b, c, d, w13);		/* 45 */
	WUPDATE(w14, w11, w6, w0);	R3(d, e, a, b, c, w14);		/* 46 */
	WUPDATE(w15, w12, w7, w1);	R3(c, d, e, a, b, w15);		/* 47 */
	WUPDATE(w0, w13, w8, w2);	R3(b, c, d, e, a, w0);		/* 48 */
	WUPDATE(w1, w14, w9, w3);	R3(a, b, c, d, e, w1);		/* 49 */
	WUPDATE(w2, w15, w10, w4);	R3(e, a, b, c, d, w2);		/* 50 */
	WUPDATE(w3, w0, w11, w5);	R3(d, e, a, b, c, w3);		/* 51 */
	WUPDATE(w4, w1, w12, w6);	R3(c, d, e, a, b, w4);		/* 52 */
	WUPDATE(w5, w2, w13, w7);	R3(b, c, d, e, a, w5);		/* 53 */
	WUPDATE(w6, w3, w14, w8);	R3(a, b, c, d, e, w6);		/* 54 */
	WUPDATE(w7, w4, w15, w9);	R3(e, a, b, c, d, w7);		/* 55 */
	WUPDATE(w8, w5, w0, w10);	R3(d, e, a, b, c, w8);		/* 56 */
	WUPDATE(w9, w6, w1, w11);	R3(c, d, e, a, b, w9);		/* 57 */
	WUPDATE(w10, w7, w2, w12);	R3(b, c, d, e, a, w10);		/* 58 */
	WUPDATE(w11, w8, w3, w13);	R3(a, b, c, d, e, w11);		/* 59 */

	WUPDATE(w12, w9, w4, w14);	R4(e, a, b, c, d, w12);		/* 60 */
	WUPDATE(w13, w10, w5, w15);	R4(d, e, a, b, c, w13);		/* 61 */
	WUPDATE(w14, w11, w6, w0);	R4(c, d, e, a, b, w14);		/* 62 */
	WUPDATE(w15, w12, w7, w1);	R4(b, c, d, e, a, w15);		/* 63 */
	WUPDATE(w0, w13, w8, w2);	R4(a, b, c, d, e, w0);		/* 64 */
	WUPDATE(w1, w14, w9, w3);	R4(e, a, b, c, d, w1);		/* 65 */
	WUPDATE(w2, w15, w10, w4);	R4(d, e, a, b, c, w2);		/* 66 */
	WUPDATE(w3, w0, w11, w5);	R4(c, d, e, a, b, w3);		/* 67 */
	WUPDATE(w4, w1, w12, w6);	R4(b, c, d, e, a, w4);		/* 68 */
	WUPDATE(w5, w2, w13, w7);	R4(a, b, c, d, e, w5);		/* 69 */
	WUPDATE(w6, w3, w14, w8);	R4(e, a, b, c, d, w6);		/* 70 */
	WUPDATE(w7, w4, w15, w9);	R4(d, e, a, b, c, w7);		/* 71 */
	WUPDATE(w8, w5, w0, w10);	R4(c, d, e, a, b, w8);		/* 72 */
	WUPDATE(w9, w6, w1, w11);	R4(b, c, d, e, a, w9);		/* 73 */
	WUPDATE(w10, w7, w2, w12);	R4(a, b, c, d, e, w10);		/* 74 */
	WUPDATE(w11, w8, w3, w13);	R4(e, a, b, c, d, w11);		/* 75 */
	WUPDATE(w12, w9, w4, w14);	R4(d, e, a, b, c, w12);		/* 76 */
	WUPDATE(w13, w10, w5, w15);	R4(c, d, e, a, b, w13);		/* 77 */
	WUPDATE(w14, w11, w6, w0);	R4(b, c, d, e, a, w14);		/* 78 */
	WUPDATE(w15, w12, w7, w1);	R4(a, b, c, d, e, w15);		/* 79 */

	mass[0] += a;
	mass[1] += b;
	mass[2] += c;
	mass[3] += d;
	mass[4] += e;
}

__constant__ __u32 g_cSHA1baseCode[5];

__global__ void
sha_transform(int *ret_block, __u32 *in_block)
{
	__u32 *block = in_block + ((blockIdx.x << 6) + threadIdx.x) * 16;
	__u8 *pos_cur;

	__u32 a, b, c, d, e;
	/* Register (instead of array) is a win in most cases */
	__u32 w0, w1, w2, w3, w4, w5, w6, w7;
	__u32 w8, w9, w10, w11, w12, w13, w14, w15;
	__u32 wi[16];
	wi[0] = block[0];
	wi[1] = block[1];
	wi[2] = block[2];
	wi[3] = block[3];
	wi[4] = block[4];
	wi[5] = block[5];
	wi[6] = block[6];
	wi[7] = block[7];
	wi[8] = block[8];
	wi[9] = block[9];
	wi[10] = block[10];
	wi[11] = block[11];
	wi[12] = block[12];
	wi[13] = block[13];
	wi[14] = block[14];
	wi[15] = block[15];



	while (true) {
		pos_cur = (__u8*)wi;
		while (true) {
			if ((*pos_cur) == 126) {
				(*pos_cur) = 33;
				pos_cur++;
				continue;
			}
			(*pos_cur)++;

			a = g_cSHA1baseCode[0];
			b = g_cSHA1baseCode[1];
			c = g_cSHA1baseCode[2];
			d = g_cSHA1baseCode[3];
			e = g_cSHA1baseCode[4];

/*			w15 = FETCH_32((__u8 *)(block + 15));
			w14 = FETCH_32((__u8 *)(block + 14));
			w13 = FETCH_32((__u8 *)(block + 13));
			w12 = FETCH_32((__u8 *)(block + 12));
			w11 = FETCH_32((__u8 *)(block + 11));
			w10 = FETCH_32((__u8 *)(block + 10));
			w9 = FETCH_32((__u8 *)(block + 9));
			w8 = FETCH_32((__u8 *)(block + 8));
			w7 = FETCH_32((__u8 *)(block + 7));
			w6 = FETCH_32((__u8 *)(block + 6));
			w5 = FETCH_32((__u8 *)(block + 5));
			w4 = FETCH_32((__u8 *)(block + 4));
			w3 = FETCH_32((__u8 *)(block + 3));
			w2 = FETCH_32((__u8 *)(block + 2));
			w1 = FETCH_32((__u8 *)(block + 1));
			w0 = FETCH_32((__u8 *)(block + 0));
			*/
			w15 = wi[15];
			w14 = wi[14];
			w13 = wi[13];
			w12 = wi[12];
			w11 = wi[11];
			w10 = wi[10];
			w9 = wi[9];
			w8 = wi[8];
			w7 = wi[7];
			w6 = wi[6];
			w5 = wi[5];
			w4 = wi[4];
			w3 = wi[3];
			w2 = wi[2];
			w1 = wi[1];
			w0 = wi[0];

			/* Round 1 */
			R1(e, a, b, c, d, w0);		/*  0 */
			R1(d, e, a, b, c, w1);		/*  1 */
			R1(c, d, e, a, b, w2);		/*  2 */
			R1(b, c, d, e, a, w3);		/*  3 */
			R1(a, b, c, d, e, w4);		/*  4 */
			R1(e, a, b, c, d, w5);		/*  5 */
			R1(d, e, a, b, c, w6);		/*  6 */
			R1(c, d, e, a, b, w7);		/*  7 */
			R1(b, c, d, e, a, w8);		/*  8 */
			R1(a, b, c, d, e, w9);		/*  9 */
			R1(e, a, b, c, d, w10);		/* 10 */
			R1(d, e, a, b, c, w11);		/* 11 */
			R1(c, d, e, a, b, w12);		/* 12 */
			R1(b, c, d, e, a, w13);		/* 13 */
			R1(a, b, c, d, e, w14);		/* 14 */
			R1(e, a, b, c, d, w15);		/* 15 */
			WUPDATE(w0, w13, w8, w2);	R1(d, e, a, b, c, w0);		/* 16 */
			WUPDATE(w1, w14, w9, w3);	R1(c, d, e, a, b, w1);		/* 17 */
			WUPDATE(w2, w15, w10, w4);	R1(b, c, d, e, a, w2);		/* 18 */
			WUPDATE(w3, w0, w11, w5);	R1(a, b, c, d, e, w3);		/* 19 */

			/* Round 2 */
			WUPDATE(w4, w1, w12, w6);	R2(e, a, b, c, d, w4);		/* 20 */
			WUPDATE(w5, w2, w13, w7);	R2(d, e, a, b, c, w5);		/* 21 */
			WUPDATE(w6, w3, w14, w8);	R2(c, d, e, a, b, w6);		/* 22 */
			WUPDATE(w7, w4, w15, w9);	R2(b, c, d, e, a, w7);		/* 23 */
			WUPDATE(w8, w5, w0, w10);	R2(a, b, c, d, e, w8);		/* 24 */
			WUPDATE(w9, w6, w1, w11);	R2(e, a, b, c, d, w9);		/* 25 */
			WUPDATE(w10, w7, w2, w12);	R2(d, e, a, b, c, w10);		/* 26 */
			WUPDATE(w11, w8, w3, w13);	R2(c, d, e, a, b, w11);		/* 27 */
			WUPDATE(w12, w9, w4, w14);	R2(b, c, d, e, a, w12);		/* 28 */
			WUPDATE(w13, w10, w5, w15);	R2(a, b, c, d, e, w13);		/* 29 */
			WUPDATE(w14, w11, w6, w0);	R2(e, a, b, c, d, w14);		/* 30 */
			WUPDATE(w15, w12, w7, w1);	R2(d, e, a, b, c, w15);		/* 31 */
			WUPDATE(w0, w13, w8, w2);	R2(c, d, e, a, b, w0);		/* 32 */
			WUPDATE(w1, w14, w9, w3);	R2(b, c, d, e, a, w1);		/* 33 */
			WUPDATE(w2, w15, w10, w4);	R2(a, b, c, d, e, w2);		/* 34 */
			WUPDATE(w3, w0, w11, w5);	R2(e, a, b, c, d, w3);		/* 35 */
			WUPDATE(w4, w1, w12, w6);	R2(d, e, a, b, c, w4);		/* 36 */
			WUPDATE(w5, w2, w13, w7);	R2(c, d, e, a, b, w5);		/* 37 */
			WUPDATE(w6, w3, w14, w8);	R2(b, c, d, e, a, w6);		/* 38 */
			WUPDATE(w7, w4, w15, w9);	R2(a, b, c, d, e, w7);		/* 39 */

			/* Round 3 */
			WUPDATE(w8, w5, w0, w10);	R3(e, a, b, c, d, w8);		/* 40 */
			WUPDATE(w9, w6, w1, w11);	R3(d, e, a, b, c, w9);		/* 41 */
			WUPDATE(w10, w7, w2, w12);	R3(c, d, e, a, b, w10);		/* 42 */
			WUPDATE(w11, w8, w3, w13);	R3(b, c, d, e, a, w11);		/* 43 */
			WUPDATE(w12, w9, w4, w14);	R3(a, b, c, d, e, w12);		/* 44 */
			WUPDATE(w13, w10, w5, w15);	R3(e, a, b, c, d, w13);		/* 45 */
			WUPDATE(w14, w11, w6, w0);	R3(d, e, a, b, c, w14);		/* 46 */
			WUPDATE(w15, w12, w7, w1);	R3(c, d, e, a, b, w15);		/* 47 */
			WUPDATE(w0, w13, w8, w2);	R3(b, c, d, e, a, w0);		/* 48 */
			WUPDATE(w1, w14, w9, w3);	R3(a, b, c, d, e, w1);		/* 49 */
			WUPDATE(w2, w15, w10, w4);	R3(e, a, b, c, d, w2);		/* 50 */
			WUPDATE(w3, w0, w11, w5);	R3(d, e, a, b, c, w3);		/* 51 */
			WUPDATE(w4, w1, w12, w6);	R3(c, d, e, a, b, w4);		/* 52 */
			WUPDATE(w5, w2, w13, w7);	R3(b, c, d, e, a, w5);		/* 53 */
			WUPDATE(w6, w3, w14, w8);	R3(a, b, c, d, e, w6);		/* 54 */
			WUPDATE(w7, w4, w15, w9);	R3(e, a, b, c, d, w7);		/* 55 */
			WUPDATE(w8, w5, w0, w10);	R3(d, e, a, b, c, w8);		/* 56 */
			WUPDATE(w9, w6, w1, w11);	R3(c, d, e, a, b, w9);		/* 57 */
			WUPDATE(w10, w7, w2, w12);	R3(b, c, d, e, a, w10);		/* 58 */
			WUPDATE(w11, w8, w3, w13);	R3(a, b, c, d, e, w11);		/* 59 */

			WUPDATE(w12, w9, w4, w14);	R4(e, a, b, c, d, w12);		/* 60 */
			WUPDATE(w13, w10, w5, w15);	R4(d, e, a, b, c, w13);		/* 61 */
			WUPDATE(w14, w11, w6, w0);	R4(c, d, e, a, b, w14);		/* 62 */
			WUPDATE(w15, w12, w7, w1);	R4(b, c, d, e, a, w15);		/* 63 */
			WUPDATE(w0, w13, w8, w2);	R4(a, b, c, d, e, w0);		/* 64 */
			WUPDATE(w1, w14, w9, w3);	R4(e, a, b, c, d, w1);		/* 65 */
			WUPDATE(w2, w15, w10, w4);	R4(d, e, a, b, c, w2);		/* 66 */
			WUPDATE(w3, w0, w11, w5);	R4(c, d, e, a, b, w3);		/* 67 */
			WUPDATE(w4, w1, w12, w6);	R4(b, c, d, e, a, w4);		/* 68 */
			WUPDATE(w5, w2, w13, w7);	R4(a, b, c, d, e, w5);		/* 69 */
			WUPDATE(w6, w3, w14, w8);	R4(e, a, b, c, d, w6);		/* 70 */
			WUPDATE(w7, w4, w15, w9);	R4(d, e, a, b, c, w7);		/* 71 */
			WUPDATE(w8, w5, w0, w10);	R4(c, d, e, a, b, w8);		/* 72 */
			WUPDATE(w9, w6, w1, w11);	R4(b, c, d, e, a, w9);		/* 73 */
			WUPDATE(w10, w7, w2, w12);	R4(a, b, c, d, e, w10);		/* 74 */
			WUPDATE(w11, w8, w3, w13);	R4(e, a, b, c, d, w11);		/* 75 */
			WUPDATE(w12, w9, w4, w14);	R4(d, e, a, b, c, w12);		/* 76 */
			WUPDATE(w13, w10, w5, w15);	R4(c, d, e, a, b, w13);		/* 77 */
			WUPDATE(w14, w11, w6, w0);	R4(b, c, d, e, a, w14);		/* 78 */
			WUPDATE(w15, w12, w7, w1);	R4(a, b, c, d, e, w15);		/* 79 */
			a += g_cSHA1baseCode[0];
			
			if (((a) == 0)) {
				b += g_cSHA1baseCode[1];
				if ((b & 0xfff00000) == 0) {
					block[0] = wi[0];
					block[1] = wi[1];
					block[2] = wi[2];
					block[3] = wi[3];
					block[4] = wi[4];
					block[5] = wi[5];
					block[6] = wi[6];
					block[7] = wi[7];
					block[8] = wi[8];
					block[9] = wi[9];
					block[10] = wi[10];
					block[11] = wi[11];
					block[12] = wi[12];
					block[13] = wi[13];
					block[14] = wi[14];
					block[15] = wi[15];

					(*ret_block) = (blockIdx.x << 6) + threadIdx.x;
					return;
				}
			}
			if ((*ret_block) != -1)
				return;

			break;
		}
	}
}
#include <random>
#include <chrono>

int main(int argc, char **argv)
{
	__u32 buf[5];
	SHA1Init(buf);
	sha_transformINIT(buf, (unsigned char*)argv[1]);
	
	std::default_random_engine generator(std::chrono::system_clock::now().time_since_epoch().count());
	std::uniform_int_distribution<int> distribution(33, 126);

	unsigned char data[2048 * 64];
	//memset(data, 33, 2048 * 64);
	for (int j = 0; j < 2048; j++) {
		for (int i = 0; i < 56; i++)
			data[j*64 + i] = distribution(generator);
		//data[j * 64] = 33 + (j % 94);
		//data[j * 64 + 1] = 33 + int(j / 94);

		data[j * 64 + 52] = 0x80;
		memset(j * 64 + data + 56, 0, 8);
		data[j * 64 + 61] = 0x03;
		data[j * 64 + 60] = 0xb8;
	}

	int iRetVal = -1;
    // Add vectors in parallel.
    hipError_t cudaStatus = addWithCuda(buf, data, &iRetVal);
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "addWithCuda failed!");
        return 1;
    }
	for (int i = 0; i < 13; i++)
		for (int j = 3; j >= 0; j--)
			printf("%x ", data[iRetVal * 64 + (i << 2) + j]);
	printf("%x %x %x", data[iRetVal * 64 + 55], data[iRetVal * 64 + 54], data[iRetVal * 64 + 53]);

    // cudaDeviceReset must be called before exiting in order for profiling and
    // tracing tools such as Nsight and Visual Profiler to show complete traces.
    cudaStatus = hipDeviceReset();
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipDeviceReset failed!");
        return 1;
    }

    return 0;
}

// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(__u32 SHA1Sum[], __u8 SHA1Data[], int *retVal)
{
	__u32 *dev_SHA1Data = 0;
	int *dev_retVal = 0;
    hipError_t cudaStatus;

    // Choose which GPU to run on, change this on a multi-GPU system.
    cudaStatus = hipSetDevice(0);
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipSetDevice failed!  Do you have a CUDA-capable GPU installed?");
        goto Error;
    }

    cudaStatus = hipMalloc((void**)&dev_SHA1Data, 2048 * 64 * sizeof(__u8));
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipMalloc failed!");
        goto Error;
    }

	cudaStatus = hipMalloc((void**)&dev_retVal, sizeof(int));
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMalloc failed!");
		goto Error;
	}

	cudaStatus = hipMemcpyToSymbol(HIP_SYMBOL(g_cSHA1baseCode), SHA1Sum, 5 * sizeof(__u32));
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipMemcpyToSymbol failed!");
        goto Error;
    }

    cudaStatus = hipMemcpy(dev_SHA1Data, SHA1Data, 2048 * 64 * sizeof(__u8), hipMemcpyHostToDevice);
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipMemcpy failed!");
        goto Error;
    }

	cudaStatus = hipMemcpy(dev_retVal, retVal, sizeof(int), hipMemcpyHostToDevice);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy failed!");
		goto Error;
	}

    // Launch a kernel on the GPU with one thread for each element.
	sha_transform <<<32, 64>>>(dev_retVal, dev_SHA1Data);

    // Check for any errors launching the kernel
    cudaStatus = hipGetLastError();
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
        goto Error;
    }
    
    // cudaDeviceSynchronize waits for the kernel to finish, and returns
    // any errors encountered during the launch.
    cudaStatus = hipDeviceSynchronize();
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
        goto Error;
    }

    // Copy output vector from GPU buffer to host memory.
    cudaStatus = hipMemcpy(SHA1Data, dev_SHA1Data, 2048 * 64 * sizeof(__u8), hipMemcpyDeviceToHost);
    if (cudaStatus != hipSuccess) {
        fprintf(stderr, "hipMemcpy failed!");
        goto Error;
    }

	// Copy output vector from GPU buffer to host memory.
	cudaStatus = hipMemcpy(retVal, dev_retVal, sizeof(int), hipMemcpyDeviceToHost);
	if (cudaStatus != hipSuccess) {
		fprintf(stderr, "hipMemcpy failed!");
		goto Error;
	}

Error:
    hipFree(dev_SHA1Data);
	hipFree(dev_retVal);

    return cudaStatus;
}

	.text
	.file	"kernel.hip"
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z8SHA1InitPj
.LCPI0_0:
	.long	1732584193                      # 0x67452301
	.long	4023233417                      # 0xefcdab89
	.long	2562383102                      # 0x98badcfe
	.long	271733878                       # 0x10325476
	.text
	.globl	_Z8SHA1InitPj
	.type	_Z8SHA1InitPj,@function
_Z8SHA1InitPj:                          # @_Z8SHA1InitPj
	.cfi_startproc
# %bb.0:
	movaps	.LCPI0_0(%rip), %xmm0           # xmm0 = [1732584193,4023233417,2562383102,271733878]
	movups	%xmm0, (%rdi)
	movl	$-1009589776, 16(%rdi)          # imm = 0xC3D2E1F0
	retq
.Lfunc_end0:
	.size	_Z8SHA1InitPj, .Lfunc_end0-_Z8SHA1InitPj
	.cfi_endproc
                                        # -- End function
	.globl	_Z17sha_transformINITPjPh       # -- Begin function _Z17sha_transformINITPjPh
	.type	_Z17sha_transformINITPjPh,@function
_Z17sha_transformINITPjPh:              # @_Z17sha_transformINITPjPh
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, -8(%rsp)                  # 8-byte Spill
	movl	(%rdi), %r11d
	movl	4(%rdi), %r9d
	movl	8(%rdi), %r8d
	movl	12(%rdi), %eax
	movl	16(%rdi), %ecx
	movl	%ecx, -36(%rsp)                 # 4-byte Spill
	movl	8(%rsi), %r12d
	movl	(%rsi), %edx
	movl	4(%rsi), %ebx
	bswapl	%ebx
	bswapl	%edx
	movq	%rdx, %r14
	movq	%rdx, -72(%rsp)                 # 8-byte Spill
	movl	%r11d, %r10d
	roll	$5, %r10d
	movq	%rax, %rdx
	xorl	%r8d, %eax
	movq	%r9, %r15
	movq	%r9, -16(%rsp)                  # 8-byte Spill
	andl	%r15d, %eax
	xorl	%edx, %eax
	movq	%rdx, -24(%rsp)                 # 8-byte Spill
	addl	%ecx, %r10d
	addl	%eax, %r10d
	movl	$1518500249, %eax               # imm = 0x5A827999
	addl	%r14d, %r10d
	addl	%eax, %r10d
                                        # kill: def $r15d killed $r15d killed $r15 def $r15
	roll	$30, %r15d
	movl	%r15d, %r14d
	xorl	%r8d, %r14d
	movl	%r11d, -40(%rsp)                # 4-byte Spill
	andl	%r11d, %r14d
	xorl	%r8d, %r14d
	movq	%r8, -32(%rsp)                  # 8-byte Spill
	addl	%edx, %r14d
	addl	%ebx, %r14d
	movl	%r10d, %ecx
	roll	$5, %ecx
	movq	%r12, %rdx
	bswapl	%edx
	movq	%rdx, -64(%rsp)                 # 8-byte Spill
	movl	$1518500249, %eax               # imm = 0x5A827999
	addl	%eax, %r14d
	addl	%ecx, %r14d
                                        # kill: def $r11d killed $r11d def $r11
	roll	$30, %r11d
	movl	%r15d, %r12d
	xorl	%r11d, %r12d
	andl	%r10d, %r12d
	xorl	%r15d, %r12d
	addl	%r8d, %r12d
	addl	%edx, %r12d
	movl	%r14d, %ecx
	roll	$5, %ecx
	addl	%eax, %r12d
	movl	$1518500249, %eax               # imm = 0x5A827999
	addl	%ecx, %r12d
	roll	$30, %r10d
	movl	12(%rsi), %ecx
	bswapl	%ecx
	movl	%ecx, %edx
	movl	%ecx, -44(%rsp)                 # 4-byte Spill
	movl	%r10d, %ecx
	xorl	%r11d, %ecx
	andl	%r14d, %ecx
	xorl	%r11d, %ecx
	addl	%edx, %r15d
	addl	%ecx, %r15d
	movl	%r12d, %ecx
	roll	$5, %ecx
	addl	%eax, %r15d
	addl	%ecx, %r15d
	movl	16(%rsi), %ecx
	bswapl	%ecx
	movl	%ecx, %edx
	movl	%ecx, -120(%rsp)                # 4-byte Spill
	roll	$30, %r14d
	movl	%r15d, %ecx
	roll	$5, %ecx
	movl	%r14d, %edi
	xorl	%r10d, %edi
	andl	%r12d, %edi
	xorl	%r10d, %edi
	addl	%edx, %r11d
	addl	%edi, %r11d
	addl	%eax, %r11d
	addl	%ecx, %r11d
	movl	20(%rsi), %ecx
	bswapl	%ecx
	movl	%ecx, -116(%rsp)                # 4-byte Spill
	roll	$30, %r12d
	movl	%r12d, %edi
	xorl	%r14d, %edi
	andl	%r15d, %edi
	xorl	%r14d, %edi
	addl	%ecx, %r10d
	addl	%edi, %r10d
	movl	%r11d, %edi
	roll	$5, %edi
	addl	%eax, %r10d
	addl	%edi, %r10d
	movl	24(%rsi), %ecx
	bswapl	%ecx
	movl	%ecx, -100(%rsp)                # 4-byte Spill
	roll	$30, %r15d
	movl	%r15d, %edi
	xorl	%r12d, %edi
	andl	%r11d, %edi
	xorl	%r12d, %edi
	addl	%ecx, %r14d
	addl	%edi, %r14d
	movl	%r10d, %edi
	roll	$5, %edi
	addl	%eax, %r14d
	addl	%edi, %r14d
	roll	$30, %r11d
	movl	28(%rsi), %ecx
	bswapl	%ecx
	movl	%ecx, -104(%rsp)                # 4-byte Spill
	movl	%r11d, %r8d
	xorl	%r15d, %r8d
	andl	%r10d, %r8d
	xorl	%r15d, %r8d
	addl	%ecx, %r12d
	addl	%r8d, %r12d
	movl	%r14d, %r8d
	roll	$5, %r8d
	addl	%eax, %r12d
	addl	%r8d, %r12d
	movl	32(%rsi), %edi
	bswapl	%edi
	roll	$30, %r10d
	movl	%r12d, %r8d
	roll	$5, %r8d
	movl	%r10d, %r9d
	xorl	%r11d, %r9d
	andl	%r14d, %r9d
	xorl	%r11d, %r9d
	addl	%edi, %r15d
	movl	%edi, -88(%rsp)                 # 4-byte Spill
	addl	%r9d, %r15d
	addl	%eax, %r15d
	addl	%r8d, %r15d
	movl	36(%rsi), %ecx
	bswapl	%ecx
	movl	%ecx, -96(%rsp)                 # 4-byte Spill
	roll	$30, %r14d
	movl	%r14d, %r8d
	xorl	%r10d, %r8d
	andl	%r12d, %r8d
	xorl	%r10d, %r8d
	addl	%ecx, %r11d
	addl	%r8d, %r11d
	movl	%r15d, %r8d
	roll	$5, %r8d
	addl	%eax, %r11d
	addl	%r8d, %r11d
	movl	40(%rsi), %r13d
	bswapl	%r13d
	roll	$30, %r12d
	movl	%r12d, %r8d
	xorl	%r14d, %r8d
	andl	%r15d, %r8d
	xorl	%r14d, %r8d
	addl	%r13d, %r10d
	movl	%r13d, -92(%rsp)                # 4-byte Spill
	addl	%r8d, %r10d
	movl	%r11d, %r8d
	roll	$5, %r8d
	addl	%eax, %r10d
	addl	%r8d, %r10d
	roll	$30, %r15d
	movl	44(%rsi), %edx
	bswapl	%edx
	movl	%edx, -80(%rsp)                 # 4-byte Spill
	movl	%r15d, %r8d
	xorl	%r12d, %r8d
	andl	%r11d, %r8d
	xorl	%r12d, %r8d
	addl	%edx, %r14d
	addl	%r8d, %r14d
	movl	%r10d, %r8d
	roll	$5, %r8d
	addl	%eax, %r14d
	addl	%r8d, %r14d
	movl	48(%rsi), %eax
	bswapl	%eax
	movl	%eax, -108(%rsp)                # 4-byte Spill
	roll	$30, %r11d
	movl	%r14d, %r8d
	roll	$5, %r8d
	movl	%r11d, %r9d
	xorl	%r15d, %r9d
	andl	%r10d, %r9d
	xorl	%r15d, %r9d
	addl	%eax, %r12d
	addl	%r9d, %r12d
	movl	$1518500249, %eax               # imm = 0x5A827999
	addl	%eax, %r12d
	addl	%r8d, %r12d
	movl	52(%rsi), %ebp
	bswapl	%ebp
	roll	$30, %r10d
	movl	%r10d, %r8d
	xorl	%r11d, %r8d
	andl	%r14d, %r8d
	xorl	%r11d, %r8d
	addl	%ebp, %r15d
	addl	%r8d, %r15d
	movl	%r12d, %r8d
	roll	$5, %r8d
	addl	%eax, %r15d
	movl	$1518500249, %ecx               # imm = 0x5A827999
	addl	%r8d, %r15d
	movl	56(%rsi), %edx
	bswapl	%edx
	roll	$30, %r14d
	movl	%r14d, %r8d
	xorl	%r10d, %r8d
	andl	%r12d, %r8d
	xorl	%r10d, %r8d
	addl	%edx, %r11d
	movl	%edx, %r9d
	movl	%edx, -84(%rsp)                 # 4-byte Spill
	addl	%r8d, %r11d
	movl	%r15d, %r8d
	roll	$5, %r8d
	addl	%ecx, %r11d
	addl	%r8d, %r11d
	movl	60(%rsi), %eax
	roll	$30, %r12d
	bswapl	%eax
	movl	%r12d, %esi
	xorl	%r14d, %esi
	andl	%r15d, %esi
	xorl	%r14d, %esi
	addl	%eax, %r10d
	addl	%esi, %r10d
	movl	%r11d, %esi
	roll	$5, %esi
	addl	%ecx, %r10d
	addl	%esi, %r10d
	movl	%edi, %esi
	xorl	%ebp, %esi
	movq	-72(%rsp), %rdx                 # 8-byte Reload
	movq	-64(%rsp), %rdi                 # 8-byte Reload
	xorl	%edi, %edx
	xorl	%esi, %edx
	roll	$30, %r15d
	roll	%edx
	movq	%rdx, -72(%rsp)                 # 8-byte Spill
	movl	%r10d, %esi
	roll	$5, %esi
	movl	%r15d, %r8d
	xorl	%r12d, %r8d
	andl	%r11d, %r8d
	xorl	%r12d, %r8d
	addl	%edx, %r14d
	addl	%r8d, %r14d
	addl	%ecx, %r14d
	roll	$30, %r11d
	addl	%esi, %r14d
	movl	-96(%rsp), %ecx                 # 4-byte Reload
	movl	%ecx, %esi
	xorl	%r9d, %esi
	movl	-44(%rsp), %r9d                 # 4-byte Reload
	xorl	%r9d, %ebx
	xorl	%esi, %ebx
	roll	%ebx
	movq	%rbx, -56(%rsp)                 # 8-byte Spill
	movl	%r11d, %esi
	xorl	%r15d, %esi
	andl	%r10d, %esi
	xorl	%r15d, %esi
	addl	%ebx, %r12d
	addl	%esi, %r12d
	movl	%r14d, %esi
	roll	$5, %esi
	movl	$1518500249, %edx               # imm = 0x5A827999
	addl	%edx, %r12d
	addl	%esi, %r12d
	movl	%r13d, %esi
	movl	%eax, -76(%rsp)                 # 4-byte Spill
	xorl	%eax, %esi
	movq	%rdi, %r13
	xorl	-120(%rsp), %r13d               # 4-byte Folded Reload
	xorl	%esi, %r13d
	roll	$30, %r10d
	roll	%r13d
	movq	%r13, -64(%rsp)                 # 8-byte Spill
	movl	%r10d, %esi
	xorl	%r11d, %esi
	andl	%r14d, %esi
	xorl	%r11d, %esi
	addl	%r13d, %r15d
	addl	%esi, %r15d
	movl	%r12d, %esi
	roll	$5, %esi
	addl	%edx, %r15d
	movl	$1518500249, %r8d               # imm = 0x5A827999
	addl	%esi, %r15d
	xorl	%eax, %ecx
	movl	-104(%rsp), %edi                # 4-byte Reload
	xorl	%edi, %ecx
	movl	%ecx, -112(%rsp)                # 4-byte Spill
	xorl	%ebp, %edi
	movl	-116(%rsp), %edx                # 4-byte Reload
	xorl	%edx, %edi
	movl	%edi, %esi
	xorl	-80(%rsp), %edx                 # 4-byte Folded Reload
	xorl	%r9d, %edx
	roll	$30, %r14d
	xorl	-72(%rsp), %edx                 # 4-byte Folded Reload
	roll	%edx
	movl	%r14d, %ecx
	xorl	%r10d, %ecx
	andl	%r12d, %ecx
	xorl	%r10d, %ecx
	addl	%edx, %r11d
	movl	%edx, -104(%rsp)                # 4-byte Spill
	addl	%ecx, %r11d
	movl	%r15d, %ecx
	roll	$5, %ecx
	addl	%r8d, %r11d
	roll	$30, %r12d
	movl	-88(%rsp), %r8d                 # 4-byte Reload
	movl	%r8d, %r9d
	xorl	-84(%rsp), %r9d                 # 4-byte Folded Reload
	movl	-100(%rsp), %r13d               # 4-byte Reload
	xorl	%r13d, %r9d
	xorl	-108(%rsp), %r13d               # 4-byte Folded Reload
	xorl	-120(%rsp), %r13d               # 4-byte Folded Reload
	movq	-56(%rsp), %rdi                 # 8-byte Reload
	xorl	%edi, %r13d
	roll	%r13d
	addl	%ecx, %r11d
	movl	%r11d, %ecx
	roll	$5, %ecx
	movl	%r12d, %eax
	xorl	%r14d, %eax
	xorl	%r15d, %eax
	addl	%r13d, %r10d
	movl	%r13d, %ebx
	movl	%r13d, -116(%rsp)               # 4-byte Spill
	addl	%eax, %r10d
	roll	$30, %r15d
	movl	$1859775393, %eax               # imm = 0x6ED9EBA1
	addl	%eax, %r10d
	movl	%esi, %eax
	movq	-64(%rsp), %r13                 # 8-byte Reload
	xorl	%r13d, %eax
	roll	%eax
	addl	%ecx, %r10d
	movl	%r10d, %ecx
	roll	$5, %ecx
	movl	%r15d, %esi
	xorl	%r12d, %esi
	xorl	%r11d, %esi
	addl	%eax, %r14d
	movl	%eax, -120(%rsp)                # 4-byte Spill
	addl	%esi, %r14d
	movl	$1859775393, %esi               # imm = 0x6ED9EBA1
	addl	%esi, %r14d
	roll	$30, %r11d
	addl	%ecx, %r14d
	xorl	%edx, %r9d
	roll	%r9d
	movl	%r11d, %ecx
	xorl	%r15d, %ecx
	xorl	%r10d, %ecx
	addl	%r9d, %r12d
	movl	%r9d, -100(%rsp)                # 4-byte Spill
	addl	%ecx, %r12d
	movl	%r14d, %ecx
	roll	$5, %ecx
	addl	%esi, %r12d
	addl	%ecx, %r12d
	roll	$30, %r10d
	movl	-112(%rsp), %edx                # 4-byte Reload
	xorl	%ebx, %edx
	roll	%edx
	movl	%edx, -112(%rsp)                # 4-byte Spill
	movl	%r10d, %ecx
	xorl	%r11d, %ecx
	xorl	%r14d, %ecx
	addl	%edx, %r15d
	addl	%ecx, %r15d
	movl	%r12d, %ecx
	roll	$5, %ecx
	movl	$1859775393, %edx               # imm = 0x6ED9EBA1
	addl	%edx, %r15d
	addl	%ecx, %r15d
	roll	$30, %r14d
	movl	%r8d, %ebx
	movl	-92(%rsp), %r8d                 # 4-byte Reload
	xorl	%r8d, %ebx
	xorl	-72(%rsp), %ebx                 # 4-byte Folded Reload
	xorl	%eax, %ebx
	roll	%ebx
	movl	%r14d, %ecx
	xorl	%r10d, %ecx
	xorl	%r12d, %ecx
	addl	%ebx, %r11d
	movl	%ebx, -88(%rsp)                 # 4-byte Spill
	addl	%ecx, %r11d
	movl	%r15d, %ecx
	roll	$5, %ecx
	addl	%edx, %r11d
	roll	$30, %r12d
	movl	-96(%rsp), %eax                 # 4-byte Reload
	movl	-80(%rsp), %edx                 # 4-byte Reload
	xorl	%edx, %eax
	xorl	%edi, %eax
	xorl	%r9d, %eax
	roll	%eax
	addl	%ecx, %r11d
	movl	%r11d, %ecx
	roll	$5, %ecx
	movl	%r12d, %esi
	xorl	%r14d, %esi
	xorl	%r15d, %esi
	addl	%eax, %r10d
	movl	%eax, %edi
	movl	%eax, -96(%rsp)                 # 4-byte Spill
	addl	%esi, %r10d
	movl	$1859775393, %eax               # imm = 0x6ED9EBA1
	addl	%eax, %r10d
	roll	$30, %r15d
	addl	%ecx, %r10d
	movl	%r8d, %ecx
	movl	-108(%rsp), %esi                # 4-byte Reload
	xorl	%esi, %ecx
	xorl	%r13d, %ecx
	movl	-112(%rsp), %r13d               # 4-byte Reload
	xorl	%r13d, %ecx
	roll	%ecx
	movl	%ecx, %r8d
	movl	%r15d, %ecx
	xorl	%r12d, %ecx
	xorl	%r11d, %ecx
	addl	%r8d, %r14d
	movl	%r8d, -92(%rsp)                 # 4-byte Spill
	addl	%ecx, %r14d
	movl	%r10d, %ecx
	roll	$5, %ecx
	addl	%eax, %r14d
	addl	%ecx, %r14d
	roll	$30, %r11d
	movl	%edx, %r9d
	xorl	%ebp, %r9d
	xorl	-104(%rsp), %r9d                # 4-byte Folded Reload
	xorl	%ebx, %r9d
	roll	%r9d
	movl	%r11d, %ecx
	xorl	%r15d, %ecx
	xorl	%r10d, %ecx
	addl	%r9d, %r12d
	movl	%r9d, -80(%rsp)                 # 4-byte Spill
	addl	%ecx, %r12d
	movl	%r14d, %ecx
	roll	$5, %ecx
	movl	$1859775393, %edx               # imm = 0x6ED9EBA1
	addl	%edx, %r12d
	addl	%ecx, %r12d
	roll	$30, %r10d
	movl	%esi, %ecx
	movl	-84(%rsp), %eax                 # 4-byte Reload
	xorl	%eax, %ecx
	xorl	-116(%rsp), %ecx                # 4-byte Folded Reload
	xorl	%edi, %ecx
	roll	%ecx
	movl	%ecx, %edi
	movl	%r10d, %ecx
	xorl	%r11d, %ecx
	xorl	%r14d, %ecx
	addl	%edi, %r15d
	movl	%edi, -108(%rsp)                # 4-byte Spill
	addl	%ecx, %r15d
	movl	%r12d, %ecx
	roll	$5, %ecx
	addl	%edx, %r15d
	movl	$1859775393, %ebx               # imm = 0x6ED9EBA1
	roll	$30, %r14d
	movl	-76(%rsp), %edx                 # 4-byte Reload
	xorl	%edx, %ebp
	xorl	-120(%rsp), %ebp                # 4-byte Folded Reload
	xorl	%r8d, %ebp
	roll	%ebp
	addl	%ecx, %r15d
	movl	%r15d, %ecx
	roll	$5, %ecx
	movl	%r14d, %esi
	xorl	%r10d, %esi
	xorl	%r12d, %esi
	addl	%ebp, %r11d
	addl	%esi, %r11d
	addl	%ebx, %r11d
	roll	$30, %r12d
	addl	%ecx, %r11d
	movq	-72(%rsp), %r8                  # 8-byte Reload
	xorl	%r8d, %eax
	xorl	-100(%rsp), %eax                # 4-byte Folded Reload
	xorl	%r9d, %eax
	roll	%eax
	movl	%r12d, %ecx
	xorl	%r14d, %ecx
	xorl	%r15d, %ecx
	addl	%eax, %r10d
	movl	%eax, -84(%rsp)                 # 4-byte Spill
	addl	%ecx, %r10d
	movl	%r11d, %ecx
	roll	$5, %ecx
	addl	%ebx, %r10d
	addl	%ecx, %r10d
	roll	$30, %r15d
	movq	-56(%rsp), %r9                  # 8-byte Reload
	xorl	%r9d, %edx
	xorl	%r13d, %edx
	xorl	%edi, %edx
	roll	%edx
	movl	%r15d, %ecx
	xorl	%r12d, %ecx
	xorl	%r11d, %ecx
	addl	%edx, %r14d
	movl	%edx, -76(%rsp)                 # 4-byte Spill
	addl	%ecx, %r14d
	movl	%r10d, %ecx
	roll	$5, %ecx
	addl	%ebx, %r14d
	movl	$1859775393, %edi               # imm = 0x6ED9EBA1
	addl	%ecx, %r14d
	roll	$30, %r11d
	movq	%r8, %rcx
	movq	-64(%rsp), %r8                  # 8-byte Reload
	xorl	%r8d, %ecx
	xorl	-88(%rsp), %ecx                 # 4-byte Folded Reload
	xorl	%ebp, %ecx
	roll	%ecx
	movq	%rcx, %rsi
	movq	%rcx, -72(%rsp)                 # 8-byte Spill
	movl	%r11d, %ecx
	xorl	%r15d, %ecx
	xorl	%r10d, %ecx
	addl	%esi, %r12d
	addl	%ecx, %r12d
	movl	%r14d, %ecx
	roll	$5, %ecx
	addl	%edi, %r12d
	roll	$30, %r10d
	movl	-104(%rsp), %ebx                # 4-byte Reload
	xorl	%ebx, %r9d
	xorl	-96(%rsp), %r9d                 # 4-byte Folded Reload
	xorl	%eax, %r9d
	roll	%r9d
	addl	%ecx, %r12d
	movl	%r12d, %ecx
	roll	$5, %ecx
	movl	%r10d, %esi
	xorl	%r11d, %esi
	xorl	%r14d, %esi
	addl	%r9d, %r15d
	movq	%r9, -56(%rsp)                  # 8-byte Spill
	addl	%esi, %r15d
	movl	$1859775393, %eax               # imm = 0x6ED9EBA1
	addl	%eax, %r15d
	roll	$30, %r14d
	addl	%ecx, %r15d
	movq	%r8, %rcx
	movl	-116(%rsp), %r13d               # 4-byte Reload
	xorl	%r13d, %ecx
	xorl	-92(%rsp), %ecx                 # 4-byte Folded Reload
	xorl	%edx, %ecx
	roll	%ecx
	movq	%rcx, %rsi
	movl	%r14d, %ecx
	xorl	%r10d, %ecx
	xorl	%r12d, %ecx
	addl	%esi, %r11d
	movq	%rsi, -64(%rsp)                 # 8-byte Spill
	addl	%ecx, %r11d
	movl	%r15d, %ecx
	roll	$5, %ecx
	addl	%eax, %r11d
	addl	%ecx, %r11d
	roll	$30, %r12d
	movl	%ebx, %eax
	movl	-120(%rsp), %r8d                # 4-byte Reload
	xorl	%r8d, %eax
	xorl	-80(%rsp), %eax                 # 4-byte Folded Reload
	xorl	-72(%rsp), %eax                 # 4-byte Folded Reload
	roll	%eax
	movl	%r12d, %ecx
	xorl	%r14d, %ecx
	xorl	%r15d, %ecx
	addl	%eax, %r10d
	movl	%eax, -104(%rsp)                # 4-byte Spill
	addl	%ecx, %r10d
	movl	%r11d, %ecx
	roll	$5, %ecx
	addl	%edi, %r10d
	movl	$1859775393, %edx               # imm = 0x6ED9EBA1
	addl	%ecx, %r10d
	roll	$30, %r15d
	movl	-100(%rsp), %edi                # 4-byte Reload
	xorl	%edi, %r13d
	xorl	-108(%rsp), %r13d               # 4-byte Folded Reload
	xorl	%r9d, %r13d
	roll	%r13d
	movl	%r15d, %ecx
	xorl	%r12d, %ecx
	xorl	%r11d, %ecx
	addl	%r13d, %r14d
	movl	%r13d, %ebx
	movl	%r13d, -116(%rsp)               # 4-byte Spill
	addl	%ecx, %r14d
	movl	%r10d, %ecx
	roll	$5, %ecx
	addl	%edx, %r14d
	roll	$30, %r11d
	movl	%r8d, %r13d
	movl	-112(%rsp), %edx                # 4-byte Reload
	xorl	%edx, %r13d
	xorl	%ebp, %r13d
	xorl	%esi, %r13d
	roll	%r13d
	addl	%ecx, %r14d
	movl	%r14d, %ecx
	roll	$5, %ecx
	movl	%r11d, %esi
	xorl	%r15d, %esi
	xorl	%r10d, %esi
	addl	%r13d, %r12d
	movl	%r13d, -120(%rsp)               # 4-byte Spill
	addl	%esi, %r12d
	movl	$1859775393, %esi               # imm = 0x6ED9EBA1
	addl	%esi, %r12d
	roll	$30, %r10d
	addl	%ecx, %r12d
	movl	-88(%rsp), %r9d                 # 4-byte Reload
	xorl	%r9d, %edi
	xorl	-84(%rsp), %edi                 # 4-byte Folded Reload
	xorl	%eax, %edi
	roll	%edi
	movl	%r10d, %ecx
	xorl	%r11d, %ecx
	xorl	%r14d, %ecx
	addl	%edi, %r15d
	movl	%edi, -100(%rsp)                # 4-byte Spill
	addl	%ecx, %r15d
	movl	%r12d, %ecx
	roll	$5, %ecx
	addl	%esi, %r15d
	movl	$1859775393, %eax               # imm = 0x6ED9EBA1
	addl	%ecx, %r15d
	roll	$30, %r14d
	movl	-96(%rsp), %esi                 # 4-byte Reload
	xorl	%esi, %edx
	xorl	-76(%rsp), %edx                 # 4-byte Folded Reload
	xorl	%ebx, %edx
	roll	%edx
	movl	%r14d, %ecx
	xorl	%r10d, %ecx
	xorl	%r12d, %ecx
	addl	%edx, %r11d
	movl	%edx, -112(%rsp)                # 4-byte Spill
	addl	%ecx, %r11d
	addl	%eax, %r11d
	movl	%r15d, %eax
	roll	$5, %eax
	addl	%eax, %r11d
	roll	$30, %r12d
	movl	%r15d, %eax
	andl	%r12d, %eax
	movl	%r15d, %ecx
	orl	%r12d, %ecx
	andl	%r14d, %ecx
	orl	%eax, %ecx
	movl	%r9d, %eax
	movl	-92(%rsp), %r8d                 # 4-byte Reload
	xorl	%r8d, %eax
	xorl	-72(%rsp), %eax                 # 4-byte Folded Reload
	xorl	%r13d, %eax
	roll	%eax
	movl	%eax, -88(%rsp)                 # 4-byte Spill
	addl	%eax, %r10d
	addl	%ecx, %r10d
	movl	%r11d, %eax
	roll	$5, %eax
	addl	%eax, %r10d
	roll	$30, %r15d
	movl	%esi, %r13d
	movl	-80(%rsp), %r9d                 # 4-byte Reload
	xorl	%r9d, %r13d
	xorl	-56(%rsp), %r13d                # 4-byte Folded Reload
	xorl	%edi, %r13d
	roll	%r13d
	movl	%r11d, %eax
	andl	%r15d, %eax
	movl	%r11d, %ecx
	orl	%r15d, %ecx
	andl	%r12d, %ecx
	orl	%eax, %ecx
	addl	%r13d, %r14d
	movl	%r13d, -96(%rsp)                # 4-byte Spill
	addl	%ecx, %r14d
	movl	$-1894007588, %edi              # imm = 0x8F1BBCDC
	leal	(%r10,%rdi), %ecx
	movl	%ecx, %eax
	roll	$5, %eax
	addl	%eax, %r14d
	roll	$30, %r11d
	movl	%ecx, %eax
	andl	%r11d, %eax
	shldl	$30, %ecx, %r10d
	orl	%r11d, %ecx
	andl	%r15d, %ecx
	orl	%eax, %ecx
	movl	%r8d, %esi
	movl	-108(%rsp), %r8d                # 4-byte Reload
	xorl	%r8d, %esi
	xorl	-64(%rsp), %esi                 # 4-byte Folded Reload
	xorl	%edx, %esi
	roll	%esi
	movl	%esi, -92(%rsp)                 # 4-byte Spill
	leal	(%r14,%rdi), %eax
	movl	%eax, %edx
	roll	$5, %edx
	addl	%esi, %r12d
	addl	%ecx, %r12d
	addl	%edx, %r12d
	movl	%eax, %ecx
	andl	%r10d, %ecx
	shldl	$30, %eax, %r14d
	orl	%r10d, %eax
	andl	%r11d, %eax
	orl	%ecx, %eax
	xorl	%ebp, %r9d
	xorl	-104(%rsp), %r9d                # 4-byte Folded Reload
	xorl	-88(%rsp), %r9d                 # 4-byte Folded Reload
	roll	%r9d
	addl	%r9d, %r15d
	movl	%r9d, %esi
	movl	%r9d, -80(%rsp)                 # 4-byte Spill
	addl	%eax, %r15d
	leal	(%r12,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r15d
	movl	-84(%rsp), %ebx                 # 4-byte Reload
	xorl	%ebx, %r8d
	xorl	-116(%rsp), %r8d                # 4-byte Folded Reload
	xorl	%r13d, %r8d
	roll	%r8d
	movl	%r8d, -108(%rsp)                # 4-byte Spill
	movl	%eax, %ecx
	andl	%r14d, %ecx
	shldl	$30, %eax, %r12d
	orl	%r14d, %eax
	andl	%r10d, %eax
	orl	%ecx, %eax
	addl	%r8d, %r11d
	addl	%eax, %r11d
	leal	(%r15,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r11d
	movl	%eax, %ecx
	andl	%r12d, %ecx
	shldl	$30, %eax, %r15d
	orl	%r12d, %eax
	andl	%r14d, %eax
	orl	%ecx, %eax
	movl	-76(%rsp), %r9d                 # 4-byte Reload
	xorl	%r9d, %ebp
	xorl	-120(%rsp), %ebp                # 4-byte Folded Reload
	xorl	-92(%rsp), %ebp                 # 4-byte Folded Reload
	roll	%ebp
	addl	%ebp, %r10d
	addl	%eax, %r10d
	leal	(%r11,%rdi), %ecx
	movl	%ecx, %eax
	roll	$5, %eax
	addl	%eax, %r10d
	movl	%ecx, %eax
	andl	%r15d, %eax
	shldl	$30, %ecx, %r11d
	orl	%r15d, %ecx
	andl	%r12d, %ecx
	orl	%eax, %ecx
	movl	%ebx, %eax
	movq	-72(%rsp), %r8                  # 8-byte Reload
	xorl	%r8d, %eax
	xorl	-100(%rsp), %eax                # 4-byte Folded Reload
	xorl	%esi, %eax
	roll	%eax
	movl	%eax, %esi
	leal	(%r10,%rdi), %eax
	movl	%eax, %edx
	roll	$5, %edx
	addl	%esi, %r14d
	movl	%esi, -84(%rsp)                 # 4-byte Spill
	addl	%ecx, %r14d
	addl	%edx, %r14d
	movl	%eax, %ecx
	andl	%r11d, %ecx
	shldl	$30, %eax, %r10d
	orl	%r11d, %eax
	andl	%r15d, %eax
	orl	%ecx, %eax
	movl	%r9d, %ecx
	movq	-56(%rsp), %r9                  # 8-byte Reload
	xorl	%r9d, %ecx
	xorl	-112(%rsp), %ecx                # 4-byte Folded Reload
	xorl	-108(%rsp), %ecx                # 4-byte Folded Reload
	roll	%ecx
	movl	%ecx, -76(%rsp)                 # 4-byte Spill
	addl	%ecx, %r12d
	addl	%eax, %r12d
	leal	(%r14,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r12d
	movq	%r8, %rcx
	movq	-64(%rsp), %r8                  # 8-byte Reload
	xorl	%r8d, %ecx
	xorl	-88(%rsp), %ecx                 # 4-byte Folded Reload
	xorl	%ebp, %ecx
	roll	%ecx
	movq	%rcx, %rdx
	movq	%rcx, -72(%rsp)                 # 8-byte Spill
	movl	%eax, %ecx
	andl	%r10d, %ecx
	shldl	$30, %eax, %r14d
	orl	%r10d, %eax
	andl	%r11d, %eax
	orl	%ecx, %eax
	addl	%edx, %r15d
	addl	%eax, %r15d
	leal	(%r12,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r15d
	movl	%eax, %ecx
	andl	%r14d, %ecx
	shldl	$30, %eax, %r12d
	orl	%r14d, %eax
	andl	%r10d, %eax
	orl	%ecx, %eax
	movl	-104(%rsp), %ebx                # 4-byte Reload
	xorl	%ebx, %r9d
	xorl	-96(%rsp), %r9d                 # 4-byte Folded Reload
	xorl	%esi, %r9d
	roll	%r9d
	addl	%r9d, %r11d
	addl	%eax, %r11d
	leal	(%r15,%rdi), %ecx
	movl	%ecx, %eax
	roll	$5, %eax
	addl	%eax, %r11d
	movl	%ecx, %eax
	andl	%r12d, %eax
	shldl	$30, %ecx, %r15d
	orl	%r12d, %ecx
	andl	%r14d, %ecx
	orl	%eax, %ecx
	movq	%r8, %rax
	movl	-116(%rsp), %r13d               # 4-byte Reload
	xorl	%r13d, %eax
	xorl	-92(%rsp), %eax                 # 4-byte Folded Reload
	xorl	-76(%rsp), %eax                 # 4-byte Folded Reload
	roll	%eax
	movq	%rax, %rsi
	movq	%rax, -64(%rsp)                 # 8-byte Spill
	leal	(%r11,%rdi), %eax
	movl	%eax, %edx
	roll	$5, %edx
	addl	%esi, %r10d
	addl	%ecx, %r10d
	addl	%edx, %r10d
	movl	%eax, %ecx
	andl	%r15d, %ecx
	shldl	$30, %eax, %r11d
	orl	%r15d, %eax
	andl	%r12d, %eax
	orl	%ecx, %eax
	movl	-120(%rsp), %r8d                # 4-byte Reload
	xorl	%r8d, %ebx
	xorl	-80(%rsp), %ebx                 # 4-byte Folded Reload
	xorl	-72(%rsp), %ebx                 # 4-byte Folded Reload
	roll	%ebx
	addl	%ebx, %r14d
	movl	%ebx, %edx
	movl	%ebx, -104(%rsp)                # 4-byte Spill
	addl	%eax, %r14d
	leal	(%r10,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r14d
	movl	-100(%rsp), %esi                # 4-byte Reload
	xorl	%esi, %r13d
	xorl	-108(%rsp), %r13d               # 4-byte Folded Reload
	xorl	%r9d, %r13d
	roll	%r13d
	movl	%r13d, -116(%rsp)               # 4-byte Spill
	movl	%eax, %ecx
	andl	%r11d, %ecx
	shldl	$30, %eax, %r10d
	orl	%r11d, %eax
	andl	%r15d, %eax
	orl	%ecx, %eax
	addl	%r13d, %r12d
	addl	%eax, %r12d
	leal	(%r14,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r12d
	movl	%eax, %ecx
	andl	%r10d, %ecx
	shldl	$30, %eax, %r14d
	orl	%r10d, %eax
	andl	%r11d, %eax
	orl	%ecx, %eax
	movl	%r8d, %ecx
	movl	-112(%rsp), %ebx                # 4-byte Reload
	xorl	%ebx, %ecx
	xorl	%ebp, %ecx
	xorl	-64(%rsp), %ecx                 # 4-byte Folded Reload
	roll	%ecx
	movl	%ecx, -120(%rsp)                # 4-byte Spill
	addl	%ecx, %r15d
	addl	%eax, %r15d
	leal	(%r12,%rdi), %ecx
	movl	%ecx, %eax
	roll	$5, %eax
	addl	%eax, %r15d
	movl	%ecx, %eax
	andl	%r14d, %eax
	shldl	$30, %ecx, %r12d
	orl	%r14d, %ecx
	andl	%r10d, %ecx
	orl	%eax, %ecx
	movl	%esi, %r13d
	movl	-88(%rsp), %r8d                 # 4-byte Reload
	xorl	%r8d, %r13d
	xorl	-84(%rsp), %r13d                # 4-byte Folded Reload
	xorl	%edx, %r13d
	roll	%r13d
	leal	(%r15,%rdi), %eax
	movl	%eax, %edx
	roll	$5, %edx
	addl	%r13d, %r11d
	movl	%r13d, -100(%rsp)               # 4-byte Spill
	addl	%ecx, %r11d
	addl	%edx, %r11d
	movl	%eax, %ecx
	andl	%r12d, %ecx
	shldl	$30, %eax, %r15d
	orl	%r12d, %eax
	andl	%r14d, %eax
	orl	%ecx, %eax
	movl	-96(%rsp), %esi                 # 4-byte Reload
	xorl	%esi, %ebx
	xorl	-76(%rsp), %ebx                 # 4-byte Folded Reload
	xorl	-116(%rsp), %ebx                # 4-byte Folded Reload
	roll	%ebx
	movl	%ebx, -112(%rsp)                # 4-byte Spill
	addl	%ebx, %r10d
	addl	%eax, %r10d
	leal	(%r11,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r10d
	movl	-92(%rsp), %ebx                 # 4-byte Reload
	xorl	%ebx, %r8d
	xorl	-72(%rsp), %r8d                 # 4-byte Folded Reload
	xorl	-120(%rsp), %r8d                # 4-byte Folded Reload
	roll	%r8d
	movl	%r8d, -88(%rsp)                 # 4-byte Spill
	movl	%eax, %ecx
	andl	%r15d, %ecx
	shldl	$30, %eax, %r11d
	orl	%r15d, %eax
	andl	%r12d, %eax
	orl	%ecx, %eax
	addl	%r8d, %r14d
	addl	%eax, %r14d
	leal	(%r10,%rdi), %eax
	movl	%eax, %ecx
	roll	$5, %ecx
	addl	%ecx, %r14d
	movl	%eax, %ecx
	andl	%r11d, %ecx
	shldl	$30, %eax, %r10d
	orl	%r11d, %eax
	andl	%r15d, %eax
	orl	%ecx, %eax
	movl	-80(%rsp), %r8d                 # 4-byte Reload
	xorl	%r8d, %esi
	xorl	%r9d, %esi
	xorl	%r13d, %esi
	roll	%esi
	movl	%esi, -96(%rsp)                 # 4-byte Spill
	addl	%esi, %r12d
	addl	%eax, %r12d
	leal	(%r14,%rdi), %ecx
	movl	%ecx, %eax
	roll	$5, %eax
	addl	%eax, %r12d
	movl	%ecx, %eax
	andl	%r10d, %eax
	shldl	$30, %ecx, %r14d
	orl	%r10d, %ecx
	andl	%r11d, %ecx
	orl	%eax, %ecx
	xorl	-108(%rsp), %ebx                # 4-byte Folded Reload
	xorl	-64(%rsp), %ebx                 # 4-byte Folded Reload
	xorl	-112(%rsp), %ebx                # 4-byte Folded Reload
	roll	%ebx
	movl	%ebx, -92(%rsp)                 # 4-byte Spill
	leal	(%r12,%rdi), %eax
	movl	%eax, %edx
	roll	$5, %edx
	addl	%ebx, %r15d
	addl	%ecx, %r15d
	addl	%edx, %r15d
	movl	%eax, %ecx
	andl	%r14d, %ecx
	shldl	$30, %eax, %r12d
	orl	%r14d, %eax
	andl	%r10d, %eax
	orl	%ecx, %eax
	xorl	%ebp, %r8d
	xorl	-104(%rsp), %r8d                # 4-byte Folded Reload
	movl	-88(%rsp), %edx                 # 4-byte Reload
	xorl	%edx, %r8d
	roll	%r8d
	movl	%r12d, %ecx
	xorl	%r14d, %ecx
	leal	(%r15,%rdi), %edx
	xorl	%edx, %ecx
	shldl	$30, %edx, %r15d
	roll	$5, %edx
	addl	%r8d, %r11d
	movl	%r8d, %r13d
	movl	%r8d, -80(%rsp)                 # 4-byte Spill
	addl	%eax, %r11d
	addl	%edx, %r11d
	addl	%r11d, %edi
	movl	-108(%rsp), %ebx                # 4-byte Reload
	movl	-84(%rsp), %r8d                 # 4-byte Reload
	xorl	%r8d, %ebx
	xorl	-116(%rsp), %ebx                # 4-byte Folded Reload
	xorl	-96(%rsp), %ebx                 # 4-byte Folded Reload
	roll	%ebx
	movl	%edi, %esi
	roll	$5, %esi
	addl	%ebx, %r10d
	movl	%ebx, -108(%rsp)                # 4-byte Spill
	addl	%ecx, %r10d
	movl	$-899497514, %ecx               # imm = 0xCA62C1D6
	addl	%ecx, %r10d
	movl	$-899497514, %edx               # imm = 0xCA62C1D6
	movl	-76(%rsp), %ecx                 # 4-byte Reload
	xorl	%ecx, %ebp
	xorl	-120(%rsp), %ebp                # 4-byte Folded Reload
	xorl	-92(%rsp), %ebp                 # 4-byte Folded Reload
	roll	%ebp
	addl	%esi, %r10d
	movl	%r15d, %eax
	xorl	%r12d, %eax
	xorl	%edi, %eax
	addl	%ebp, %r14d
	addl	%eax, %r14d
	shrdl	$2, %r11d, %edi
	movl	%r10d, %eax
	roll	$5, %eax
	addl	%edx, %r14d
	addl	%eax, %r14d
	movq	-72(%rsp), %rdx                 # 8-byte Reload
	xorl	%edx, %r8d
	xorl	-100(%rsp), %r8d                # 4-byte Folded Reload
	xorl	%r13d, %r8d
	roll	%r8d
	movl	%edi, %eax
	xorl	%r15d, %eax
	xorl	%r10d, %eax
	addl	%r8d, %r12d
	movl	%r8d, %r11d
	movl	%r8d, -84(%rsp)                 # 4-byte Spill
	addl	%eax, %r12d
	movl	%r14d, %eax
	roll	$5, %eax
	movl	$-899497514, %esi               # imm = 0xCA62C1D6
	addl	%esi, %r12d
	addl	%eax, %r12d
	roll	$30, %r10d
	movl	%ecx, %r8d
	xorl	%r9d, %r8d
	xorl	-112(%rsp), %r8d                # 4-byte Folded Reload
	xorl	%ebx, %r8d
	roll	%r8d
	movl	%r10d, %eax
	xorl	%edi, %eax
	xorl	%r14d, %eax
	addl	%r8d, %r15d
	movl	%r8d, -76(%rsp)                 # 4-byte Spill
	addl	%eax, %r15d
	movl	%r12d, %eax
	roll	$5, %eax
	addl	%esi, %r15d
	addl	%eax, %r15d
	roll	$30, %r14d
	movq	%rdx, %r13
	movq	-64(%rsp), %rsi                 # 8-byte Reload
	xorl	%esi, %r13d
	xorl	-88(%rsp), %r13d                # 4-byte Folded Reload
	xorl	%ebp, %r13d
	roll	%r13d
	movl	%r14d, %eax
	xorl	%r10d, %eax
	xorl	%r12d, %eax
	addl	%r13d, %edi
	movq	%r13, -72(%rsp)                 # 8-byte Spill
	addl	%eax, %edi
	movl	%r15d, %eax
	roll	$5, %eax
	movl	$-899497514, %edx               # imm = 0xCA62C1D6
	addl	%edx, %edi
	roll	$30, %r12d
	movl	-104(%rsp), %ebx                # 4-byte Reload
	xorl	%ebx, %r9d
	xorl	-96(%rsp), %r9d                 # 4-byte Folded Reload
	xorl	%r11d, %r9d
	roll	%r9d
	addl	%eax, %edi
	movl	%edi, %eax
	roll	$5, %eax
	movl	%r12d, %ecx
	xorl	%r14d, %ecx
	xorl	%r15d, %ecx
	addl	%r9d, %r10d
	addl	%ecx, %r10d
	addl	%edx, %r10d
	movl	$-899497514, %r11d              # imm = 0xCA62C1D6
	roll	$30, %r15d
	addl	%eax, %r10d
	movq	%rsi, %rdx
	movl	-116(%rsp), %ecx                # 4-byte Reload
	xorl	%ecx, %edx
	xorl	-92(%rsp), %edx                 # 4-byte Folded Reload
	xorl	%r8d, %edx
	roll	%edx
	movl	%r15d, %eax
	xorl	%r12d, %eax
	xorl	%edi, %eax
	addl	%edx, %r14d
	movq	%rdx, -64(%rsp)                 # 8-byte Spill
	addl	%eax, %r14d
	movl	%r10d, %eax
	roll	$5, %eax
	addl	%r11d, %r14d
	movl	$-899497514, %esi               # imm = 0xCA62C1D6
	addl	%eax, %r14d
	roll	$30, %edi
	movl	-120(%rsp), %r8d                # 4-byte Reload
	xorl	%r8d, %ebx
	xorl	-80(%rsp), %ebx                 # 4-byte Folded Reload
	xorl	%r13d, %ebx
	roll	%ebx
	movl	%edi, %eax
	xorl	%r15d, %eax
	xorl	%r10d, %eax
	addl	%ebx, %r12d
	movl	%ebx, -104(%rsp)                # 4-byte Spill
	addl	%eax, %r12d
	movl	%r14d, %eax
	roll	$5, %eax
	addl	%esi, %r12d
	movl	$-899497514, %r11d              # imm = 0xCA62C1D6
	addl	%eax, %r12d
	roll	$30, %r10d
	movl	-100(%rsp), %esi                # 4-byte Reload
	movl	%ecx, %r13d
	xorl	%esi, %r13d
	xorl	-108(%rsp), %r13d               # 4-byte Folded Reload
	xorl	%r9d, %r13d
	roll	%r13d
	movl	%r10d, %eax
	xorl	%edi, %eax
	xorl	%r14d, %eax
	addl	%r13d, %r15d
	movl	%r13d, -116(%rsp)               # 4-byte Spill
	addl	%eax, %r15d
	movl	%r12d, %eax
	roll	$5, %eax
	addl	%r11d, %r15d
	roll	$30, %r14d
	movl	-112(%rsp), %r11d               # 4-byte Reload
	xorl	%r11d, %r8d
	xorl	%ebp, %r8d
	xorl	%edx, %r8d
	roll	%r8d
	movl	%r8d, -120(%rsp)                # 4-byte Spill
	addl	%eax, %r15d
	movl	%r15d, %eax
	roll	$5, %eax
	movl	%r14d, %ecx
	xorl	%r10d, %ecx
	xorl	%r12d, %ecx
	addl	%r8d, %edi
	addl	%ecx, %edi
	movl	$-899497514, %ecx               # imm = 0xCA62C1D6
	addl	%ecx, %edi
	roll	$30, %r12d
	addl	%eax, %edi
	movl	-88(%rsp), %edx                 # 4-byte Reload
	xorl	%edx, %esi
	xorl	-84(%rsp), %esi                 # 4-byte Folded Reload
	xorl	%ebx, %esi
	roll	%esi
	movl	%r12d, %eax
	xorl	%r14d, %eax
	xorl	%r15d, %eax
	addl	%esi, %r10d
	movl	%esi, %ebx
	movl	%esi, -100(%rsp)                # 4-byte Spill
	addl	%eax, %r10d
	movl	%edi, %eax
	roll	$5, %eax
	addl	%ecx, %r10d
	addl	%eax, %r10d
	roll	$30, %r15d
	movl	-96(%rsp), %esi                 # 4-byte Reload
	xorl	%esi, %r11d
	xorl	-76(%rsp), %r11d                # 4-byte Folded Reload
	xorl	%r13d, %r11d
	roll	%r11d
	movl	%r15d, %eax
	xorl	%r12d, %eax
	xorl	%edi, %eax
	addl	%r11d, %r14d
	movl	%r11d, -112(%rsp)               # 4-byte Spill
	addl	%eax, %r14d
	movl	%r10d, %eax
	roll	$5, %eax
	movl	$-899497514, %ecx               # imm = 0xCA62C1D6
	addl	%ecx, %r14d
	addl	%eax, %r14d
	roll	$30, %edi
	movl	%edx, %r13d
	movl	-92(%rsp), %r8d                 # 4-byte Reload
	xorl	%r8d, %r13d
	xorl	-72(%rsp), %r13d                # 4-byte Folded Reload
	xorl	-120(%rsp), %r13d               # 4-byte Folded Reload
	roll	%r13d
	movl	%edi, %eax
	xorl	%r15d, %eax
	xorl	%r10d, %eax
	addl	%r13d, %r12d
	addl	%eax, %r12d
	movl	%r14d, %eax
	roll	$5, %eax
	addl	%ecx, %r12d
	roll	$30, %r10d
	movl	-80(%rsp), %edx                 # 4-byte Reload
	xorl	%edx, %esi
	xorl	%r9d, %esi
	xorl	%ebx, %esi
	roll	%esi
	movl	%esi, %ebx
	addl	%eax, %r12d
	movl	%r12d, %eax
	roll	$5, %eax
	movl	%r10d, %ecx
	xorl	%edi, %ecx
	xorl	%r14d, %ecx
	addl	%esi, %r15d
	addl	%ecx, %r15d
	movl	$-899497514, %ecx               # imm = 0xCA62C1D6
	addl	%ecx, %r15d
	addl	%eax, %r15d
	movl	-108(%rsp), %esi                # 4-byte Reload
	xorl	%esi, %r8d
	xorl	-64(%rsp), %r8d                 # 4-byte Folded Reload
	roll	$30, %r14d
	xorl	%r11d, %r8d
	roll	%r8d
	movl	%r8d, %ecx
	movl	%r14d, %eax
	xorl	%r10d, %eax
	xorl	%r12d, %eax
	addl	%r8d, %edi
	addl	%eax, %edi
	movl	%r15d, %eax
	roll	$5, %eax
	movl	$-899497514, %r8d               # imm = 0xCA62C1D6
	addl	%r8d, %edi
	addl	%eax, %edi
	xorl	%ebp, %edx
	xorl	-104(%rsp), %edx                # 4-byte Folded Reload
	roll	$30, %r12d
	xorl	%r13d, %edx
	roll	%edx
	movl	%edx, %r11d
	movl	%r12d, %eax
	xorl	%r14d, %eax
	xorl	%r15d, %eax
	addl	%edx, %r10d
	addl	%eax, %r10d
	movl	%edi, %eax
	roll	$5, %eax
	addl	%r8d, %r10d
	movl	$-899497514, %edx               # imm = 0xCA62C1D6
	addl	%eax, %r10d
	movl	-84(%rsp), %r8d                 # 4-byte Reload
	xorl	%r8d, %esi
	xorl	-116(%rsp), %esi                # 4-byte Folded Reload
	xorl	%ebx, %esi
	roll	$30, %r15d
	roll	%esi
	movl	%r15d, %eax
	xorl	%r12d, %eax
	xorl	%edi, %eax
	addl	%esi, %r14d
	addl	%eax, %r14d
	movl	-76(%rsp), %r13d                # 4-byte Reload
	xorl	%r13d, %ebp
	xorl	-120(%rsp), %ebp                # 4-byte Folded Reload
	xorl	%ecx, %ebp
	movl	%r10d, %eax
	roll	$5, %eax
	addl	%edx, %r14d
	roll	$30, %edi
	roll	%ebp
	addl	%eax, %r14d
	movl	%r14d, %eax
	roll	$5, %eax
	addl	%r12d, %ebp
	movl	%edi, %ecx
	xorl	%r15d, %ecx
	xorl	%r10d, %ecx
	addl	%ecx, %ebp
	addl	%edx, %ebp
	addl	%eax, %ebp
	movq	-72(%rsp), %rdx                 # 8-byte Reload
	xorl	%r8d, %edx
	xorl	-100(%rsp), %edx                # 4-byte Folded Reload
	xorl	%r11d, %edx
	roll	%edx
	addl	%r15d, %edx
	roll	$30, %r10d
	movl	%r10d, %eax
	xorl	%edi, %eax
	xorl	%r14d, %eax
	addl	%eax, %edx
	movl	%ebp, %eax
	roll	$5, %eax
	addl	%eax, %edx
	xorl	%r13d, %r9d
	xorl	-112(%rsp), %r9d                # 4-byte Folded Reload
	xorl	%esi, %r9d
	roll	%r9d
	addl	-40(%rsp), %r9d                 # 4-byte Folded Reload
	roll	$30, %r14d
	addl	%edi, %r9d
	movl	%r14d, %eax
	xorl	%r10d, %eax
	xorl	%ebp, %eax
	addl	%eax, %r9d
	movl	$-899497514, %eax               # imm = 0xCA62C1D6
	addl	%eax, %r9d
	addl	%edx, %eax
	roll	$5, %eax
	addl	%eax, %r9d
	movq	-8(%rsp), %rcx                  # 8-byte Reload
	movl	%r9d, (%rcx)
	movq	-16(%rsp), %rax                 # 8-byte Reload
	addl	%edx, %eax
	addl	$-899497514, %eax               # imm = 0xCA62C1D6
	movl	%eax, 4(%rcx)
	roll	$30, %ebp
	addl	-32(%rsp), %ebp                 # 4-byte Folded Reload
	movl	%ebp, 8(%rcx)
	addl	-24(%rsp), %r14d                # 4-byte Folded Reload
	movl	%r14d, 12(%rcx)
	addl	-36(%rsp), %r10d                # 4-byte Folded Reload
	movl	%r10d, 16(%rcx)
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z17sha_transformINITPjPh, .Lfunc_end1-_Z17sha_transformINITPjPh
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__sha_transformPiPj # -- Begin function _Z28__device_stub__sha_transformPiPj
	.type	_Z28__device_stub__sha_transformPiPj,@function
_Z28__device_stub__sha_transformPiPj:   # @_Z28__device_stub__sha_transformPiPj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13sha_transformPiPj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__sha_transformPiPj, .Lfunc_end2-_Z28__device_stub__sha_transformPiPj
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	1732584193                      # 0x67452301
	.long	4023233417                      # 0xefcdab89
	.long	2562383102                      # 0x98badcfe
	.long	271733878                       # 0x10325476
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$131144, %rsp                   # imm = 0x20048
	.cfi_def_cfa_offset 131200
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movaps	.LCPI3_0(%rip), %xmm0           # xmm0 = [1732584193,4023233417,2562383102,271733878]
	leaq	32(%rsp), %rdi
	movaps	%xmm0, (%rdi)
	movl	$-1009589776, 16(%rdi)          # imm = 0xC3D2E1F0
	movq	8(%rsi), %rsi
	callq	_Z17sha_transformINITPjPh
	callq	_ZNSt6chrono3_V212system_clock3nowEv
	movq	%rax, %rcx
	movabsq	$8589934597, %rdx               # imm = 0x200000005
	mulq	%rdx
	movq	%rcx, %rax
	subq	%rdx, %rax
	shrq	%rax
	addq	%rdx, %rax
	shrq	$30, %rax
	movq	%rax, %rdx
	shlq	$31, %rdx
	subq	%rdx, %rax
	leaq	(%rcx,%rax), %rdx
	cmpq	$1, %rdx
	adcq	%rcx, %rax
	leaq	16(%rsp), %rbx
	movq	%rax, (%rbx)
	movabsq	$541165879329, %rax             # imm = 0x7E00000021
	leaq	24(%rsp), %r14
	movq	%rax, (%r14)
	leaq	64(%rsp), %r15
	xorl	%r12d, %r12d
.LBB3_1:                                # %.preheader26
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	movq	%r12, %r13
	shlq	$6, %r13
	movq	$-56, %rbp
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	callq	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
	movb	%al, 56(%r15,%rbp)
	incq	%rbp
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	movb	$-128, 116(%rsp,%r13)
	movq	$0, 120(%rsp,%r13)
	movw	$952, 124(%rsp,%r13)            # imm = 0x3B8
	incq	%r12
	addq	$64, %r15
	cmpq	$2048, %r12                     # imm = 0x800
	jne	.LBB3_1
# %bb.4:
	leaq	12(%rsp), %rdx
	movl	$-1, (%rdx)
	leaq	32(%rsp), %rdi
	leaq	64(%rsp), %rsi
	callq	_Z11addWithCudaPjPhPi
	testl	%eax, %eax
	jne	.LBB3_13
# %bb.5:                                # %.preheader.preheader
	xorl	%ebx, %ebx
	xorl	%ebp, %ebp
.LBB3_6:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_7 Depth 2
	movl	$3, %r14d
.LBB3_7:                                #   Parent Loop BB3_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	12(%rsp), %eax
	shll	$6, %eax
	addl	%ebx, %eax
	addl	%r14d, %eax
	cltq
	movzbl	64(%rsp,%rax), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	addl	$-1, %r14d
	jb	.LBB3_7
# %bb.8:                                #   in Loop: Header=BB3_6 Depth=1
	incl	%ebp
	addl	$4, %ebx
	cmpl	$13, %ebp
	jne	.LBB3_6
# %bb.9:
	movslq	12(%rsp), %rax
	shlq	$6, %rax
	movzbl	119(%rsp,%rax), %esi
	cltq
	movzbl	118(%rsp,%rax), %edx
	movzbl	117(%rsp,%rax), %ecx
	xorl	%ebx, %ebx
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	callq	hipDeviceReset
	testl	%eax, %eax
	jne	.LBB3_10
.LBB3_12:
	movl	%ebx, %eax
	addq	$131144, %rsp                   # imm = 0x20048
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_13:
	.cfi_def_cfa_offset 131200
	movq	stderr(%rip), %rcx
	movl	$.L.str, %edi
	movl	$19, %esi
	jmp	.LBB3_11
.LBB3_10:
	movq	stderr(%rip), %rcx
	movl	$.L.str.3, %edi
	movl	$22, %esi
.LBB3_11:
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$1, %ebx
	jmp	.LBB3_12
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z11addWithCudaPjPhPi           # -- Begin function _Z11addWithCudaPjPhPi
	.type	_Z11addWithCudaPjPhPi,@function
_Z11addWithCudaPjPhPi:                  # @_Z11addWithCudaPjPhPi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	xorl	%eax, %eax
	movq	%rax, 8(%rsp)
	movq	%rax, (%rsp)
	xorl	%edi, %edi
	callq	hipSetDevice
	testl	%eax, %eax
	jne	.LBB4_1
# %bb.2:
	leaq	8(%rsp), %rdi
	movl	$131072, %esi                   # imm = 0x20000
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_3
# %bb.6:
	movq	%rsp, %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB4_3
# %bb.7:
	movl	$g_cSHA1baseCode, %edi
	movl	$20, %edx
	movq	%r12, %rsi
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipMemcpyToSymbol
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.9:
	movq	8(%rsp), %rdi
	movl	$131072, %edx                   # imm = 0x20000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.11:
	movq	(%rsp), %rdi
	movl	$4, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.12:
	movabsq	$4294967328, %rdi               # imm = 0x100000020
	leaq	32(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_14
# %bb.13:
	movq	(%rsp), %rdi
	movq	8(%rsp), %rsi
	callq	_Z28__device_stub__sha_transformPiPj
.LBB4_14:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB4_15
# %bb.16:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB4_17
# %bb.18:
	movq	8(%rsp), %rsi
	movl	$131072, %edx                   # imm = 0x20000
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.19:
	movq	(%rsp), %rsi
	movl	$4, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
	testl	%eax, %eax
	je	.LBB4_21
# %bb.20:
	movl	%eax, %ebp
	movq	stderr(%rip), %rcx
	movl	$.L.str.7, %edi
	movl	$17, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	movl	%ebp, %ebx
	jmp	.LBB4_21
.LBB4_10:
	movl	%eax, %ebx
	movq	stderr(%rip), %rcx
	movl	$.L.str.7, %edi
	jmp	.LBB4_4
.LBB4_3:
	movl	%eax, %ebx
	movq	stderr(%rip), %rcx
	movl	$.L.str.5, %edi
.LBB4_4:
	movl	$17, %esi
	jmp	.LBB4_5
.LBB4_1:
	movl	%eax, %ebx
	movq	stderr(%rip), %rcx
	movl	$.L.str.4, %edi
	movl	$63, %esi
	jmp	.LBB4_5
.LBB4_8:
	movl	%eax, %ebx
	movq	stderr(%rip), %rcx
	movl	$.L.str.6, %edi
	movl	$25, %esi
.LBB4_5:
	movl	$1, %edx
	callq	fwrite@PLT
.LBB4_21:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movl	%ebx, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_15:
	.cfi_def_cfa_offset 64
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %esi
	movq	%r14, %rdi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB4_21
.LBB4_17:
	movl	%eax, %ebx
	movq	stderr(%rip), %rdi
	movl	$.L.str.9, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB4_21
.Lfunc_end4:
	.size	_Z11addWithCudaPjPhPi, .Lfunc_end4-_Z11addWithCudaPjPhPi
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,comdat
	.weak	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
	.p2align	1, 0x90
	.type	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movq	%rdi, %r15
	movslq	4(%rdx), %rbp
	movslq	(%rdx), %rdi
	subq	%rdi, %rbp
	cmpq	$2147483644, %rbp               # imm = 0x7FFFFFFC
	ja	.LBB5_4
# %bb.1:
	incq	%rbp
	movl	$2147483645, %eax               # imm = 0x7FFFFFFD
	xorl	%edx, %edx
	divl	%ebp
	movl	%eax, %ecx
	imulq	%rcx, %rbp
	movq	(%rbx), %rdx
	movabsq	$8589934597, %r8                # imm = 0x200000005
.LBB5_2:                                # =>This Inner Loop Header: Depth=1
	imulq	$16807, %rdx, %rsi              # imm = 0x41A7
	movq	%rsi, %rax
	mulq	%r8
	movq	%rsi, %rax
	subq	%rdx, %rax
	shrq	%rax
	addq	%rdx, %rax
	shrq	$30, %rax
	movq	%rax, %rdx
	shlq	$31, %rdx
	subq	%rdx, %rax
	leaq	(%rsi,%rax), %rdx
	addq	%rsi, %rax
	decq	%rax
	cmpq	%rbp, %rax
	jae	.LBB5_2
# %bb.3:
	movq	%rdx, (%rbx)
	xorl	%edx, %edx
	divq	%rcx
	jmp	.LBB5_9
.LBB5_4:
	cmpq	$2147483645, %rbp               # imm = 0x7FFFFFFD
	jne	.LBB5_5
# %bb.10:
	imulq	$16807, (%rbx), %rcx            # imm = 0x41A7
	movabsq	$8589934597, %rdx               # imm = 0x200000005
	movq	%rcx, %rax
	mulq	%rdx
	movq	%rcx, %rax
	subq	%rdx, %rax
	shrq	%rax
	addq	%rdx, %rax
	shrq	$30, %rax
	movq	%rax, %rdx
	shlq	$31, %rdx
	subq	%rdx, %rax
	leaq	(%rcx,%rax), %rdx
	movq	%rdx, (%rbx)
	addq	%rcx, %rax
	decq	%rax
	jmp	.LBB5_9
.LBB5_5:                                # %.preheader
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	movq	%rbp, %rax
	shrq	%rax
	movabsq	$-9223372028264841207, %rcx     # imm = 0x8000000200000009
	mulq	%rcx
	movq	%rdx, %r12
	shrq	$29, %r12
	leaq	8(%rsp), %r13
	movabsq	$8589934597, %r14               # imm = 0x200000005
.LBB5_6:                                # =>This Inner Loop Header: Depth=1
	movl	$0, 8(%rsp)
	movl	%r12d, 12(%rsp)
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	callq	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
	movslq	%eax, %rsi
	leaq	(%rsi,%rsi), %rax
	shlq	$31, %rsi
	subq	%rax, %rsi
	imulq	$16807, (%rbx), %rcx            # imm = 0x41A7
	movq	%rcx, %rax
	mulq	%r14
	movq	%rcx, %rax
	subq	%rdx, %rax
	shrq	%rax
	addq	%rdx, %rax
	shrq	$30, %rax
	movq	%rax, %rdx
	shlq	$31, %rdx
	subq	%rdx, %rax
	addq	%rcx, %rax
	movq	%rax, (%rbx)
	addq	%rsi, %rax
	decq	%rax
	cmpq	%rbp, %rax
	ja	.LBB5_6
# %bb.7:                                #   in Loop: Header=BB5_6 Depth=1
	cmpq	%rsi, %rax
	jb	.LBB5_6
# %bb.8:                                # %.loopexit.loopexit
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movl	(%rcx), %edi
.LBB5_9:                                # %.loopexit
	addl	%edi, %eax
                                        # kill: def $eax killed $eax killed $rax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE, .Lfunc_end5-_ZNSt24uniform_int_distributionIiEclISt26linear_congruential_engineImLm16807ELm0ELm2147483647EEEEiRT_RKNS0_10param_typeE
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13sha_transformPiPj, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$g_cSHA1baseCode, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$20, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	g_cSHA1baseCode,@object         # @g_cSHA1baseCode
	.local	g_cSHA1baseCode
	.comm	g_cSHA1baseCode,20,16
	.type	_Z13sha_transformPiPj,@object   # @_Z13sha_transformPiPj
	.section	.rodata,"a",@progbits
	.globl	_Z13sha_transformPiPj
	.p2align	3, 0x0
_Z13sha_transformPiPj:
	.quad	_Z28__device_stub__sha_transformPiPj
	.size	_Z13sha_transformPiPj, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"addWithCuda failed!"
	.size	.L.str, 20

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%x "
	.size	.L.str.1, 4

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%x %x %x"
	.size	.L.str.2, 9

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipDeviceReset failed!"
	.size	.L.str.3, 23

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"hipSetDevice failed!  Do you have a CUDA-capable GPU installed?"
	.size	.L.str.4, 64

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipMalloc failed!"
	.size	.L.str.5, 18

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"hipMemcpyToSymbol failed!"
	.size	.L.str.6, 26

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"hipMemcpy failed!"
	.size	.L.str.7, 18

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"addKernel launch failed: %s\n"
	.size	.L.str.8, 29

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"hipDeviceSynchronize returned error code %d after launching addKernel!\n"
	.size	.L.str.9, 72

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z13sha_transformPiPj"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"g_cSHA1baseCode"
	.size	.L__unnamed_2, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__sha_transformPiPj
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym g_cSHA1baseCode
	.addrsig_sym _Z13sha_transformPiPj
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13sha_transformPiPj   ; -- Begin function _Z13sha_transformPiPj
	.globl	_Z13sha_transformPiPj
	.p2align	8
	.type	_Z13sha_transformPiPj,@function
_Z13sha_transformPiPj:                  ; @_Z13sha_transformPiPj
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 4, v0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, g_cSHA1baseCode@rel32@lo+4
	s_addc_u32 s1, s1, g_cSHA1baseCode@rel32@hi+12
	s_load_b128 s[0:3], s[0:1], 0x0
	v_lshl_add_u32 v1, s15, 10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v17, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v18, vcc_lo, s7, v2, vcc_lo
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, g_cSHA1baseCode@rel32@lo+20
	s_addc_u32 s7, s7, g_cSHA1baseCode@rel32@hi+28
	s_clause 0x3
	global_load_b128 v[1:4], v[17:18], off
	global_load_b128 v[5:8], v[17:18], off offset:16
	global_load_b128 v[9:12], v[17:18], off offset:32
	global_load_b128 v[13:16], v[17:18], off offset:48
	s_load_b32 s8, s[6:7], 0x0
	v_alignbit_b32 v22, s0, s0, 27
	v_alignbit_b32 v20, s1, s1, 2
	s_xor_b32 s9, s3, s2
	v_alignbit_b32 v21, s0, s0, 2
	s_and_b32 s9, s9, s1
	v_mov_b32_e32 v19, 33
	v_readfirstlane_b32 s10, v20
	s_xor_b32 s9, s9, s3
	v_add_nc_u32_e32 v24, 0x5a827999, v21
	s_add_i32 s7, s2, 0x5a827999
	s_mov_b32 s6, 0
	s_xor_b32 s10, s10, s2
	s_waitcnt vmcnt(3)
	scratch_store_b128 off, v[1:4], off offset:16
	s_waitcnt vmcnt(2)
	scratch_store_b128 off, v[5:8], off offset:32
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[9:12], off offset:48
	s_waitcnt vmcnt(0)
	scratch_store_b128 off, v[13:16], off offset:64
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v23, s8, v22
	s_sub_i32 s8, 0, s0
	s_and_b32 s0, s10, s0
	v_xor_b32_e32 v22, v20, v21
	s_xor_b32 s0, s0, s2
	v_add_nc_u32_e32 v25, s9, v23
	v_add_nc_u32_e32 v23, 0x5a827999, v20
	s_add_i32 s2, s3, s0
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $sgpr9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s2, s2, 0x5a827999
	v_add_nc_u32_e32 v25, 0x5a827999, v25
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	scratch_load_u8 v1, off, off offset:16
	v_mov_b32_e32 v2, 16
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_eq_u16_e32 0x7e, v1
	s_cbranch_execz .LBB0_5
; %bb.2:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v3, 16
	s_mov_b32 s10, 0
.LBB0_3:                                ; %.lr.ph
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_u8 v1, v3, off offset:1
	v_add_nc_u32_e32 v2, 1, v3
	scratch_store_b8 v3, v19, off
	v_mov_b32_e32 v3, v2
	s_waitcnt vmcnt(0)
	v_cmp_ne_u16_e32 vcc_lo, 0x7e, v1
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_3
; %bb.4:                                ; %Flow
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_5:                                ; %Flow1496
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u16 v1, v1, 1
	s_mov_b32 s10, -1
	s_or_b32 s9, s9, exec_lo
	scratch_store_b8 v2, v1, off
	s_clause 0x3
	scratch_load_b128 v[13:16], off, off offset:16
	scratch_load_b128 v[9:12], off, off offset:32
	scratch_load_b128 v[5:8], off, off offset:48
	scratch_load_b128 v[1:4], off, off offset:64
	s_waitcnt vmcnt(3)
	v_add_nc_u32_e32 v26, v25, v13
	v_add_nc_u32_e32 v29, s7, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v27, v26, v26, 27
	v_and_b32_e32 v28, v26, v22
	v_alignbit_b32 v26, v26, v26, 2
	v_add3_u32 v27, s2, v14, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v28, v28, v20
	v_alignbit_b32 v30, v27, v27, 27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add3_u32 v28, v29, v28, v30
	v_add_nc_u32_e32 v29, v23, v16
	v_bfi_b32 v30, v27, v26, v21
	v_alignbit_b32 v27, v27, v27, 2
	v_alignbit_b32 v31, v28, v28, 27
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v29, v29, v30, v31
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v30, v24, v9
	v_bfi_b32 v31, v28, v27, v26
	v_alignbit_b32 v28, v28, v28, 2
	v_alignbit_b32 v32, v29, v29, 27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_bfi_b32 v33, v29, v28, v27
	v_alignbit_b32 v29, v29, v29, 2
	v_add3_u32 v30, v30, v31, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v26, v10, v26, v33
	v_alignbit_b32 v31, v30, v30, 27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_bfi_b32 v32, v30, v29, v28
	v_alignbit_b32 v30, v30, v30, 2
	v_add3_u32 v26, v26, v31, 0x5a827999
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v27, v11, v27, v32
	v_alignbit_b32 v31, v26, v26, 27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_bfi_b32 v32, v26, v30, v29
	v_alignbit_b32 v26, v26, v26, 2
	v_add3_u32 v27, v27, v31, 0x5a827999
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v28, v12, v28, v32
	v_alignbit_b32 v31, v27, v27, 27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_bfi_b32 v32, v27, v26, v30
	v_alignbit_b32 v27, v27, v27, 2
	v_add3_u32 v28, v28, v31, 0x5a827999
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v29, v5, v29, v32
	v_alignbit_b32 v31, v28, v28, 27
	v_bfi_b32 v32, v28, v27, v26
	v_alignbit_b32 v28, v28, v28, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v29, v29, v31, 0x5a827999
	v_add3_u32 v30, v6, v30, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v31, v29, v29, 27
	v_bfi_b32 v32, v29, v28, v27
	v_alignbit_b32 v29, v29, v29, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v30, v30, v31, 0x5a827999
	v_add3_u32 v26, v7, v26, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v31, v30, v30, 27
	v_bfi_b32 v32, v30, v29, v28
	v_alignbit_b32 v30, v30, v30, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v26, v26, v31, 0x5a827999
	v_add3_u32 v27, v8, v27, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v31, v26, v26, 27
	v_bfi_b32 v32, v26, v30, v29
	v_alignbit_b32 v26, v26, v26, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v27, v27, v31, 0x5a827999
	s_waitcnt vmcnt(0)
	v_add3_u32 v28, v1, v28, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v27, v27, 27
	v_bfi_b32 v32, v27, v26, v30
	v_alignbit_b32 v27, v27, v27, 2
	v_add3_u32 v28, v28, v31, 0x5a827999
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v29, v2, v29, v32
	v_alignbit_b32 v31, v28, v28, 27
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_bfi_b32 v32, v28, v27, v26
	v_alignbit_b32 v28, v28, v28, 2
	v_add3_u32 v29, v29, v31, 0x5a827999
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v30, v3, v30, v32
	v_xor_b32_e32 v32, v5, v2
	v_alignbit_b32 v31, v29, v29, 27
	v_bfi_b32 v33, v29, v28, v27
	v_alignbit_b32 v29, v29, v29, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v30, v30, v31, 0x5a827999
	v_xor3_b32 v31, v32, v15, v13
	v_add3_u32 v26, v4, v26, v33
	v_xor_b32_e32 v33, v6, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v32, v30, v30, 27
	v_alignbit_b32 v31, v31, v31, 31
	v_bfi_b32 v34, v30, v29, v28
	v_alignbit_b32 v30, v30, v30, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v26, v26, v32, 0x5a827999
	v_xor3_b32 v32, v33, v16, v14
	v_add3_u32 v27, v31, v27, v34
	v_xor_b32_e32 v34, v7, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v33, v26, v26, 27
	v_alignbit_b32 v32, v32, v32, 31
	v_bfi_b32 v35, v26, v30, v29
	v_alignbit_b32 v26, v26, v26, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v27, v27, v33, 0x5a827999
	v_xor3_b32 v33, v34, v9, v15
	v_add3_u32 v28, v32, v28, v35
	v_xor_b32_e32 v35, v10, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v34, v27, v27, 27
	v_alignbit_b32 v33, v33, v33, 31
	v_bfi_b32 v36, v27, v26, v30
	v_alignbit_b32 v27, v27, v27, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v28, v28, v34, 0x5a827999
	v_xor3_b32 v34, v35, v16, v31
	v_add3_u32 v29, v33, v29, v36
	v_xor_b32_e32 v36, v11, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v35, v28, v28, 27
	v_alignbit_b32 v34, v34, v34, 31
	v_bfi_b32 v37, v28, v27, v26
	v_alignbit_b32 v28, v28, v28, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v29, v29, v35, 0x5a827999
	v_xor3_b32 v35, v36, v9, v32
	v_add3_u32 v30, v34, v30, v37
	v_xor_b32_e32 v37, v12, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v36, v29, v29, 27
	v_alignbit_b32 v35, v35, v35, 31
	v_xor3_b32 v38, v28, v27, v29
	v_alignbit_b32 v29, v29, v29, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v30, v30, v36, 0x5a827999
	v_xor3_b32 v36, v37, v10, v33
	v_add3_u32 v26, v35, v26, v38
	v_xor_b32_e32 v38, v5, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v37, v30, v30, 27
	v_alignbit_b32 v36, v36, v36, 31
	v_xor3_b32 v39, v29, v28, v30
	v_alignbit_b32 v30, v30, v30, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v26, v26, v37, 0x6ed9eba1
	v_xor3_b32 v37, v38, v11, v34
	v_add3_u32 v27, v36, v27, v39
	v_xor_b32_e32 v39, v6, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v38, v26, v26, 27
	v_alignbit_b32 v37, v37, v37, 31
	v_xor3_b32 v40, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v27, v27, v38, 0x6ed9eba1
	v_xor3_b32 v38, v39, v12, v35
	v_add3_u32 v28, v37, v28, v40
	v_xor_b32_e32 v40, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v39, v27, v27, 27
	v_alignbit_b32 v38, v38, v38, 31
	v_xor3_b32 v41, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v28, v28, v39, 0x6ed9eba1
	v_xor3_b32 v39, v40, v31, v36
	v_add3_u32 v29, v38, v29, v41
	v_xor_b32_e32 v41, v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v40, v28, v28, 27
	v_alignbit_b32 v39, v39, v39, 31
	v_xor3_b32 v42, v27, v26, v28
	v_alignbit_b32 v28, v28, v28, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v29, v29, v40, 0x6ed9eba1
	v_xor3_b32 v40, v41, v32, v37
	v_add3_u32 v30, v39, v30, v42
	v_xor_b32_e32 v42, v7, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v41, v29, v29, 27
	v_alignbit_b32 v40, v40, v40, 31
	v_xor3_b32 v43, v28, v27, v29
	v_alignbit_b32 v29, v29, v29, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v30, v30, v41, 0x6ed9eba1
	v_xor3_b32 v41, v42, v33, v38
	v_add3_u32 v26, v40, v26, v43
	v_xor_b32_e32 v43, v8, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v42, v30, v30, 27
	v_alignbit_b32 v41, v41, v41, 31
	v_xor3_b32 v44, v29, v28, v30
	v_alignbit_b32 v30, v30, v30, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v26, v26, v42, 0x6ed9eba1
	v_xor3_b32 v42, v43, v34, v39
	v_add3_u32 v27, v41, v27, v44
	v_xor_b32_e32 v44, v1, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v43, v26, v26, 27
	v_alignbit_b32 v42, v42, v42, 31
	v_xor3_b32 v45, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v27, v27, v43, 0x6ed9eba1
	v_xor3_b32 v43, v44, v35, v40
	v_add3_u32 v28, v42, v28, v45
	v_xor_b32_e32 v45, v2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v44, v27, v27, 27
	v_alignbit_b32 v43, v43, v43, 31
	v_xor3_b32 v46, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v28, v28, v44, 0x6ed9eba1
	v_xor3_b32 v44, v45, v36, v41
	v_add3_u32 v29, v43, v29, v46
	v_xor_b32_e32 v46, v31, v3
	v_xor_b32_e32 v31, v31, v33
	v_alignbit_b32 v45, v28, v28, 27
	v_alignbit_b32 v44, v44, v44, 31
	v_xor3_b32 v47, v27, v26, v28
	v_alignbit_b32 v28, v28, v28, 2
	v_xor_b32_e32 v33, v35, v33
	v_add3_u32 v29, v29, v45, 0x6ed9eba1
	v_xor3_b32 v45, v46, v37, v42
	v_add3_u32 v30, v44, v30, v47
	v_xor_b32_e32 v47, v32, v4
	v_xor3_b32 v31, v31, v39, v44
	v_alignbit_b32 v46, v29, v29, 27
	v_alignbit_b32 v45, v45, v45, 31
	v_xor3_b32 v48, v28, v27, v29
	v_alignbit_b32 v29, v29, v29, 2
	v_xor_b32_e32 v32, v34, v32
	v_add3_u32 v30, v30, v46, 0x6ed9eba1
	v_xor3_b32 v46, v47, v38, v43
	v_add3_u32 v26, v45, v26, v48
	v_alignbit_b32 v31, v31, v31, 31
	v_xor3_b32 v32, v32, v40, v45
	v_alignbit_b32 v47, v30, v30, 27
	v_alignbit_b32 v46, v46, v46, 31
	v_xor3_b32 v48, v29, v28, v30
	v_alignbit_b32 v30, v30, v30, 2
	v_alignbit_b32 v32, v32, v32, 31
	v_add3_u32 v26, v26, v47, 0x6ed9eba1
	v_xor3_b32 v33, v33, v41, v46
	v_add3_u32 v27, v46, v27, v48
	v_xor_b32_e32 v34, v34, v36
	v_xor_b32_e32 v35, v37, v35
	v_alignbit_b32 v47, v26, v26, 27
	v_xor3_b32 v48, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	v_alignbit_b32 v33, v33, v33, 31
	v_xor3_b32 v34, v34, v42, v31
	v_add3_u32 v27, v27, v47, 0x6ed9eba1
	v_add3_u32 v28, v31, v28, v48
	v_xor3_b32 v35, v35, v43, v32
	v_xor_b32_e32 v36, v38, v36
	v_alignbit_b32 v34, v34, v34, 31
	v_alignbit_b32 v47, v27, v27, 27
	v_xor3_b32 v48, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	v_alignbit_b32 v35, v35, v35, 31
	v_xor3_b32 v36, v36, v44, v33
	v_add3_u32 v28, v28, v47, 0x6ed9eba1
	v_add3_u32 v29, v32, v29, v48
	v_xor_b32_e32 v37, v37, v39
	v_xor_b32_e32 v38, v40, v38
	v_alignbit_b32 v36, v36, v36, 31
	v_alignbit_b32 v47, v28, v28, 27
	v_xor3_b32 v48, v27, v26, v28
	v_alignbit_b32 v28, v28, v28, 2
	v_xor3_b32 v37, v37, v45, v34
	v_xor3_b32 v38, v38, v46, v35
	v_add3_u32 v29, v29, v47, 0x6ed9eba1
	v_add3_u32 v30, v33, v30, v48
	v_xor_b32_e32 v39, v41, v39
	v_alignbit_b32 v37, v37, v37, 31
	v_alignbit_b32 v38, v38, v38, 31
	v_alignbit_b32 v47, v29, v29, 27
	v_xor3_b32 v48, v28, v27, v29
	v_alignbit_b32 v29, v29, v29, 2
	v_xor3_b32 v39, v39, v31, v36
	v_xor_b32_e32 v40, v40, v42
	v_add3_u32 v30, v30, v47, 0x6ed9eba1
	v_add3_u32 v26, v34, v26, v48
	v_xor_b32_e32 v41, v43, v41
	v_alignbit_b32 v39, v39, v39, 31
	v_xor3_b32 v40, v40, v32, v37
	v_alignbit_b32 v47, v30, v30, 27
	v_xor3_b32 v48, v29, v28, v30
	v_alignbit_b32 v30, v30, v30, 2
	v_xor3_b32 v41, v41, v33, v38
	v_alignbit_b32 v40, v40, v40, 31
	v_add3_u32 v26, v26, v47, 0x6ed9eba1
	v_add3_u32 v27, v35, v27, v48
	v_xor_b32_e32 v42, v44, v42
	v_alignbit_b32 v41, v41, v41, 31
	v_xor_b32_e32 v43, v43, v45
	v_alignbit_b32 v47, v26, v26, 27
	v_xor3_b32 v48, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	v_xor3_b32 v42, v42, v34, v39
	v_xor3_b32 v43, v43, v35, v40
	v_add3_u32 v27, v27, v47, 0x6ed9eba1
	v_add3_u32 v28, v36, v28, v48
	v_xor_b32_e32 v44, v46, v44
	v_alignbit_b32 v42, v42, v42, 31
	v_alignbit_b32 v43, v43, v43, 31
	v_alignbit_b32 v47, v27, v27, 27
	v_xor3_b32 v48, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	v_xor3_b32 v44, v44, v36, v41
	v_xor_b32_e32 v45, v31, v45
	v_add3_u32 v28, v28, v47, 0x6ed9eba1
	v_add3_u32 v29, v37, v29, v48
	v_xor_b32_e32 v46, v46, v32
	v_alignbit_b32 v44, v44, v44, 31
	v_xor3_b32 v45, v45, v37, v42
	v_alignbit_b32 v47, v28, v28, 27
	v_xor3_b32 v48, v27, v26, v28
	v_alignbit_b32 v28, v28, v28, 2
	v_add_nc_u32_e32 v26, v26, v39
	v_alignbit_b32 v45, v45, v45, 31
	v_add3_u32 v29, v29, v47, 0x6ed9eba1
	v_add3_u32 v30, v38, v30, v48
	v_xor3_b32 v46, v46, v38, v43
	v_xor_b32_e32 v31, v33, v31
	v_xor_b32_e32 v32, v34, v32
	v_alignbit_b32 v47, v29, v29, 27
	v_xor_b32_e32 v48, v29, v27
	v_alignbit_b32 v29, v29, v29, 2
	v_alignbit_b32 v46, v46, v46, 31
	v_xor3_b32 v31, v31, v39, v44
	v_add3_u32 v30, v30, v47, 0x6ed9eba1
	v_bfi_b32 v47, v48, v28, v27
	v_add_nc_u32_e32 v27, v27, v40
	v_xor3_b32 v32, v32, v40, v45
	v_alignbit_b32 v31, v31, v31, 31
	v_alignbit_b32 v48, v30, v30, 27
	v_xor_b32_e32 v33, v33, v35
	v_xor_b32_e32 v34, v36, v34
	v_alignbit_b32 v32, v32, v32, 31
	v_xor_b32_e32 v35, v37, v35
	v_add3_u32 v26, v26, v47, v48
	v_xor_b32_e32 v47, v30, v28
	v_alignbit_b32 v30, v30, v30, 2
	v_xor3_b32 v33, v33, v41, v46
	v_xor3_b32 v34, v34, v42, v31
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v26
	v_bfi_b32 v47, v47, v29, v28
	v_add_nc_u32_e32 v28, v28, v41
	v_alignbit_b32 v33, v33, v33, 31
	v_alignbit_b32 v34, v34, v34, 31
	v_alignbit_b32 v49, v48, v48, 27
	v_alignbit_b32 v26, v26, v48, 2
	v_xor3_b32 v35, v35, v43, v32
	v_xor_b32_e32 v36, v36, v38
	v_xor_b32_e32 v37, v39, v37
	v_add3_u32 v27, v27, v47, v49
	v_xor_b32_e32 v47, v48, v29
	v_alignbit_b32 v35, v35, v35, 31
	v_xor3_b32 v36, v36, v44, v33
	v_xor3_b32 v37, v37, v45, v34
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v27
	v_bfi_b32 v47, v47, v30, v29
	v_add_nc_u32_e32 v29, v29, v42
	v_alignbit_b32 v36, v36, v36, 31
	v_alignbit_b32 v37, v37, v37, 31
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v27, v27, v49, 2
	v_xor_b32_e32 v38, v40, v38
	v_xor_b32_e32 v39, v39, v41
	v_xor_b32_e32 v40, v42, v40
	v_add3_u32 v28, v28, v47, v50
	v_xor_b32_e32 v47, v49, v30
	v_xor3_b32 v38, v38, v46, v35
	v_xor3_b32 v39, v39, v31, v36
	v_xor3_b32 v40, v40, v32, v37
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v28
	v_bfi_b32 v47, v47, v26, v30
	v_add_nc_u32_e32 v30, v30, v43
	v_alignbit_b32 v38, v38, v38, 31
	v_alignbit_b32 v39, v39, v39, 31
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v28, v28, v48, 2
	v_alignbit_b32 v40, v40, v40, 31
	v_xor_b32_e32 v41, v43, v41
	v_xor_b32_e32 v42, v42, v44
	v_add3_u32 v29, v29, v47, v50
	v_xor_b32_e32 v47, v48, v26
	v_xor_b32_e32 v43, v45, v43
	v_xor3_b32 v41, v41, v33, v38
	v_xor3_b32 v42, v42, v34, v39
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v29
	v_bfi_b32 v47, v47, v27, v26
	v_add_nc_u32_e32 v26, v26, v44
	v_alignbit_b32 v41, v41, v41, 31
	v_alignbit_b32 v42, v42, v42, 31
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v29, v29, v49, 2
	v_xor3_b32 v43, v43, v35, v40
	v_xor_b32_e32 v44, v46, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v30, v30, v47, v50
	v_xor_b32_e32 v47, v49, v27
	v_alignbit_b32 v43, v43, v43, 31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v44, v44, v36, v41
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v30
	s_delay_alu instid0(VALU_DEP_4)
	v_bfi_b32 v47, v47, v28, v27
	v_add_nc_u32_e32 v27, v27, v45
	v_xor_b32_e32 v45, v45, v31
	v_alignbit_b32 v44, v44, v44, 31
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v30, v30, v48, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v45, v45, v37, v42
	v_add3_u32 v26, v26, v47, v50
	v_xor_b32_e32 v47, v48, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v45, v45, v45, 31
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v29, v28
	v_add_nc_u32_e32 v28, v28, v46
	v_xor_b32_e32 v46, v32, v46
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v26, v26, v49, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v46, v46, v38, v43
	v_add3_u32 v27, v27, v47, v50
	v_xor_b32_e32 v47, v49, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v46, v46, v46, 31
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v30, v29
	v_add_nc_u32_e32 v29, v29, v31
	v_xor_b32_e32 v31, v33, v31
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v27, v27, v48, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v31, v31, v39, v44
	v_add3_u32 v28, v28, v47, v50
	v_xor_b32_e32 v47, v48, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v31, v31, v31, 31
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v26, v30
	v_add_nc_u32_e32 v30, v30, v32
	v_xor_b32_e32 v32, v32, v34
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v28, v28, v49, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v32, v32, v40, v45
	v_add3_u32 v29, v29, v47, v50
	v_xor_b32_e32 v47, v49, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v32, v32, v32, 31
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v27, v26
	v_add_nc_u32_e32 v26, v26, v33
	v_xor_b32_e32 v33, v35, v33
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v29, v29, v48, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v33, v33, v41, v46
	v_add3_u32 v30, v30, v47, v50
	v_xor_b32_e32 v47, v48, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v33, v33, v33, 31
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v28, v27
	v_add_nc_u32_e32 v27, v27, v34
	v_xor_b32_e32 v34, v36, v34
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v30, v30, v49, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v34, v34, v42, v31
	v_add3_u32 v26, v26, v47, v50
	v_xor_b32_e32 v47, v49, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v34, v34, v34, 31
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v29, v28
	v_add_nc_u32_e32 v28, v28, v35
	v_xor_b32_e32 v35, v35, v37
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v26, v26, v48, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v35, v35, v43, v32
	v_add3_u32 v27, v27, v47, v50
	v_xor_b32_e32 v47, v48, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v35, v35, v35, 31
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v30, v29
	v_add_nc_u32_e32 v29, v29, v36
	v_xor_b32_e32 v36, v38, v36
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v27, v27, v49, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v36, v36, v44, v33
	v_add3_u32 v28, v28, v47, v50
	v_xor_b32_e32 v47, v49, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v36, v36, v36, 31
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v26, v30
	v_add_nc_u32_e32 v30, v30, v37
	v_xor_b32_e32 v37, v39, v37
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v28, v28, v48, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v37, v37, v45, v34
	v_add3_u32 v29, v29, v47, v50
	v_xor_b32_e32 v47, v48, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v37, v37, v37, 31
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v27, v26
	v_add_nc_u32_e32 v26, v26, v38
	v_xor_b32_e32 v38, v38, v40
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v29, v29, v49, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v38, v38, v46, v35
	v_add3_u32 v30, v30, v47, v50
	v_xor_b32_e32 v47, v49, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v38, v38, v38, 31
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v28, v27
	v_add_nc_u32_e32 v27, v27, v39
	v_xor_b32_e32 v39, v41, v39
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v30, v30, v48, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v39, v39, v31, v36
	v_add3_u32 v26, v26, v47, v50
	v_xor_b32_e32 v47, v48, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v39, v39, v39, 31
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v29, v28
	v_add_nc_u32_e32 v28, v28, v40
	v_xor_b32_e32 v40, v42, v40
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v26, v26, v49, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v40, v40, v32, v37
	v_add3_u32 v27, v27, v47, v50
	v_xor_b32_e32 v47, v49, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v40, v40, v40, 31
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v30, v29
	v_add_nc_u32_e32 v29, v29, v41
	v_xor_b32_e32 v41, v41, v43
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v27, v27, v48, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v28, v28, v47, v50
	v_xor_b32_e32 v47, v48, v30
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_bfi_b32 v47, v47, v26, v30
	v_add_nc_u32_e32 v30, v30, v42
	v_xor_b32_e32 v42, v44, v42
	v_alignbit_b32 v50, v49, v49, 27
	v_alignbit_b32 v28, v28, v49, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v29, v29, v47, v50
	v_xor_b32_e32 v47, v49, v26
	v_add_nc_u32_e32 v48, 0x8f1bbcdc, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v47, v47, v27, v26
	v_alignbit_b32 v50, v48, v48, 27
	v_alignbit_b32 v29, v29, v48, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v30, v30, v47, v50
	v_xor3_b32 v47, v28, v27, v48
	v_add_nc_u32_e32 v49, 0x8f1bbcdc, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v26, v43, v26, v47
	v_alignbit_b32 v47, v49, v49, 27
	v_xor3_b32 v48, v29, v28, v49
	v_alignbit_b32 v30, v30, v49, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v26, v26, v47, 0xca62c1d6
	v_add3_u32 v27, v44, v27, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v26, v26, 27
	v_xor3_b32 v48, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v27, v27, v47, 0xca62c1d6
	v_add3_u32 v28, v45, v28, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v27, v27, 27
	v_xor3_b32 v48, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v28, v28, v47, 0xca62c1d6
	v_add3_u32 v29, v46, v29, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v28, v28, 27
	v_xor3_b32 v48, v27, v26, v28
	v_alignbit_b32 v28, v28, v28, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v29, v29, v47, 0xca62c1d6
	v_add3_u32 v30, v31, v30, v48
	v_xor_b32_e32 v31, v31, v45
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v47, v29, v29, 27
	v_xor3_b32 v48, v28, v27, v29
	v_alignbit_b32 v29, v29, v29, 2
	v_add3_u32 v30, v30, v47, 0xca62c1d6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v26, v32, v26, v48
	v_xor_b32_e32 v32, v32, v46
	v_alignbit_b32 v47, v30, v30, 27
	v_xor3_b32 v48, v29, v28, v30
	v_alignbit_b32 v30, v30, v30, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v26, v26, v47, 0xca62c1d6
	v_add3_u32 v27, v33, v27, v48
	v_xor3_b32 v33, v41, v33, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v26, v26, 27
	v_xor3_b32 v48, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	v_alignbit_b32 v33, v33, v33, 31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v27, v27, v47, 0xca62c1d6
	v_add3_u32 v28, v34, v28, v48
	v_xor3_b32 v34, v42, v34, v39
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v27, v27, 27
	v_xor3_b32 v48, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	v_alignbit_b32 v34, v34, v34, 31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add3_u32 v28, v28, v47, 0xca62c1d6
	v_add3_u32 v29, v35, v29, v48
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v31, v31, v37, v34
	v_alignbit_b32 v47, v28, v28, 27
	v_xor3_b32 v48, v27, v26, v28
	v_alignbit_b32 v28, v28, v28, 2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v31, v31, v31, 31
	v_add3_u32 v29, v29, v47, 0xca62c1d6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v30, v36, v30, v48
	v_alignbit_b32 v47, v29, v29, 27
	v_xor3_b32 v48, v28, v27, v29
	v_alignbit_b32 v29, v29, v29, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v30, v30, v47, 0xca62c1d6
	v_add3_u32 v26, v37, v26, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v30, v30, 27
	v_xor3_b32 v48, v29, v28, v30
	v_alignbit_b32 v30, v30, v30, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v26, v26, v47, 0xca62c1d6
	v_add3_u32 v27, v38, v27, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v26, v26, 27
	v_xor3_b32 v48, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v27, v27, v47, 0xca62c1d6
	v_add3_u32 v28, v39, v28, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v47, v27, v27, 27
	v_xor3_b32 v48, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v28, v28, v47, 0xca62c1d6
	v_add3_u32 v29, v40, v29, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v41, v28, v28, 27
	v_xor3_b32 v47, v27, v26, v28
	v_alignbit_b32 v28, v28, v28, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v29, v29, v41, 0xca62c1d6
	v_add3_u32 v30, v33, v30, v47
	v_xor_b32_e32 v41, v45, v43
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v39, v29, v29, 27
	v_xor3_b32 v42, v28, v27, v29
	v_xor3_b32 v35, v41, v35, v40
	v_alignbit_b32 v29, v29, v29, 2
	v_xor_b32_e32 v40, v44, v46
	v_add3_u32 v30, v30, v39, 0xca62c1d6
	v_add3_u32 v26, v34, v26, v42
	v_alignbit_b32 v35, v35, v35, 31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor3_b32 v33, v40, v36, v33
	v_alignbit_b32 v39, v30, v30, 27
	v_xor3_b32 v41, v29, v28, v30
	v_alignbit_b32 v30, v30, v30, 2
	v_xor3_b32 v32, v32, v38, v35
	v_alignbit_b32 v33, v33, v33, 31
	v_add3_u32 v26, v26, v39, 0xca62c1d6
	v_add3_u32 v27, v35, v27, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v32, v32, v32, 31
	v_alignbit_b32 v36, v26, v26, 27
	v_xor3_b32 v39, v30, v29, v26
	v_alignbit_b32 v26, v26, v26, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v27, v27, v36, 0xca62c1d6
	v_add3_u32 v28, v33, v28, v39
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v33, v27, v27, 27
	v_xor3_b32 v34, v26, v30, v27
	v_alignbit_b32 v27, v27, v27, 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v28, v28, v33, 0xca62c1d6
	v_add3_u32 v29, v31, v29, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_alignbit_b32 v31, v28, v28, 27
	v_xor3_b32 v26, v27, v26, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v27, v29, v31, 0xca62c1d6
	v_add3_u32 v26, v32, v30, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v28, v27, v27, 27
	v_add_nc_u32_e32 v27, s1, v27
	v_add3_u32 v26, v26, v28, 0xca62c1d6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e32 vcc_lo, 0xfffff, v27
	v_cmp_ne_u32_e64 s0, s8, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s11, s0, vcc_lo
	s_and_saveexec_b32 s0, s11
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_1 Depth=1
	s_load_b32 s10, s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s10, -1
	s_cselect_b32 s10, -1, 0
	s_and_not1_b32 s9, s9, exec_lo
	s_or_not1_b32 s10, s10, exec_lo
.LBB0_7:                                ; %Flow1497
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s10
	s_or_b32 s6, s0, s6
	s_and_not1_b32 s0, s3, exec_lo
	s_and_b32 s3, s9, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s0, s3
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_1
; %bb.8:                                ; %loop.exit.guard
	s_or_b32 exec_lo, exec_lo, s6
	s_and_saveexec_b32 s0, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_lshl_add_u32 v0, s15, 6, v0
	v_mov_b32_e32 v19, 0
	s_clause 0x3
	global_store_b128 v[17:18], v[13:16], off
	global_store_b128 v[17:18], v[9:12], off offset:16
	global_store_b128 v[17:18], v[5:8], off offset:32
	global_store_b128 v[17:18], v[1:4], off offset:48
	global_store_b32 v19, v0, s[4:5]
.LBB0_10:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13sha_transformPiPj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 80
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 51
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13sha_transformPiPj, .Lfunc_end0-_Z13sha_transformPiPj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5992
; NumSgprs: 18
; NumVgprs: 51
; ScratchSize: 80
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 51
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	g_cSHA1baseCode         ; @g_cSHA1baseCode
	.type	g_cSHA1baseCode,@object
	.section	.bss,"aw",@nobits
	.globl	g_cSHA1baseCode
	.p2align	4, 0x0
g_cSHA1baseCode:
	.zero	20
	.size	g_cSHA1baseCode, 20

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym g_cSHA1baseCode
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z13sha_transformPiPj
    .private_segment_fixed_size: 80
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z13sha_transformPiPj.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     51
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
