#include <stdio.h>
#include <stdlib.h>
#include <math.h>

template <class T>
class vector3d
{
    public: 
        T x, y, z;

        vector3d()
        {
            x = 0;
            y = 0;
            z = 0;
        }

        vector3d(T x_, T y_, T z_)
        {
            x = x_;
            y = y_;
            z = z_;
        }

        __host__ __device__ inline vector3d& operator +=(const vector3d& rhs)
        {
            x += rhs.x;
            y += rhs.y;
            z += rhs.z;
            return *this;
        }

        __host__ __device__ inline vector3d& operator +(const vector3d& rhs)
        {
            *this += rhs;
            return *this;
        }

        __host__ __device__ inline vector3d& operator /=(const T& rhs)
        {
            x /= rhs;
            y /= rhs;
            z /= rhs;
            return *this;
        }

        __host__ __device__ inline vector3d& operator /(const T& rhs)
        {
            *this /= rhs;
            return *this;
        }

        __host__ __device__ inline void test()
        {
            int test = 0;
            test++;
        }
        
};

__global__ void vecAdd(vector3d<float> *a, vector3d<float> *b, vector3d<float> *c, int n)
{
    int id = blockIdx.x*blockDim.x+threadIdx.x;

    if (id < n)
    {
        // c[id].x = a[id].x + b[id].x;
        // c[id].y = a[id].y + b[id].y;
        // c[id].z = a[id].z + b[id].z;

        c[id] = a[id] + b[id];

        c[id].test();
    }
}
 
int main( int argc, char* argv[] )
{
    // Size of vectors
    int n = 1000000;
    float n_f = 1000000.0f;
 		
    // Host input vectors
    vector3d<float> *h_a;
    vector3d<float> *h_b;
    
    //Host output vector
    vector3d<float> *h_c;
 
    // Device input vectors
    vector3d<float> *d_a;
    vector3d<float> *d_b;

    //Device output vector
    vector3d<float> *d_c;
 
    // Size, in bytes, of each vector
    size_t bytes = n*sizeof(vector3d<float>);
 
    // Allocate memory for each vector on host
    h_a = new vector3d<float>[bytes](); //(vector3d<float>*)malloc(bytes);
    h_b = new vector3d<float>[bytes](); //(vector3d<float>*)malloc(bytes);
    h_c = new vector3d<float>[bytes](); //(vector3d<float>*)malloc(bytes);
 
    // Allocate memory for each vector on GPU
    cudaMalloc(&d_a, bytes);
    cudaMalloc(&d_b, bytes);
    cudaMalloc(&d_c, bytes);
 
    // Initialize vectors on host
    for(int i = 0; i <= n; i++ ) {
        h_a[i] = vector3d<float>(1,2,3);
        h_b[i] = vector3d<float>(1,2,3);
    }
 
    // Copy host vectors to device
    cudaMemcpy( d_a, h_a, bytes, cudaMemcpyHostToDevice);
    cudaMemcpy( d_b, h_b, bytes, cudaMemcpyHostToDevice);
 
    int blockSize, gridSize;
 
    // Number of threads in each thread block
    blockSize = 1024;
 
    // Number of thread blocks in grid
    gridSize = (int)ceil((float)n/blockSize);
 
    // Execute the kernel
    vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);

    // Copy array back to host
    cudaMemcpy( h_c, d_c, bytes, cudaMemcpyDeviceToHost );
 
    // Sum up vector c and print result divided by n, this should equal 1 within error
    vector3d<float> sum;
    for(int i=0; i<=n; i++)
        sum += h_c[i];

    printf("final result: %f, %f, %f\n", sum.x / n_f, sum.y / n_f, sum.z / n_f);
    printf("final result: %f, %f, %f\n", sum.x, sum.y, sum.z);
 
    // Release device memory
    cudaFree(d_a);
    cudaFree(d_b);
    cudaFree(d_c);
 
    // Release host memory
    free(h_a);
    free(h_b);
    free(h_c);
 
    return 0;
}

	.file	"tmpxft_00281261_00000000-6_vectorAdd_obj.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z43__device_stub__Z6vecAddP8vector3dIfES1_S1_iP8vector3dIfES1_S1_i
	.type	_Z43__device_stub__Z6vecAddP8vector3dIfES1_S1_iP8vector3dIfES1_S1_i, @function
_Z43__device_stub__Z6vecAddP8vector3dIfES1_S1_iP8vector3dIfES1_S1_i:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6vecAddP8vector3dIfES1_S1_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z43__device_stub__Z6vecAddP8vector3dIfES1_S1_iP8vector3dIfES1_S1_i, .-_Z43__device_stub__Z6vecAddP8vector3dIfES1_S1_iP8vector3dIfES1_S1_i
	.globl	_Z6vecAddP8vector3dIfES1_S1_i
	.type	_Z6vecAddP8vector3dIfES1_S1_i, @function
_Z6vecAddP8vector3dIfES1_S1_i:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z43__device_stub__Z6vecAddP8vector3dIfES1_S1_iP8vector3dIfES1_S1_i
	.cfi_endproc
.LFE2060:
	.size	_Z6vecAddP8vector3dIfES1_S1_i, .-_Z6vecAddP8vector3dIfES1_S1_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC5:
	.string	"final result: %f, %f, %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$144000000, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	_Znam@PLT
	movq	%rax, %rbp
	leaq	144000000(%rax), %rdx
.L9:
	movl	$0x00000000, (%rax)
	addq	$12, %rax
	movl	$0x00000000, -8(%rax)
	movl	$0x00000000, -4(%rax)
	cmpq	%rdx, %rax
	jne	.L9
	movl	$144000000, %edi
	call	_Znam@PLT
	movq	%rax, %rbx
	leaq	144000000(%rax), %rdx
.L10:
	movl	$0x00000000, (%rax)
	addq	$12, %rax
	movl	$0x00000000, -8(%rax)
	movl	$0x00000000, -4(%rax)
	cmpq	%rdx, %rax
	jne	.L10
	movl	$144000000, %edi
	call	_Znam@PLT
	movq	%rax, %r12
	movq	%rax, %r13
	leaq	144000000(%rax), %rdx
.L11:
	movl	$0x00000000, (%rax)
	addq	$12, %rax
	movl	$0x00000000, -8(%rax)
	movl	$0x00000000, -4(%rax)
	cmpq	%rax, %rdx
	jne	.L11
	leaq	24(%rsp), %rdi
	movl	$12000000, %esi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$12000000, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$12000000, %esi
	call	cudaMalloc@PLT
	movss	.LC1(%rip), %xmm2
	movss	.LC2(%rip), %xmm1
	xorl	%eax, %eax
	movss	.LC3(%rip), %xmm0
.L12:
	movss	%xmm2, 0(%rbp,%rax)
	movss	%xmm1, 4(%rbp,%rax)
	movss	%xmm0, 8(%rbp,%rax)
	movss	%xmm2, (%rbx,%rax)
	movss	%xmm1, 4(%rbx,%rax)
	movss	%xmm0, 8(%rbx,%rax)
	addq	$12, %rax
	cmpq	$12000012, %rax
	jne	.L12
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$12000000, %edx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$12000000, %edx
	call	cudaMemcpy@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294968273, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1000000, %ecx
	movq	24(%rsp), %rdi
	call	_Z43__device_stub__Z6vecAddP8vector3dIfES1_S1_iP8vector3dIfES1_S1_i
.L13:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$12000000, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	xorps	%xmm5, %xmm5
	leaq	12000012(%r12), %rax
	movaps	%xmm5, %xmm4
	movaps	%xmm5, %xmm3
.L14:
	addss	0(%r13), %xmm3
	addss	4(%r13), %xmm4
	addq	$12, %r13
	addss	-4(%r13), %xmm5
	cmpq	%rax, %r13
	jne	.L14
	movss	.LC4(%rip), %xmm6
	movaps	%xmm5, %xmm2
	movaps	%xmm4, %xmm1
	movb	$3, %al
	movaps	%xmm3, %xmm0
	leaq	.LC5(%rip), %r13
	movl	$2, %edi
	movss	%xmm5, 12(%rsp)
	divss	%xmm6, %xmm2
	movq	%r13, %rsi
	movss	%xmm4, 8(%rsp)
	movss	%xmm3, 4(%rsp)
	divss	%xmm6, %xmm1
	cvtss2sd	%xmm2, %xmm2
	divss	%xmm6, %xmm0
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	%r13, %rsi
	movb	$3, %al
	movss	4(%rsp), %xmm3
	movss	12(%rsp), %xmm5
	movl	$2, %edi
	movss	8(%rsp), %xmm4
	cvtss2sd	%xmm3, %xmm0
	cvtss2sd	%xmm5, %xmm2
	cvtss2sd	%xmm4, %xmm1
	call	__printf_chk@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z6vecAddP8vector3dIfES1_S1_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6vecAddP8vector3dIfES1_S1_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.align 4
.LC2:
	.long	1073741824
	.align 4
.LC3:
	.long	1077936128
	.align 4
.LC4:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>

template <class T>
class vector3d
{
    public: 
        T x, y, z;

        vector3d()
        {
            x = 0;
            y = 0;
            z = 0;
        }

        vector3d(T x_, T y_, T z_)
        {
            x = x_;
            y = y_;
            z = z_;
        }

        __host__ __device__ inline vector3d& operator +=(const vector3d& rhs)
        {
            x += rhs.x;
            y += rhs.y;
            z += rhs.z;
            return *this;
        }

        __host__ __device__ inline vector3d& operator +(const vector3d& rhs)
        {
            *this += rhs;
            return *this;
        }

        __host__ __device__ inline vector3d& operator /=(const T& rhs)
        {
            x /= rhs;
            y /= rhs;
            z /= rhs;
            return *this;
        }

        __host__ __device__ inline vector3d& operator /(const T& rhs)
        {
            *this /= rhs;
            return *this;
        }

        __host__ __device__ inline void test()
        {
            int test = 0;
            test++;
        }
        
};

__global__ void vecAdd(vector3d<float> *a, vector3d<float> *b, vector3d<float> *c, int n)
{
    int id = blockIdx.x*blockDim.x+threadIdx.x;

    if (id < n)
    {
        // c[id].x = a[id].x + b[id].x;
        // c[id].y = a[id].y + b[id].y;
        // c[id].z = a[id].z + b[id].z;

        c[id] = a[id] + b[id];

        c[id].test();
    }
}
 
int main( int argc, char* argv[] )
{
    // Size of vectors
    int n = 1000000;
    float n_f = 1000000.0f;
 		
    // Host input vectors
    vector3d<float> *h_a;
    vector3d<float> *h_b;
    
    //Host output vector
    vector3d<float> *h_c;
 
    // Device input vectors
    vector3d<float> *d_a;
    vector3d<float> *d_b;

    //Device output vector
    vector3d<float> *d_c;
 
    // Size, in bytes, of each vector
    size_t bytes = n*sizeof(vector3d<float>);
 
    // Allocate memory for each vector on host
    h_a = new vector3d<float>[bytes](); //(vector3d<float>*)malloc(bytes);
    h_b = new vector3d<float>[bytes](); //(vector3d<float>*)malloc(bytes);
    h_c = new vector3d<float>[bytes](); //(vector3d<float>*)malloc(bytes);
 
    // Allocate memory for each vector on GPU
    hipMalloc(&d_a, bytes);
    hipMalloc(&d_b, bytes);
    hipMalloc(&d_c, bytes);
 
    // Initialize vectors on host
    for(int i = 0; i <= n; i++ ) {
        h_a[i] = vector3d<float>(1,2,3);
        h_b[i] = vector3d<float>(1,2,3);
    }
 
    // Copy host vectors to device
    hipMemcpy( d_a, h_a, bytes, hipMemcpyHostToDevice);
    hipMemcpy( d_b, h_b, bytes, hipMemcpyHostToDevice);
 
    int blockSize, gridSize;
 
    // Number of threads in each thread block
    blockSize = 1024;
 
    // Number of thread blocks in grid
    gridSize = (int)ceil((float)n/blockSize);
 
    // Execute the kernel
    vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);

    // Copy array back to host
    hipMemcpy( h_c, d_c, bytes, hipMemcpyDeviceToHost );
 
    // Sum up vector c and print result divided by n, this should equal 1 within error
    vector3d<float> sum;
    for(int i=0; i<=n; i++)
        sum += h_c[i];

    printf("final result: %f, %f, %f\n", sum.x / n_f, sum.y / n_f, sum.z / n_f);
    printf("final result: %f, %f, %f\n", sum.x, sum.y, sum.z);
 
    // Release device memory
    hipFree(d_a);
    hipFree(d_b);
    hipFree(d_c);
 
    // Release host memory
    free(h_a);
    free(h_b);
    free(h_c);
 
    return 0;
}

	.text
	.file	"vectorAdd_obj.hip"
	.globl	_Z21__device_stub__vecAddP8vector3dIfES1_S1_i # -- Begin function _Z21__device_stub__vecAddP8vector3dIfES1_S1_i
	.type	_Z21__device_stub__vecAddP8vector3dIfES1_S1_i,@function
_Z21__device_stub__vecAddP8vector3dIfES1_S1_i: # @_Z21__device_stub__vecAddP8vector3dIfES1_S1_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6vecAddP8vector3dIfES1_S1_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__vecAddP8vector3dIfES1_S1_i, .Lfunc_end0-_Z21__device_stub__vecAddP8vector3dIfES1_S1_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$144000000, %edi                # imm = 0x8954400
	callq	_Znam
	movq	%rax, %rbx
	movl	$144000000, %edx                # imm = 0x8954400
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$144000000, %edi                # imm = 0x8954400
	callq	_Znam
	movq	%rax, %r14
	movl	$144000000, %edx                # imm = 0x8954400
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movl	$144000000, %edi                # imm = 0x8954400
	callq	_Znam
	movq	%rax, %r15
	movl	$144000000, %edx                # imm = 0x8954400
	movq	%rax, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	leaq	24(%rsp), %rdi
	movl	$12000000, %esi                 # imm = 0xB71B00
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$12000000, %esi                 # imm = 0xB71B00
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$12000000, %esi                 # imm = 0xB71B00
	callq	hipMalloc
	movl	$8, %eax
	movabsq	$4611686019492741120, %rcx      # imm = 0x400000003F800000
	movl	$1077936128, %edx               # imm = 0x40400000
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movq	%rcx, -8(%rbx,%rax)
	movl	%edx, (%rbx,%rax)
	movq	%rcx, -8(%r14,%rax)
	movl	%edx, (%r14,%rax)
	addq	$12, %rax
	cmpq	$12000020, %rax                 # imm = 0xB71B14
	jne	.LBB1_1
# %bb.2:
	movq	24(%rsp), %rdi
	movl	$12000000, %edx                 # imm = 0xB71B00
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$12000000, %edx                 # imm = 0xB71B00
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294968273, %rdi               # imm = 0x1000003D1
	leaq	47(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$1000000, %ecx                  # imm = 0xF4240
	callq	_Z21__device_stub__vecAddP8vector3dIfES1_S1_i
.LBB1_4:
	movq	8(%rsp), %rsi
	movl	$12000000, %edx                 # imm = 0xB71B00
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	movl	$8, %eax
	xorps	%xmm1, %xmm1
	xorps	%xmm3, %xmm3
.LBB1_5:                                # =>This Inner Loop Header: Depth=1
	addss	-8(%r15,%rax), %xmm0
	addss	-4(%r15,%rax), %xmm1
	addss	(%r15,%rax), %xmm3
	addq	$12, %rax
	cmpq	$12000020, %rax                 # imm = 0xB71B14
	jne	.LBB1_5
# %bb.6:
	movss	.LCPI1_0(%rip), %xmm2           # xmm2 = mem[0],zero,zero,zero
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	divss	%xmm2, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movss	%xmm1, 40(%rsp)                 # 4-byte Spill
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movss	%xmm3, 36(%rsp)                 # 4-byte Spill
	divss	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	movl	$.L.str, %edi
	movb	$3, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	44(%rsp), %xmm0                 # 4-byte Folded Reload
	xorps	%xmm1, %xmm1
	cvtss2sd	40(%rsp), %xmm1                 # 4-byte Folded Reload
	xorps	%xmm2, %xmm2
	cvtss2sd	36(%rsp), %xmm2                 # 4-byte Folded Reload
	movl	$.L.str, %edi
	movb	$3, %al
	callq	printf
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6vecAddP8vector3dIfES1_S1_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6vecAddP8vector3dIfES1_S1_i,@object # @_Z6vecAddP8vector3dIfES1_S1_i
	.section	.rodata,"a",@progbits
	.globl	_Z6vecAddP8vector3dIfES1_S1_i
	.p2align	3, 0x0
_Z6vecAddP8vector3dIfES1_S1_i:
	.quad	_Z21__device_stub__vecAddP8vector3dIfES1_S1_i
	.size	_Z6vecAddP8vector3dIfES1_S1_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"final result: %f, %f, %f\n"
	.size	.L.str, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6vecAddP8vector3dIfES1_S1_i"
	.size	.L__unnamed_1, 30

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__vecAddP8vector3dIfES1_S1_i
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6vecAddP8vector3dIfES1_S1_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6vecAddP8vector3dIfES1_S1_i ; -- Begin function _Z6vecAddP8vector3dIfES1_S1_i
	.globl	_Z6vecAddP8vector3dIfES1_S1_i
	.p2align	8
	.type	_Z6vecAddP8vector3dIfES1_S1_i,@function
_Z6vecAddP8vector3dIfES1_S1_i:          ; @_Z6vecAddP8vector3dIfES1_S1_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_i64_i32 v[6:7], null, v1, 12, 0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v7, vcc_lo
	global_load_b96 v[0:2], v[0:1], off
	global_load_b96 v[3:5], v[8:9], off
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v0, v0, v3 :: v_dual_add_f32 v1, v1, v4
	v_add_f32_e32 v2, v2, v5
	global_store_b96 v[8:9], v[0:2], off
	global_load_b32 v2, v[8:9], off offset:8
	v_add_co_u32 v0, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off offset:8
	global_load_b64 v[2:3], v[8:9], off
	s_waitcnt vmcnt(0)
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6vecAddP8vector3dIfES1_S1_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6vecAddP8vector3dIfES1_S1_i, .Lfunc_end0-_Z6vecAddP8vector3dIfES1_S1_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 220
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6vecAddP8vector3dIfES1_S1_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6vecAddP8vector3dIfES1_S1_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
