#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>

#include <iostream>

#define BLOCK_SIZE 512

#define checkCuda(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess) {
      fprintf(stdout,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

#define SET_SIZE 64
#define LINE_SIZE 128
#define STRIDE LINE_SIZE*SET_SIZE

__global__ void kernel(char *out, char *in, int size) {
    long tid = threadIdx.x + blockIdx.x * blockDim.x;
    if (tid < size) out[tid] = in[(tid*STRIDE)%size];
}

void benchmark(char *out_host, char *in_host, int size) {
    char *out_gpu, *in_gpu;

    // Allocate arrays in GPU memory
    checkCuda(cudaMalloc((void**)&(out_gpu), size*sizeof(char)));
    checkCuda(cudaMalloc((void**)&(in_gpu), size*sizeof(char)));

    // Copy input to GPU
    checkCuda(cudaMemcpy(in_gpu, in_host, size*sizeof(char), cudaMemcpyHostToDevice));

    dim3 dimGrid(1+(size-1)/BLOCK_SIZE);
    dim3 dimBlock(BLOCK_SIZE);

    // Execute kernel
    kernel<<<dimGrid, dimBlock>>>(out_gpu, in_gpu, size);

    // Print any errors that may have occured in kernel
    checkCuda(cudaPeekAtLastError());

    // Retrieve results from the GPU
    checkCuda(cudaMemcpy(out_host, out_gpu, size*sizeof(char), cudaMemcpyDeviceToHost));

    // Free resources and end the program
    checkCuda(cudaFree(out_gpu));
    checkCuda(cudaFree(in_gpu));
}

	.file	"tmpxft_00259100_00000000-6_benchGPU.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3635:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stdout(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z28__device_stub__Z6kernelPcS_iPcS_i
	.type	_Z28__device_stub__Z6kernelPcS_iPcS_i, @function
_Z28__device_stub__Z6kernelPcS_iPcS_i:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6kernelPcS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L12:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z28__device_stub__Z6kernelPcS_iPcS_i, .-_Z28__device_stub__Z6kernelPcS_iPcS_i
	.globl	_Z6kernelPcS_i
	.type	_Z6kernelPcS_i, @function
_Z6kernelPcS_i:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z6kernelPcS_iPcS_i
	.cfi_endproc
.LFE3662:
	.size	_Z6kernelPcS_i, .-_Z6kernelPcS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/keelimeguy/eece5640-final/master/CustomBenchmarks/CUSTOM1/benchGPU.cu"
	.text
	.globl	_Z9benchmarkPcS_i
	.type	_Z9benchmarkPcS_i, @function
_Z9benchmarkPcS_i:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movslq	%edx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%r12, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	leaq	.LC1(%rip), %rbx
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$31, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$32, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	8(%rsp), %rdi
	movq	%r12, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$35, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	leal	-1(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$512, %ecx
	cltd
	idivl	%ecx
	movl	$8388609, %edx
	movl	$1, %ecx
	salq	$9, %rdx
	incl	%eax
	movl	%eax, 16(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r12d, %edx
	call	_Z28__device_stub__Z6kernelPcS_iPcS_i
.L18:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$44, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rsi
	movq	%r12, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$47, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$50, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$51, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z9benchmarkPcS_i, .-_Z9benchmarkPcS_i
	.section	.rodata.str1.1
.LC2:
	.string	"_Z6kernelPcS_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6kernelPcS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

#include <iostream>

#define BLOCK_SIZE 512

#define checkCuda(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess) {
      fprintf(stdout,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

#define SET_SIZE 64
#define LINE_SIZE 128
#define STRIDE LINE_SIZE*SET_SIZE

__global__ void kernel(char *out, char *in, int size) {
    long tid = threadIdx.x + blockIdx.x * blockDim.x;
    if (tid < size) out[tid] = in[(tid*STRIDE)%size];
}

void benchmark(char *out_host, char *in_host, int size) {
    char *out_gpu, *in_gpu;

    // Allocate arrays in GPU memory
    checkCuda(hipMalloc((void**)&(out_gpu), size*sizeof(char)));
    checkCuda(hipMalloc((void**)&(in_gpu), size*sizeof(char)));

    // Copy input to GPU
    checkCuda(hipMemcpy(in_gpu, in_host, size*sizeof(char), hipMemcpyHostToDevice));

    dim3 dimGrid(1+(size-1)/BLOCK_SIZE);
    dim3 dimBlock(BLOCK_SIZE);

    // Execute kernel
    kernel<<<dimGrid, dimBlock>>>(out_gpu, in_gpu, size);

    // Print any errors that may have occured in kernel
    checkCuda(hipPeekAtLastError());

    // Retrieve results from the GPU
    checkCuda(hipMemcpy(out_host, out_gpu, size*sizeof(char), hipMemcpyDeviceToHost));

    // Free resources and end the program
    checkCuda(hipFree(out_gpu));
    checkCuda(hipFree(in_gpu));
}

	.text
	.file	"benchGPU.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z21__device_stub__kernelPcS_i  # -- Begin function _Z21__device_stub__kernelPcS_i
	.type	_Z21__device_stub__kernelPcS_i,@function
_Z21__device_stub__kernelPcS_i:         # @_Z21__device_stub__kernelPcS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6kernelPcS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__kernelPcS_i, .Lfunc_end0-_Z21__device_stub__kernelPcS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z9benchmarkPcS_i               # -- Begin function _Z9benchmarkPcS_i
	.type	_Z9benchmarkPcS_i,@function
_Z9benchmarkPcS_i:                      # @_Z9benchmarkPcS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %r15d
	movq	%rsi, %r12
	movq	%rdi, %r14
	movslq	%edx, %rbx
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.3:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.5:                                # %_Z9gpuAssert10hipError_tPKcib.exit14
	movq	(%rsp), %rdi
	movq	%r12, %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.7:                                # %_Z9gpuAssert10hipError_tPKcib.exit16
	leal	-1(%r15), %eax
	leal	510(%r15), %edi
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$9, %edi
	incl	%edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.8:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	%r15d, %edx
	callq	_Z21__device_stub__kernelPcS_i
.LBB1_9:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.11:                               # %_Z9gpuAssert10hipError_tPKcib.exit18
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.14:                               # %_Z9gpuAssert10hipError_tPKcib.exit20
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.16:                               # %_Z9gpuAssert10hipError_tPKcib.exit22
	movq	(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.18:                               # %_Z9gpuAssert10hipError_tPKcib.exit24
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:
	.cfi_def_cfa_offset 64
	movl	%eax, %ebp
	movq	stdout(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$31, %r8d
	jmp	.LBB1_2
.LBB1_4:
	movl	%eax, %ebp
	movq	stdout(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$32, %r8d
	jmp	.LBB1_2
.LBB1_6:
	movl	%eax, %ebp
	movq	stdout(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$35, %r8d
	jmp	.LBB1_2
.LBB1_10:
	movl	%eax, %ebp
	movq	stdout(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$44, %r8d
.LBB1_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB1_12:
	movl	%eax, %ebx
	movq	stdout(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$47, %r8d
	jmp	.LBB1_13
.LBB1_15:
	movl	%eax, %ebx
	movq	stdout(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$50, %r8d
	jmp	.LBB1_13
.LBB1_17:
	movl	%eax, %ebx
	movq	stdout(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$51, %r8d
.LBB1_13:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z9benchmarkPcS_i, .Lfunc_end1-_Z9benchmarkPcS_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6kernelPcS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6kernelPcS_i,@object          # @_Z6kernelPcS_i
	.section	.rodata,"a",@progbits
	.globl	_Z6kernelPcS_i
	.p2align	3, 0x0
_Z6kernelPcS_i:
	.quad	_Z21__device_stub__kernelPcS_i
	.size	_Z6kernelPcS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/keelimeguy/eece5640-final/master/CustomBenchmarks/CUSTOM1/benchGPU.hip"
	.size	.L.str, 133

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.1, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6kernelPcS_i"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__kernelPcS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6kernelPcS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6kernelPcS_i          ; -- Begin function _Z6kernelPcS_i
	.globl	_Z6kernelPcS_i
	.p2align	8
	.type	_Z6kernelPcS_i,@function
_Z6kernelPcS_i:                         ; @_Z6kernelPcS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x10
	s_mov_b32 s4, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	v_mov_b32_e32 v2, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmpx_gt_i64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_cvt_f32_u32_e32 v0, s2
	v_cvt_f32_u32_e32 v2, s3
	s_sub_u32 s4, 0, s2
	s_subb_u32 s5, 0, s3
	v_lshrrev_b32_e32 v10, 19, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v2, 0x4f800000, v0
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v0
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v0, v2, 0xcf800000, v0
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, s4, v2
	v_mul_hi_u32 v4, s4, v0
	v_mul_lo_u32 v5, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_mul_lo_u32 v4, s4, v0
	v_add_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, v4
	v_mul_lo_u32 v6, v0, v3
	v_mul_hi_u32 v7, v0, v3
	v_mul_hi_u32 v8, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_mul_hi_u32 v9, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s4, v0
	v_mul_lo_u32 v5, s5, v0
	v_mul_lo_u32 v4, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s4, v0
	s_load_b128 s[4:7], s[0:1], 0x0
	v_add_nc_u32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, v4
	v_mul_lo_u32 v6, v0, v3
	v_mul_hi_u32 v7, v0, v3
	v_mul_hi_u32 v8, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_mul_hi_u32 v9, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_lshlrev_b32_e32 v8, 13, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v9, vcc_lo, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v11, v8, v0
	v_mad_u64_u32 v[4:5], null, v10, v0, 0
	v_mad_u64_u32 v[2:3], null, v8, v9, 0
	v_mad_u64_u32 v[6:7], null, v10, v9, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v11, v2
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v4
	v_add_co_ci_u32_e32 v0, vcc_lo, v2, v5, vcc_lo
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v5, s3, v0
	v_mad_u64_u32 v[2:3], null, s2, v0, 0
	v_mul_lo_u32 v0, s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v2, vcc_lo, v8, v2
	v_add3_u32 v0, v3, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v10, v0
	v_subrev_co_ci_u32_e64 v3, s0, s3, v3, vcc_lo
	v_sub_co_ci_u32_e32 v0, vcc_lo, v10, v0, vcc_lo
	v_sub_co_u32 v4, vcc_lo, v2, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v5, s0, 0, v3, vcc_lo
	v_cmp_le_u32_e64 s0, s2, v2
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	v_cndmask_b32_e64 v6, 0, -1, s0
	v_cmp_le_u32_e64 s0, s2, v4
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 0, -1, s0
	v_cmp_le_u32_e64 s0, s3, v5
	v_cndmask_b32_e64 v8, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v7, v8, v7, vcc_lo
	v_sub_co_u32 v8, vcc_lo, v4, s2
	v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v6, v9, v6, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v5, v3 :: v_dual_cndmask_b32 v4, v4, v8
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v0, vcc_lo
	v_add_co_u32 v0, s0, s4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, null, s5, 0, s0
	global_load_u8 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6kernelPcS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6kernelPcS_i, .Lfunc_end0-_Z6kernelPcS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 900
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6kernelPcS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6kernelPcS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
