/* This program is designed to take the first
 derivative of a 3 dimensional function */

// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>

// includes, project
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <cufft.h>
#include <cuComplex.h>
#define NX 256
#define NY 256
#define NZ 256
#define NZ2 (NZ/2 + 1)
#define NN (NX*NY*NZ)
#define L (2.0*M_PI)
#define TX 8
#define TY 8
#define TZ 8

int divUp(int a, int b) { return (a + b - 1) / b; }

void writeData(const char *name, double *data, int size)
{
	int i = 0;
	FILE *out = fopen(name, "wb");
	for (i = 0; i < size; ++i){
		fwrite( (void*)(&data[i]), sizeof(data[i]), 1, out);
	}

	fclose(out);

	return;
}

__device__
int idxClip(int idx, int idxMax){
	return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}

__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
	return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
	// Note: using column-major indexing format
}

__global__ 
void initialize(cufftDoubleReal *f1, cufftDoubleReal *f2)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	const int k = blockIdx.z * blockDim.z + threadIdx.z;
	if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
	const int idx = flatten(i, j, k, NX, NY, NZ);

	// Create physical vectors in temporary memory
	double x = i * (double)L / NX;
	double y = j * (double)L / NY;
	double z = k * (double)L / NZ;

	// Initialize starting array
	f1[idx] = sin(x)*cos(y)*cos(z);

	// Calculate exact derivative of starting array
	f2[idx] = cos(x)*cos(y)*cos(z);

	return;
}

__global__
void waveDomain(double *k1)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;

	if (i < NX/2)
		k1[i] = (double)i;
	else
		k1[i] = (double)i - NX;

	return;
}

__global__
void multIk(cufftDoubleComplex *f, cufftDoubleComplex *fIk, double *wave, const int dir)
{	// Function to multiply the function fhat by i*k
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	const int k = blockIdx.z * blockDim.z + threadIdx.z;
	if ((i >= NX) || (j >= NY) || (k >= NZ2)) return;
	const int idx = flatten(i, j, k, NX, NY, NZ2);

	// i*k*(a + bi) = -k*b + i*k*a

	if(dir == 1){ // Takes derivative in 1 direction (usually x)
		fIk[idx].x = -wave[i]*f[idx].y;
		fIk[idx].y = wave[i]*f[idx].x;
	}
	if(dir == 2){	// Takes derivative in 2 direction (usually y)
		fIk[idx].x = -wave[j]*f[idx].y;
		fIk[idx].y = wave[j]*f[idx].x;
	}
	if(dir == 3){
		fIk[idx].x = -wave[k]*f[idx].y;
		fIk[idx].y = wave[k]*f[idx].x;
	}

	return;
}

__global__
void complexScale( cufftDoubleComplex *f)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	const int k = blockIdx.z * blockDim.z + threadIdx.z;
	if ((i >= NX) || (j >= NY) || (k >= NZ2)) return;
	const int idx = flatten(i, j, k, NX, NY, NZ2);

	f[idx].x = f[idx].x / ( (double)NN );
	f[idx].y = f[idx].y / ( (double)NN );

	return;
}

void fftder(cufftHandle p, cufftHandle invp, double *wave, cufftDoubleReal *f, cufftDoubleReal *fp, int dir)
{
	// Define loop variables
	cufftDoubleComplex *fhat;
	cufftDoubleComplex *fphat;

	// Allocate memory for temporary arrays
	cudaMallocManaged((void**)&fhat, sizeof(cufftDoubleComplex)*NX*NY*(NZ2) );
	cudaMallocManaged((void**)&fphat, sizeof(cufftDoubleComplex)*NX*NY*(NZ2) );

	// Take Fourier Transform of function
	if (cufftExecD2Z(p, f, fhat ) != CUFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecD2Z failed");
		return;	
	}

	// Launch CUDA kernel to take derivative in Fourier Space;
	const dim3 blockSize(TX, TY, TZ);
	const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
	// Multiplies fhat by I*k (definition of derivative in wavespace)
	multIk<<<gridSize, blockSize>>>(fhat, fphat, wave, dir);
	// Scales the vectors by NX*NY*NZ to account for Fourier Transform
	complexScale<<<gridSize, blockSize>>>(fphat);

	// Inverse Fourier Transform to physical space.
	if (cufftExecZ2D(invp, fphat, fp) != CUFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecZ2D failed");
	return;	}

	// Clear memory
	cudaFree(fhat);
	cudaFree(fphat);

	return;
}

int main (void)
{
	// Set CUDA to run on GTX 980 (currently device 0)
	int deviceNum = 0;

	cudaSetDevice(deviceNum);

    cudaDeviceProp prop;
    cudaGetDeviceProperties(&prop, deviceNum);
    printf("  Device name: %s\n", prop.name);
    printf("  Memory Clock Rate (KHz): %d\n",
           prop.memoryClockRate);
    printf("  Memory Bus Width (bits): %d\n",
           prop.memoryBusWidth);
    printf("  Peak Memory Bandwidth (GB/s): %f\n\n",
 			2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);

	//Create plan for cuFFT
	cufftHandle plan;
	cufftHandle invplan;

	if (cufftPlan3d(&plan, NX, NY, NZ, CUFFT_D2Z) != CUFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecD2Z failed");
		cudaError_t err = cudaGetLastError(); }

	if (cufftPlan3d(&invplan, NX, NY, NZ, CUFFT_Z2D)  != CUFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecD2Z failed");
		cudaError_t err = cudaGetLastError(); }

	// Declare variables
	int i, j, k, idx;
	double *kx = 0;
	cufftDoubleReal *u;
	cufftDoubleReal *dudx;
	cufftDoubleReal *dudx_exact;

	// Allocate memory for arrays
	cudaMallocManaged(&kx, NX*sizeof(double));
	cudaMallocManaged(&u, sizeof(cufftDoubleComplex)*NX*NY*NZ2 );
	cudaMallocManaged(&dudx, sizeof(cufftDoubleReal)*NN );
	cudaMallocManaged(&dudx_exact, sizeof(cufftDoubleReal)*NN );

	// Launch CUDA kernel to initialize velocity field
	const dim3 blockSize(TX, TY, TZ);
	const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));

	int count;
	for (count = 0; count < 11; ++count){

	initialize<<<gridSize, blockSize>>>(u, dudx_exact);
	
	// Setup wavespace domain
	waveDomain<<<gridSize, blockSize>>>(kx);

	cudaDeviceSynchronize();		// Added this line to prevent compiler error: "Bus error (core dumped)".

	// Take derivative using Fourier Transforms
	fftder(plan, invplan, kx, u, dudx, 1);

	// takeFFT(plan, invplan, u, u_fft);
	cudaDeviceSynchronize();

	}

	printf("Using the GPU %s. The number of elements in the array is %2d.\n",prop.name,NX*NY*NZ);
	printf("Displaying 50 results:\n");
	printf("  Index         Error     \n");
	printf(" -------     ----------- \n");
	for (i = 0; i < 1; ++i){
		for (j = 0; j < 1; ++j){
			for (k = 50; k < 101; ++k){
				idx = k + NZ*j + NZ*NY*i;
				printf(" %d             %4.4g \n",idx, dudx[idx]-dudx_exact[idx]);
			}
		}
	}

	// Write output data to file (for additional analysis if desired)
	writeData("dudx",dudx, NX*NY*NZ);
	writeData("dudx_exact", dudx_exact, NX*NY*NZ);
	writeData("u", u, NX*NY*NZ);

	//Clean variables
	cufftDestroy(plan);
	cufftDestroy(invplan);

	cudaFree(u);
	cudaFree(dudx);
	cudaFree(dudx_exact);
	cudaFree(kx);

	cudaDeviceReset();

	return 0;
}

	.file	"tmpxft_003af62f_00000000-6_cuFFT_Test_3D.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3967:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3967:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5divUpii
	.type	_Z5divUpii, @function
_Z5divUpii:
.LFB3959:
	.cfi_startproc
	endbr64
	leal	-1(%rsi,%rdi), %eax
	cltd
	idivl	%esi
	ret
	.cfi_endproc
.LFE3959:
	.size	_Z5divUpii, .-_Z5divUpii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"wb"
	.text
	.globl	_Z9writeDataPKcPdi
	.type	_Z9writeDataPKcPdi, @function
_Z9writeDataPKcPdi:
.LFB3960:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%edx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movq	%rsi, %rbx
	leaq	.LC0(%rip), %rsi
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	fopen@PLT
	movq	%rax, %rbp
.L4:
	cmpl	%r12d, %r13d
	jge	.L8
	movq	%rbx, %rdi
	movq	%rbp, %rcx
	movl	$1, %edx
	movl	$8, %esi
	call	fwrite@PLT
	incl	%r13d
	addq	$8, %rbx
	jmp	.L4
.L8:
	popq	%rax
	.cfi_def_cfa_offset 40
	movq	%rbp, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE3960:
	.size	_Z9writeDataPKcPdi, .-_Z9writeDataPKcPdi
	.globl	_Z7idxClipii
	.type	_Z7idxClipii, @function
_Z7idxClipii:
.LFB3961:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3961:
	.size	_Z7idxClipii, .-_Z7idxClipii
	.globl	_Z7flatteniiiiii
	.type	_Z7flatteniiiiii, @function
_Z7flatteniiiiii:
.LFB3962:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3962:
	.size	_Z7flatteniiiiii, .-_Z7flatteniiiiii
	.globl	_Z32__device_stub__Z10initializePdS_PdS_
	.type	_Z32__device_stub__Z10initializePdS_PdS_, @function
_Z32__device_stub__Z10initializePdS_PdS_:
.LFB3989:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10initializePdS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3989:
	.size	_Z32__device_stub__Z10initializePdS_PdS_, .-_Z32__device_stub__Z10initializePdS_PdS_
	.globl	_Z10initializePdS_
	.type	_Z10initializePdS_, @function
_Z10initializePdS_:
.LFB3990:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10initializePdS_PdS_
	.cfi_endproc
.LFE3990:
	.size	_Z10initializePdS_, .-_Z10initializePdS_
	.globl	_Z30__device_stub__Z10waveDomainPdPd
	.type	_Z30__device_stub__Z10waveDomainPdPd, @function
_Z30__device_stub__Z10waveDomainPdPd:
.LFB3991:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z10waveDomainPd(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L18:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3991:
	.size	_Z30__device_stub__Z10waveDomainPdPd, .-_Z30__device_stub__Z10waveDomainPdPd
	.globl	_Z10waveDomainPd
	.type	_Z10waveDomainPd, @function
_Z10waveDomainPd:
.LFB3992:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z10waveDomainPdPd
	.cfi_endproc
.LFE3992:
	.size	_Z10waveDomainPd, .-_Z10waveDomainPd
	.globl	_Z38__device_stub__Z6multIkP7double2S0_PdiP7double2S0_Pdi
	.type	_Z38__device_stub__Z6multIkP7double2S0_PdiP7double2S0_Pdi, @function
_Z38__device_stub__Z6multIkP7double2S0_PdiP7double2S0_Pdi:
.LFB3993:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6multIkP7double2S0_Pdi(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3993:
	.size	_Z38__device_stub__Z6multIkP7double2S0_PdiP7double2S0_Pdi, .-_Z38__device_stub__Z6multIkP7double2S0_PdiP7double2S0_Pdi
	.globl	_Z6multIkP7double2S0_Pdi
	.type	_Z6multIkP7double2S0_Pdi, @function
_Z6multIkP7double2S0_Pdi:
.LFB3994:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z6multIkP7double2S0_PdiP7double2S0_Pdi
	.cfi_endproc
.LFE3994:
	.size	_Z6multIkP7double2S0_Pdi, .-_Z6multIkP7double2S0_Pdi
	.globl	_Z39__device_stub__Z12complexScaleP7double2P7double2
	.type	_Z39__device_stub__Z12complexScaleP7double2P7double2, @function
_Z39__device_stub__Z12complexScaleP7double2P7double2:
.LFB3995:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z12complexScaleP7double2(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L28:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3995:
	.size	_Z39__device_stub__Z12complexScaleP7double2P7double2, .-_Z39__device_stub__Z12complexScaleP7double2P7double2
	.globl	_Z12complexScaleP7double2
	.type	_Z12complexScaleP7double2, @function
_Z12complexScaleP7double2:
.LFB3996:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z12complexScaleP7double2P7double2
	.cfi_endproc
.LFE3996:
	.size	_Z12complexScaleP7double2, .-_Z12complexScaleP7double2
	.section	.rodata.str1.1
.LC1:
	.string	"CUFFT error: ExecD2Z failed"
.LC2:
	.string	"CUFFT error: ExecZ2D failed"
	.text
	.globl	_Z6fftderiiPdS_S_i
	.type	_Z6fftderiiPdS_S_i, @function
_Z6fftderiiPdS_S_i:
.LFB3963:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%edi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	movl	$1, %edx
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r8, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	movl	$135266304, %esi
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rdi
	call	cudaMallocManaged@PLT
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$135266304, %esi
	call	cudaMallocManaged@PLT
	movq	(%rsp), %rdx
	movq	%r15, %rsi
	movl	%r14d, %edi
	call	cufftExecD2Z@PLT
	leaq	.LC1(%rip), %rdx
	testl	%eax, %eax
	jne	.L42
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$8, %ecx
	movl	$32, %esi
	movabsq	$34359738376, %rdx
	movl	$8, 24(%rsp)
	movabsq	$137438953504, %rdi
	movq	%rdx, 16(%rsp)
	movq	%rdi, 28(%rsp)
	movl	$32, 36(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r13d, %ecx
	movq	%r12, %rdx
	call	_Z38__device_stub__Z6multIkP7double2S0_PdiP7double2S0_Pdi
.L36:
	movl	24(%rsp), %ecx
	movq	16(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	28(%rsp), %rdi
	movl	36(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	movq	8(%rsp), %rdi
	call	_Z39__device_stub__Z12complexScaleP7double2P7double2
.L37:
	movq	8(%rsp), %rsi
	movq	%rbp, %rdx
	movl	%ebx, %edi
	call	cufftExecZ2D@PLT
	testl	%eax, %eax
	je	.L38
	leaq	.LC2(%rip), %rdx
.L42:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L33
.L38:
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
.L33:
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3963:
	.size	_Z6fftderiiPdS_S_i, .-_Z6fftderiiPdS_S_i
	.section	.rodata.str1.1
.LC3:
	.string	"  Device name: %s\n"
.LC4:
	.string	"  Memory Clock Rate (KHz): %d\n"
.LC5:
	.string	"  Memory Bus Width (bits): %d\n"
.LC7:
	.string	"  Peak Memory Bandwidth (GB/s): %f\n\n"
.LC8:
	.string	"Using the GPU %s. The number of elements in the array is %2d.\n"
.LC9:
	.string	"Displaying 50 results:\n"
.LC10:
	.string	"  Index         Error     \n"
.LC11:
	.string	" -------     ----------- \n"
.LC12:
	.string	" %d             %4.4g \n"
.LC13:
	.string	"dudx"
.LC14:
	.string	"dudx_exact"
.LC15:
	.string	"u"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3964:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$1104, %rsp
	.cfi_def_cfa_offset 1136
	movq	%fs:40, %rax
	movq	%rax, 1096(%rsp)
	xorl	%eax, %eax
	leaq	64(%rsp), %rbx
	call	cudaSetDevice@PLT
	xorl	%esi, %esi
	movq	%rbx, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movq	%rbx, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC3(%rip), %rsi
	call	__printf_chk@PLT
	movl	672(%rsp), %edx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	676(%rsp), %edx
	leaq	.LC5(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	$8, %ecx
	movl	$2, %edi
	movl	676(%rsp), %eax
	cvtsi2sdl	672(%rsp), %xmm0
	leaq	.LC7(%rip), %rsi
	cltd
	idivl	%ecx
	addsd	%xmm0, %xmm0
	cvtsi2sdl	%eax, %xmm1
	movb	$1, %al
	mulsd	%xmm1, %xmm0
	divsd	.LC6(%rip), %xmm0
	call	__printf_chk@PLT
	movq	%rsp, %rdi
	movl	$106, %r8d
	movl	$256, %ecx
	movl	$256, %edx
	movl	$256, %esi
	call	cufftPlan3d@PLT
	testl	%eax, %eax
	je	.L44
	movq	stderr(%rip), %rdi
	leaq	.LC1(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	call	cudaGetLastError@PLT
.L44:
	leaq	4(%rsp), %rdi
	movl	$108, %r8d
	movl	$256, %ecx
	movl	$256, %edx
	movl	$256, %esi
	call	cufftPlan3d@PLT
	testl	%eax, %eax
	je	.L45
	movq	stderr(%rip), %rdi
	leaq	.LC1(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	call	cudaGetLastError@PLT
.L45:
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$2048, %esi
	movq	%rax, 8(%rsp)
	movl	$11, %ebp
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$135266304, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$134217728, %esi
	call	cudaMallocManaged@PLT
	leaq	32(%rsp), %rdi
	movl	$1, %edx
	movl	$134217728, %esi
	call	cudaMallocManaged@PLT
	movl	$8, 48(%rsp)
	movabsq	$34359738376, %rax
	movq	%rax, 40(%rsp)
	movabsq	$137438953504, %rax
	movq	%rax, 52(%rsp)
	movl	$32, 60(%rsp)
.L48:
	movl	48(%rsp), %ecx
	movq	40(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z32__device_stub__Z10initializePdS_PdS_
.L46:
	movl	48(%rsp), %ecx
	movq	40(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	movq	8(%rsp), %rdi
	call	_Z30__device_stub__Z10waveDomainPdPd
.L47:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %r8
	movq	16(%rsp), %rcx
	movl	$1, %r9d
	movq	8(%rsp), %rdx
	movl	4(%rsp), %esi
	movl	(%rsp), %edi
	call	_Z6fftderiiPdS_S_i
	call	cudaDeviceSynchronize@PLT
	decl	%ebp
	jne	.L48
	movq	%rbx, %rdx
	movl	$16777216, %ecx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC8(%rip), %rsi
	movl	$400, %ebp
	movl	$50, %ebx
	call	__printf_chk@PLT
	leaq	.LC9(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC11(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC12(%rip), %r12
.L49:
	movq	24(%rsp), %rax
	movl	%ebx, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	incl	%ebx
	movsd	(%rax,%rbp), %xmm0
	movq	32(%rsp), %rax
	subsd	(%rax,%rbp), %xmm0
	movb	$1, %al
	addq	$8, %rbp
	call	__printf_chk@PLT
	cmpl	$101, %ebx
	jne	.L49
	movq	24(%rsp), %rsi
	movl	$16777216, %edx
	leaq	.LC13(%rip), %rdi
	call	_Z9writeDataPKcPdi
	movq	32(%rsp), %rsi
	movl	$16777216, %edx
	leaq	.LC14(%rip), %rdi
	call	_Z9writeDataPKcPdi
	movq	16(%rsp), %rsi
	movl	$16777216, %edx
	leaq	.LC15(%rip), %rdi
	call	_Z9writeDataPKcPdi
	movl	(%rsp), %edi
	call	cufftDestroy@PLT
	movl	4(%rsp), %edi
	call	cufftDestroy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	movq	1096(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$1104, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3964:
	.size	main, .-main
	.section	.rodata.str1.1
.LC16:
	.string	"_Z12complexScaleP7double2"
.LC17:
	.string	"_Z6multIkP7double2S0_Pdi"
.LC18:
	.string	"_Z10waveDomainPd"
.LC19:
	.string	"_Z10initializePdS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3998:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC16(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12complexScaleP7double2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6multIkP7double2S0_Pdi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10waveDomainPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10initializePdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3998:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC6:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* This program is designed to take the first
 derivative of a 3 dimensional function */

// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>

// includes, project
#include <hip/hip_runtime.h>

#include <hipfft/hipfft.h>
#include <hip/hip_complex.h>
#define NX 256
#define NY 256
#define NZ 256
#define NZ2 (NZ/2 + 1)
#define NN (NX*NY*NZ)
#define L (2.0*M_PI)
#define TX 8
#define TY 8
#define TZ 8

int divUp(int a, int b) { return (a + b - 1) / b; }

void writeData(const char *name, double *data, int size)
{
	int i = 0;
	FILE *out = fopen(name, "wb");
	for (i = 0; i < size; ++i){
		fwrite( (void*)(&data[i]), sizeof(data[i]), 1, out);
	}

	fclose(out);

	return;
}

__device__
int idxClip(int idx, int idxMax){
	return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}

__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
	return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
	// Note: using column-major indexing format
}

__global__ 
void initialize(hipfftDoubleReal *f1, hipfftDoubleReal *f2)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	const int k = blockIdx.z * blockDim.z + threadIdx.z;
	if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
	const int idx = flatten(i, j, k, NX, NY, NZ);

	// Create physical vectors in temporary memory
	double x = i * (double)L / NX;
	double y = j * (double)L / NY;
	double z = k * (double)L / NZ;

	// Initialize starting array
	f1[idx] = sin(x)*cos(y)*cos(z);

	// Calculate exact derivative of starting array
	f2[idx] = cos(x)*cos(y)*cos(z);

	return;
}

__global__
void waveDomain(double *k1)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;

	if (i < NX/2)
		k1[i] = (double)i;
	else
		k1[i] = (double)i - NX;

	return;
}

__global__
void multIk(hipfftDoubleComplex *f, hipfftDoubleComplex *fIk, double *wave, const int dir)
{	// Function to multiply the function fhat by i*k
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	const int k = blockIdx.z * blockDim.z + threadIdx.z;
	if ((i >= NX) || (j >= NY) || (k >= NZ2)) return;
	const int idx = flatten(i, j, k, NX, NY, NZ2);

	// i*k*(a + bi) = -k*b + i*k*a

	if(dir == 1){ // Takes derivative in 1 direction (usually x)
		fIk[idx].x = -wave[i]*f[idx].y;
		fIk[idx].y = wave[i]*f[idx].x;
	}
	if(dir == 2){	// Takes derivative in 2 direction (usually y)
		fIk[idx].x = -wave[j]*f[idx].y;
		fIk[idx].y = wave[j]*f[idx].x;
	}
	if(dir == 3){
		fIk[idx].x = -wave[k]*f[idx].y;
		fIk[idx].y = wave[k]*f[idx].x;
	}

	return;
}

__global__
void complexScale( hipfftDoubleComplex *f)
{
	const int i = blockIdx.x * blockDim.x + threadIdx.x;
	const int j = blockIdx.y * blockDim.y + threadIdx.y;
	const int k = blockIdx.z * blockDim.z + threadIdx.z;
	if ((i >= NX) || (j >= NY) || (k >= NZ2)) return;
	const int idx = flatten(i, j, k, NX, NY, NZ2);

	f[idx].x = f[idx].x / ( (double)NN );
	f[idx].y = f[idx].y / ( (double)NN );

	return;
}

void fftder(hipfftHandle p, hipfftHandle invp, double *wave, hipfftDoubleReal *f, hipfftDoubleReal *fp, int dir)
{
	// Define loop variables
	hipfftDoubleComplex *fhat;
	hipfftDoubleComplex *fphat;

	// Allocate memory for temporary arrays
	hipMallocManaged((void**)&fhat, sizeof(hipfftDoubleComplex)*NX*NY*(NZ2) );
	hipMallocManaged((void**)&fphat, sizeof(hipfftDoubleComplex)*NX*NY*(NZ2) );

	// Take Fourier Transform of function
	if (hipfftExecD2Z(p, f, fhat ) != HIPFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecD2Z failed");
		return;	
	}

	// Launch CUDA kernel to take derivative in Fourier Space;
	const dim3 blockSize(TX, TY, TZ);
	const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
	// Multiplies fhat by I*k (definition of derivative in wavespace)
	multIk<<<gridSize, blockSize>>>(fhat, fphat, wave, dir);
	// Scales the vectors by NX*NY*NZ to account for Fourier Transform
	complexScale<<<gridSize, blockSize>>>(fphat);

	// Inverse Fourier Transform to physical space.
	if (hipfftExecZ2D(invp, fphat, fp) != HIPFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecZ2D failed");
	return;	}

	// Clear memory
	hipFree(fhat);
	hipFree(fphat);

	return;
}

int main (void)
{
	// Set CUDA to run on GTX 980 (currently device 0)
	int deviceNum = 0;

	hipSetDevice(deviceNum);

    hipDeviceProp_t prop;
    hipGetDeviceProperties(&prop, deviceNum);
    printf("  Device name: %s\n", prop.name);
    printf("  Memory Clock Rate (KHz): %d\n",
           prop.memoryClockRate);
    printf("  Memory Bus Width (bits): %d\n",
           prop.memoryBusWidth);
    printf("  Peak Memory Bandwidth (GB/s): %f\n\n",
 			2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);

	//Create plan for cuFFT
	hipfftHandle plan;
	hipfftHandle invplan;

	if (hipfftPlan3d(&plan, NX, NY, NZ, HIPFFT_D2Z) != HIPFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecD2Z failed");
		hipError_t err = hipGetLastError(); }

	if (hipfftPlan3d(&invplan, NX, NY, NZ, HIPFFT_Z2D)  != HIPFFT_SUCCESS){
		fprintf(stderr, "CUFFT error: ExecD2Z failed");
		hipError_t err = hipGetLastError(); }

	// Declare variables
	int i, j, k, idx;
	double *kx = 0;
	hipfftDoubleReal *u;
	hipfftDoubleReal *dudx;
	hipfftDoubleReal *dudx_exact;

	// Allocate memory for arrays
	hipMallocManaged(&kx, NX*sizeof(double));
	hipMallocManaged(&u, sizeof(hipfftDoubleComplex)*NX*NY*NZ2 );
	hipMallocManaged(&dudx, sizeof(hipfftDoubleReal)*NN );
	hipMallocManaged(&dudx_exact, sizeof(hipfftDoubleReal)*NN );

	// Launch CUDA kernel to initialize velocity field
	const dim3 blockSize(TX, TY, TZ);
	const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));

	int count;
	for (count = 0; count < 11; ++count){

	initialize<<<gridSize, blockSize>>>(u, dudx_exact);
	
	// Setup wavespace domain
	waveDomain<<<gridSize, blockSize>>>(kx);

	hipDeviceSynchronize();		// Added this line to prevent compiler error: "Bus error (core dumped)".

	// Take derivative using Fourier Transforms
	fftder(plan, invplan, kx, u, dudx, 1);

	// takeFFT(plan, invplan, u, u_fft);
	hipDeviceSynchronize();

	}

	printf("Using the GPU %s. The number of elements in the array is %2d.\n",prop.name,NX*NY*NZ);
	printf("Displaying 50 results:\n");
	printf("  Index         Error     \n");
	printf(" -------     ----------- \n");
	for (i = 0; i < 1; ++i){
		for (j = 0; j < 1; ++j){
			for (k = 50; k < 101; ++k){
				idx = k + NZ*j + NZ*NY*i;
				printf(" %d             %4.4g \n",idx, dudx[idx]-dudx_exact[idx]);
			}
		}
	}

	// Write output data to file (for additional analysis if desired)
	writeData("dudx",dudx, NX*NY*NZ);
	writeData("dudx_exact", dudx_exact, NX*NY*NZ);
	writeData("u", u, NX*NY*NZ);

	//Clean variables
	hipfftDestroy(plan);
	hipfftDestroy(invplan);

	hipFree(u);
	hipFree(dudx);
	hipFree(dudx_exact);
	hipFree(kx);

	hipDeviceReset();

	return 0;
}

	.text
	.file	"cuFFT_Test_3D.hip"
	.globl	_Z5divUpii                      # -- Begin function _Z5divUpii
	.type	_Z5divUpii,@function
_Z5divUpii:                             # @_Z5divUpii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	leal	(%rdi,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
	retq
.Lfunc_end0:
	.size	_Z5divUpii, .Lfunc_end0-_Z5divUpii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9writeDataPKcPdi              # -- Begin function _Z9writeDataPKcPdi
	.type	_Z9writeDataPKcPdi,@function
_Z9writeDataPKcPdi:                     # @_Z9writeDataPKcPdi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebp
	movq	%rsi, %rbx
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %r14
	testl	%ebp, %ebp
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r15d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$8, %esi
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%r14, %rcx
	callq	fwrite
	addq	$8, %rbx
	decq	%r15
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movq	%r14, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end1:
	.size	_Z9writeDataPKcPdi, .Lfunc_end1-_Z9writeDataPKcPdi
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__initializePdS_ # -- Begin function _Z25__device_stub__initializePdS_
	.type	_Z25__device_stub__initializePdS_,@function
_Z25__device_stub__initializePdS_:      # @_Z25__device_stub__initializePdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10initializePdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__initializePdS_, .Lfunc_end2-_Z25__device_stub__initializePdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__waveDomainPd # -- Begin function _Z25__device_stub__waveDomainPd
	.type	_Z25__device_stub__waveDomainPd,@function
_Z25__device_stub__waveDomainPd:        # @_Z25__device_stub__waveDomainPd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10waveDomainPd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z25__device_stub__waveDomainPd, .Lfunc_end3-_Z25__device_stub__waveDomainPd
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi # -- Begin function _Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.type	_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi,@function
_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi: # @_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi, .Lfunc_end4-_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE # -- Begin function _Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE
	.type	_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE,@function
_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE: # @_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12complexScaleP15HIP_vector_typeIdLj2EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE, .Lfunc_end5-_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z6fftderP14hipfftHandle_tS0_PdS1_S1_i # -- Begin function _Z6fftderP14hipfftHandle_tS0_PdS1_S1_i
	.type	_Z6fftderP14hipfftHandle_tS0_PdS1_S1_i,@function
_Z6fftderP14hipfftHandle_tS0_PdS1_S1_i: # @_Z6fftderP14hipfftHandle_tS0_PdS1_S1_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, 12(%rsp)                  # 4-byte Spill
	movq	%r8, %rbx
	movq	%rcx, %r12
	movq	%rdx, %r15
	movq	%rsi, %r14
	movq	%rdi, %r13
	leaq	16(%rsp), %rbp
	movl	$135266304, %esi                # imm = 0x8100000
	movq	%rbp, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movl	$135266304, %esi                # imm = 0x8100000
	movl	$1, %edx
	callq	hipMallocManaged
	movq	(%rbp), %rdx
	movq	%r13, %rdi
	movq	%r12, %rsi
	callq	hipfftExecD2Z
	testl	%eax, %eax
	jne	.LBB6_1
# %bb.3:
	movabsq	$137438953504, %r13             # imm = 0x2000000020
	movabsq	$34359738376, %r12              # imm = 0x800000008
	movq	%r13, %rdi
	movl	$32, %esi
	movq	%r12, %rdx
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_5
# %bb.4:
	movq	16(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	%r15, %rdx
	movl	12(%rsp), %ecx                  # 4-byte Reload
	callq	_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi
.LBB6_5:
	movq	%r13, %rdi
	movl	$32, %esi
	movq	%r12, %rdx
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB6_7
# %bb.6:
	movq	(%rsp), %rdi
	callq	_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE
.LBB6_7:
	movq	(%rsp), %rsi
	movq	%r14, %rdi
	movq	%rbx, %rdx
	callq	hipfftExecZ2D
	testl	%eax, %eax
	jne	.LBB6_8
# %bb.9:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
.LBB6_10:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB6_1:
	.cfi_def_cfa_offset 80
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	jmp	.LBB6_2
.LBB6_8:
	movq	stderr(%rip), %rcx
	movl	$.L.str.2, %edi
.LBB6_2:
	movl	$27, %esi
	movl	$1, %edx
	callq	fwrite
	jmp	.LBB6_10
.Lfunc_end6:
	.size	_Z6fftderP14hipfftHandle_tS0_PdS1_S1_i, .Lfunc_end6-_Z6fftderP14hipfftHandle_tS0_PdS1_S1_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI7_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$1520, %rsp                     # imm = 0x5F0
	.cfi_def_cfa_offset 1552
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	xorl	%edi, %edi
	callq	hipSetDevice
	leaq	48(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	movl	$.L.str.3, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	608(%rbx), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movl	612(%rbx), %esi
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
	cvtsi2sdl	608(%rbx), %xmm1
	movl	612(%rbx), %eax
	leal	7(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$3, %ecx
	cvtsi2sd	%ecx, %xmm0
	addsd	%xmm1, %xmm1
	mulsd	%xmm1, %xmm0
	divsd	.LCPI7_0(%rip), %xmm0
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	leaq	40(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %edx                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$106, %r8d
	callq	hipfftPlan3d
	testl	%eax, %eax
	jne	.LBB7_1
.LBB7_2:
	leaq	32(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	movl	$256, %edx                      # imm = 0x100
	movl	$256, %ecx                      # imm = 0x100
	movl	$108, %r8d
	callq	hipfftPlan3d
	testl	%eax, %eax
	jne	.LBB7_3
.LBB7_4:
	movabsq	$137438953504, %rbx             # imm = 0x2000000020
	movabsq	$34359738376, %r14              # imm = 0x800000008
	leaq	24(%rsp), %rdi
	movq	$0, (%rdi)
	movl	$2048, %esi                     # imm = 0x800
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %rdi
	movl	$135266304, %esi                # imm = 0x8100000
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$134217728, %esi                # imm = 0x8000000
	movl	$1, %edx
	callq	hipMallocManaged
	movq	%rsp, %rdi
	movl	$134217728, %esi                # imm = 0x8000000
	movl	$1, %edx
	callq	hipMallocManaged
	movl	$11, %ebp
.LBB7_5:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	$32, %esi
	movq	%r14, %rdx
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_7
# %bb.6:                                #   in Loop: Header=BB7_5 Depth=1
	movq	16(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z25__device_stub__initializePdS_
.LBB7_7:                                #   in Loop: Header=BB7_5 Depth=1
	movq	%rbx, %rdi
	movl	$32, %esi
	movq	%r14, %rdx
	movl	$8, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_9
# %bb.8:                                #   in Loop: Header=BB7_5 Depth=1
	movq	24(%rsp), %rdi
	callq	_Z25__device_stub__waveDomainPd
.LBB7_9:                                #   in Loop: Header=BB7_5 Depth=1
	callq	hipDeviceSynchronize
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movl	$1, %r9d
	callq	_Z6fftderP14hipfftHandle_tS0_PdS1_S1_i
	callq	hipDeviceSynchronize
	decl	%ebp
	jne	.LBB7_5
# %bb.10:                               # %.critedge
	leaq	48(%rsp), %rsi
	movl	$.L.str.7, %edi
	movl	$16777216, %edx                 # imm = 0x1000000
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$50, %ebx
.LBB7_11:                               # =>This Inner Loop Header: Depth=1
	movq	8(%rsp), %rax
	movsd	(%rax,%rbx,8), %xmm0            # xmm0 = mem[0],zero
	movq	(%rsp), %rax
	subsd	(%rax,%rbx,8), %xmm0
	movl	$.L.str.11, %edi
	movl	%ebx, %esi
	movb	$1, %al
	callq	printf
	incq	%rbx
	cmpq	$101, %rbx
	jne	.LBB7_11
# %bb.12:
	movq	8(%rsp), %rsi
	movl	$.L.str.12, %edi
	movl	$16777216, %edx                 # imm = 0x1000000
	callq	_Z9writeDataPKcPdi
	movq	(%rsp), %rsi
	movl	$.L.str.13, %edi
	movl	$16777216, %edx                 # imm = 0x1000000
	callq	_Z9writeDataPKcPdi
	movq	16(%rsp), %rsi
	movl	$.L.str.14, %edi
	movl	$16777216, %edx                 # imm = 0x1000000
	callq	_Z9writeDataPKcPdi
	movq	40(%rsp), %rdi
	callq	hipfftDestroy
	movq	32(%rsp), %rdi
	callq	hipfftDestroy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$1520, %rsp                     # imm = 0x5F0
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_1:
	.cfi_def_cfa_offset 1552
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$27, %esi
	movl	$1, %edx
	callq	fwrite
	callq	hipGetLastError
	jmp	.LBB7_2
.LBB7_3:
	movq	stderr(%rip), %rcx
	movl	$.L.str.1, %edi
	movl	$27, %esi
	movl	$1, %edx
	callq	fwrite
	callq	hipGetLastError
	jmp	.LBB7_4
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10initializePdS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10waveDomainPd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12complexScaleP15HIP_vector_typeIdLj2EE, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"wb"
	.size	.L.str, 3

	.type	_Z10initializePdS_,@object      # @_Z10initializePdS_
	.section	.rodata,"a",@progbits
	.globl	_Z10initializePdS_
	.p2align	3, 0x0
_Z10initializePdS_:
	.quad	_Z25__device_stub__initializePdS_
	.size	_Z10initializePdS_, 8

	.type	_Z10waveDomainPd,@object        # @_Z10waveDomainPd
	.globl	_Z10waveDomainPd
	.p2align	3, 0x0
_Z10waveDomainPd:
	.quad	_Z25__device_stub__waveDomainPd
	.size	_Z10waveDomainPd, 8

	.type	_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi,@object # @_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.globl	_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.p2align	3, 0x0
_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi:
	.quad	_Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.size	_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi, 8

	.type	_Z12complexScaleP15HIP_vector_typeIdLj2EE,@object # @_Z12complexScaleP15HIP_vector_typeIdLj2EE
	.globl	_Z12complexScaleP15HIP_vector_typeIdLj2EE
	.p2align	3, 0x0
_Z12complexScaleP15HIP_vector_typeIdLj2EE:
	.quad	_Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE
	.size	_Z12complexScaleP15HIP_vector_typeIdLj2EE, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"CUFFT error: ExecD2Z failed"
	.size	.L.str.1, 28

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"CUFFT error: ExecZ2D failed"
	.size	.L.str.2, 28

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"  Device name: %s\n"
	.size	.L.str.3, 19

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"  Memory Clock Rate (KHz): %d\n"
	.size	.L.str.4, 31

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"  Memory Bus Width (bits): %d\n"
	.size	.L.str.5, 31

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"  Peak Memory Bandwidth (GB/s): %f\n\n"
	.size	.L.str.6, 37

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Using the GPU %s. The number of elements in the array is %2d.\n"
	.size	.L.str.7, 63

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	" %d             %4.4g \n"
	.size	.L.str.11, 24

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"dudx"
	.size	.L.str.12, 5

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"dudx_exact"
	.size	.L.str.13, 11

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"u"
	.size	.L.str.14, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10initializePdS_"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10waveDomainPd"
	.size	.L__unnamed_2, 17

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi"
	.size	.L__unnamed_3, 41

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z12complexScaleP15HIP_vector_typeIdLj2EE"
	.size	.L__unnamed_4, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Displaying 50 results:"
	.size	.Lstr, 23

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"  Index         Error     "
	.size	.Lstr.1, 27

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	" -------     ----------- "
	.size	.Lstr.2, 26

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__initializePdS_
	.addrsig_sym _Z25__device_stub__waveDomainPd
	.addrsig_sym _Z21__device_stub__multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.addrsig_sym _Z27__device_stub__complexScaleP15HIP_vector_typeIdLj2EE
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10initializePdS_
	.addrsig_sym _Z10waveDomainPd
	.addrsig_sym _Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.addrsig_sym _Z12complexScaleP15HIP_vector_typeIdLj2EE
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10initializePdS_      ; -- Begin function _Z10initializePdS_
	.globl	_Z10initializePdS_
	.p2align	8
	.type	_Z10initializePdS_,@function
_Z10initializePdS_:                     ; @_Z10initializePdS_
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x1c
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s3, s3, 0xffff
	v_mad_u64_u32 v[30:31], null, s13, s2, v[1:2]
	v_mad_u64_u32 v[31:32], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[32:33], null, s15, s3, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max3_i32 v0, v30, v31, v32
	v_cmpx_gt_i32_e32 0x100, v0
	s_cbranch_execz .LBB0_26
; %bb.1:
	v_cvt_f64_i32_e32 v[0:1], v30
	s_mov_b32 s5, 0x401921fb
	s_mov_b32 s4, 0x54442d18
                                        ; implicit-def: $vgpr48
                                        ; implicit-def: $vgpr33_vgpr34
                                        ; implicit-def: $vgpr35_vgpr36
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[0:1], v[0:1], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[6:7], v[0:1], -8
	v_cmp_ngt_f64_e64 s3, 0x41d00000, |v[6:7]|
	v_trig_preop_f64 v[18:19], |v[6:7]|, 0
	v_trig_preop_f64 v[10:11], |v[6:7]|, 1
	v_ldexp_f64 v[22:23], |v[6:7]|, 0xffffff80
	v_trig_preop_f64 v[0:1], |v[6:7]|, 2
	v_and_b32_e32 v45, 0x7fffffff, v7
	s_and_saveexec_b32 s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s2
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[6:7]|
	v_mov_b32_e32 v33, 0
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v3, v45, v23 :: v_dual_cndmask_b32 v2, v6, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[4:5], v[18:19], v[2:3]
	v_mul_f64 v[8:9], v[10:11], v[2:3]
	v_mul_f64 v[26:27], v[0:1], v[2:3]
	v_fma_f64 v[12:13], v[18:19], v[2:3], -v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[10:11], v[2:3], -v[8:9]
	v_fma_f64 v[2:3], v[0:1], v[2:3], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[8:9], v[12:13]
	v_add_f64 v[16:17], v[14:15], -v[8:9]
	v_add_f64 v[24:25], v[4:5], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[14:15], -v[16:17]
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_ldexp_f64 v[16:17], v[24:25], -2
	v_add_f64 v[4:5], v[24:25], -v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[8:9], v[8:9], -v[20:21]
	v_add_f64 v[20:21], v[26:27], v[28:29]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[16:17]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[4:5], v[14:15], -v[4:5]
	v_add_f64 v[8:9], v[12:13], v[8:9]
	v_fract_f64_e32 v[12:13], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[20:21], v[8:9]
	v_dual_cndmask_b32 v13, 0, v13 :: v_dual_cndmask_b32 v12, 0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[12:13], v[12:13], 2
	v_add_f64 v[16:17], v[4:5], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[16:17], v[12:13]
	v_add_f64 v[4:5], v[16:17], -v[4:5]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[24:25]
	v_add_f64 v[24:25], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[14:15], -v[4:5]
	v_cndmask_b32_e64 v34, 0, 0x40100000, vcc_lo
	v_add_f64 v[38:39], v[20:21], -v[24:25]
	v_add_f64 v[24:25], v[28:29], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], v[33:34]
	v_add_f64 v[34:35], v[14:15], -v[20:21]
	v_add_f64 v[28:29], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[16:17], v[12:13]
	v_add_f64 v[40:41], v[14:15], -v[34:35]
	v_add_f64 v[8:9], v[8:9], -v[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_cvt_i32_f64_e32 v36, v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], -v[40:41]
	v_cvt_f64_i32_e32 v[34:35], v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[20:21]
	v_add_f64 v[12:13], v[12:13], -v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[24:25], v[8:9]
	v_add_f64 v[20:21], v[16:17], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[8:9], v[20:21], -v[12:13]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	v_add_f64 v[4:5], v[16:17], -v[8:9]
	v_cndmask_b32_e64 v34, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v48, s2, 0, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_add_f64 v[4:5], v[20:21], -v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[4:5], v[2:3]
	v_mul_f64 v[12:13], v[8:9], s[4:5]
	v_add_f64 v[4:5], v[8:9], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[8:9], s[4:5], -v[12:13]
	v_add_f64 v[2:3], v[2:3], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[8:9], s[8:9], v[14:15]
	v_fma_f64 v[2:3], v[2:3], s[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[33:34], v[12:13], v[2:3]
	v_add_f64 v[4:5], v[33:34], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[35:36], v[2:3], -v[4:5]
.LBB0_3:                                ; %Flow65
	s_and_not1_saveexec_b32 s2, s6
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[2:3], |v[6:7]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[2:3], v[2:3]
	v_fma_f64 v[4:5], v[2:3], s[4:5], |v[6:7]|
	v_mul_f64 v[8:9], v[2:3], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v48, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[2:3], s[6:7], v[4:5]
	v_add_f64 v[12:13], v[4:5], v[8:9]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[12:13]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_fma_f64 v[8:9], v[2:3], s[6:7], v[8:9]
	v_add_f64 v[4:5], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[8:9]
	v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[33:34], v[14:15], v[4:5]
	v_add_f64 v[8:9], v[33:34], -v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[35:36], v[4:5], -v[8:9]
.LBB0_5:                                ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_cvt_f64_i32_e32 v[2:3], v31
	s_mov_b32 s5, 0x401921fb
	s_mov_b32 s4, 0x54442d18
                                        ; implicit-def: $vgpr49
                                        ; implicit-def: $vgpr37_vgpr38
                                        ; implicit-def: $vgpr39_vgpr40
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[2:3], v[2:3], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[8:9], v[2:3], -8
	v_cmp_ngt_f64_e64 s33, 0x41d00000, |v[8:9]|
	v_trig_preop_f64 v[20:21], |v[8:9]|, 0
	v_trig_preop_f64 v[14:15], |v[8:9]|, 1
	v_ldexp_f64 v[24:25], |v[8:9]|, 0xffffff80
	v_trig_preop_f64 v[2:3], |v[8:9]|, 2
	v_and_b32_e32 v46, 0x7fffffff, v9
	s_and_saveexec_b32 s2, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s2
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[8:9]|
	v_mov_b32_e32 v51, 0
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v5, v46, v25 :: v_dual_cndmask_b32 v4, v8, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[12:13], v[20:21], v[4:5]
	v_mul_f64 v[16:17], v[14:15], v[4:5]
	v_mul_f64 v[43:44], v[2:3], v[4:5]
	v_fma_f64 v[26:27], v[20:21], v[4:5], -v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[49:50], v[14:15], v[4:5], -v[16:17]
	v_fma_f64 v[4:5], v[2:3], v[4:5], -v[43:44]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[16:17], v[26:27]
	v_add_f64 v[37:38], v[28:29], -v[16:17]
	v_add_f64 v[41:42], v[12:13], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[39:40], v[28:29], -v[37:38]
	v_add_f64 v[26:27], v[26:27], -v[37:38]
	v_ldexp_f64 v[37:38], v[41:42], -2
	v_add_f64 v[12:13], v[41:42], -v[12:13]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[16:17], -v[39:40]
	v_add_f64 v[39:40], v[43:44], v[49:50]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[37:38]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[28:29], -v[12:13]
	v_add_f64 v[16:17], v[26:27], v[16:17]
	v_fract_f64_e32 v[26:27], v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[39:40], v[16:17]
	v_dual_cndmask_b32 v27, 0, v27 :: v_dual_cndmask_b32 v26, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[26:27], v[26:27], 2
	v_add_f64 v[37:38], v[12:13], v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[37:38], v[26:27]
	v_add_f64 v[12:13], v[37:38], -v[12:13]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[41:42]
	v_add_f64 v[41:42], v[39:40], -v[43:44]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[28:29], -v[12:13]
	v_cndmask_b32_e64 v52, 0, 0x40100000, vcc_lo
	v_add_f64 v[56:57], v[39:40], -v[41:42]
	v_add_f64 v[41:42], v[49:50], -v[41:42]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[26:27], v[51:52]
	v_add_f64 v[52:53], v[28:29], -v[39:40]
	v_add_f64 v[49:50], v[43:44], -v[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[54:55], v[37:38], v[26:27]
	v_add_f64 v[58:59], v[28:29], -v[52:53]
	v_add_f64 v[16:17], v[16:17], -v[52:53]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[41:42], v[41:42], v[49:50]
	v_cvt_i32_f64_e32 v47, v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[39:40], v[39:40], -v[58:59]
	v_cvt_f64_i32_e32 v[52:53], v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[39:40]
	v_add_f64 v[26:27], v[26:27], -v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[41:42], v[16:17]
	v_add_f64 v[39:40], v[37:38], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[16:17]
	v_add_f64 v[16:17], v[39:40], -v[26:27]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[12:13], v[4:5]
	v_add_f64 v[12:13], v[37:38], -v[16:17]
	v_cndmask_b32_e64 v52, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v49, s2, 0, v47, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[12:13]
	v_add_f64 v[12:13], v[39:40], -v[51:52]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[12:13], v[4:5]
	v_mul_f64 v[26:27], v[16:17], s[4:5]
	v_add_f64 v[12:13], v[16:17], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[28:29], v[16:17], s[4:5], -v[26:27]
	v_add_f64 v[4:5], v[4:5], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[16:17], s[8:9], v[28:29]
	v_fma_f64 v[4:5], v[4:5], s[4:5], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[37:38], v[26:27], v[4:5]
	v_add_f64 v[12:13], v[37:38], -v[26:27]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[39:40], v[4:5], -v[12:13]
.LBB0_7:                                ; %Flow64
	s_and_not1_saveexec_b32 s2, s6
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[4:5], |v[8:9]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[4:5], v[4:5]
	v_fma_f64 v[12:13], v[4:5], s[4:5], |v[8:9]|
	v_mul_f64 v[16:17], v[4:5], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v49, v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[4:5], s[6:7], v[12:13]
	v_add_f64 v[26:27], v[12:13], v[16:17]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[26:27]
	v_add_f64 v[26:27], v[26:27], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_fma_f64 v[16:17], v[4:5], s[6:7], v[16:17]
	v_add_f64 v[12:13], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[16:17]
	v_fma_f64 v[12:13], v[4:5], s[4:5], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[37:38], v[28:29], v[12:13]
	v_add_f64 v[16:17], v[37:38], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[39:40], v[12:13], -v[16:17]
.LBB0_9:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_cvt_f64_i32_e32 v[4:5], v32
	s_mov_b32 s5, 0x401921fb
	s_mov_b32 s4, 0x54442d18
                                        ; implicit-def: $vgpr50
                                        ; implicit-def: $vgpr41_vgpr42
                                        ; implicit-def: $vgpr43_vgpr44
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[4:5], v[4:5], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[12:13], v[4:5], -8
	v_cmp_ngt_f64_e64 s34, 0x41d00000, |v[12:13]|
	v_trig_preop_f64 v[26:27], |v[12:13]|, 0
	v_trig_preop_f64 v[16:17], |v[12:13]|, 1
	v_ldexp_f64 v[28:29], |v[12:13]|, 0xffffff80
	v_trig_preop_f64 v[4:5], |v[12:13]|, 2
	v_and_b32_e32 v47, 0x7fffffff, v13
	s_and_saveexec_b32 s2, s34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s2
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[12:13]|
	v_mov_b32_e32 v66, 0
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v42, v47, v29 :: v_dual_cndmask_b32 v41, v12, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[43:44], v[26:27], v[41:42]
	v_mul_f64 v[50:51], v[16:17], v[41:42]
	v_mul_f64 v[62:63], v[4:5], v[41:42]
	v_fma_f64 v[52:53], v[26:27], v[41:42], -v[43:44]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[64:65], v[16:17], v[41:42], -v[50:51]
	v_fma_f64 v[41:42], v[4:5], v[41:42], -v[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[54:55], v[50:51], v[52:53]
	v_add_f64 v[56:57], v[54:55], -v[50:51]
	v_add_f64 v[60:61], v[43:44], v[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[58:59], v[54:55], -v[56:57]
	v_add_f64 v[52:53], v[52:53], -v[56:57]
	v_ldexp_f64 v[56:57], v[60:61], -2
	v_add_f64 v[43:44], v[60:61], -v[43:44]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[50:51], v[50:51], -v[58:59]
	v_add_f64 v[58:59], v[62:63], v[64:65]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[56:57]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[43:44], v[54:55], -v[43:44]
	v_add_f64 v[50:51], v[52:53], v[50:51]
	v_fract_f64_e32 v[52:53], v[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[54:55], v[58:59], v[50:51]
	v_dual_cndmask_b32 v53, 0, v53 :: v_dual_cndmask_b32 v52, 0, v52
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[52:53], v[52:53], 2
	v_add_f64 v[56:57], v[43:44], v[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[60:61], v[56:57], v[52:53]
	v_add_f64 v[43:44], v[56:57], -v[43:44]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[60:61]
	v_add_f64 v[60:61], v[58:59], -v[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[43:44], v[54:55], -v[43:44]
	v_cndmask_b32_e64 v67, 0, 0x40100000, vcc_lo
	v_add_f64 v[71:72], v[58:59], -v[60:61]
	v_add_f64 v[60:61], v[64:65], -v[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[52:53], v[52:53], v[66:67]
	v_add_f64 v[67:68], v[54:55], -v[58:59]
	v_add_f64 v[64:65], v[62:63], -v[71:72]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[69:70], v[56:57], v[52:53]
	v_add_f64 v[73:74], v[54:55], -v[67:68]
	v_add_f64 v[50:51], v[50:51], -v[67:68]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[60:61], v[60:61], v[64:65]
	v_cvt_i32_f64_e32 v69, v[69:70]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[58:59], v[58:59], -v[73:74]
	v_cvt_f64_i32_e32 v[67:68], v69
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[50:51], v[50:51], v[58:59]
	v_add_f64 v[52:53], v[52:53], -v[67:68]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[50:51], v[60:61], v[50:51]
	v_add_f64 v[58:59], v[56:57], v[52:53]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[41:42], v[50:51]
	v_add_f64 v[50:51], v[58:59], -v[52:53]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[41:42], v[43:44], v[41:42]
	v_add_f64 v[43:44], v[56:57], -v[50:51]
	v_cndmask_b32_e64 v67, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v50, s2, 0, v69, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[41:42], v[41:42], v[43:44]
	v_add_f64 v[43:44], v[58:59], -v[66:67]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[51:52], v[43:44], v[41:42]
	v_mul_f64 v[53:54], v[51:52], s[4:5]
	v_add_f64 v[43:44], v[51:52], -v[43:44]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[55:56], v[51:52], s[4:5], -v[53:54]
	v_add_f64 v[41:42], v[41:42], -v[43:44]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[43:44], v[51:52], s[8:9], v[55:56]
	v_fma_f64 v[43:44], v[41:42], s[4:5], v[43:44]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[41:42], v[53:54], v[43:44]
	v_add_f64 v[51:52], v[41:42], -v[53:54]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[43:44], v[43:44], -v[51:52]
.LBB0_11:                               ; %Flow63
	s_and_not1_saveexec_b32 s2, s6
	s_cbranch_execz .LBB0_13
; %bb.12:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[41:42], |v[12:13]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[50:51], v[41:42]
	v_fma_f64 v[41:42], v[50:51], s[4:5], |v[12:13]|
	v_mul_f64 v[43:44], v[50:51], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[54:55], v[50:51], s[6:7], v[41:42]
	v_add_f64 v[52:53], v[41:42], v[43:44]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[41:42], v[41:42], -v[52:53]
	v_add_f64 v[52:53], v[52:53], -v[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[41:42], v[43:44]
	v_fma_f64 v[43:44], v[50:51], s[6:7], v[43:44]
	v_add_f64 v[41:42], v[52:53], v[41:42]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[41:42], v[41:42], -v[43:44]
	v_fma_f64 v[43:44], v[50:51], s[4:5], v[41:42]
	v_cvt_i32_f64_e32 v50, v[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[41:42], v[54:55], v[43:44]
	v_add_f64 v[52:53], v[41:42], -v[54:55]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[43:44], v[43:44], -v[52:53]
.LBB0_13:                               ; %_ZL3cosd.exit35
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_f64 v[51:52], v[33:34], v[33:34]
	s_mov_b32 s20, 0x9037ab78
	s_mov_b32 s22, 0x46cc5e42
	s_mov_b32 s21, 0x3e21eeb6
	s_mov_b32 s23, 0xbda907db
	s_mov_b32 s24, 0xa17f65f6
	s_mov_b32 s25, 0xbe927e4f
	s_mov_b32 s26, 0x19f4ec90
	s_mov_b32 s27, 0x3efa01a0
	s_mov_b32 s28, 0x16c16967
	s_mov_b32 s29, 0xbf56c16c
	s_mov_b32 s30, 0x55555555
	s_mov_b32 s31, 0x3fa55555
	s_mov_b32 s16, 0xb42fdfa7
	s_mov_b32 s18, 0xf9a43bb8
	s_mov_b32 s17, 0xbe5ae600
	s_mov_b32 s19, 0x3de5e0b2
	s_mov_b32 s14, 0x796cde01
	s_mov_b32 s15, 0x3ec71de3
	s_mov_b32 s10, 0x19e83e5c
	s_mov_b32 s11, 0xbf2a01a0
	s_mov_b32 s12, 0x11110bb3
	s_mov_b32 s13, 0x3f811111
	s_mov_b32 s9, 0xbfc55555
	s_mov_b32 s8, s30
	v_max_i32_e32 v30, 0, v30
	v_max_i32_e32 v31, 0, v31
	v_max_i32_e32 v32, 0, v32
	s_load_b128 s[4:7], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v30, 16, v30
	v_lshl_or_b32 v30, v31, 8, v30
	v_mul_f64 v[53:54], v[51:52], 0.5
	v_fma_f64 v[59:60], v[51:52], s[22:23], s[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[55:56], -v[53:54], 1.0
	v_fma_f64 v[59:60], v[51:52], v[59:60], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[57:58], -v[55:56], 1.0
	v_fma_f64 v[59:60], v[51:52], v[59:60], s[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[53:54], v[57:58], -v[53:54]
	v_fma_f64 v[59:60], v[51:52], v[59:60], s[28:29]
	v_mul_f64 v[57:58], v[51:52], v[51:52]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[53:54], v[33:34], -v[35:36], v[53:54]
	v_fma_f64 v[59:60], v[51:52], v[59:60], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[53:54], v[57:58], v[59:60], v[53:54]
	v_mul_f64 v[57:58], v[33:34], -v[51:52]
	v_mul_f64 v[59:60], v[35:36], 0.5
	v_add_f64 v[53:54], v[55:56], v[53:54]
	v_fma_f64 v[55:56], v[51:52], s[18:19], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[55:56], v[51:52], v[55:56], s[14:15]
	v_fma_f64 v[55:56], v[51:52], v[55:56], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[55:56], v[51:52], v[55:56], s[12:13]
	v_fma_f64 v[55:56], v[57:58], v[55:56], v[59:60]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[51:52], v[55:56], -v[35:36]
	v_fma_f64 v[35:36], v[57:58], s[8:9], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[33:34], v[33:34], -v[35:36]
	v_and_b32_e32 v35, 1, v48
	v_cmp_eq_u32_e32 vcc_lo, 0, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v34, v54, v34 :: v_dual_cndmask_b32 v33, v53, v33
	v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x1f8
	v_lshlrev_b32_e32 v35, 30, v48
	v_xor_b32_e32 v35, v35, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v35, 0x80000000, v35
	v_xor_b32_e32 v34, v34, v35
	v_mul_f64 v[35:36], v[37:38], v[37:38]
	v_cndmask_b32_e32 v33, 0, v33, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v34, 0x7ff80000, v34, vcc_lo
	v_mul_f64 v[51:52], v[35:36], 0.5
	v_fma_f64 v[57:58], v[35:36], s[22:23], s[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[53:54], -v[51:52], 1.0
	v_fma_f64 v[57:58], v[35:36], v[57:58], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[55:56], -v[53:54], 1.0
	v_fma_f64 v[57:58], v[35:36], v[57:58], s[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[51:52], v[55:56], -v[51:52]
	v_fma_f64 v[57:58], v[35:36], v[57:58], s[28:29]
	v_mul_f64 v[55:56], v[35:36], v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[51:52], v[37:38], -v[39:40], v[51:52]
	v_fma_f64 v[57:58], v[35:36], v[57:58], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[51:52], v[55:56], v[57:58], v[51:52]
	v_mul_f64 v[55:56], v[37:38], -v[35:36]
	v_mul_f64 v[57:58], v[39:40], 0.5
	v_add_f64 v[51:52], v[53:54], v[51:52]
	v_fma_f64 v[53:54], v[35:36], s[18:19], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[53:54], v[35:36], v[53:54], s[14:15]
	v_fma_f64 v[53:54], v[35:36], v[53:54], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[53:54], v[35:36], v[53:54], s[12:13]
	v_fma_f64 v[53:54], v[55:56], v[53:54], v[57:58]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[35:36], v[35:36], v[53:54], -v[39:40]
	v_fma_f64 v[35:36], v[55:56], s[8:9], v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[35:36], v[37:38], -v[35:36]
	v_and_b32_e32 v37, 1, v49
	v_cmp_eq_u32_e64 s2, 0, v37
	v_lshlrev_b32_e32 v37, 30, v49
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_and_b32_e32 v37, 0x80000000, v37
	v_xor_b32_e32 v36, 0x80000000, v36
	v_cndmask_b32_e64 v35, v35, v51, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v36, v36, v52, s2
	v_cmp_class_f64_e64 s2, v[8:9], 0x1f8
	v_xor_b32_e32 v36, v36, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v35, 0, v35, s2
	v_cndmask_b32_e64 v36, 0x7ff80000, v36, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f64 v[33:34], v[33:34], v[35:36]
	v_add_nc_u32_e32 v35, v30, v32
	v_and_b32_e32 v32, 1, v50
	v_mul_f64 v[30:31], v[41:42], v[41:42]
	v_cmp_eq_u32_e64 s0, 0, v32
	v_lshlrev_b32_e32 v32, 30, v50
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v32, 0x80000000, v32
	v_mul_f64 v[36:37], v[30:31], 0.5
	v_fma_f64 v[51:52], v[30:31], s[22:23], s[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], -v[36:37], 1.0
	v_fma_f64 v[51:52], v[30:31], v[51:52], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[48:49], -v[38:39], 1.0
	v_fma_f64 v[51:52], v[30:31], v[51:52], s[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[48:49], -v[36:37]
	v_fma_f64 v[51:52], v[30:31], v[51:52], s[28:29]
	v_mul_f64 v[48:49], v[30:31], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[41:42], -v[43:44], v[36:37]
	v_fma_f64 v[51:52], v[30:31], v[51:52], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[48:49], v[51:52], v[36:37]
	v_mul_f64 v[48:49], v[41:42], -v[30:31]
	v_mul_f64 v[51:52], v[43:44], 0.5
	v_add_f64 v[36:37], v[38:39], v[36:37]
	v_fma_f64 v[38:39], v[30:31], s[18:19], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[30:31], v[38:39], s[14:15]
	v_fma_f64 v[38:39], v[30:31], v[38:39], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[38:39], v[30:31], v[38:39], s[12:13]
	v_fma_f64 v[38:39], v[48:49], v[38:39], v[51:52]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[30:31], v[38:39], -v[43:44]
	v_fma_f64 v[30:31], v[48:49], s[8:9], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[30:31], v[41:42], -v[30:31]
	v_xor_b32_e32 v31, 0x80000000, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v36, s0
	v_mov_b32_e32 v36, 0
	v_cndmask_b32_e64 v31, v31, v37, s0
	v_cmp_class_f64_e64 s0, v[12:13], 0x1f8
                                        ; implicit-def: $vgpr37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v31, v31, v32
	v_cndmask_b32_e64 v30, 0, v30, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v31, 0x7ff80000, v31, s0
	v_mul_f64 v[32:33], v[33:34], v[30:31]
	v_lshlrev_b64 v[30:31], 3, v[35:36]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v34, s1, s4, v30
	v_add_co_ci_u32_e64 v35, s1, s5, v31, s1
	global_store_b64 v[34:35], v[32:33], off
                                        ; implicit-def: $vgpr32_vgpr33
                                        ; implicit-def: $vgpr34_vgpr35
	s_and_saveexec_b32 s1, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s1
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_cmp_le_f64_e64 s1, 0x7b000000, |v[6:7]|
	v_mov_b32_e32 v48, v36
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0x3ff921fb
	s_mov_b32 s10, 0x33145c07
	s_mov_b32 s11, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, v45, v23, s1
	v_cndmask_b32_e64 v6, v6, v22, s1
	v_mul_f64 v[22:23], v[18:19], v[6:7]
	v_mul_f64 v[32:33], v[10:11], v[6:7]
	v_mul_f64 v[43:44], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[18:19], v[6:7], -v[22:23]
	v_fma_f64 v[10:11], v[10:11], v[6:7], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], v[6:7], -v[43:44]
	v_add_f64 v[34:35], v[32:33], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[37:38], v[34:35], -v[32:33]
	v_add_f64 v[41:42], v[22:23], v[34:35]
	v_add_f64 v[39:40], v[34:35], -v[37:38]
	v_add_f64 v[18:19], v[18:19], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[37:38], v[41:42], -2
	v_add_f64 v[22:23], v[41:42], -v[22:23]
	v_add_f64 v[32:33], v[32:33], -v[39:40]
	v_add_f64 v[39:40], v[43:44], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[37:38]|
	v_add_f64 v[22:23], v[34:35], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[32:33]
	v_fract_f64_e32 v[32:33], v[37:38]
	v_add_f64 v[34:35], v[39:40], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v33, 0, v33, s1
	v_cndmask_b32_e64 v32, 0, v32, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[32:33], v[32:33], 2
	v_add_f64 v[37:38], v[22:23], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[37:38], v[32:33]
	v_add_f64 v[6:7], v[37:38], -v[22:23]
	v_cmp_gt_f64_e64 s1, 0, v[41:42]
	v_add_f64 v[41:42], v[39:40], -v[43:44]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[34:35], -v[6:7]
	v_cndmask_b32_e64 v49, 0, 0x40100000, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[52:53], v[39:40], -v[41:42]
	v_add_f64 v[10:11], v[10:11], -v[41:42]
	v_add_f64 v[32:33], v[32:33], v[48:49]
	v_add_f64 v[48:49], v[34:35], -v[39:40]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[41:42], v[43:44], -v[52:53]
	v_add_f64 v[50:51], v[37:38], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[54:55], v[34:35], -v[48:49]
	v_add_f64 v[18:19], v[18:19], -v[48:49]
	v_add_f64 v[10:11], v[10:11], v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v45, v[50:51]
	v_add_f64 v[39:40], v[39:40], -v[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[48:49], v45
	v_add_f64 v[18:19], v[18:19], v[39:40]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[32:33], -v[48:49]
	v_add_f64 v[10:11], v[10:11], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[37:38], v[32:33]
	v_add_f64 v[0:1], v[0:1], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[18:19], -v[32:33]
	v_cmp_le_f64_e64 s1, 0.5, v[18:19]
	v_add_f64 v[0:1], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[37:38], -v[10:11]
	v_mov_b32_e32 v10, v36
	v_cndmask_b32_e64 v11, 0, 0x3ff00000, s1
	v_add_co_ci_u32_e64 v37, s3, 0, v45, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], v[6:7]
	v_add_f64 v[6:7], v[18:19], -v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[6:7], v[0:1]
	v_mul_f64 v[18:19], v[10:11], s[8:9]
	v_add_f64 v[6:7], v[10:11], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[10:11], s[8:9], -v[18:19]
	v_add_f64 v[0:1], v[0:1], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], s[10:11], v[22:23]
	v_fma_f64 v[0:1], v[0:1], s[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[18:19], v[0:1]
	v_add_f64 v[6:7], v[32:33], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[34:35], v[0:1], -v[6:7]
                                        ; implicit-def: $vgpr6_vgpr7
.LBB0_15:                               ; %Flow62
	s_and_not1_saveexec_b32 s1, s4
	s_cbranch_execz .LBB0_17
; %bb.16:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[0:1], |v[6:7]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[0:1], v[0:1]
	v_fma_f64 v[6:7], v[0:1], s[4:5], |v[6:7]|
	v_mul_f64 v[10:11], v[0:1], s[8:9]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v37, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[0:1], s[8:9], v[6:7]
	v_add_f64 v[18:19], v[6:7], v[10:11]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[10:11]
	v_fma_f64 v[10:11], v[0:1], s[8:9], v[10:11]
	v_add_f64 v[6:7], v[18:19], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_fma_f64 v[6:7], v[0:1], s[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[22:23], v[6:7]
	v_add_f64 v[10:11], v[32:33], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[34:35], v[6:7], -v[10:11]
.LBB0_17:                               ; %_ZL3cosd.exit40
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr6_vgpr7
	s_and_saveexec_b32 s1, s33
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s1
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_cmp_le_f64_e64 s1, 0x7b000000, |v[8:9]|
	v_mov_b32_e32 v40, 0
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0x3ff921fb
	s_mov_b32 s10, 0x33145c07
	s_mov_b32 s11, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, v46, v25, s1
	v_cndmask_b32_e64 v0, v8, v24, s1
	v_mul_f64 v[6:7], v[20:21], v[0:1]
	v_mul_f64 v[8:9], v[14:15], v[0:1]
	v_mul_f64 v[38:39], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[20:21], v[0:1], -v[6:7]
	v_fma_f64 v[14:15], v[14:15], v[0:1], -v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[2:3], v[0:1], -v[38:39]
	v_add_f64 v[18:19], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[8:9]
	v_add_f64 v[24:25], v[6:7], v[18:19]
	v_add_f64 v[22:23], v[18:19], -v[20:21]
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[20:21], v[24:25], -2
	v_add_f64 v[6:7], v[24:25], -v[6:7]
	v_add_f64 v[8:9], v[8:9], -v[22:23]
	v_add_f64 v[22:23], v[38:39], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[20:21]|
	v_add_f64 v[6:7], v[18:19], -v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[10:11], v[8:9]
	v_fract_f64_e32 v[10:11], v[20:21]
	v_add_f64 v[18:19], v[22:23], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 0, v11, s1
	v_cndmask_b32_e64 v10, 0, v10, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[10:11], v[10:11], 2
	v_add_f64 v[20:21], v[6:7], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[20:21], v[10:11]
	v_add_f64 v[2:3], v[20:21], -v[6:7]
	v_cmp_gt_f64_e64 s1, 0, v[24:25]
	v_add_f64 v[24:25], v[22:23], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[18:19], -v[2:3]
	v_cndmask_b32_e64 v41, 0, 0x40100000, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[45:46], v[22:23], -v[24:25]
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	v_add_f64 v[10:11], v[10:11], v[40:41]
	v_add_f64 v[41:42], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[38:39], -v[45:46]
	v_add_f64 v[43:44], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[48:49], v[18:19], -v[41:42]
	v_add_f64 v[8:9], v[8:9], -v[41:42]
	v_add_f64 v[14:15], v[14:15], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v36, v[43:44]
	v_add_f64 v[22:23], v[22:23], -v[48:49]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[41:42], v36
	v_add_f64 v[8:9], v[8:9], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[41:42]
	v_add_f64 v[6:7], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[20:21], v[10:11]
	v_add_f64 v[0:1], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[8:9], -v[10:11]
	v_cmp_le_f64_e64 s1, 0.5, v[8:9]
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[20:21], -v[6:7]
	v_cndmask_b32_e64 v41, 0, 0x3ff00000, s1
	v_add_co_ci_u32_e64 v10, s3, 0, v36, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], v[2:3]
	v_add_f64 v[2:3], v[8:9], -v[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[2:3], v[0:1]
	v_mul_f64 v[8:9], v[6:7], s[8:9]
	v_add_f64 v[2:3], v[6:7], -v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[6:7], s[8:9], -v[8:9]
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[6:7], s[10:11], v[14:15]
	v_fma_f64 v[2:3], v[0:1], s[8:9], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[8:9], v[2:3]
	v_add_f64 v[6:7], v[0:1], -v[8:9]
                                        ; implicit-def: $vgpr8_vgpr9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[6:7], v[2:3], -v[6:7]
.LBB0_19:                               ; %Flow60
	s_and_not1_saveexec_b32 s1, s4
	s_cbranch_execz .LBB0_21
; %bb.20:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[0:1], |v[8:9]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[2:3], v[0:1]
	v_fma_f64 v[0:1], v[2:3], s[4:5], |v[8:9]|
	v_mul_f64 v[6:7], v[2:3], s[8:9]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[2:3], s[8:9], v[0:1]
	v_add_f64 v[8:9], v[0:1], v[6:7]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[0:1], v[0:1], -v[8:9]
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[0:1], v[6:7]
	v_fma_f64 v[6:7], v[2:3], s[8:9], v[6:7]
	v_add_f64 v[0:1], v[8:9], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -v[6:7]
	v_fma_f64 v[6:7], v[2:3], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[10:11], v[6:7]
	v_add_f64 v[8:9], v[0:1], -v[10:11]
	v_cvt_i32_f64_e32 v10, v[2:3]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[8:9]
.LBB0_21:                               ; %_ZL3cosd.exit45
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr2_vgpr3
                                        ; implicit-def: $vgpr8_vgpr9
	s_and_saveexec_b32 s1, s34
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s1
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_cmp_le_f64_e64 s1, 0x7b000000, |v[12:13]|
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0x3ff921fb
	s_mov_b32 s10, 0x33145c07
	s_mov_b32 s11, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v47, v29, s1
	v_cndmask_b32_e64 v2, v12, v28, s1
	v_mov_b32_e32 v28, 0
	v_mul_f64 v[8:9], v[26:27], v[2:3]
	v_mul_f64 v[11:12], v[16:17], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[26:27], v[2:3], -v[8:9]
	v_mul_f64 v[26:27], v[4:5], v[2:3]
	v_fma_f64 v[15:16], v[16:17], v[2:3], -v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[11:12], v[13:14]
	v_fma_f64 v[2:3], v[4:5], v[2:3], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[18:19], -v[11:12]
	v_add_f64 v[24:25], v[8:9], v[18:19]
	v_add_f64 v[22:23], v[18:19], -v[20:21]
	v_add_f64 v[13:14], v[13:14], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[20:21], v[24:25], -2
	v_add_f64 v[8:9], v[24:25], -v[8:9]
	v_add_f64 v[11:12], v[11:12], -v[22:23]
	v_add_f64 v[22:23], v[26:27], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[20:21]|
	v_add_f64 v[8:9], v[18:19], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[13:14], v[11:12]
	v_fract_f64_e32 v[13:14], v[20:21]
	v_add_f64 v[17:18], v[22:23], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, 0, v14, s1
	v_cndmask_b32_e64 v13, 0, v13, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[13:14], v[13:14], 2
	v_add_f64 v[19:20], v[8:9], v[17:18]
	v_add_f64 v[38:39], v[17:18], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[24:25], v[19:20], v[13:14]
	v_add_f64 v[44:45], v[17:18], -v[38:39]
	v_add_f64 v[11:12], v[11:12], -v[38:39]
	v_add_f64 v[4:5], v[19:20], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e64 s1, 0, v[24:25]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	v_add_f64 v[4:5], v[17:18], -v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, 0, 0x40100000, s1
	v_add_f64 v[42:43], v[22:23], -v[24:25]
	v_add_f64 v[15:16], v[15:16], -v[24:25]
	v_add_f64 v[21:22], v[22:23], -v[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[13:14], v[28:29]
	v_add_f64 v[24:25], v[26:27], -v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[21:22]
	v_add_f64 v[40:41], v[19:20], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], v[24:25]
	v_cvt_i32_f64_e32 v29, v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[15:16], v[11:12]
	v_cvt_f64_i32_e32 v[38:39], v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_add_f64 v[13:14], v[13:14], -v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[4:5], v[2:3]
	v_add_f64 v[15:16], v[19:20], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[15:16], -v[13:14]
	v_cmp_le_f64_e64 s1, 0.5, v[15:16]
	v_add_f64 v[4:5], v[19:20], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v11, s3, 0, v29, s1
	v_cndmask_b32_e64 v29, 0, 0x3ff00000, s1
	v_add_f64 v[2:3], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[15:16], -v[28:29]
	v_add_f64 v[8:9], v[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[8:9], s[8:9]
	v_add_f64 v[4:5], v[8:9], -v[4:5]
	v_fma_f64 v[14:15], v[8:9], s[8:9], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], -v[4:5]
	v_fma_f64 v[4:5], v[8:9], s[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[2:3], s[8:9], v[4:5]
	v_add_f64 v[2:3], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[2:3], -v[12:13]
                                        ; implicit-def: $vgpr12_vgpr13
	v_add_f64 v[8:9], v[4:5], -v[8:9]
.LBB0_23:                               ; %Flow
	s_and_not1_saveexec_b32 s1, s4
	s_cbranch_execz .LBB0_25
; %bb.24:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[2:3], |v[12:13]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[4:5], v[2:3]
	v_fma_f64 v[2:3], v[4:5], s[4:5], |v[12:13]|
	v_mul_f64 v[8:9], v[4:5], s[8:9]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[4:5], s[8:9], v[2:3]
	v_add_f64 v[11:12], v[2:3], v[8:9]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], -v[11:12]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[8:9]
	v_fma_f64 v[8:9], v[4:5], s[8:9], v[8:9]
	v_add_f64 v[2:3], v[11:12], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], -v[8:9]
	v_fma_f64 v[8:9], v[4:5], s[4:5], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[13:14], v[8:9]
	v_add_f64 v[11:12], v[2:3], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[11:12]
	v_cvt_i32_f64_e32 v11, v[4:5]
.LBB0_25:                               ; %_ZL3cosd.exit50
	s_or_b32 exec_lo, exec_lo, s1
	v_mul_f64 v[4:5], v[32:33], v[32:33]
	v_mul_f64 v[12:13], v[0:1], v[0:1]
	v_mul_f64 v[14:15], v[2:3], v[2:3]
	s_mov_b32 s4, 0xb42fdfa7
	s_mov_b32 s8, 0xf9a43bb8
	s_mov_b32 s5, 0xbe5ae600
	s_mov_b32 s9, 0x3de5e0b2
	s_mov_b32 s10, 0x9037ab78
	s_mov_b32 s12, 0x46cc5e42
	s_mov_b32 s11, 0x3e21eeb6
	s_mov_b32 s13, 0xbda907db
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f64 v[46:47], v[34:35], 0.5
	v_mul_f64 v[48:49], v[6:7], 0.5
	v_mul_f64 v[60:61], v[8:9], 0.5
	v_fma_f64 v[16:17], v[4:5], s[8:9], s[4:5]
	v_fma_f64 v[18:19], v[12:13], s[8:9], s[4:5]
	v_fma_f64 v[20:21], v[14:15], s[8:9], s[4:5]
	v_fma_f64 v[22:23], v[4:5], s[12:13], s[10:11]
	v_mul_f64 v[24:25], v[4:5], 0.5
	v_fma_f64 v[26:27], v[12:13], s[12:13], s[10:11]
	v_mul_f64 v[28:29], v[12:13], 0.5
	s_mov_b32 s4, 0xa17f65f6
	s_mov_b32 s8, 0x19e83e5c
	s_mov_b32 s5, 0xbe927e4f
	s_mov_b32 s9, 0xbf2a01a0
	v_mul_f64 v[38:39], v[14:15], 0.5
	v_fma_f64 v[40:41], v[14:15], s[12:13], s[10:11]
	s_mov_b32 s10, 0x19f4ec90
	s_mov_b32 s12, 0x11110bb3
	s_mov_b32 s11, 0x3efa01a0
	s_mov_b32 s13, 0x3f811111
	v_mul_f64 v[50:51], v[32:33], -v[4:5]
	v_mul_f64 v[52:53], v[0:1], -v[12:13]
	v_mul_f64 v[62:63], v[2:3], -v[14:15]
	v_fma_f64 v[16:17], v[4:5], v[16:17], s[14:15]
	v_fma_f64 v[18:19], v[12:13], v[18:19], s[14:15]
	v_fma_f64 v[20:21], v[14:15], v[20:21], s[14:15]
	v_fma_f64 v[22:23], v[4:5], v[22:23], s[4:5]
	v_add_f64 v[42:43], -v[24:25], 1.0
	v_fma_f64 v[26:27], v[12:13], v[26:27], s[4:5]
	v_add_f64 v[44:45], -v[28:29], 1.0
	v_add_f64 v[54:55], -v[38:39], 1.0
	v_fma_f64 v[40:41], v[14:15], v[40:41], s[4:5]
	s_mov_b32 s4, 0x16c16967
	s_mov_b32 s5, 0xbf56c16c
	v_fma_f64 v[16:17], v[4:5], v[16:17], s[8:9]
	v_fma_f64 v[18:19], v[12:13], v[18:19], s[8:9]
	v_fma_f64 v[20:21], v[14:15], v[20:21], s[8:9]
	v_fma_f64 v[22:23], v[4:5], v[22:23], s[10:11]
	v_add_f64 v[56:57], -v[42:43], 1.0
	v_fma_f64 v[26:27], v[12:13], v[26:27], s[10:11]
	v_add_f64 v[58:59], -v[44:45], 1.0
	s_mov_b32 s8, 0x55555555
	s_mov_b32 s9, 0x3fa55555
	v_add_f64 v[64:65], -v[54:55], 1.0
	v_fma_f64 v[40:41], v[14:15], v[40:41], s[10:11]
	v_fma_f64 v[16:17], v[4:5], v[16:17], s[12:13]
	v_fma_f64 v[18:19], v[12:13], v[18:19], s[12:13]
	v_fma_f64 v[20:21], v[14:15], v[20:21], s[12:13]
	v_fma_f64 v[22:23], v[4:5], v[22:23], s[4:5]
	v_add_f64 v[24:25], v[56:57], -v[24:25]
	v_fma_f64 v[26:27], v[12:13], v[26:27], s[4:5]
	v_add_f64 v[28:29], v[58:59], -v[28:29]
	v_add_f64 v[38:39], v[64:65], -v[38:39]
	v_fma_f64 v[40:41], v[14:15], v[40:41], s[4:5]
	s_mov_b32 s5, 0xbfc55555
	s_mov_b32 s4, s8
	v_fma_f64 v[16:17], v[50:51], v[16:17], v[46:47]
	v_fma_f64 v[18:19], v[52:53], v[18:19], v[48:49]
	v_fma_f64 v[20:21], v[62:63], v[20:21], v[60:61]
	v_mul_f64 v[46:47], v[4:5], v[4:5]
	v_mul_f64 v[48:49], v[12:13], v[12:13]
	v_fma_f64 v[16:17], v[4:5], v[16:17], -v[34:35]
	v_fma_f64 v[4:5], v[4:5], v[22:23], s[8:9]
	v_fma_f64 v[22:23], v[32:33], -v[34:35], v[24:25]
	v_fma_f64 v[18:19], v[12:13], v[18:19], -v[6:7]
	v_fma_f64 v[12:13], v[12:13], v[26:27], s[8:9]
	v_fma_f64 v[6:7], v[0:1], -v[6:7], v[28:29]
	v_fma_f64 v[20:21], v[14:15], v[20:21], -v[8:9]
	v_mul_f64 v[24:25], v[14:15], v[14:15]
	v_fma_f64 v[14:15], v[14:15], v[40:41], s[8:9]
	v_fma_f64 v[8:9], v[2:3], -v[8:9], v[38:39]
	v_fma_f64 v[16:17], v[50:51], s[4:5], v[16:17]
	v_fma_f64 v[4:5], v[46:47], v[4:5], v[22:23]
	v_fma_f64 v[18:19], v[52:53], s[4:5], v[18:19]
	v_fma_f64 v[6:7], v[48:49], v[12:13], v[6:7]
	v_fma_f64 v[12:13], v[62:63], s[4:5], v[20:21]
	v_fma_f64 v[8:9], v[24:25], v[14:15], v[8:9]
	v_lshlrev_b32_e32 v14, 30, v37
	v_add_f64 v[16:17], v[32:33], -v[16:17]
	v_add_f64 v[4:5], v[42:43], v[4:5]
	v_add_f64 v[0:1], v[0:1], -v[18:19]
	v_and_b32_e32 v18, 1, v37
	v_add_f64 v[6:7], v[44:45], v[6:7]
	v_add_f64 v[2:3], v[2:3], -v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s3, 0, v18
	v_add_f64 v[8:9], v[54:55], v[8:9]
	v_cndmask_b32_e64 v4, v16, v4, s3
	v_lshlrev_b32_e32 v15, 30, v10
	v_and_b32_e32 v10, 1, v10
	v_xor_b32_e32 v1, 0x80000000, v1
	v_xor_b32_e32 v3, 0x80000000, v3
	v_and_b32_e32 v14, 0x80000000, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e64 s1, 0, v10
	v_xor_b32_e32 v10, 0x80000000, v17
	v_cndmask_b32_e64 v6, v0, v6, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v10, v5, s3
	v_cndmask_b32_e64 v1, v1, v7, s1
	v_xor_b32_e32 v5, v0, v14
	v_dual_cndmask_b32 v0, 0, v4 :: v_dual_and_b32 v15, 0x80000000, v15
	v_cndmask_b32_e64 v4, 0, v6, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v1, v15
	v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0x7ff80000, v7, s2
	v_mul_f64 v[0:1], v[0:1], v[4:5]
	v_and_b32_e32 v4, 1, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_lshlrev_b32_e32 v4, 30, v11
	v_dual_cndmask_b32 v2, v2, v8 :: v_dual_cndmask_b32 v3, v3, v9
	v_and_b32_e32 v4, 0x80000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, 0, v2, s0
	v_xor_b32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 0x7ff80000, v3, s0
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	v_add_co_u32 v2, vcc_lo, s6, v30
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v31, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
.LBB0_26:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10initializePdS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 75
		.amdhsa_next_free_sgpr 35
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10initializePdS_, .Lfunc_end0-_Z10initializePdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8224
; NumSgprs: 37
; NumVgprs: 75
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 37
; NumVGPRsForWavesPerEU: 75
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z10waveDomainPd        ; -- Begin function _Z10waveDomainPd
	.globl	_Z10waveDomainPd
	.p2align	8
	.type	_Z10waveDomainPd,@function
_Z10waveDomainPd:                       ; @_Z10waveDomainPd
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x14
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_add_nc_u32_e32 v0, 0xffffff00, v1
	v_cmp_gt_i32_e32 vcc_lo, 0x80, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[3:4], v0
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10waveDomainPd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10waveDomainPd, .Lfunc_end1-_Z10waveDomainPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi ; -- Begin function _Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.globl	_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
	.p2align	8
	.type	_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi,@function
_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi: ; @_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x2c
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[8:9], null, s14, s4, v[4:5]
	v_mad_u64_u32 v[1:2], null, s13, s2, v[3:4]
	s_and_b32 s2, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v0, v1, v8
	v_cmp_gt_i32_e32 vcc_lo, 0x100, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, 0x81, v5
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_17
; %bb.1:                                ; %NodeBlock74
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_max_i32_e32 v2, 0, v8
	v_max_i32_e32 v3, 0, v1
	v_max_i32_e32 v0, 0, v5
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, v3, 8, v2
	v_mad_u64_u32 v[3:4], null, 0x81, v2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s2, 2
	s_cbranch_scc1 .LBB2_5
; %bb.2:                                ; %NodeBlock
	s_cmp_gt_i32 s2, 2
	s_cbranch_scc0 .LBB2_6
; %bb.3:                                ; %LeafBlock72
	s_cmp_eq_u32 s2, 3
	s_mov_b32 s8, 0
	s_cbranch_scc0 .LBB2_7
; %bb.4:
	v_ashrrev_i32_e32 v6, 31, v5
	v_mov_b32_e32 v4, 0
	s_mov_b32 s3, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_lshlrev_b64 v[9:10], 4, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v9
	global_load_b64 v[11:12], v[4:5], off
	global_load_b64 v[13:14], v[6:7], off offset:8
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[11:12], v[13:14], -v[11:12]
	global_store_b64 v[9:10], v[11:12], off
	s_branch .LBB2_8
.LBB2_5:
	s_mov_b32 s8, -1
                                        ; implicit-def: $vgpr9_vgpr10
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr4_vgpr5
	s_branch .LBB2_11
.LBB2_6:
	s_mov_b32 s8, -1
.LBB2_7:
                                        ; implicit-def: $vgpr9_vgpr10
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr4_vgpr5
.LBB2_8:                                ; %Flow76
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccz .LBB2_10
; %bb.9:
	v_ashrrev_i32_e32 v9, 31, v8
	v_mov_b32_e32 v4, 0
	s_mov_b32 s3, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[8:9]
	v_lshlrev_b64 v[9:10], 4, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, s6, v9
	global_load_b64 v[11:12], v[4:5], off
	global_load_b64 v[13:14], v[6:7], off offset:8
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f64 v[11:12], v[13:14], -v[11:12]
	global_store_b64 v[9:10], v[11:12], off
.LBB2_10:                               ; %Flow78
	s_mov_b32 s8, 0
.LBB2_11:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s8
	s_cbranch_vccz .LBB2_15
; %bb.12:                               ; %LeafBlock
	s_cmp_eq_u32 s2, 1
	s_cbranch_scc0 .LBB2_14
; %bb.13:
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v4, 0
	s_mov_b32 s3, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_lshlrev_b64 v[2:3], 4, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
	global_load_b64 v[0:1], v[4:5], off
	global_load_b64 v[8:9], v[6:7], off offset:8
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[8:9], -v[0:1]
	v_add_co_u32 v9, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v3, vcc_lo
	global_store_b64 v[9:10], v[0:1], off
	s_branch .LBB2_15
.LBB2_14:
                                        ; implicit-def: $vgpr9_vgpr10
                                        ; implicit-def: $vgpr6_vgpr7
                                        ; implicit-def: $vgpr4_vgpr5
.LBB2_15:                               ; %Flow79
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB2_17
; %bb.16:                               ; %.sink.split
	global_load_b64 v[0:1], v[4:5], off
	global_load_b64 v[2:3], v[6:7], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[0:1], v[2:3]
	global_store_b64 v[9:10], v[0:1], off offset:8
.LBB2_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi, .Lfunc_end2-_Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 680
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z12complexScaleP15HIP_vector_typeIdLj2EE ; -- Begin function _Z12complexScaleP15HIP_vector_typeIdLj2EE
	.globl	_Z12complexScaleP15HIP_vector_typeIdLj2EE
	.p2align	8
	.type	_Z12complexScaleP15HIP_vector_typeIdLj2EE,@function
_Z12complexScaleP15HIP_vector_typeIdLj2EE: ; @_Z12complexScaleP15HIP_vector_typeIdLj2EE
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x14
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s13, s2, v[3:4]
	v_mad_u64_u32 v[2:3], null, s14, s4, v[4:5]
	s_and_b32 s2, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v0, v1, v2
	v_cmp_gt_i32_e32 vcc_lo, 0x100, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, 0x81, v3
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_2
; %bb.1:
	v_max_i32_e32 v2, 0, v2
	v_max_i32_e32 v1, 0, v1
	s_load_b64 s[0:1], s[0:1], 0x0
	v_max_i32_e32 v0, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v3, v1, 8, v2
	v_mad_u64_u32 v[1:2], null, 0x81, v3, v[0:1]
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	global_load_b128 v[0:3], v[4:5], off
	s_waitcnt vmcnt(0)
	v_ldexp_f64 v[0:1], v[0:1], 0xffffffe8
	v_ldexp_f64 v[2:3], v[2:3], 0xffffffe8
	global_store_b128 v[4:5], v[0:3], off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12complexScaleP15HIP_vector_typeIdLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z12complexScaleP15HIP_vector_typeIdLj2EE, .Lfunc_end3-_Z12complexScaleP15HIP_vector_typeIdLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 272
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10initializePdS_
    .private_segment_fixed_size: 0
    .sgpr_count:     37
    .sgpr_spill_count: 0
    .symbol:         _Z10initializePdS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     75
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10waveDomainPd
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10waveDomainPd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6multIkP15HIP_vector_typeIdLj2EES1_Pdi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12complexScaleP15HIP_vector_typeIdLj2EE
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12complexScaleP15HIP_vector_typeIdLj2EE.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
