#include "includes.h"
__global__ void ReplaceKernelA(const float* p_Input, float* p_Output, int p_Width, int p_Height, float hueRangeA, float hueRangeB, float hueRangeWithRollOffA, float hueRangeWithRollOffB, float satRangeA, float satRangeB, float satRolloff, float valRangeA, float valRangeB, float valRolloff, int OutputAlpha, int DisplayAlpha, float p_Black, float p_White) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < p_Width && y < p_Height) {
const int index = (y * p_Width + x) * 4;
float hcoeff, scoeff, vcoeff;
float r, g, b, h, s, v;
r = p_Input[index];
g = p_Input[index + 1];
b = p_Input[index + 2];
float min = fmin(fmin(r, g), b);
float max = fmax(fmax(r, g), b);
v = max;
float delta = max - min;
if (max != 0.0f) {
s = delta / max;
} else {
s = 0.0f;
h = 0.0f;
}
if (delta == 0.0f) {
h = 0.0f;
} else if (r == max) {
h = (g - b) / delta;
} else if (g == max) {
h = 2 + (b - r) / delta;
} else {
h = 4 + (r - g) / delta;
}
h *= 1 / 6.0f;
if (h < 0.0f) {
h += 1.0f;
}
h *= 360.0f;
float h0 = hueRangeA;
float h1 = hueRangeB;
float h0mrolloff = hueRangeWithRollOffA;
float h1prolloff = hueRangeWithRollOffB;
if ( ( h1 < h0 && (h <= h1 || h0 <= h) ) || (h0 <= h && h <= h1) ) {
hcoeff = 1.0f;
} else {
float c0 = 0.0f;
float c1 = 0.0f;
if ( ( h0 < h0mrolloff && (h <= h0 || h0mrolloff <= h) ) || (h0mrolloff <= h && h <= h0) ) {
c0 = h0 == (h0mrolloff + 360.0f) || h0 == h0mrolloff ? 1.0f : !(( h0 < h0mrolloff && (h <= h0 || h0mrolloff <= h) ) || (h0mrolloff <= h && h <= h0)) ? 0.0f :
((h < h0mrolloff ? h + 360.0f : h) - h0mrolloff) / ((h0 < h0mrolloff ? h0 + 360.0f : h0) - h0mrolloff);
}
if ( ( h1prolloff < h1 && (h <= h1prolloff || h1 <= h) ) || (h1 <= h && h <= h1prolloff) ) {
c1 = !(( h1prolloff < h1 && (h <= h1prolloff || h1 <= h) ) || (h1 <= h && h <= h1prolloff)) ? 0.0f : h1prolloff == h1 ? 1.0f :
((h1prolloff < h1 ? h1prolloff + 360.0f : h1prolloff) - (h < h1 ? h + 360.0f : h)) / ((h1prolloff < h1 ? h1prolloff + 360.0f : h1prolloff) - h1);
}
hcoeff = fmax(c0, c1);
}
float s0 = satRangeA;
float s1 = satRangeB;
float s0mrolloff = s0 - satRolloff;
float s1prolloff = s1 + satRolloff;
if ( s0 <= s && s <= s1 ) {
scoeff = 1.0f;
} else if ( s0mrolloff <= s && s <= s0 ) {
scoeff = (s - s0mrolloff) / satRolloff;
} else if ( s1 <= s && s <= s1prolloff ) {
scoeff = (s1prolloff - s) / satRolloff;
} else {
scoeff = 0.0f;
}
float v0 = valRangeA;
float v1 = valRangeB;
float v0mrolloff = v0 - valRolloff;
float v1prolloff = v1 + valRolloff;
if ( (v0 <= v) && (v <= v1) ) {
vcoeff = 1.0f;
} else if ( v0mrolloff <= v && v <= v0 ) {
vcoeff = (v - v0mrolloff) / valRolloff;
} else if ( v1 <= v && v <= v1prolloff ) {
vcoeff = (v1prolloff - v) / valRolloff;
} else {
vcoeff = 0.0f;
}
float coeff = fmin(fmin(hcoeff, scoeff), vcoeff);
float A = OutputAlpha == 0 ? 1.0f : OutputAlpha == 1 ? hcoeff : OutputAlpha == 2 ? scoeff :
OutputAlpha == 3 ? vcoeff : OutputAlpha == 4 ? fmin(hcoeff, scoeff) : OutputAlpha == 5 ?
fmin(hcoeff, vcoeff) : OutputAlpha == 6 ? fmin(scoeff, vcoeff) : fmin(fmin(hcoeff, scoeff), vcoeff);
if (DisplayAlpha == 0)
A = coeff;
if (p_Black > 0.0f)
A = fmax(A - (p_Black * 4.0f) * (1.0f - A), 0.0f);
if (p_White > 0.0f)
A = fmin(A * (1.0f + p_White * 4.0f), 1.0f);
p_Output[index] = h;
p_Output[index + 1] = s;
p_Output[index + 2] = v;
p_Output[index + 3] = A;
}}
	.file	"tmpxft_00252f3e_00000000-6_ReplaceKernelA.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z53__device_stub__Z14ReplaceKernelAPKfPfiiffffffffffiiffPKfPfiiffffffffffiiff
	.type	_Z53__device_stub__Z14ReplaceKernelAPKfPfiiffffffffffiiffPKfPfiiffffffffffiiff, @function
_Z53__device_stub__Z14ReplaceKernelAPKfPfiiffffffffffiiffPKfPfiiffffffffffiiff:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 44(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 40(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movss	%xmm0, 36(%rsp)
	movss	%xmm1, 32(%rsp)
	movss	%xmm2, 28(%rsp)
	movss	%xmm3, 24(%rsp)
	movss	%xmm4, 20(%rsp)
	movss	%xmm5, 16(%rsp)
	movss	%xmm6, 12(%rsp)
	movss	%xmm7, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	%rsp, %rax
	movq	%rax, 256(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z14ReplaceKernelAPKfPfiiffffffffffiiff(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 320
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L2:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z53__device_stub__Z14ReplaceKernelAPKfPfiiffffffffffiiffPKfPfiiffffffffffiiff, .-_Z53__device_stub__Z14ReplaceKernelAPKfPfiiffffffffffiiffPKfPfiiffffffffffiiff
	.globl	_Z14ReplaceKernelAPKfPfiiffffffffffiiff
	.type	_Z14ReplaceKernelAPKfPfiiffffffffffiiff, @function
_Z14ReplaceKernelAPKfPfiiffffffffffiiff:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z14ReplaceKernelAPKfPfiiffffffffffiiffPKfPfiiffffffffffiiff
	.cfi_endproc
.LFE2033:
	.size	_Z14ReplaceKernelAPKfPfiiffffffffffiiff, .-_Z14ReplaceKernelAPKfPfiiffffffffffiiff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14ReplaceKernelAPKfPfiiffffffffffiiff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14ReplaceKernelAPKfPfiiffffffffffiiff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ReplaceKernelA(const float* p_Input, float* p_Output, int p_Width, int p_Height, float hueRangeA, float hueRangeB, float hueRangeWithRollOffA, float hueRangeWithRollOffB, float satRangeA, float satRangeB, float satRolloff, float valRangeA, float valRangeB, float valRolloff, int OutputAlpha, int DisplayAlpha, float p_Black, float p_White) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < p_Width && y < p_Height) {
const int index = (y * p_Width + x) * 4;
float hcoeff, scoeff, vcoeff;
float r, g, b, h, s, v;
r = p_Input[index];
g = p_Input[index + 1];
b = p_Input[index + 2];
float min = fmin(fmin(r, g), b);
float max = fmax(fmax(r, g), b);
v = max;
float delta = max - min;
if (max != 0.0f) {
s = delta / max;
} else {
s = 0.0f;
h = 0.0f;
}
if (delta == 0.0f) {
h = 0.0f;
} else if (r == max) {
h = (g - b) / delta;
} else if (g == max) {
h = 2 + (b - r) / delta;
} else {
h = 4 + (r - g) / delta;
}
h *= 1 / 6.0f;
if (h < 0.0f) {
h += 1.0f;
}
h *= 360.0f;
float h0 = hueRangeA;
float h1 = hueRangeB;
float h0mrolloff = hueRangeWithRollOffA;
float h1prolloff = hueRangeWithRollOffB;
if ( ( h1 < h0 && (h <= h1 || h0 <= h) ) || (h0 <= h && h <= h1) ) {
hcoeff = 1.0f;
} else {
float c0 = 0.0f;
float c1 = 0.0f;
if ( ( h0 < h0mrolloff && (h <= h0 || h0mrolloff <= h) ) || (h0mrolloff <= h && h <= h0) ) {
c0 = h0 == (h0mrolloff + 360.0f) || h0 == h0mrolloff ? 1.0f : !(( h0 < h0mrolloff && (h <= h0 || h0mrolloff <= h) ) || (h0mrolloff <= h && h <= h0)) ? 0.0f :
((h < h0mrolloff ? h + 360.0f : h) - h0mrolloff) / ((h0 < h0mrolloff ? h0 + 360.0f : h0) - h0mrolloff);
}
if ( ( h1prolloff < h1 && (h <= h1prolloff || h1 <= h) ) || (h1 <= h && h <= h1prolloff) ) {
c1 = !(( h1prolloff < h1 && (h <= h1prolloff || h1 <= h) ) || (h1 <= h && h <= h1prolloff)) ? 0.0f : h1prolloff == h1 ? 1.0f :
((h1prolloff < h1 ? h1prolloff + 360.0f : h1prolloff) - (h < h1 ? h + 360.0f : h)) / ((h1prolloff < h1 ? h1prolloff + 360.0f : h1prolloff) - h1);
}
hcoeff = fmax(c0, c1);
}
float s0 = satRangeA;
float s1 = satRangeB;
float s0mrolloff = s0 - satRolloff;
float s1prolloff = s1 + satRolloff;
if ( s0 <= s && s <= s1 ) {
scoeff = 1.0f;
} else if ( s0mrolloff <= s && s <= s0 ) {
scoeff = (s - s0mrolloff) / satRolloff;
} else if ( s1 <= s && s <= s1prolloff ) {
scoeff = (s1prolloff - s) / satRolloff;
} else {
scoeff = 0.0f;
}
float v0 = valRangeA;
float v1 = valRangeB;
float v0mrolloff = v0 - valRolloff;
float v1prolloff = v1 + valRolloff;
if ( (v0 <= v) && (v <= v1) ) {
vcoeff = 1.0f;
} else if ( v0mrolloff <= v && v <= v0 ) {
vcoeff = (v - v0mrolloff) / valRolloff;
} else if ( v1 <= v && v <= v1prolloff ) {
vcoeff = (v1prolloff - v) / valRolloff;
} else {
vcoeff = 0.0f;
}
float coeff = fmin(fmin(hcoeff, scoeff), vcoeff);
float A = OutputAlpha == 0 ? 1.0f : OutputAlpha == 1 ? hcoeff : OutputAlpha == 2 ? scoeff :
OutputAlpha == 3 ? vcoeff : OutputAlpha == 4 ? fmin(hcoeff, scoeff) : OutputAlpha == 5 ?
fmin(hcoeff, vcoeff) : OutputAlpha == 6 ? fmin(scoeff, vcoeff) : fmin(fmin(hcoeff, scoeff), vcoeff);
if (DisplayAlpha == 0)
A = coeff;
if (p_Black > 0.0f)
A = fmax(A - (p_Black * 4.0f) * (1.0f - A), 0.0f);
if (p_White > 0.0f)
A = fmin(A * (1.0f + p_White * 4.0f), 1.0f);
p_Output[index] = h;
p_Output[index + 1] = s;
p_Output[index + 2] = v;
p_Output[index + 3] = A;
}}
	.text
	.file	"ReplaceKernelA.hip"
	.globl	_Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff # -- Begin function _Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff
	.type	_Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff,@function
_Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff: # @_Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$264, %rsp                      # imm = 0x108
	.cfi_def_cfa_offset 320
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsp, %rax
	movq	%rdi, (%rax)
	leaq	72(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	52(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	44(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	40(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	36(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	32(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	28(%rsp), %r15
	movss	%xmm4, (%r15)
	leaq	24(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	20(%rsp), %r13
	movss	%xmm6, (%r13)
	leaq	16(%rsp), %rbp
	movss	%xmm7, (%rbp)
	leaq	12(%rsp), %rax
	movl	%r8d, (%rax)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rsp, %r9
	movq	%r9, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r14, 56(%rbx)
	movq	%r15, 64(%rbx)
	movq	%r12, 72(%rbx)
	movq	%r13, 80(%rbx)
	movq	%rbp, 88(%rbx)
	leaq	320(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	328(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	movq	%rax, 112(%rbx)
	movq	%r8, 120(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	64(%rsp), %r12
	leaq	56(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14ReplaceKernelAPKfPfiiffffffffffiiff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$280, %rsp                      # imm = 0x118
	.cfi_adjust_cfa_offset -280
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff, .Lfunc_end0-_Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14ReplaceKernelAPKfPfiiffffffffffiiff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14ReplaceKernelAPKfPfiiffffffffffiiff,@object # @_Z14ReplaceKernelAPKfPfiiffffffffffiiff
	.section	.rodata,"a",@progbits
	.globl	_Z14ReplaceKernelAPKfPfiiffffffffffiiff
	.p2align	3, 0x0
_Z14ReplaceKernelAPKfPfiiffffffffffiiff:
	.quad	_Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff
	.size	_Z14ReplaceKernelAPKfPfiiffffffffffiiff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14ReplaceKernelAPKfPfiiffffffffffiiff"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__ReplaceKernelAPKfPfiiffffffffffiiff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14ReplaceKernelAPKfPfiiffffffffffiiff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14ReplaceKernelAPKfPfiiffffffffffiiff ; -- Begin function _Z14ReplaceKernelAPKfPfiiffffffffffiiff
	.globl	_Z14ReplaceKernelAPKfPfiiffffffffffiiff
	.p2align	8
	.type	_Z14ReplaceKernelAPKfPfiiffffffffffiiff,@function
_Z14ReplaceKernelAPKfPfiiffffffffffiiff: ; @_Z14ReplaceKernelAPKfPfiiffffffffffiiff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b512 s[16:31], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s16, v0
	v_cmp_gt_i32_e64 s2, s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_95
; %bb.1:
	v_mul_lo_u32 v1, v1, s16
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v0, v1, v0, 2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
	s_mov_b32 s0, exec_lo
	global_load_b96 v[3:5], v[0:1], off
	s_waitcnt vmcnt(0)
	v_min3_f32 v0, v3, v4, v5
	v_max3_f32 v2, v3, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v1, v2, v0 :: v_dual_mov_b32 v0, 0
	v_cmpx_neq_f32_e32 0, v1
	s_cbranch_execz .LBB0_11
; %bb.2:
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr0
	v_cmpx_neq_f32_e32 v3, v2
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.3:
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $vgpr0
	v_cmpx_neq_f32_e32 v4, v2
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_sub_f32_e32 v0, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v1, v1, v0
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v0, v1, v0
	v_mul_f32_e32 v8, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v3, v8, v5
	v_fmac_f32_e32 v8, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v8, v5
	v_div_fmas_f32 v3, v3, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v3, v1, v0
                                        ; implicit-def: $vgpr3_vgpr4_vgpr5
	v_add_f32_e32 v0, 4.0, v0
.LBB0_5:                                ; %Flow383
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_sub_f32_e32 v0, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v1, v1, v0
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v0, v1, v0
	v_mul_f32_e32 v8, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v3, v8, v5
	v_fmac_f32_e32 v8, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v8, v5
	v_div_fmas_f32 v3, v3, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v3, v1, v0
	v_add_f32_e32 v0, 2.0, v0
.LBB0_7:                                ; %Flow384
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr3_vgpr4_vgpr5
.LBB0_8:                                ; %Flow386
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_sub_f32_e32 v0, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v1, v1, v0
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v0, v1, v0
	v_mul_f32_e32 v8, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v3, v8, v5
	v_fmac_f32_e32 v8, v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v8, v5
	v_div_fmas_f32 v3, v3, v4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v0, v3, v1, v0
.LBB0_10:                               ; %Flow387
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_11:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f32_e32 v3, 0x3e2aaaab, v0
	v_fma_f32 v0, 0x3e2aaaab, v0, 1.0
	v_cmp_nlt_f32_e64 s5, s19, s18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v0, v3, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s5
	v_mul_f32_e32 v0, 0x43b40000, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nge_f32_e64 s0, s19, v0
	v_cmp_nle_f32_e64 s1, s18, v0
	s_cbranch_vccnz .LBB0_13
; %bb.12:
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s0, s0, s1
	s_and_not1_b32 s1, s5, exec_lo
	s_and_b32 s4, s0, exec_lo
	s_mov_b32 s0, 1.0
	s_or_b32 s5, s1, s4
	s_branch .LBB0_14
.LBB0_13:
                                        ; implicit-def: $sgpr0
.LBB0_14:                               ; %Flow381
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v3, s0
	s_and_saveexec_b32 s4, s5
	s_cbranch_execz .LBB0_45
; %bb.15:
	v_cmp_nle_f32_e32 vcc_lo, s18, v0
	v_cmp_nge_f32_e64 s0, s19, v0
	v_mov_b32_e32 v3, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_44
; %bb.16:
	v_cmp_nlt_f32_e64 s7, s18, s20
	v_cmp_lt_f32_e64 s0, s18, s20
	s_mov_b32 s8, 0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 vcc_lo, exec_lo, s7
	s_mov_b32 s1, s7
	s_cbranch_vccnz .LBB0_18
; %bb.17:
	v_cmp_nge_f32_e32 vcc_lo, s18, v0
	v_cmp_nle_f32_e64 s1, s20, v0
	s_and_not1_b32 s6, s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_xor_b32 s8, s1, -1
	s_and_b32 s1, s1, exec_lo
	s_and_b32 s8, s8, exec_lo
	s_or_b32 s1, s6, s1
.LBB0_18:                               ; %Flow377
                                        ; implicit-def: $sgpr9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s1
; %bb.19:
	v_cmp_le_f32_e32 vcc_lo, s20, v0
	v_cmp_ge_f32_e64 s1, s18, v0
	s_and_not1_b32 s8, s8, exec_lo
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s8, s1
; %bb.20:                               ; %Flow378
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v3, s9
	s_and_saveexec_b32 s6, s8
	s_cbranch_execz .LBB0_29
; %bb.21:
	v_add_f32_e64 v3, 0x43b40000, s20
	v_cmp_eq_f32_e64 s1, s18, s20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_f32_e32 vcc_lo, s18, v3
	v_mov_b32_e32 v3, 1.0
	s_or_b32 s1, s1, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_29
; %bb.22:
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s8, 0
	s_cbranch_vccnz .LBB0_24
; %bb.23:
	v_cmp_nge_f32_e32 vcc_lo, s18, v0
	v_cmp_nle_f32_e64 s1, s20, v0
	s_and_not1_b32 s7, s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_xor_b32 s8, s1, -1
	s_and_b32 s1, s1, exec_lo
	s_and_b32 s8, s8, exec_lo
	s_or_b32 s7, s7, s1
.LBB0_24:                               ; %Flow373
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s7
; %bb.25:
	v_cmp_le_f32_e32 vcc_lo, s20, v0
	v_cmp_ge_f32_e64 s1, s18, v0
	s_and_not1_b32 s7, s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_b32 s8, s1, exec_lo
	s_mov_b32 s1, 0
	s_or_b32 s8, s7, s8
; %bb.26:                               ; %Flow374
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v3, s1
	s_and_saveexec_b32 s1, s8
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_add_f32_e32 v3, 0x43b40000, v0
	v_add_f32_e64 v4, 0x43b40000, s18
	v_cmp_gt_f32_e32 vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, s18, v4, s0
	v_dual_cndmask_b32 v3, v0, v3 :: v_dual_subrev_f32 v4, s20, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_f32_e32 v3, s20, v3
	v_div_scale_f32 v5, null, v4, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v5, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	v_div_scale_f32 v9, vcc_lo, v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v9, v8
	v_fma_f32 v11, -v5, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v8
	v_fma_f32 v5, -v5, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v5, v5, v8, v10
	v_div_fixup_f32 v3, v5, v4, v3
.LBB0_28:                               ; %Flow375
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_29:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s6
	v_cmp_nlt_f32_e64 s7, s21, s19
	v_cmp_lt_f32_e64 s0, s21, s19
	s_mov_b32 s8, 0
	s_and_b32 vcc_lo, exec_lo, s7
	s_mov_b32 s1, s7
	s_cbranch_vccnz .LBB0_31
; %bb.30:
	v_cmp_nge_f32_e32 vcc_lo, s21, v0
	v_cmp_nle_f32_e64 s1, s19, v0
	s_and_not1_b32 s6, s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_xor_b32 s8, s1, -1
	s_and_b32 s1, s1, exec_lo
	s_and_b32 s8, s8, exec_lo
	s_or_b32 s1, s6, s1
.LBB0_31:                               ; %Flow370
                                        ; implicit-def: $sgpr9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s6, s1
; %bb.32:
	v_cmp_le_f32_e32 vcc_lo, s19, v0
	v_cmp_ge_f32_e64 s1, s21, v0
	s_and_not1_b32 s8, s8, exec_lo
	s_mov_b32 s9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s8, s8, s1
; %bb.33:                               ; %Flow371
	s_or_b32 exec_lo, exec_lo, s6
	v_mov_b32_e32 v4, s9
	s_and_saveexec_b32 s6, s8
	s_cbranch_execz .LBB0_43
; %bb.34:
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b32 s8, 0
	s_cbranch_vccnz .LBB0_36
; %bb.35:
	v_cmp_nge_f32_e32 vcc_lo, s21, v0
	v_cmp_nle_f32_e64 s1, s19, v0
	s_and_not1_b32 s7, s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_xor_b32 s8, s1, -1
	s_and_b32 s1, s1, exec_lo
	s_and_b32 s8, s8, exec_lo
	s_or_b32 s7, s7, s1
.LBB0_36:                               ; %Flow367
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s9, s7
; %bb.37:
	v_cmp_le_f32_e32 vcc_lo, s19, v0
	v_cmp_ge_f32_e64 s1, s21, v0
	s_and_not1_b32 s7, s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_b32 s8, s1, exec_lo
	s_mov_b32 s1, 0
	s_or_b32 s8, s7, s8
; %bb.38:                               ; %Flow368
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v4, s1
	s_and_saveexec_b32 s1, s8
	s_cbranch_execz .LBB0_42
; %bb.39:
	v_cmp_eq_f32_e64 s7, s21, s19
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_41
; %bb.40:
	v_add_f32_e64 v4, 0x43b40000, s21
	v_add_f32_e32 v5, 0x43b40000, v0
	v_cmp_gt_f32_e32 vcc_lo, s19, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, s21, v4, s0
	v_cndmask_b32_e32 v5, v0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v4, v5 :: v_dual_subrev_f32 v4, s19, v4
	v_div_scale_f32 v8, null, v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	v_fmac_f32_e32 v9, v10, v9
	v_div_scale_f32 v10, vcc_lo, v5, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v10, v9
	v_fma_f32 v12, -v8, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v9
	v_fma_f32 v8, -v8, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v9, v11
	v_div_fixup_f32 v4, v8, v4, v5
	s_branch .LBB0_42
.LBB0_41:
	v_mov_b32_e32 v4, 1.0
.LBB0_42:                               ; %Flow369
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_43:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	v_dual_max_f32 v4, v4, v4 :: v_dual_max_f32 v3, v3, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_max_f32_e32 v3, v3, v4
.LBB0_44:                               ; %Flow379
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_45:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s4
	v_div_scale_f32 v4, null, v2, v2, v1
	v_div_scale_f32 v9, vcc_lo, v1, v2, v1
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v4, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v8, v5
	v_mul_f32_e32 v8, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v4, v8, v9
	v_fmac_f32_e32 v8, v10, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, -v4, v8, v9
	v_div_fmas_f32 v4, v4, v5, v8
	v_mov_b32_e32 v5, 1.0
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v4, v2, v1
	v_dual_mov_b32 v4, 1.0 :: v_dual_cndmask_b32 v1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nle_f32_e32 vcc_lo, s22, v1
	v_cmp_nge_f32_e64 s0, s23, v1
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_53
; %bb.46:
	v_sub_f32_e64 v8, s22, s24
	v_cmp_ge_f32_e64 s0, s22, v1
                                        ; implicit-def: $vgpr4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_f32_e32 vcc_lo, v8, v1
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s0
	s_xor_b32 s0, exec_lo, s4
	s_cbranch_execz .LBB0_48
; %bb.47:
	v_sub_f32_e32 v4, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v8, null, s24, s24, v4
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_div_scale_f32 v10, vcc_lo, v4, s24, v4
	v_mul_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v11, v10
	v_fmac_f32_e32 v11, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v11, v10
	v_div_fmas_f32 v8, v8, v9, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v4, v8, s24, v4
.LBB0_48:                               ; %Flow364
	s_and_not1_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_52
; %bb.49:
	v_add_f32_e64 v8, s23, s24
	v_cmp_le_f32_e32 vcc_lo, s23, v1
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_f32_e64 s0, v1, v8
	s_and_b32 s5, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s5
	s_cbranch_execz .LBB0_51
; %bb.50:
	v_sub_f32_e32 v4, v8, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v8, null, s24, s24, v4
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_div_scale_f32 v10, vcc_lo, v4, s24, v4
	v_mul_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v11, v10
	v_fmac_f32_e32 v11, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v11, v10
	v_div_fmas_f32 v8, v8, v9, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v4, v8, s24, v4
.LBB0_51:                               ; %Flow363
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_52:                               ; %Flow365
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_53:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_nle_f32_e32 vcc_lo, s25, v2
	v_cmp_nge_f32_e64 s0, s26, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_61
; %bb.54:
	v_sub_f32_e64 v8, s25, s27
	v_cmp_ge_f32_e64 s0, s25, v2
                                        ; implicit-def: $vgpr5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_f32_e32 vcc_lo, v8, v2
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s0
	s_xor_b32 s0, exec_lo, s4
	s_cbranch_execz .LBB0_56
; %bb.55:
	v_sub_f32_e32 v5, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v8, null, s27, s27, v5
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_div_scale_f32 v10, vcc_lo, v5, s27, v5
	v_mul_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v11, v10
	v_fmac_f32_e32 v11, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v11, v10
	v_div_fmas_f32 v8, v8, v9, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v5, v8, s27, v5
.LBB0_56:                               ; %Flow361
	s_and_not1_saveexec_b32 s4, s0
	s_cbranch_execz .LBB0_60
; %bb.57:
	v_add_f32_e64 v8, s26, s27
	v_cmp_le_f32_e32 vcc_lo, s26, v2
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_f32_e64 s0, v2, v8
	s_and_b32 s5, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s5
	s_cbranch_execz .LBB0_59
; %bb.58:
	v_sub_f32_e32 v5, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v8, null, s27, s27, v5
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v9
	v_div_scale_f32 v10, vcc_lo, v5, s27, v5
	v_mul_f32_e32 v11, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v8, v11, v10
	v_fmac_f32_e32 v11, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v8, v11, v10
	v_div_fmas_f32 v8, v8, v9, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v5, v8, s27, v5
.LBB0_59:                               ; %Flow360
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_60:                               ; %Flow362
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_61:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_max_f32 v10, v4, v4 :: v_dual_max_f32 v11, v3, v3
	s_cmp_lt_i32 s28, 3
	v_dual_max_f32 v9, v5, v5 :: v_dual_min_f32 v8, v11, v10
	s_cbranch_scc1 .LBB0_66
; %bb.62:                               ; %NodeBlock344
	s_cmp_gt_i32 s28, 4
	s_cbranch_scc0 .LBB0_67
; %bb.63:                               ; %NodeBlock342
	s_cmp_gt_i32 s28, 5
	s_cbranch_scc0 .LBB0_68
; %bb.64:                               ; %LeafBlock340
	s_cmp_eq_u32 s28, 6
	s_cbranch_scc0 .LBB0_69
; %bb.65:
	v_min_f32_e32 v10, v10, v9
	s_mov_b32 s0, 0
	s_branch .LBB0_70
.LBB0_66:
	s_mov_b32 s1, -1
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr10
	s_branch .LBB0_81
.LBB0_67:
	s_mov_b32 s1, -1
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr10
	s_branch .LBB0_74
.LBB0_68:
	s_mov_b32 s1, -1
	s_mov_b32 s0, 0
                                        ; implicit-def: $vgpr10
	s_branch .LBB0_71
.LBB0_69:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr10
.LBB0_70:                               ; %Flow354
	s_mov_b32 s1, 0
.LBB0_71:                               ; %Flow353
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_73
; %bb.72:
	v_min_f32_e32 v10, v11, v9
.LBB0_73:                               ; %Flow355
	s_mov_b32 s1, 0
.LBB0_74:                               ; %Flow352
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_80
; %bb.75:                               ; %NodeBlock338
	s_cmp_gt_i32 s28, 3
	s_cbranch_scc0 .LBB0_77
; %bb.76:
	s_mov_b32 s1, 0
	s_branch .LBB0_78
.LBB0_77:
	s_mov_b32 s1, -1
.LBB0_78:                               ; %Flow
	v_mov_b32_e32 v10, v8
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_80
; %bb.79:
	v_mov_b32_e32 v10, v5
.LBB0_80:                               ; %Flow356
	s_mov_b32 s1, 0
.LBB0_81:                               ; %Flow351
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_92
; %bb.82:                               ; %NodeBlock336
	s_cmp_gt_i32 s28, 0
	s_cbranch_scc0 .LBB0_85
; %bb.83:                               ; %NodeBlock
	s_cmp_gt_i32 s28, 1
	s_cbranch_scc0 .LBB0_86
; %bb.84:
	s_mov_b32 s1, 0
	s_branch .LBB0_87
.LBB0_85:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr10
	s_branch .LBB0_90
.LBB0_86:
	s_mov_b32 s1, -1
                                        ; implicit-def: $vgpr4
.LBB0_87:                               ; %Flow349
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_89
; %bb.88:
	v_mov_b32_e32 v4, v3
.LBB0_89:                               ; %Flow350
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v10, v4
	s_mov_b32 s1, 0
.LBB0_90:                               ; %Flow358
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_92
; %bb.91:                               ; %LeafBlock
	v_mov_b32_e32 v10, 1.0
	s_cmp_lg_u32 s28, 0
	s_cselect_b32 s0, -1, 0
.LBB0_92:                               ; %Flow357
	v_min_f32_e32 v3, v8, v9
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_94
; %bb.93:
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v10, v3
.LBB0_94:
	s_cmp_eq_u32 s29, 0
	v_mul_f32_e64 v4, s30, 4.0
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v10, v3, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, s30, 0
	v_sub_f32_e32 v5, 1.0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v4, v5, v3
	v_fma_f32 v5, s31, 4.0, 1.0
	v_max_f32_e32 v4, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, s31, 0
	v_mul_f32_e32 v4, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_f32_e32 v4, 1.0, v4
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v7, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
.LBB0_95:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14ReplaceKernelAPKfPfiiffffffffffiiff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14ReplaceKernelAPKfPfiiffffffffffiiff, .Lfunc_end0-_Z14ReplaceKernelAPKfPfiiffffffffffiiff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2884
; NumSgprs: 34
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14ReplaceKernelAPKfPfiiffffffffffiiff
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z14ReplaceKernelAPKfPfiiffffffffffiiff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
