#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>

const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)

// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
  }
}

// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
  // shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
  __shared__ double tile[TILE_DIM*TILE_DIM];

  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
  }

  __syncthreads();


  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
  }
}

// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
  // shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
  __shared__ double tile[TILE_DIM*TILE_DIM];

  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
  }

  __syncthreads();

  idx = blockIdx.y * TILE_DIM + threadIdx.x;
  idy = blockIdx.x * TILE_DIM + threadIdx.y;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
  }
}

// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
  // shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
  __shared__ double tile[TILE_DIM][TILE_DIM+1];

  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
  }

  __syncthreads();

  idx = blockIdx.y * TILE_DIM + threadIdx.x;
  idy = blockIdx.x * TILE_DIM + threadIdx.y;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
  }
}

int main(void) {
  int cols = 1<<10, rows = 1<<10;

  int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
  int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
  dim3 dimBlock(blockSizex, blockSizey, 1);
  dim3 dimGrid(grid_cols, grid_rows, 1);

  // Allocate memory in host RAM
  double *h_mat_in = new double[cols*rows];
  double *h_mat_out = new double[cols*rows];

  // Initialize h_mat_in
  std::srand(1103);
  for (int i = 0; i < rows; i++)
    for (int j = 0; j < cols; j++)
//      h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
      h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);

  // capture the GPU start time
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start, 0);

  // Allocate memory on device
  double *d_mat_in, *d_mat_out;
  cudaMalloc(&d_mat_in, cols*rows*sizeof(double));
  cudaMalloc(&d_mat_out, cols*rows*sizeof(double));

  // Copy matrix in from host to device
  cudaMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), cudaMemcpyHostToDevice);

  // Run kernel
  gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
  gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
  gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
  gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);

  // Copy result from device to host
  cudaMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), cudaMemcpyDeviceToHost);
  cudaThreadSynchronize();

  // get GPU stop time
  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);

  float elapsedTime;
  cudaEventElapsedTime(&elapsedTime, start, stop);

  // Check results
  int check_flag = 1;
  for (int i = 0; i < rows; i++)
    for (int j = 0; j < cols; j++)
      if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
        check_flag = 0;

  if (!check_flag)
    std::cout << "GPU matrix transpose not success!!!" << std::endl;
  else {
    std::cout << "GPU matrix transpose success!!!" << std::endl;
    std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
  }
  // Free memory
  cudaFree(d_mat_in);
  cudaFree(d_mat_out);
  delete [] h_mat_in;
  delete [] h_mat_out;

  return 0;
}

	.file	"tmpxft_0039c383_00000000-6_gpucpptranspose.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
	.type	_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_, @function
_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z22gpu_matrix_trans_naivePdS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_, .-_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
	.globl	_Z22gpu_matrix_trans_naivePdS_
	.type	_Z22gpu_matrix_trans_naivePdS_, @function
_Z22gpu_matrix_trans_naivePdS_:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
	.cfi_endproc
.LFE3661:
	.size	_Z22gpu_matrix_trans_naivePdS_, .-_Z22gpu_matrix_trans_naivePdS_
	.globl	_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
	.type	_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_, @function
_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z26gpu_matrix_trans_sharedmemPdS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_, .-_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
	.globl	_Z26gpu_matrix_trans_sharedmemPdS_
	.type	_Z26gpu_matrix_trans_sharedmemPdS_, @function
_Z26gpu_matrix_trans_sharedmemPdS_:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
	.cfi_endproc
.LFE3663:
	.size	_Z26gpu_matrix_trans_sharedmemPdS_, .-_Z26gpu_matrix_trans_sharedmemPdS_
	.globl	_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
	.type	_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_, @function
_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z33gpu_matrix_trans_coales_sharedmemPdS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_, .-_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
	.globl	_Z33gpu_matrix_trans_coales_sharedmemPdS_
	.type	_Z33gpu_matrix_trans_coales_sharedmemPdS_, @function
_Z33gpu_matrix_trans_coales_sharedmemPdS_:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
	.cfi_endproc
.LFE3665:
	.size	_Z33gpu_matrix_trans_coales_sharedmemPdS_, .-_Z33gpu_matrix_trans_coales_sharedmemPdS_
	.globl	_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
	.type	_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_, @function
_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L18:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_, .-_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
	.globl	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.type	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, @function
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
	.cfi_endproc
.LFE3667:
	.size	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .-_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"GPU matrix transpose not success!!!"
.LC2:
	.string	"GPU matrix transpose success!!!"
.LC3:
	.string	"GPU matrix multiplication time: "
.LC4:
	.string	" ms."
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$8388608, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$34359738400, %rax
	movl	$1, 56(%rsp)
	movl	$1, 68(%rsp)
	movq	%rax, 48(%rsp)
	movabsq	$137438953504, %rax
	movq	%rax, 60(%rsp)
	call	_Znam@PLT
	movl	$8388608, %edi
	movq	%rax, %rbx
	call	_Znam@PLT
	movl	$1103, %edi
	movq	%rax, %rbp
	call	srand@PLT
.L24:
	movq	%r13, %r14
	xorl	%r12d, %r12d
	salq	$13, %r14
	addq	%rbx, %r14
.L25:
	call	rand@PLT
	cvtsi2sdl	%eax, %xmm0
	divsd	.LC0(%rip), %xmm0
	movsd	%xmm0, (%r14,%r12,8)
	incq	%r12
	cmpq	$1024, %r12
	jne	.L25
	incq	%r13
	cmpq	$1024, %r13
	jne	.L24
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	32(%rsp), %rdi
	movl	$8388608, %esi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movl	$8388608, %esi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$8388608, %edx
	call	cudaMemcpy@PLT
	movl	56(%rsp), %ecx
	movl	68(%rsp), %esi
	xorl	%r9d, %r9d
	movq	48(%rsp), %rdx
	movq	60(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z44__device_stub__Z22gpu_matrix_trans_naivePdS_PdS_
.L27:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z48__device_stub__Z26gpu_matrix_trans_sharedmemPdS_PdS_
.L28:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z55__device_stub__Z33gpu_matrix_trans_coales_sharedmemPdS_PdS_
.L29:
	movl	56(%rsp), %ecx
	movq	48(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	60(%rsp), %rdi
	movl	68(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	_Z67__device_stub__Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_PdS_
.L30:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movl	$8388608, %edx
	movq	%rbp, %rdi
	call	cudaMemcpy@PLT
	call	cudaThreadSynchronize@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	xorl	%eax, %eax
	movl	$1, %edi
.L31:
	movq	%rax, %rcx
	leaq	0(%rbp,%rax,8), %rsi
	xorl	%edx, %edx
	salq	$13, %rcx
	addq	%rbx, %rcx
.L34:
	movsd	(%rsi), %xmm0
	ucomisd	(%rcx,%rdx,8), %xmm0
	jp	.L39
	je	.L32
.L39:
	xorl	%edi, %edi
.L32:
	incq	%rdx
	addq	$8192, %rsi
	cmpq	$1024, %rdx
	jne	.L34
	incq	%rax
	cmpq	$1024, %rax
	jne	.L31
	testl	%edi, %edi
	leaq	_ZSt4cout(%rip), %r12
	jne	.L36
	leaq	.LC1(%rip), %rsi
	movq	%r12, %rdi
	jmp	.L43
.L36:
	leaq	.LC2(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	leaq	.LC3(%rip), %rsi
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	12(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
.L43:
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	_ZdaPv@PLT
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$80, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_"
.LC6:
	.string	"_Z33gpu_matrix_trans_coales_sharedmemPdS_"
.LC7:
	.string	"_Z26gpu_matrix_trans_sharedmemPdS_"
.LC8:
	.string	"_Z22gpu_matrix_trans_naivePdS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z33gpu_matrix_trans_coales_sharedmemPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26gpu_matrix_trans_sharedmemPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22gpu_matrix_trans_naivePdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	-4194304
	.long	1105199103
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <cstdlib>
#include <ctime>

const int blockSizex = 32;
const int blockSizey = 8;
const int TILE_DIM = blockSizex;
#define imin(a, b) (a<b?a:b)

// Naive matrix transpose
__global__
void gpu_matrix_trans_naive(double *mat_in, double *mat_out) {
  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[idy + j + idx*width] = mat_in[(idy+j)*width + idx];
  }
}

// Transpose via shared memory
__global__
void gpu_matrix_trans_sharedmem(double *mat_in, double *mat_out) {
  // shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
  __shared__ double tile[TILE_DIM*TILE_DIM];

  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM] = mat_in[(idy+j)*width + idx];
  }

  __syncthreads();


  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[(idy+j)*width + idx] = tile[threadIdx.x*TILE_DIM + threadIdx.y + j];
  }
}

// Coalesced Transpose via shared memory
__global__
void gpu_matrix_trans_coales_sharedmem(double *mat_in, double *mat_out) {
  // shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
  __shared__ double tile[TILE_DIM*TILE_DIM];

  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    tile[threadIdx.x*TILE_DIM + threadIdx.y + j] = mat_in[(idy+j)*width + idx];
  }

  __syncthreads();

  idx = blockIdx.y * TILE_DIM + threadIdx.x;
  idy = blockIdx.x * TILE_DIM + threadIdx.y;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[(idy+j)*width + idx] = tile[threadIdx.x + (threadIdx.y+j)*TILE_DIM];
  }
}

// Coalesced Transpose via shared memory without bank conflict
__global__
void gpu_matrix_trans_coales_sharedmem_NoBankConfl(double *mat_in, double *mat_out) {
  // shared memory (48KB/N per block), N is the number of blocks on the same multiprocessor
  __shared__ double tile[TILE_DIM][TILE_DIM+1];

  int idx = blockIdx.x * TILE_DIM + threadIdx.x;
  int idy = blockIdx.y * TILE_DIM + threadIdx.y;
  int width = gridDim.x * TILE_DIM;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    tile[threadIdx.y+j][threadIdx.x] = mat_in[(idy+j)*width + idx];
  }

  __syncthreads();

  idx = blockIdx.y * TILE_DIM + threadIdx.x;
  idy = blockIdx.x * TILE_DIM + threadIdx.y;

  for (int j = 0; j < TILE_DIM; j += blockSizey) {
    mat_out[(idy+j)*width + idx] = tile[threadIdx.x][threadIdx.y+j];
  }
}

int main(void) {
  int cols = 1<<10, rows = 1<<10;

  int grid_cols = imin(512, (cols + TILE_DIM - 1)/TILE_DIM);
  int grid_rows = imin(512, (rows + TILE_DIM - 1)/TILE_DIM);
  dim3 dimBlock(blockSizex, blockSizey, 1);
  dim3 dimGrid(grid_cols, grid_rows, 1);

  // Allocate memory in host RAM
  double *h_mat_in = new double[cols*rows];
  double *h_mat_out = new double[cols*rows];

  // Initialize h_mat_in
  std::srand(1103);
  for (int i = 0; i < rows; i++)
    for (int j = 0; j < cols; j++)
//      h_mat_in[i*cols+j] = double (((generator() % (1000 - 0 + 1)) + 0)/1000);
      h_mat_in[i*cols+j] = double(std::rand())/double(RAND_MAX);

  // capture the GPU start time
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start, 0);

  // Allocate memory on device
  double *d_mat_in, *d_mat_out;
  hipMalloc(&d_mat_in, cols*rows*sizeof(double));
  hipMalloc(&d_mat_out, cols*rows*sizeof(double));

  // Copy matrix in from host to device
  hipMemcpy(d_mat_in, h_mat_in, cols*rows*sizeof(double), hipMemcpyHostToDevice);

  // Run kernel
  gpu_matrix_trans_naive<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
  gpu_matrix_trans_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
  gpu_matrix_trans_coales_sharedmem<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);
  gpu_matrix_trans_coales_sharedmem_NoBankConfl<<<dimGrid, dimBlock>>>(d_mat_in, d_mat_out);

  // Copy result from device to host
  hipMemcpy(h_mat_out, d_mat_out, cols*rows*sizeof(double), hipMemcpyDeviceToHost);
  hipDeviceSynchronize();

  // get GPU stop time
  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);

  float elapsedTime;
  hipEventElapsedTime(&elapsedTime, start, stop);

  // Check results
  int check_flag = 1;
  for (int i = 0; i < rows; i++)
    for (int j = 0; j < cols; j++)
      if (h_mat_out[j*rows + i] != h_mat_in[i*cols + j])
        check_flag = 0;

  if (!check_flag)
    std::cout << "GPU matrix transpose not success!!!" << std::endl;
  else {
    std::cout << "GPU matrix transpose success!!!" << std::endl;
    std::cout << "GPU matrix multiplication time: " << elapsedTime << " ms." << std::endl;
  }
  // Free memory
  hipFree(d_mat_in);
  hipFree(d_mat_out);
  delete [] h_mat_in;
  delete [] h_mat_out;

  return 0;
}

	.text
	.file	"gpucpptranspose.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z37__device_stub__gpu_matrix_trans_naivePdS_ # -- Begin function _Z37__device_stub__gpu_matrix_trans_naivePdS_
	.type	_Z37__device_stub__gpu_matrix_trans_naivePdS_,@function
_Z37__device_stub__gpu_matrix_trans_naivePdS_: # @_Z37__device_stub__gpu_matrix_trans_naivePdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22gpu_matrix_trans_naivePdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__gpu_matrix_trans_naivePdS_, .Lfunc_end0-_Z37__device_stub__gpu_matrix_trans_naivePdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_ # -- Begin function _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
	.type	_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_,@function
_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_: # @_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26gpu_matrix_trans_sharedmemPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_, .Lfunc_end1-_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_ # -- Begin function _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
	.type	_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_,@function
_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_: # @_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z33gpu_matrix_trans_coales_sharedmemPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_, .Lfunc_end2-_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_ # -- Begin function _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.type	_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@function
_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_: # @_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .Lfunc_end3-_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI4_0:
	.quad	0x41dfffffffc00000              # double 2147483647
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$8388608, %edi                  # imm = 0x800000
	callq	_Znam
	movq	%rax, %rbx
	movl	$8388608, %edi                  # imm = 0x800000
	callq	_Znam
	movq	%rax, %r14
	movl	$1103, %edi                     # imm = 0x44F
	callq	srand
	xorl	%r15d, %r15d
	movq	%rbx, %r12
.LBB4_1:                                # %.preheader99
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_2 Depth 2
	xorl	%r13d, %r13d
.LBB4_2:                                #   Parent Loop BB4_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	movsd	.LCPI4_0(%rip), %xmm1           # xmm1 = mem[0],zero
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	divsd	%xmm1, %xmm0
	movsd	%xmm0, (%r12,%r13,8)
	incq	%r13
	cmpq	$1024, %r13                     # imm = 0x400
	jne	.LBB4_2
# %bb.3:                                #   in Loop: Header=BB4_1 Depth=1
	incq	%r15
	addq	$8192, %r12                     # imm = 0x2000
	cmpq	$1024, %r15                     # imm = 0x400
	jne	.LBB4_1
# %bb.4:
	movabsq	$137438953504, %r12             # imm = 0x2000000020
	movabsq	$34359738400, %r15              # imm = 0x800000020
	leaq	32(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	8(%rsp), %r13
	movl	$8388608, %esi                  # imm = 0x800000
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$8388608, %esi                  # imm = 0x800000
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$8388608, %edx                  # imm = 0x800000
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z37__device_stub__gpu_matrix_trans_naivePdS_
.LBB4_6:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_8
# %bb.7:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
.LBB4_8:
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.9:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
.LBB4_10:
	xorl	%r13d, %r13d
	movl	$1, %ebp
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_12
# %bb.11:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
.LBB4_12:
	movq	(%rsp), %rsi
	movl	$8388608, %edx                  # imm = 0x800000
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	28(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	%r14, %rax
	movq	%rbx, %rcx
	xorl	%edx, %edx
.LBB4_13:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_14 Depth 2
	movq	%rax, %rsi
	xorl	%edi, %edi
.LBB4_14:                               #   Parent Loop BB4_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movsd	(%rsi), %xmm0                   # xmm0 = mem[0],zero
	ucomisd	(%rcx,%rdi,8), %xmm0
	cmovnel	%r13d, %ebp
	cmovpl	%r13d, %ebp
	incq	%rdi
	addq	$8192, %rsi                     # imm = 0x2000
	cmpq	$1024, %rdi                     # imm = 0x400
	jne	.LBB4_14
# %bb.15:                               #   in Loop: Header=BB4_13 Depth=1
	incq	%rdx
	addq	$8192, %rcx                     # imm = 0x2000
	addq	$8, %rax
	cmpq	$1024, %rdx                     # imm = 0x400
	jne	.LBB4_13
# %bb.16:
	movl	$_ZSt4cout, %r15d
	movl	$_ZSt4cout, %edi
	testl	%ebp, %ebp
	je	.LBB4_17
# %bb.18:
	movl	$.L.str.1, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$32, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	28(%rsp), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r15
	movl	$.L.str.3, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	jmp	.LBB4_19
.LBB4_17:
	movl	$.L.str, %esi
	movl	$35, %edx
.LBB4_19:
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	_ZdaPv
	movq	%r14, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22gpu_matrix_trans_naivePdS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26gpu_matrix_trans_sharedmemPdS_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z33gpu_matrix_trans_coales_sharedmemPdS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22gpu_matrix_trans_naivePdS_,@object # @_Z22gpu_matrix_trans_naivePdS_
	.section	.rodata,"a",@progbits
	.globl	_Z22gpu_matrix_trans_naivePdS_
	.p2align	3, 0x0
_Z22gpu_matrix_trans_naivePdS_:
	.quad	_Z37__device_stub__gpu_matrix_trans_naivePdS_
	.size	_Z22gpu_matrix_trans_naivePdS_, 8

	.type	_Z26gpu_matrix_trans_sharedmemPdS_,@object # @_Z26gpu_matrix_trans_sharedmemPdS_
	.globl	_Z26gpu_matrix_trans_sharedmemPdS_
	.p2align	3, 0x0
_Z26gpu_matrix_trans_sharedmemPdS_:
	.quad	_Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
	.size	_Z26gpu_matrix_trans_sharedmemPdS_, 8

	.type	_Z33gpu_matrix_trans_coales_sharedmemPdS_,@object # @_Z33gpu_matrix_trans_coales_sharedmemPdS_
	.globl	_Z33gpu_matrix_trans_coales_sharedmemPdS_
	.p2align	3, 0x0
_Z33gpu_matrix_trans_coales_sharedmemPdS_:
	.quad	_Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
	.size	_Z33gpu_matrix_trans_coales_sharedmemPdS_, 8

	.type	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@object # @_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.globl	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.p2align	3, 0x0
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_:
	.quad	_Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.size	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"GPU matrix transpose not success!!!"
	.size	.L.str, 36

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"GPU matrix transpose success!!!"
	.size	.L.str.1, 32

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"GPU matrix multiplication time: "
	.size	.L.str.2, 33

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" ms."
	.size	.L.str.3, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z22gpu_matrix_trans_naivePdS_"
	.size	.L__unnamed_1, 31

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z26gpu_matrix_trans_sharedmemPdS_"
	.size	.L__unnamed_2, 35

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z33gpu_matrix_trans_coales_sharedmemPdS_"
	.size	.L__unnamed_3, 42

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_"
	.size	.L__unnamed_4, 54

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__gpu_matrix_trans_naivePdS_
	.addrsig_sym _Z41__device_stub__gpu_matrix_trans_sharedmemPdS_
	.addrsig_sym _Z48__device_stub__gpu_matrix_trans_coales_sharedmemPdS_
	.addrsig_sym _Z60__device_stub__gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22gpu_matrix_trans_naivePdS_
	.addrsig_sym _Z26gpu_matrix_trans_sharedmemPdS_
	.addrsig_sym _Z33gpu_matrix_trans_coales_sharedmemPdS_
	.addrsig_sym _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22gpu_matrix_trans_naivePdS_ ; -- Begin function _Z22gpu_matrix_trans_naivePdS_
	.globl	_Z22gpu_matrix_trans_naivePdS_
	.p2align	8
	.type	_Z22gpu_matrix_trans_naivePdS_,@function
_Z22gpu_matrix_trans_naivePdS_:         ; @_Z22gpu_matrix_trans_naivePdS_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_lshl_b32 s5, s14, 5
	s_lshl_b32 s6, s15, 5
	s_load_b128 s[0:3], s[0:1], 0x0
	v_add_nc_u32_e32 v2, s5, v1
	v_add_nc_u32_e32 v3, s6, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, s4, v2
	v_mul_lo_u32 v3, s4, v3
	s_lshl_b32 s4, s4, 8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v2, 5, v2
	v_lshlrev_b32_e32 v3, 5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v2, v0, v2, s6
	v_add3_u32 v0, v1, v3, s5
	s_mov_b32 s5, -8
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s5, s5, 8
	v_add_nc_u32_e32 v5, s5, v2
	s_cmp_gt_u32 s5, 23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 3, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	global_load_b64 v[3:4], v[3:4], off
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[5:6], v[3:4], off
	s_cbranch_scc0 .LBB0_1
; %bb.2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22gpu_matrix_trans_naivePdS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22gpu_matrix_trans_naivePdS_, .Lfunc_end0-_Z22gpu_matrix_trans_naivePdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26gpu_matrix_trans_sharedmemPdS_ ; -- Begin function _Z26gpu_matrix_trans_sharedmemPdS_
	.globl	_Z26gpu_matrix_trans_sharedmemPdS_
	.p2align	8
	.type	_Z26gpu_matrix_trans_sharedmemPdS_,@function
_Z26gpu_matrix_trans_sharedmemPdS_:     ; @_Z26gpu_matrix_trans_sharedmemPdS_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x10
	v_bfe_u32 v3, v0, 10, 10
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_lshl_b32 s5, s14, 5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s15, 5, v3
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, s4, v1
	s_lshl_b32 s4, s4, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v0, 5, v1
	v_lshlrev_b32_e32 v1, 3, v4
	v_add3_u32 v0, v4, v0, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v5, v3, 8, v1
	s_mov_b32 s5, -8
	v_mov_b32_e32 v1, v0
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s5, s5, 8
	s_cmp_gt_u32 s5, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 3, v[1:2]
	v_add_nc_u32_e32 v1, s4, v1
	v_add_co_u32 v6, vcc_lo, s0, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v5, v[6:7]
	v_add_nc_u32_e32 v5, 0x800, v5
	s_cbranch_scc0 .LBB1_1
; %bb.2:
	v_lshlrev_b32_e32 v1, 3, v3
	s_mov_b32 s0, -8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v2, v4, 8, v1
.LBB1_3:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[3:4], v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v2, 64, v2
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_gt_u32 s0, 23
	v_lshlrev_b64 v[5:6], 3, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b64 v[5:6], v[3:4], off
	s_cbranch_scc0 .LBB1_3
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26gpu_matrix_trans_sharedmemPdS_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z26gpu_matrix_trans_sharedmemPdS_, .Lfunc_end1-_Z26gpu_matrix_trans_sharedmemPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 300
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z33gpu_matrix_trans_coales_sharedmemPdS_ ; -- Begin function _Z33gpu_matrix_trans_coales_sharedmemPdS_
	.globl	_Z33gpu_matrix_trans_coales_sharedmemPdS_
	.p2align	8
	.type	_Z33gpu_matrix_trans_coales_sharedmemPdS_,@function
_Z33gpu_matrix_trans_coales_sharedmemPdS_: ; @_Z33gpu_matrix_trans_coales_sharedmemPdS_
; %bb.0:
	s_load_b32 s5, s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	s_lshl_b32 s6, s15, 5
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_lshl_b32 s7, s14, 5
	v_add_nc_u32_e32 v1, s6, v2
	v_lshlrev_b32_e32 v0, 3, v2
	s_mov_b32 s8, -8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v4, v3, 8, v0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, s5, v1
	s_lshl_b32 s4, s5, 8
	v_lshlrev_b32_e32 v1, 5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v3, v1, s7
.LBB2_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s8, s8, 8
	s_cmp_gt_u32 s8, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[5:6]
	v_add_nc_u32_e32 v4, 64, v4
	s_cbranch_scc0 .LBB2_1
; %bb.2:
	v_add_nc_u32_e32 v0, s7, v2
	v_lshlrev_b32_e32 v1, 3, v3
	s_mov_b32 s0, -8
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mul_lo_u32 v0, s5, v0
	v_lshl_add_u32 v2, v2, 8, v1
	buffer_gl0_inv
	v_lshlrev_b32_e32 v0, 5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v3, v0, s6
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[3:4], v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v2, 0x800, v2
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_gt_u32 s0, 23
	v_lshlrev_b64 v[5:6], 3, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b64 v[5:6], v[3:4], off
	s_cbranch_scc0 .LBB2_3
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z33gpu_matrix_trans_coales_sharedmemPdS_
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z33gpu_matrix_trans_coales_sharedmemPdS_, .Lfunc_end2-_Z33gpu_matrix_trans_coales_sharedmemPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_ ; -- Begin function _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.globl	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
	.p2align	8
	.type	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_,@function
_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_: ; @_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
; %bb.0:
	s_load_b32 s5, s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	s_lshl_b32 s6, s15, 5
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v3, 0x3ff, v0
	s_lshl_b32 s7, s14, 5
	v_add_nc_u32_e32 v1, s6, v2
	s_mov_b32 s8, -8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v0, 3, v3
	v_mad_u32_u24 v4, 0x108, v2, v0
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v1, s5, v1
	s_lshl_b32 s4, s5, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 5, v1
	v_add3_u32 v0, v3, v1, s7
.LBB3_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s8, s8, 8
	s_cmp_gt_u32 s8, 23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 3, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v4, v[5:6]
	v_add_nc_u32_e32 v4, 0x840, v4
	s_cbranch_scc0 .LBB3_1
; %bb.2:
	v_add_nc_u32_e32 v0, s7, v2
	v_lshlrev_b32_e32 v1, 3, v2
	s_mov_b32 s0, -8
	s_waitcnt lgkmcnt(0)
	s_barrier
	v_mul_lo_u32 v0, s5, v0
	v_mad_u32_u24 v2, 0x108, v3, v1
	buffer_gl0_inv
	v_lshlrev_b32_e32 v0, 5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v0, v3, v0, s6
.LBB3_3:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b64 v[3:4], v2
	v_ashrrev_i32_e32 v1, 31, v0
	v_add_nc_u32_e32 v2, 64, v2
	s_add_i32 s0, s0, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_gt_u32 s0, 23
	v_lshlrev_b64 v[5:6], 3, v[0:1]
	v_add_nc_u32_e32 v0, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s2, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b64 v[5:6], v[3:4], off
	s_cbranch_scc0 .LBB3_3
; %bb.4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
		.amdhsa_group_segment_fixed_size 8448
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_, .Lfunc_end3-_Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8448 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22gpu_matrix_trans_naivePdS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22gpu_matrix_trans_naivePdS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26gpu_matrix_trans_sharedmemPdS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z26gpu_matrix_trans_sharedmemPdS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z33gpu_matrix_trans_coales_sharedmemPdS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z33gpu_matrix_trans_coales_sharedmemPdS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8448
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z45gpu_matrix_trans_coales_sharedmem_NoBankConflPdS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
