#include <stdio.h>
#include <stdlib.h>
#include <math.h>

#define TILE_WIDTH 16

__global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns)
{
    int i = TILE_WIDTH * blockIdx.y + threadIdx.y;
    int j = TILE_WIDTH * blockIdx.x + threadIdx.x;

    if (i < rows && j < columns)
        c[i * columns + j] = a[i * columns + j] + b[i * columns + j];
}


int m_add(int *a, int *b, int *c, int rows, int columns)
{
    int *da,
        *db,
        *dc,
        size = rows * columns * sizeof(int);

    cudaMalloc((void **)&da, size);
    cudaMalloc((void **)&db, size);
    cudaMalloc((void **)&dc, size);

    cudaMemcpy(da, a, size, cudaMemcpyHostToDevice);
    cudaMemcpy(db, b, size, cudaMemcpyHostToDevice);

    dim3 dimGrid(ceil((float)columns / TILE_WIDTH),
                 ceil((float)rows / TILE_WIDTH),
                 1);
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
    _gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns);

    cudaMemcpy(c, dc, size, cudaMemcpyDeviceToHost);
    cudaFree(da); cudaFree(db); cudaFree(dc);

    return 0;
}


int main()
{
    int *A, *B, *C;
    int i, j;

    //Input
    int linhas, colunas;

    scanf("%d", &linhas);
    scanf("%d", &colunas);

    //Alocando memória na CPU
    A = (int *)malloc(sizeof(int)*linhas*colunas);
    B = (int *)malloc(sizeof(int)*linhas*colunas);
    C = (int *)malloc(sizeof(int)*linhas*colunas);

    //Inicializar
    for(i = 0; i < linhas; i++){
        for(j = 0; j < colunas; j++){
            A[i*colunas+j] =  B[i*colunas+j] = i+j;
        }
    }

    m_add(A, B, C, linhas, colunas);

    long long int somador=0;
    //Manter esta computação na CPU
    for(i = 0; i < linhas; i++){
        for(j = 0; j < colunas; j++){
            somador+=C[i*colunas+j];
        }
    }

    printf("%lli\n", somador);

    free(A);
    free(B);
    free(C);
}

	.file	"tmpxft_00384be8_00000000-6_parallel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii
	.type	_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii, @function
_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10_gpu_m_addPiS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii, .-_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii
	.globl	_Z10_gpu_m_addPiS_S_ii
	.type	_Z10_gpu_m_addPiS_S_ii, @function
_Z10_gpu_m_addPiS_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii
	.cfi_endproc
.LFE2054:
	.size	_Z10_gpu_m_addPiS_S_ii, .-_Z10_gpu_m_addPiS_S_ii
	.globl	_Z5m_addPiS_S_ii
	.type	_Z5m_addPiS_S_ii, @function
_Z5m_addPiS_S_ii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r8d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%ecx, %ebx
	imull	%r8d, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	sall	$2, %ebx
	leaq	24(%rsp), %rdi
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	cvtsi2ssl	%ebp, %xmm0
	mulss	.LC0(%rip), %xmm0
	call	ceilf@PLT
	movss	%xmm0, 12(%rsp)
	cvtsi2ssl	%r12d, %xmm0
	mulss	.LC0(%rip), %xmm0
	call	ceilf@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	cvttss2siq	%xmm0, %rax
	movss	12(%rsp), %xmm1
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	%eax, 48(%rsp)
	cvttss2siq	%xmm1, %rax
	movl	%eax, 52(%rsp)
	movq	48(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	%r12d, %r8d
	movl	%ebp, %ecx
	movq	24(%rsp), %rdi
	call	_Z36__device_stub__Z10_gpu_m_addPiS_S_iiPiS_S_ii
.L9:
	movq	40(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rdi
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z5m_addPiS_S_ii, .-_Z5m_addPiS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"%d"
.LC2:
	.string	"%lli\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	.LC1(%rip), %rbx
	movq	%rbx, %rdi
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rsi
	call	__isoc23_scanf@PLT
	leaq	20(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	movslq	16(%rsp), %rbx
	movslq	20(%rsp), %rax
	movq	%rbx, %r13
	imulq	%rax, %rbx
	movl	%eax, 12(%rsp)
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %r12
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	12(%rsp), %r8d
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	movq	%rax, %rbx
.L13:
	cmpl	%ecx, %r13d
	jle	.L15
	movslq	%esi, %rax
	xorl	%edx, %edx
	salq	$2, %rax
.L16:
	cmpl	%edx, %r8d
	jle	.L23
	leal	(%rdx,%rcx), %edi
	incl	%edx
	movl	%edi, 0(%rbp,%rax)
	movl	%edi, (%r12,%rax)
	addq	$4, %rax
	jmp	.L16
.L23:
	incl	%ecx
	addl	%r8d, %esi
	jmp	.L13
.L15:
	movl	%r13d, %ecx
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movq	%r12, %rdi
	call	_Z5m_addPiS_S_ii
	movl	16(%rsp), %r9d
	movl	20(%rsp), %edi
	xorl	%ecx, %ecx
	xorl	%edx, %edx
	xorl	%esi, %esi
.L17:
	cmpl	%esi, %r9d
	jle	.L19
	movslq	%ecx, %rax
	leaq	(%rbx,%rax,4), %r8
	xorl	%eax, %eax
.L20:
	cmpl	%eax, %edi
	jle	.L24
	movslq	(%r8,%rax,4), %r10
	incq	%rax
	addq	%r10, %rdx
	jmp	.L20
.L24:
	incl	%esi
	addl	%edi, %ecx
	jmp	.L17
.L19:
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z10_gpu_m_addPiS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10_gpu_m_addPiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	1031798784
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>

#define TILE_WIDTH 16

__global__ void _gpu_m_add(int *a, int *b, int *c, int rows, int columns)
{
    int i = TILE_WIDTH * blockIdx.y + threadIdx.y;
    int j = TILE_WIDTH * blockIdx.x + threadIdx.x;

    if (i < rows && j < columns)
        c[i * columns + j] = a[i * columns + j] + b[i * columns + j];
}


int m_add(int *a, int *b, int *c, int rows, int columns)
{
    int *da,
        *db,
        *dc,
        size = rows * columns * sizeof(int);

    hipMalloc((void **)&da, size);
    hipMalloc((void **)&db, size);
    hipMalloc((void **)&dc, size);

    hipMemcpy(da, a, size, hipMemcpyHostToDevice);
    hipMemcpy(db, b, size, hipMemcpyHostToDevice);

    dim3 dimGrid(ceil((float)columns / TILE_WIDTH),
                 ceil((float)rows / TILE_WIDTH),
                 1);
    dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
    _gpu_m_add<<<dimGrid, dimBlock>>>(da, db, dc, rows, columns);

    hipMemcpy(c, dc, size, hipMemcpyDeviceToHost);
    hipFree(da); hipFree(db); hipFree(dc);

    return 0;
}


int main()
{
    int *A, *B, *C;
    int i, j;

    //Input
    int linhas, colunas;

    scanf("%d", &linhas);
    scanf("%d", &colunas);

    //Alocando memória na CPU
    A = (int *)malloc(sizeof(int)*linhas*colunas);
    B = (int *)malloc(sizeof(int)*linhas*colunas);
    C = (int *)malloc(sizeof(int)*linhas*colunas);

    //Inicializar
    for(i = 0; i < linhas; i++){
        for(j = 0; j < colunas; j++){
            A[i*colunas+j] =  B[i*colunas+j] = i+j;
        }
    }

    m_add(A, B, C, linhas, colunas);

    long long int somador=0;
    //Manter esta computação na CPU
    for(i = 0; i < linhas; i++){
        for(j = 0; j < colunas; j++){
            somador+=C[i*colunas+j];
        }
    }

    printf("%lli\n", somador);

    free(A);
    free(B);
    free(C);
}

	.text
	.file	"parallel.hip"
	.globl	_Z25__device_stub___gpu_m_addPiS_S_ii # -- Begin function _Z25__device_stub___gpu_m_addPiS_S_ii
	.type	_Z25__device_stub___gpu_m_addPiS_S_ii,@function
_Z25__device_stub___gpu_m_addPiS_S_ii:  # @_Z25__device_stub___gpu_m_addPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10_gpu_m_addPiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub___gpu_m_addPiS_S_ii, .Lfunc_end0-_Z25__device_stub___gpu_m_addPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function _Z5m_addPiS_S_ii
.LCPI1_0:
	.long	0x3d800000                      # float 0.0625
	.text
	.globl	_Z5m_addPiS_S_ii
	.type	_Z5m_addPiS_S_ii,@function
_Z5m_addPiS_S_ii:                       # @_Z5m_addPiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %ebp
	movl	%ecx, %r15d
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
	movq	%rsi, 24(%rsp)                  # 8-byte Spill
	movq	%rdi, %r13
	movl	%ecx, %eax
	imull	%r8d, %eax
	shll	$2, %eax
	movslq	%eax, %r14
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r13, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2ss	%ebp, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rbx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15d, %xmm0
	mulss	.LCPI1_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %rdi
	movl	%ebx, %eax
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movl	%r15d, %ecx
	movl	%ebp, %r8d
	callq	_Z25__device_stub___gpu_m_addPiS_S_ii
.LBB1_2:
	movq	(%rsp), %rsi
	movq	32(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z5m_addPiS_S_ii, .Lfunc_end1-_Z5m_addPiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%r12d, %r12d
	leaq	4(%rsp), %rbx
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movq	%rsp, %r14
	movl	$.L.str, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movslq	(%rbx), %r13
	movslq	(%r14), %rbp
	movq	%r13, %r15
	imulq	%rbp, %r15
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %rbx
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r14
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r15
	movl	%r13d, %ecx
	movl	%ebp, %r8d
	testq	%r13, %r13
	jle	.LBB2_6
# %bb.1:                                # %.preheader34.lr.ph
	xorl	%eax, %eax
.LBB2_2:                                # %.preheader34
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
	testl	%r8d, %r8d
	jle	.LBB2_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	movl	%r12d, %esi
	leaq	(%rbx,%rsi,4), %rdx
	leaq	(%r14,%rsi,4), %rsi
	xorl	%edi, %edi
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rax,%rdi), %r9d
	movl	%r9d, (%rsi,%rdi,4)
	movl	%r9d, (%rdx,%rdi,4)
	incq	%rdi
	cmpq	%rdi, %r8
	jne	.LBB2_4
.LBB2_5:                                # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	incq	%rax
	addl	%r8d, %r12d
	cmpq	%rcx, %rax
	jne	.LBB2_2
.LBB2_6:                                # %._crit_edge37
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
                                        # kill: def $ecx killed $ecx killed $rcx
                                        # kill: def $r8d killed $r8d killed $r8
	callq	_Z5m_addPiS_S_ii
	movl	4(%rsp), %eax
	xorl	%ecx, %ecx
	testl	%eax, %eax
	jle	.LBB2_7
# %bb.8:                                # %.preheader.lr.ph
	movl	(%rsp), %edx
	xorl	%edi, %edi
	xorl	%esi, %esi
.LBB2_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_11 Depth 2
	testl	%edx, %edx
	jle	.LBB2_12
# %bb.10:                               # %.lr.ph40
                                        #   in Loop: Header=BB2_9 Depth=1
	movl	%ecx, %r8d
	leaq	(%r15,%r8,4), %r8
	xorl	%r9d, %r9d
.LBB2_11:                               #   Parent Loop BB2_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	(%r8,%r9,4), %r10
	addq	%r10, %rsi
	incq	%r9
	cmpq	%r9, %rdx
	jne	.LBB2_11
.LBB2_12:                               # %._crit_edge41
                                        #   in Loop: Header=BB2_9 Depth=1
	incq	%rdi
	addl	%edx, %ecx
	cmpq	%rax, %rdi
	jne	.LBB2_9
	jmp	.LBB2_13
.LBB2_7:
	xorl	%esi, %esi
.LBB2_13:                               # %._crit_edge44
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10_gpu_m_addPiS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10_gpu_m_addPiS_S_ii,@object  # @_Z10_gpu_m_addPiS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z10_gpu_m_addPiS_S_ii
	.p2align	3, 0x0
_Z10_gpu_m_addPiS_S_ii:
	.quad	_Z25__device_stub___gpu_m_addPiS_S_ii
	.size	_Z10_gpu_m_addPiS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%lli\n"
	.size	.L.str.1, 6

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10_gpu_m_addPiS_S_ii"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub___gpu_m_addPiS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10_gpu_m_addPiS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10_gpu_m_addPiS_S_ii  ; -- Begin function _Z10_gpu_m_addPiS_S_ii
	.globl	_Z10_gpu_m_addPiS_S_ii
	.p2align	8
	.type	_Z10_gpu_m_addPiS_S_ii,@function
_Z10_gpu_m_addPiS_S_ii:                 ; @_Z10_gpu_m_addPiS_S_ii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x18
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, s15, 4, v1
	v_lshl_add_u32 v0, s14, 4, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	v_cmp_gt_i32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10_gpu_m_addPiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10_gpu_m_addPiS_S_ii, .Lfunc_end0-_Z10_gpu_m_addPiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 208
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10_gpu_m_addPiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10_gpu_m_addPiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
