#include <iostream>

using namespace std;

using T = double;

constexpr T range_min = 2.0;
constexpr T range_max = 4.0;
constexpr T range = range_max - range_min;

constexpr auto all_threads = 4096;
constexpr auto block_size = 16;
constexpr auto thread_size = all_threads / block_size;
constexpr auto warmup = 300;
constexpr auto loops = 1000;

__device__ T get_a() {
    return // 2 * log2(2 + range / thread_size * threadIdx.x);
        range_min +
        // ((T)thread_size) / ((T)threadIdx.x) * range
        range / (thread_size * block_size) *
            (blockIdx.x * thread_size + threadIdx.x);
}

__global__ void logistic() {
    const auto a = get_a();
    T x = 0.8;
    for(int index = 0; index < warmup; index++) {
        x = a * x * (1 - x);
    }
    for(int index = warmup; index < loops; index++) {
        printf("%1.8lf %1.8lf\n", a, x);
        x = a * x * (1 - x);
    }
}

int main() {
    // size_t nBytes = loops * (thread_size + 1) * sizeof(T);
    // T *x;
    // cudaMalloc((void **)&x, nBytes);
    logistic<<<block_size, thread_size>>>();
    // cudaFree(x);
    cudaDeviceReset();
}

	.file	"tmpxft_00303ec4_00000000-6_logistic.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z5get_av
	.type	_Z5get_av, @function
_Z5get_av:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z5get_av, .-_Z5get_av
	.globl	_Z26__device_stub__Z8logisticvv
	.type	_Z26__device_stub__Z8logisticvv, @function
_Z26__device_stub__Z8logisticvv:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	movabsq	$4294967297, %rax
	leaq	8(%rsp), %rcx
	movq	%rsp, %rdx
	leaq	28(%rsp), %rsi
	leaq	16(%rsp), %rdi
	movl	$1, 24(%rsp)
	movl	$1, 36(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 28(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	8(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z8logisticv(%rip), %rdi
	pushq	8(%rsp)
	.cfi_def_cfa_offset 112
	movq	44(%rsp), %rcx
	movl	52(%rsp), %r8d
	movq	32(%rsp), %rsi
	movl	40(%rsp), %edx
	leaq	80(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L4:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z26__device_stub__Z8logisticvv, .-_Z26__device_stub__Z8logisticvv
	.globl	_Z8logisticv
	.type	_Z8logisticv, @function
_Z8logisticv:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z8logisticvv
	.cfi_endproc
.LFE3662:
	.size	_Z8logisticv, .-_Z8logisticv
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	movl	$16777217, %edx
	movl	$268435457, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	salq	$8, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$4, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	call	_Z26__device_stub__Z8logisticvv
.L11:
	call	cudaDeviceReset@PLT
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8logisticv"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z8logisticv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>

using namespace std;

using T = double;

constexpr T range_min = 2.0;
constexpr T range_max = 4.0;
constexpr T range = range_max - range_min;

constexpr auto all_threads = 4096;
constexpr auto block_size = 16;
constexpr auto thread_size = all_threads / block_size;
constexpr auto warmup = 300;
constexpr auto loops = 1000;

__device__ T get_a() {
    return // 2 * log2(2 + range / thread_size * threadIdx.x);
        range_min +
        // ((T)thread_size) / ((T)threadIdx.x) * range
        range / (thread_size * block_size) *
            (blockIdx.x * thread_size + threadIdx.x);
}

__global__ void logistic() {
    const auto a = get_a();
    T x = 0.8;
    for(int index = 0; index < warmup; index++) {
        x = a * x * (1 - x);
    }
    for(int index = warmup; index < loops; index++) {
        printf("%1.8lf %1.8lf\n", a, x);
        x = a * x * (1 - x);
    }
}

int main() {
    // size_t nBytes = loops * (thread_size + 1) * sizeof(T);
    // T *x;
    // cudaMalloc((void **)&x, nBytes);
    logistic<<<block_size, thread_size>>>();
    // cudaFree(x);
    hipDeviceReset();
}

	.text
	.file	"logistic.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z23__device_stub__logisticv    # -- Begin function _Z23__device_stub__logisticv
	.type	_Z23__device_stub__logisticv,@function
_Z23__device_stub__logisticv:           # @_Z23__device_stub__logisticv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rbx
	leaq	24(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movq	%r12, %rcx
	callq	__hipPopCallConfiguration
	movq	(%rbx), %rsi
	movl	8(%rbx), %edx
	movq	(%r14), %rcx
	movl	8(%r14), %r8d
	movq	%rsp, %r9
	movl	$_Z8logisticv, %edi
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	pushq	(%r15)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$72, %rsp
	.cfi_adjust_cfa_offset -72
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__logisticv, .Lfunc_end0-_Z23__device_stub__logisticv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movabsq	$4294967312, %rdi               # imm = 0x100000010
	leaq	240(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	callq	_Z23__device_stub__logisticv
.LBB1_2:
	callq	hipDeviceReset
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8logisticv, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8logisticv,@object            # @_Z8logisticv
	.section	.rodata,"a",@progbits
	.globl	_Z8logisticv
	.p2align	3, 0x0
_Z8logisticv:
	.quad	_Z23__device_stub__logisticv
	.size	_Z8logisticv, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z8logisticv"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__logisticv
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8logisticv
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8logisticv            ; -- Begin function _Z8logisticv
	.globl	_Z8logisticv
	.p2align	8
	.type	_Z8logisticv,@function
_Z8logisticv:                           ; @_Z8logisticv
; %bb.0:
	v_lshl_add_u32 v0, s15, 8, v0
	s_mov_b32 s2, 0x9999999a
	s_mov_b32 s3, 0x3fe99999
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	v_cvt_f64_u32_e32 v[0:1], v0
	s_movk_i32 s2, 0x12c
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[33:34], 0x3f400000, v[0:1], 2.0
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[0:1], v[33:34], v[2:3]
	v_add_f64 v[2:3], -v[2:3], 1.0
	s_add_i32 s2, s2, -1
	s_cmp_eq_u32 s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	s_cbranch_scc0 .LBB0_1
; %bb.2:                                ; %.preheader34
	s_load_b64 s[2:3], s[0:1], 0x50
	v_mbcnt_lo_u32_b32 v35, -1, 0
	v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, 2
	v_mov_b32_e32 v4, 33
	v_mov_b32_e32 v10, 1
	s_mov_b32 s4, 0
	s_movk_i32 s16, 0x12c
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
                                        ;     Child Loop BB0_14 Depth 2
                                        ;     Child Loop BB0_20 Depth 2
                                        ;     Child Loop BB0_29 Depth 2
                                        ;     Child Loop BB0_32 Depth 2
                                        ;       Child Loop BB0_35 Depth 3
                                        ;       Child Loop BB0_43 Depth 3
                                        ;       Child Loop BB0_51 Depth 3
                                        ;       Child Loop BB0_59 Depth 3
                                        ;       Child Loop BB0_67 Depth 3
                                        ;       Child Loop BB0_75 Depth 3
                                        ;       Child Loop BB0_83 Depth 3
                                        ;       Child Loop BB0_91 Depth 3
                                        ;       Child Loop BB0_99 Depth 3
                                        ;       Child Loop BB0_105 Depth 3
                                        ;       Child Loop BB0_114 Depth 3
                                        ;     Child Loop BB0_122 Depth 2
                                        ;     Child Loop BB0_130 Depth 2
                                        ;     Child Loop BB0_136 Depth 2
                                        ;     Child Loop BB0_145 Depth 2
                                        ;     Child Loop BB0_150 Depth 2
                                        ;     Child Loop BB0_158 Depth 2
                                        ;     Child Loop BB0_164 Depth 2
                                        ;     Child Loop BB0_173 Depth 2
                                        ;     Child Loop BB0_177 Depth 2
                                        ;     Child Loop BB0_185 Depth 2
                                        ;     Child Loop BB0_191 Depth 2
                                        ;     Child Loop BB0_200 Depth 2
	v_dual_mov_b32 v5, v35 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_9
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[13:14], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v14
	v_and_b32_e32 v0, v0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[13:14]
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s6, 0
.LBB0_6:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[13:14]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %Flow428
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_8:                                ; %Flow430
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_9:                                ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[11:14], v6, s[2:3]
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[8:9], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s10, s6, 24
	s_mul_i32 s11, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v6
	s_add_i32 s5, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v11, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v12, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_11:                               ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v14, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v16, s7
	v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v14, s5
	v_mov_b32_e32 v15, s6
	v_mov_b32_e32 v13, s4
	s_clause 0x3
	global_store_b128 v[0:1], v[4:7], off
	global_store_b128 v[0:1], v[13:16], off offset:16
	global_store_b128 v[0:1], v[13:16], off offset:32
	global_store_b128 v[0:1], v[13:16], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_19
; %bb.12:                               ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s8 :: v_dual_mov_b32 v16, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[8:9]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s12, s12, s7
	v_add_co_u32 v7, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v12, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[7:8], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_15
; %bb.13:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s7, 0
.LBB0_14:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v13, s8 :: v_dual_mov_b32 v14, s9
	s_sleep 1
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_14
.LBB0_15:                               ; %Flow426
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v5, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_3 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_17:                               ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[5:6], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_19:                               ; %Flow427
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s10, s10, s1
	v_add_co_u32 v5, vcc_lo, v11, s11
	v_add_co_ci_u32_e32 v8, vcc_lo, s10, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_20:                               ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=2
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_22:                               ;   in Loop: Header=BB0_20 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_20 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_25
.LBB0_24:                               ;   in Loop: Header=BB0_20 Depth=2
	s_mov_b32 s1, -1
.LBB0_25:                               ; %Flow421
                                        ;   in Loop: Header=BB0_20 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_20
; %bb.26:                               ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[11:12], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_30
; %bb.27:                               ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v5, s8
	v_add_co_ci_u32_e32 v14, vcc_lo, s9, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_cndmask_b32_e32 v13, v13, v5, vcc_lo
	v_cndmask_b32_e32 v14, v14, v17, vcc_lo
	v_and_b32_e32 v0, v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, v0
	v_mov_b32_e32 v15, v7
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v16, v1, vcc_lo
	v_mov_b32_e32 v16, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_30
; %bb.28:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
.LBB0_29:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[15:16]
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_29
.LBB0_30:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_117
; %bb.31:                               ;   in Loop: Header=BB0_3 Depth=1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v36, 2, v11
	v_dual_mov_b32 v14, v12 :: v_dual_and_b32 v13, -3, v11
	s_mov_b64 s[8:9], 15
.LBB0_32:                               ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_35 Depth 3
                                        ;       Child Loop BB0_43 Depth 3
                                        ;       Child Loop BB0_51 Depth 3
                                        ;       Child Loop BB0_59 Depth 3
                                        ;       Child Loop BB0_67 Depth 3
                                        ;       Child Loop BB0_75 Depth 3
                                        ;       Child Loop BB0_83 Depth 3
                                        ;       Child Loop BB0_91 Depth 3
                                        ;       Child Loop BB0_99 Depth 3
                                        ;       Child Loop BB0_105 Depth 3
                                        ;       Child Loop BB0_114 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[8:9], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s10, s8, 56
	s_cselect_b32 s11, s9, 0
	s_cmp_gt_u32 s10, 7
	s_cbranch_scc1 .LBB0_37
; %bb.33:                               ;   in Loop: Header=BB0_32 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB0_36
; %bb.34:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_lshl_b64 s[0:1], s[10:11], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[6:7]
.LBB0_35:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v0, v6, s[14:15]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s12, v[5:6]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s0, s12
	v_or_b32_e32 v15, v0, v15
	v_or_b32_e32 v16, v1, v16
	s_cbranch_scc1 .LBB0_35
.LBB0_36:                               ; %Flow397
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_38
.LBB0_37:                               ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr5
.LBB0_38:                               ; %Flow399
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[6:7]
	s_cbranch_vccnz .LBB0_40
; %bb.39:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[15:16], v6, s[6:7]
	s_add_i32 s5, s10, -8
	s_add_u32 s0, s6, 8
	s_addc_u32 s1, s7, 0
.LBB0_40:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_45
; %bb.41:                               ;   in Loop: Header=BB0_32 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_44
; %bb.42:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_43:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v0, v6, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s12, v[5:6]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s5, s14
	v_or_b32_e32 v17, v0, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v1, v18
	s_cbranch_scc1 .LBB0_43
.LBB0_44:                               ; %Flow392
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB0_46
.LBB0_45:                               ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr17
.LBB0_46:                               ; %Flow394
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_48
; %bb.47:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[17:18], v6, s[0:1]
	s_add_i32 s17, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_48:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB0_53
; %bb.49:                               ;   in Loop: Header=BB0_32 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB0_52
; %bb.50:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_51:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v0, v6, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s12, v[5:6]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v19, v0, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v1, v20
	s_cbranch_scc1 .LBB0_51
.LBB0_52:                               ; %Flow387
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_54
.LBB0_53:                               ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr5
.LBB0_54:                               ; %Flow389
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_56
; %bb.55:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[19:20], v6, s[0:1]
	s_add_i32 s5, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_56:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_61
; %bb.57:                               ;   in Loop: Header=BB0_32 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_60
; %bb.58:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_59:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v0, v6, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s12, v[5:6]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s5, s14
	v_or_b32_e32 v21, v0, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v1, v22
	s_cbranch_scc1 .LBB0_59
.LBB0_60:                               ; %Flow382
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB0_62
.LBB0_61:                               ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr17
.LBB0_62:                               ; %Flow384
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_64
; %bb.63:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[21:22], v6, s[0:1]
	s_add_i32 s17, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_64:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB0_69
; %bb.65:                               ;   in Loop: Header=BB0_32 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB0_68
; %bb.66:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_67:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v0, v6, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s12, v[5:6]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v23, v0, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v1, v24
	s_cbranch_scc1 .LBB0_67
.LBB0_68:                               ; %Flow377
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_70
.LBB0_69:                               ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr5
.LBB0_70:                               ; %Flow379
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[23:24], v6, s[0:1]
	s_add_i32 s5, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_72:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_77
; %bb.73:                               ;   in Loop: Header=BB0_32 Depth=2
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_76
; %bb.74:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_75:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v0, v6, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s12, v[5:6]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s5, s14
	v_or_b32_e32 v25, v0, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v26, v1, v26
	s_cbranch_scc1 .LBB0_75
.LBB0_76:                               ; %Flow372
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB0_78
.LBB0_77:                               ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr17
.LBB0_78:                               ; %Flow374
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_80
; %bb.79:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[25:26], v6, s[0:1]
	s_add_i32 s17, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_80:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB0_85
; %bb.81:                               ;   in Loop: Header=BB0_32 Depth=2
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB0_84
; %bb.82:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[0:1]
.LBB0_83:                               ; %.preheader.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v0, v6, s[14:15]
	s_add_i32 s17, s17, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s12, v[5:6]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s17, 0
	v_or_b32_e32 v27, v0, v27
	v_or_b32_e32 v28, v1, v28
	s_cbranch_scc1 .LBB0_83
.LBB0_84:                               ; %Flow367
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s5, 0
	s_branch .LBB0_86
.LBB0_85:                               ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s5, -1
.LBB0_86:                               ; %Flow369
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_88
; %bb.87:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[27:28], v6, s[0:1]
.LBB0_88:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	v_dual_mov_b32 v5, v35 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_94
; %bb.89:                               ;   in Loop: Header=BB0_32 Depth=2
	global_load_b64 v[31:32], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v32
	v_and_b32_e32 v0, v0, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v29, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v29, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[29:30], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[29:32], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[31:32]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s12, 0
.LBB0_91:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[29:30], v6, s[2:3]
	v_dual_mov_b32 v32, v1 :: v_dual_mov_b32 v31, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v31
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[29:30]
	v_and_b32_e32 v29, v8, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v29, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[29:30], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[29:32], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[31:32]
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow362
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_93:                               ; %Flow364
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_94:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[29:32], v6, s[2:3]
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_mov_b32 s18, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v7
	v_readfirstlane_b32 s15, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[12:13], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s5, s14, 24
	s_mul_i32 s17, s14, 24
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB0_96
; %bb.95:                               ;   in Loop: Header=BB0_32 Depth=2
	v_dual_mov_b32 v7, s18 :: v_dual_mov_b32 v8, v6
	s_add_i32 s18, s5, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v29, s17
	v_add_co_ci_u32_e32 v1, vcc_lo, s18, v30, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_96:                               ;   in Loop: Header=BB0_32 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
	v_or_b32_e32 v0, 0, v14
	v_or_b32_e32 v1, v13, v36
	s_lshl_b64 s[14:15], s[14:15], 12
	s_lshl_b32 s18, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s18, s18, 28
	v_dual_cndmask_b32 v14, v0, v14 :: v_dual_cndmask_b32 v7, v1, v13
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v31, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v32, vcc_lo
	s_and_b32 s18, s18, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v5, v0
	v_and_or_b32 v13, 0xffffff1f, v7, s18
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[21:24], off offset:32
	global_store_b128 v[0:1], v[25:28], off offset:48
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_104
; %bb.97:                               ;   in Loop: Header=BB0_32 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s12 :: v_dual_mov_b32 v16, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v7
	v_readfirstlane_b32 s19, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[18:19], s[12:13]
	s_mul_i32 s15, s19, 24
	s_mul_hi_u32 s19, s18, 24
	s_mul_i32 s18, s18, 24
	s_add_i32 s19, s19, s15
	v_add_co_u32 v7, vcc_lo, v29, s18
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v30, vcc_lo
	s_mov_b32 s15, exec_lo
	global_store_b64 v[7:8], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s18, 0
.LBB0_99:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13
	s_sleep 1
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow360
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s18, exec_lo
	s_mov_b32 s15, exec_lo
	v_mbcnt_lo_u32_b32 v5, s18, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_102
; %bb.101:                              ;   in Loop: Header=BB0_32 Depth=2
	s_bcnt1_i32_b32 s18, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s18
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_102:                              ;   in Loop: Header=BB0_32 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_32 Depth=2
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s15, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[5:6], off
	s_and_b32 m0, s15, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow361
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_or_b32 exec_lo, exec_lo, s14
	s_add_i32 s5, s5, s1
	v_add_co_u32 v5, vcc_lo, v29, s17
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_105:                              ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=3
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=3
	s_mov_b32 s1, -1
.LBB0_110:                              ; %Flow355
                                        ;   in Loop: Header=BB0_105 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_105
; %bb.111:                              ;   in Loop: Header=BB0_32 Depth=2
	global_load_b128 v[13:16], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_115
; %bb.112:                              ;   in Loop: Header=BB0_32 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[17:18], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v19 :: v_dual_cndmask_b32 v15, v15, v5
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v17, v0
	v_mov_b32_e32 v17, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v18, v1, vcc_lo
	v_mov_b32_e32 v18, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[17:18]
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s8, s8, s10
	s_subb_u32 s9, s9, s11
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc1 .LBB0_32
; %bb.116:                              ; %Flow400
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_118
.LBB0_117:                              ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_118:                              ; %Flow415
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_147
; %bb.119:                              ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v5, v35 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_125
; %bb.120:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[15:16], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v16
	v_and_b32_e32 v0, v0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[15:16]
	s_cbranch_execz .LBB0_124
; %bb.121:                              ; %.preheader3.i.i.i18.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s6, 0
.LBB0_122:                              ; %.preheader3.i.i.i18
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[13:14], v6, s[2:3]
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v15, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[13:14]
	v_and_b32_e32 v13, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[15:16]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_122
; %bb.123:                              ; %Flow412
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_124:                              ; %Flow414
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_125:                              ; %.loopexit4.i.i.i13
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[15:18], v6, s[2:3]
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[8:9], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s10, s6, 24
	s_mul_i32 s11, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_127
; %bb.126:                              ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v6
	s_add_i32 s5, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v16, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_127:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v17, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v18, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v11, 0xffffff1f, v11, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v13, v6 :: v_dual_mov_b32 v20, s7
	v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v19, s6
	v_dual_mov_b32 v18, s5 :: v_dual_mov_b32 v17, s4
	s_clause 0x3
	global_store_b128 v[0:1], v[11:14], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[17:20], off offset:32
	global_store_b128 v[0:1], v[17:20], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_135
; %bb.128:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b64 v[19:20], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v17, s8 :: v_dual_mov_b32 v18, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[8:9]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s12, s12, s7
	v_add_co_u32 v7, vcc_lo, v15, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v16, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[7:8], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[17:20], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_131
; %bb.129:                              ; %.preheader1.i.i.i16.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s7, 0
.LBB0_130:                              ; %.preheader1.i.i.i16
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v12, s9
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_130
.LBB0_131:                              ; %Flow410
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v5, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_133
; %bb.132:                              ;   in Loop: Header=BB0_3 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_133:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_135
; %bb.134:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[5:6], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_135:                              ; %Flow411
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s10, s10, s1
	v_add_co_u32 v5, vcc_lo, v15, s11
	v_add_co_ci_u32_e32 v8, vcc_lo, s10, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_136:                              ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_136 Depth=2
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_138:                              ;   in Loop: Header=BB0_136 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_140
; %bb.139:                              ;   in Loop: Header=BB0_136 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_141
.LBB0_140:                              ;   in Loop: Header=BB0_136 Depth=2
	s_mov_b32 s1, -1
.LBB0_141:                              ; %Flow405
                                        ;   in Loop: Header=BB0_136 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_136
; %bb.142:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b128 v[13:16], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_146
; %bb.143:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[11:12], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v18, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v5, s8
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_mov_b32 v17, v7
	v_cndmask_b32_e32 v15, v15, v5, vcc_lo
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v11, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_146
; %bb.144:                              ; %.preheader.i.i.i15.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
.LBB0_145:                              ; %.preheader.i.i.i15
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[17:18]
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_145
.LBB0_146:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_147:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v5, v35 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_153
; %bb.148:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[17:18], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v18
	v_and_b32_e32 v0, v0, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[17:18]
	s_cbranch_execz .LBB0_152
; %bb.149:                              ; %.preheader3.i.i.i25.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s6, 0
.LBB0_150:                              ; %.preheader3.i.i.i25
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v17, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v17
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[17:18]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_150
; %bb.151:                              ; %Flow348
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_152:                              ; %Flow350
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_153:                              ; %.loopexit4.i.i.i19
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[17:20], v6, s[2:3]
	v_readfirstlane_b32 s8, v0
	v_readfirstlane_b32 s9, v1
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[8:9], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s10, s6, 24
	s_mul_i32 s11, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_155
; %bb.154:                              ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v6
	s_add_i32 s5, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v17, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v18, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_155:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v19, s6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v20, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v13, 0xffffff1f, v13, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v15, v33 :: v_dual_mov_b32 v16, v34
	v_dual_mov_b32 v22, s7 :: v_dual_mov_b32 v21, s6
	v_dual_mov_b32 v20, s5 :: v_dual_mov_b32 v19, s4
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[19:22], off offset:16
	global_store_b128 v[0:1], v[19:22], off offset:32
	global_store_b128 v[0:1], v[19:22], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_163
; %bb.156:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v13, s8 :: v_dual_mov_b32 v14, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v7
	v_readfirstlane_b32 s7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[8:9]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s12, s12, s7
	v_add_co_u32 v7, vcc_lo, v17, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s12, v18, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[15:16]
	s_cbranch_execz .LBB0_159
; %bb.157:                              ; %.preheader1.i.i.i23.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s7, 0
.LBB0_158:                              ; %.preheader1.i.i.i23
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v12, s9
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_158
.LBB0_159:                              ; %Flow346
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v5, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_161
; %bb.160:                              ;   in Loop: Header=BB0_3 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_161:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_163
; %bb.162:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[5:6], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_163:                              ; %Flow347
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s10, s10, s1
	v_add_co_u32 v5, vcc_lo, v17, s11
	v_add_co_ci_u32_e32 v8, vcc_lo, s10, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_164:                              ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_166
; %bb.165:                              ;   in Loop: Header=BB0_164 Depth=2
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_166:                              ;   in Loop: Header=BB0_164 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_168
; %bb.167:                              ;   in Loop: Header=BB0_164 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_169
.LBB0_168:                              ;   in Loop: Header=BB0_164 Depth=2
	s_mov_b32 s1, -1
.LBB0_169:                              ; %Flow341
                                        ;   in Loop: Header=BB0_164 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_164
; %bb.170:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_174
; %bb.171:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x2
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[15:16], v6, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v7, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v5, s8
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v5, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v12, v8
	v_mul_hi_u32 v8, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v5, v8, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v13, v7
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v8, vcc_lo, v14, v5, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_174
; %bb.172:                              ; %.preheader.i.i.i22.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
.LBB0_173:                              ; %.preheader.i.i.i22
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_173
.LBB0_174:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, v35
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v5
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_180
; %bb.175:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b64 v[13:14], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v14
	v_and_b32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, 24
	v_mul_hi_u32 v15, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v15, v8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	global_load_b64 v[11:12], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[13:14]
	s_cbranch_execz .LBB0_179
; %bb.176:                              ; %.preheader3.i.i.i32.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s6, 0
.LBB0_177:                              ; %.preheader3.i.i.i32
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v6, s[2:3] offset:40
	global_load_b64 v[15:16], v6, s[2:3]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[15:16]
	v_and_b32_e32 v15, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v15, 24, v[8:9]
	v_mov_b32_e32 v8, v11
	global_load_b64 v[11:12], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_177
; %bb.178:                              ; %Flow334
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_179:                              ; %Flow336
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_180:                              ; %.loopexit4.i.i.i26
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[2:3] offset:40
	global_load_b128 v[11:14], v6, s[2:3]
	v_readfirstlane_b32 s8, v7
	v_readfirstlane_b32 s9, v8
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v15
	v_readfirstlane_b32 s7, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[8:9], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s10, s6, 24
	s_mul_i32 s11, s6, 24
	s_and_saveexec_b32 s12, s0
	s_cbranch_execz .LBB0_182
; %bb.181:                              ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v8, v6
	s_add_i32 s5, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v11, s11
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v12, vcc_lo
	global_store_b128 v[15:16], v[7:10], off offset:8
.LBB0_182:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v13, v7
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v8, vcc_lo, v14, v8, vcc_lo
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v15, s6
	v_dual_mov_b32 v14, s5 :: v_dual_mov_b32 v13, s4
	s_clause 0x3
	global_store_b128 v[7:8], v[0:3], off
	global_store_b128 v[7:8], v[13:16], off offset:16
	global_store_b128 v[7:8], v[13:16], off offset:32
	global_store_b128 v[7:8], v[13:16], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_190
; %bb.183:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s8 :: v_dual_mov_b32 v16, s9
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[8:9]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s12, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s12, s12, s7
	v_add_co_u32 v0, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v12, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_186
; %bb.184:                              ; %.preheader1.i.i.i30.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s7, 0
.LBB0_185:                              ; %.preheader1.i.i.i30
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v13, s8 :: v_dual_mov_b32 v14, s9
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[15:16]
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_185
.LBB0_186:                              ; %Flow332
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[0:1], v6, s[2:3] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v5, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_188
; %bb.187:                              ;   in Loop: Header=BB0_3 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[5:6], off offset:8
.LBB0_188:                              ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_190
; %bb.189:                              ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v5, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[5:6], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_190:                              ; %Flow333
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v11, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_191:                              ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_193
; %bb.192:                              ;   in Loop: Header=BB0_191 Depth=2
	global_load_b32 v5, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_193:                              ;   in Loop: Header=BB0_191 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_191 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_196
.LBB0_195:                              ;   in Loop: Header=BB0_191 Depth=2
	s_mov_b32 s1, -1
.LBB0_196:                              ; %Flow327
                                        ;   in Loop: Header=BB0_191 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_191
; %bb.197:                              ;   in Loop: Header=BB0_3 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_201
; %bb.198:                              ;   in Loop: Header=BB0_3 Depth=1
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v5, s8
	v_add_co_ci_u32_e32 v12, vcc_lo, s9, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v5
	v_and_b32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v11, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v13, v0
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_201
; %bb.199:                              ; %.preheader.i.i.i29.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s0, 0
.LBB0_200:                              ; %.preheader.i.i.i29
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_200
.LBB0_201:                              ; %__ockl_printf_append_args.exit33
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mul_f64 v[0:1], v[33:34], v[2:3]
	v_add_f64 v[2:3], -v[2:3], 1.0
	s_add_i32 s16, s16, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmpk_eq_i32 s16, 0x3e8
	v_mul_f64 v[2:3], v[0:1], v[2:3]
	s_cbranch_scc0 .LBB0_3
; %bb.202:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8logisticv
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 256
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 37
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8logisticv, .Lfunc_end0-_Z8logisticv
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8040
; NumSgprs: 22
; NumVgprs: 37
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 37
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%1.8lf %1.8lf\n"
	.size	.str, 15

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         4
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         12
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         14
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         16
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         18
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         20
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         22
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         40
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         64
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         80
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 256
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8logisticv
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z8logisticv.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     37
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
