#include "includes.h"
/**
* Copyright 1993-2015 NVIDIA Corporation.  All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/

/***********************************************************************************\
* Standard Includes
\***********************************************************************************/
/* For the CUDA runtime routines (prefixed with "cuda_") */

/***********************************************************************************\
* # Defines
\***********************************************************************************/
#define TRUE (1)
#define FALSE (0)

/* Number of rows and columns of the global memory */
#define NUM_OF_GLOBAL_ROWS (16000)
#define NUM_OF_GLOBAL_COLS (16000)

/* Number of threads in each block */
#define BLOCK_SIZE (32)

/* Convolution Kernel size */
#define KERNEL_SIZE (2)

/* Number of row and columns of the local memory */
#define NUM_OF_LOCAL_ROWS (BLOCK_SIZE + (2 * KERNEL_SIZE))
#define NUM_OF_LOCAL_COLS (BLOCK_SIZE + (2 * KERNEL_SIZE))

/***********************************************************************************\
* Enums
\***********************************************************************************/
typedef enum Status_Tag
{
PASSED,
FAILED
}Status_T;

typedef enum Cuda_Event_Tag
{
ALLOCATE_DEVICE_MATRIX_A,
ALLOCATE_DEVICE_MATRIX_B,
COPY_MATRIX_A_FROM_HOST_TO_DEVICE,
LAUNCH_KERNEL_CONV2DDEVICE,
DEVICE_SYNCHRONIZATION,
COPY_MATRIX_B_FROM_DEVICE_TO_HOST,
FREE_DEVICE_MATRIX_A,
FREE_DEVICE_MATRIX_B
}Cuda_Event_T;

typedef enum Corner_Cell_Name_Tag
{
LEFT_TOP_PADDING_CORNER,
RIGHT_TOP_PADDING_CORNER,
LEFT_BOTTOM_PADDING_CORNER,
RIGHT_BOTTOM_PADDING_CORNER,
NUM_OF_CORNERS
}Corner_Cell_Name_T;

typedef enum Ver_Side_Cell_Name_Tag
{
LEFT_PADDING_CELL,
RIGHT_PADDING_CELL,
NUM_OF_VER_SIDES
}Ver_Side_Cell_Name_T;

typedef enum Hor_Side_Cell_Name_Tag
{
TOP_PADDING_CELL,
BOTTOM_PADDING_CELL,
NUM_OF_HOR_SIDES
}Hor_Side_Cell_Name_T;

/***********************************************************************************\
* Structures
\***********************************************************************************/
typedef struct Result_Tag
{
Status_T status;
int index;
}Result_T;

typedef struct Cell_Tag
{
int r_idx; /* Row index */
int c_idx; /* Column index */
}Cell_T;

/***********************************************************************************\
* Function Macros
\***********************************************************************************/
/* Convert matrix index to array index */
#define MATRIX_TO_ARRAY_INDEX(r_idx, c_idx, num_cols) ((r_idx*num_cols) + c_idx)

/***********************************************************************************\
* CUDA Kernel Device code for 2D Convolution
\***********************************************************************************/

/***********************************************************************************\
* Host code for 2D Convolution and comparing the result with device 2D Convolution
\***********************************************************************************/
__global__ void conv2DDevice(const int *in,  int *out)
{
int g_col_idx = blockDim.x * blockIdx.x + threadIdx.x;
int g_row_idx = blockDim.y * blockIdx.y + threadIdx.y;
int l_col_idx = threadIdx.x + KERNEL_SIZE;
int l_row_idx = threadIdx.y + KERNEL_SIZE;

__shared__ int local[NUM_OF_LOCAL_ROWS*NUM_OF_LOCAL_COLS];

/* Convert from matrix indexing to array indexing */
int g_idx = MATRIX_TO_ARRAY_INDEX(g_row_idx, g_col_idx, NUM_OF_GLOBAL_COLS);
int l_idx = MATRIX_TO_ARRAY_INDEX(l_row_idx, l_col_idx, NUM_OF_LOCAL_COLS);

if ((g_row_idx < NUM_OF_GLOBAL_ROWS) && (g_col_idx < NUM_OF_GLOBAL_COLS))
{
/* Read input elements into shared memory */

/* Fill the internal (BLOCK_SIZE*BLOCK_SIZE) matrix */
local[l_idx] = in[g_idx];

/* Fill the left and right padding columns of local memory */
if (threadIdx.x < KERNEL_SIZE)
{
Cell_T l_ver_side[NUM_OF_VER_SIDES];
Cell_T g_ver_side[NUM_OF_VER_SIDES];

/* Find left and right padding column indices of local memory */
l_ver_side[LEFT_PADDING_CELL].r_idx = l_row_idx;
l_ver_side[LEFT_PADDING_CELL].c_idx = l_col_idx - KERNEL_SIZE;

l_ver_side[RIGHT_PADDING_CELL].r_idx = l_row_idx;
l_ver_side[RIGHT_PADDING_CELL].c_idx = l_col_idx + BLOCK_SIZE;

/* Find indices of global memory whose data needs to be filled
into the left and right padding columns of local memory */
g_ver_side[LEFT_PADDING_CELL].r_idx = g_row_idx;
g_ver_side[LEFT_PADDING_CELL].c_idx = g_col_idx - KERNEL_SIZE;

g_ver_side[RIGHT_PADDING_CELL].r_idx = g_row_idx;
g_ver_side[RIGHT_PADDING_CELL].c_idx = g_col_idx + BLOCK_SIZE;

for (int cell = LEFT_PADDING_CELL; cell < NUM_OF_VER_SIDES; ++cell)
{
bool within_bounds = FALSE;

/* Check if the cell is within bounds of global matrix */
if (LEFT_PADDING_CELL == cell) {
within_bounds = (g_ver_side[cell].c_idx >= 0);
}

if (RIGHT_PADDING_CELL == cell) {
within_bounds = (g_ver_side[cell].c_idx < NUM_OF_GLOBAL_COLS);
}

/* Copy corner into local memory if it is within the bounds of global matrix */
/* Convert from matrix indexing to array indexing */
int pad_l_idx = MATRIX_TO_ARRAY_INDEX(l_ver_side[cell].r_idx, l_ver_side[cell].c_idx, NUM_OF_LOCAL_COLS);
int pad_g_idx = MATRIX_TO_ARRAY_INDEX(g_ver_side[cell].r_idx, g_ver_side[cell].c_idx, NUM_OF_GLOBAL_COLS);
if (TRUE == within_bounds) {
local[pad_l_idx] = in[pad_g_idx];
}
else {
local[pad_l_idx] = 0;
}
}
}

/* Fill the top and bottom padding rows */
if (threadIdx.y < KERNEL_SIZE)
{
Cell_T l_hor_side[NUM_OF_HOR_SIDES];
Cell_T g_hor_side[NUM_OF_HOR_SIDES];

/* Find top and bottom padding row indices of local memory */
l_hor_side[TOP_PADDING_CELL].r_idx = l_row_idx - KERNEL_SIZE;
l_hor_side[TOP_PADDING_CELL].c_idx = l_col_idx;

l_hor_side[BOTTOM_PADDING_CELL].r_idx = l_row_idx + BLOCK_SIZE;
l_hor_side[BOTTOM_PADDING_CELL].c_idx = l_col_idx;

/* Find indices of global memory whose data needs to be filled
into the top and bottom padding rows of local memory */
g_hor_side[TOP_PADDING_CELL].r_idx = g_row_idx - KERNEL_SIZE;
g_hor_side[TOP_PADDING_CELL].c_idx = g_col_idx;

g_hor_side[BOTTOM_PADDING_CELL].r_idx = g_row_idx + BLOCK_SIZE;
g_hor_side[BOTTOM_PADDING_CELL].c_idx = g_col_idx;

for (int cell = TOP_PADDING_CELL; cell < NUM_OF_HOR_SIDES; ++cell)
{
bool within_bounds = FALSE;

/* Check if the cell is within bounds of global matrix */
if (TOP_PADDING_CELL == cell) {
within_bounds = (g_hor_side[cell].r_idx >= 0);
}

if (BOTTOM_PADDING_CELL == cell) {
within_bounds = (g_hor_side[cell].r_idx < NUM_OF_GLOBAL_ROWS);
}

/* Copy corner into local memory if it is within the bounds of global matrix */
/* Convert from matrix indexing to array indexing */
int pad_l_idx = MATRIX_TO_ARRAY_INDEX(l_hor_side[cell].r_idx, l_hor_side[cell].c_idx, NUM_OF_LOCAL_COLS);
int pad_g_idx = MATRIX_TO_ARRAY_INDEX(g_hor_side[cell].r_idx, g_hor_side[cell].c_idx, NUM_OF_GLOBAL_COLS);
if (TRUE == within_bounds) {
local[pad_l_idx] = in[pad_g_idx];
}
else {
local[pad_l_idx] = 0;
}
}
}

/* Fill the corners */
if ((threadIdx.x) < KERNEL_SIZE && (threadIdx.y < KERNEL_SIZE))
{
Cell_T l_corner[NUM_OF_CORNERS];
Cell_T g_corner[NUM_OF_CORNERS];

/* Find left top, right top, left bottom and right bottom padding
corner indices of local memory */
l_corner[LEFT_TOP_PADDING_CORNER].r_idx = l_row_idx - KERNEL_SIZE;
l_corner[LEFT_TOP_PADDING_CORNER].c_idx = l_col_idx - KERNEL_SIZE;

l_corner[RIGHT_TOP_PADDING_CORNER].r_idx = l_row_idx - KERNEL_SIZE;
l_corner[RIGHT_TOP_PADDING_CORNER].c_idx = l_col_idx + BLOCK_SIZE;

l_corner[LEFT_BOTTOM_PADDING_CORNER].r_idx = l_row_idx + BLOCK_SIZE;
l_corner[LEFT_BOTTOM_PADDING_CORNER].c_idx = l_col_idx - KERNEL_SIZE;

l_corner[RIGHT_BOTTOM_PADDING_CORNER].r_idx = l_row_idx + BLOCK_SIZE;
l_corner[RIGHT_BOTTOM_PADDING_CORNER].c_idx = l_col_idx + BLOCK_SIZE;

/* Find indices of global memory whose data needs to be filled
into the left top, right top, left bottom and right bottom padding
corners of local memory */
g_corner[LEFT_TOP_PADDING_CORNER].r_idx = g_row_idx - KERNEL_SIZE;
g_corner[LEFT_TOP_PADDING_CORNER].c_idx = g_col_idx - KERNEL_SIZE;

g_corner[RIGHT_TOP_PADDING_CORNER].r_idx = g_row_idx - KERNEL_SIZE;
g_corner[RIGHT_TOP_PADDING_CORNER].c_idx = g_col_idx + BLOCK_SIZE;

g_corner[LEFT_BOTTOM_PADDING_CORNER].r_idx = g_row_idx + BLOCK_SIZE;
g_corner[LEFT_BOTTOM_PADDING_CORNER].c_idx = g_col_idx - KERNEL_SIZE;

g_corner[RIGHT_BOTTOM_PADDING_CORNER].r_idx = g_row_idx + BLOCK_SIZE;
g_corner[RIGHT_BOTTOM_PADDING_CORNER].c_idx = g_col_idx + BLOCK_SIZE;

for (int corner = LEFT_TOP_PADDING_CORNER; corner < NUM_OF_CORNERS; ++corner)
{
bool within_bounds = FALSE;

/* Check if the corner is within bounds of global matrix */
if (LEFT_TOP_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx >= 0) && (g_corner[corner].c_idx >= 0));
}

if (RIGHT_TOP_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx >= 0) && (g_corner[corner].c_idx < NUM_OF_GLOBAL_COLS));
}

if (LEFT_BOTTOM_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx < NUM_OF_GLOBAL_ROWS) && (g_corner[corner].c_idx >= 0));
}

if (RIGHT_BOTTOM_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx < NUM_OF_GLOBAL_ROWS) && (g_corner[corner].c_idx < NUM_OF_GLOBAL_COLS));
}

/* Copy corner into local memory if it is within the bounds of global matrix */
/* Convert from matrix indexing to array indexing */
int pad_l_idx = MATRIX_TO_ARRAY_INDEX(l_corner[corner].r_idx, l_corner[corner].c_idx, NUM_OF_LOCAL_COLS);
int pad_g_idx = MATRIX_TO_ARRAY_INDEX(g_corner[corner].r_idx, g_corner[corner].c_idx, NUM_OF_GLOBAL_COLS);
if (TRUE == within_bounds){
local[pad_l_idx] = in[pad_g_idx];
}
else {
local[pad_l_idx] = 0;
}
}
}

__syncthreads();

/* Apply convolution */
int result = 0;
for (int row_offset = -KERNEL_SIZE; row_offset <= KERNEL_SIZE; ++row_offset)
{
for (int col_offset = -KERNEL_SIZE; col_offset <= KERNEL_SIZE; ++col_offset)
{
/* Convert local matrix row and column to local element index */
int l_ele_idx = MATRIX_TO_ARRAY_INDEX((l_row_idx + row_offset), (l_col_idx + col_offset), NUM_OF_LOCAL_COLS);
result += local[l_ele_idx];
}
}

/* Store the result */
out[g_idx] = result;
}
}
	.file	"tmpxft_0030cf6c_00000000-6_conv2DDevice.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z12conv2DDevicePKiPiPKiPi
	.type	_Z35__device_stub__Z12conv2DDevicePKiPiPKiPi, @function
_Z35__device_stub__Z12conv2DDevicePKiPiPKiPi:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12conv2DDevicePKiPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z35__device_stub__Z12conv2DDevicePKiPiPKiPi, .-_Z35__device_stub__Z12conv2DDevicePKiPiPKiPi
	.globl	_Z12conv2DDevicePKiPi
	.type	_Z12conv2DDevicePKiPi, @function
_Z12conv2DDevicePKiPi:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z12conv2DDevicePKiPiPKiPi
	.cfi_endproc
.LFE2033:
	.size	_Z12conv2DDevicePKiPi, .-_Z12conv2DDevicePKiPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12conv2DDevicePKiPi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12conv2DDevicePKiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/**
* Copyright 1993-2015 NVIDIA Corporation.  All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/

/***********************************************************************************\
* Standard Includes
\***********************************************************************************/
/* For the CUDA runtime routines (prefixed with "cuda_") */

/***********************************************************************************\
* # Defines
\***********************************************************************************/
#define TRUE (1)
#define FALSE (0)

/* Number of rows and columns of the global memory */
#define NUM_OF_GLOBAL_ROWS (16000)
#define NUM_OF_GLOBAL_COLS (16000)

/* Number of threads in each block */
#define BLOCK_SIZE (32)

/* Convolution Kernel size */
#define KERNEL_SIZE (2)

/* Number of row and columns of the local memory */
#define NUM_OF_LOCAL_ROWS (BLOCK_SIZE + (2 * KERNEL_SIZE))
#define NUM_OF_LOCAL_COLS (BLOCK_SIZE + (2 * KERNEL_SIZE))

/***********************************************************************************\
* Enums
\***********************************************************************************/
typedef enum Status_Tag
{
PASSED,
FAILED
}Status_T;

typedef enum Cuda_Event_Tag
{
ALLOCATE_DEVICE_MATRIX_A,
ALLOCATE_DEVICE_MATRIX_B,
COPY_MATRIX_A_FROM_HOST_TO_DEVICE,
LAUNCH_KERNEL_CONV2DDEVICE,
DEVICE_SYNCHRONIZATION,
COPY_MATRIX_B_FROM_DEVICE_TO_HOST,
FREE_DEVICE_MATRIX_A,
FREE_DEVICE_MATRIX_B
}Cuda_Event_T;

typedef enum Corner_Cell_Name_Tag
{
LEFT_TOP_PADDING_CORNER,
RIGHT_TOP_PADDING_CORNER,
LEFT_BOTTOM_PADDING_CORNER,
RIGHT_BOTTOM_PADDING_CORNER,
NUM_OF_CORNERS
}Corner_Cell_Name_T;

typedef enum Ver_Side_Cell_Name_Tag
{
LEFT_PADDING_CELL,
RIGHT_PADDING_CELL,
NUM_OF_VER_SIDES
}Ver_Side_Cell_Name_T;

typedef enum Hor_Side_Cell_Name_Tag
{
TOP_PADDING_CELL,
BOTTOM_PADDING_CELL,
NUM_OF_HOR_SIDES
}Hor_Side_Cell_Name_T;

/***********************************************************************************\
* Structures
\***********************************************************************************/
typedef struct Result_Tag
{
Status_T status;
int index;
}Result_T;

typedef struct Cell_Tag
{
int r_idx; /* Row index */
int c_idx; /* Column index */
}Cell_T;

/***********************************************************************************\
* Function Macros
\***********************************************************************************/
/* Convert matrix index to array index */
#define MATRIX_TO_ARRAY_INDEX(r_idx, c_idx, num_cols) ((r_idx*num_cols) + c_idx)

/***********************************************************************************\
* CUDA Kernel Device code for 2D Convolution
\***********************************************************************************/

/***********************************************************************************\
* Host code for 2D Convolution and comparing the result with device 2D Convolution
\***********************************************************************************/
__global__ void conv2DDevice(const int *in,  int *out)
{
int g_col_idx = blockDim.x * blockIdx.x + threadIdx.x;
int g_row_idx = blockDim.y * blockIdx.y + threadIdx.y;
int l_col_idx = threadIdx.x + KERNEL_SIZE;
int l_row_idx = threadIdx.y + KERNEL_SIZE;

__shared__ int local[NUM_OF_LOCAL_ROWS*NUM_OF_LOCAL_COLS];

/* Convert from matrix indexing to array indexing */
int g_idx = MATRIX_TO_ARRAY_INDEX(g_row_idx, g_col_idx, NUM_OF_GLOBAL_COLS);
int l_idx = MATRIX_TO_ARRAY_INDEX(l_row_idx, l_col_idx, NUM_OF_LOCAL_COLS);

if ((g_row_idx < NUM_OF_GLOBAL_ROWS) && (g_col_idx < NUM_OF_GLOBAL_COLS))
{
/* Read input elements into shared memory */

/* Fill the internal (BLOCK_SIZE*BLOCK_SIZE) matrix */
local[l_idx] = in[g_idx];

/* Fill the left and right padding columns of local memory */
if (threadIdx.x < KERNEL_SIZE)
{
Cell_T l_ver_side[NUM_OF_VER_SIDES];
Cell_T g_ver_side[NUM_OF_VER_SIDES];

/* Find left and right padding column indices of local memory */
l_ver_side[LEFT_PADDING_CELL].r_idx = l_row_idx;
l_ver_side[LEFT_PADDING_CELL].c_idx = l_col_idx - KERNEL_SIZE;

l_ver_side[RIGHT_PADDING_CELL].r_idx = l_row_idx;
l_ver_side[RIGHT_PADDING_CELL].c_idx = l_col_idx + BLOCK_SIZE;

/* Find indices of global memory whose data needs to be filled
into the left and right padding columns of local memory */
g_ver_side[LEFT_PADDING_CELL].r_idx = g_row_idx;
g_ver_side[LEFT_PADDING_CELL].c_idx = g_col_idx - KERNEL_SIZE;

g_ver_side[RIGHT_PADDING_CELL].r_idx = g_row_idx;
g_ver_side[RIGHT_PADDING_CELL].c_idx = g_col_idx + BLOCK_SIZE;

for (int cell = LEFT_PADDING_CELL; cell < NUM_OF_VER_SIDES; ++cell)
{
bool within_bounds = FALSE;

/* Check if the cell is within bounds of global matrix */
if (LEFT_PADDING_CELL == cell) {
within_bounds = (g_ver_side[cell].c_idx >= 0);
}

if (RIGHT_PADDING_CELL == cell) {
within_bounds = (g_ver_side[cell].c_idx < NUM_OF_GLOBAL_COLS);
}

/* Copy corner into local memory if it is within the bounds of global matrix */
/* Convert from matrix indexing to array indexing */
int pad_l_idx = MATRIX_TO_ARRAY_INDEX(l_ver_side[cell].r_idx, l_ver_side[cell].c_idx, NUM_OF_LOCAL_COLS);
int pad_g_idx = MATRIX_TO_ARRAY_INDEX(g_ver_side[cell].r_idx, g_ver_side[cell].c_idx, NUM_OF_GLOBAL_COLS);
if (TRUE == within_bounds) {
local[pad_l_idx] = in[pad_g_idx];
}
else {
local[pad_l_idx] = 0;
}
}
}

/* Fill the top and bottom padding rows */
if (threadIdx.y < KERNEL_SIZE)
{
Cell_T l_hor_side[NUM_OF_HOR_SIDES];
Cell_T g_hor_side[NUM_OF_HOR_SIDES];

/* Find top and bottom padding row indices of local memory */
l_hor_side[TOP_PADDING_CELL].r_idx = l_row_idx - KERNEL_SIZE;
l_hor_side[TOP_PADDING_CELL].c_idx = l_col_idx;

l_hor_side[BOTTOM_PADDING_CELL].r_idx = l_row_idx + BLOCK_SIZE;
l_hor_side[BOTTOM_PADDING_CELL].c_idx = l_col_idx;

/* Find indices of global memory whose data needs to be filled
into the top and bottom padding rows of local memory */
g_hor_side[TOP_PADDING_CELL].r_idx = g_row_idx - KERNEL_SIZE;
g_hor_side[TOP_PADDING_CELL].c_idx = g_col_idx;

g_hor_side[BOTTOM_PADDING_CELL].r_idx = g_row_idx + BLOCK_SIZE;
g_hor_side[BOTTOM_PADDING_CELL].c_idx = g_col_idx;

for (int cell = TOP_PADDING_CELL; cell < NUM_OF_HOR_SIDES; ++cell)
{
bool within_bounds = FALSE;

/* Check if the cell is within bounds of global matrix */
if (TOP_PADDING_CELL == cell) {
within_bounds = (g_hor_side[cell].r_idx >= 0);
}

if (BOTTOM_PADDING_CELL == cell) {
within_bounds = (g_hor_side[cell].r_idx < NUM_OF_GLOBAL_ROWS);
}

/* Copy corner into local memory if it is within the bounds of global matrix */
/* Convert from matrix indexing to array indexing */
int pad_l_idx = MATRIX_TO_ARRAY_INDEX(l_hor_side[cell].r_idx, l_hor_side[cell].c_idx, NUM_OF_LOCAL_COLS);
int pad_g_idx = MATRIX_TO_ARRAY_INDEX(g_hor_side[cell].r_idx, g_hor_side[cell].c_idx, NUM_OF_GLOBAL_COLS);
if (TRUE == within_bounds) {
local[pad_l_idx] = in[pad_g_idx];
}
else {
local[pad_l_idx] = 0;
}
}
}

/* Fill the corners */
if ((threadIdx.x) < KERNEL_SIZE && (threadIdx.y < KERNEL_SIZE))
{
Cell_T l_corner[NUM_OF_CORNERS];
Cell_T g_corner[NUM_OF_CORNERS];

/* Find left top, right top, left bottom and right bottom padding
corner indices of local memory */
l_corner[LEFT_TOP_PADDING_CORNER].r_idx = l_row_idx - KERNEL_SIZE;
l_corner[LEFT_TOP_PADDING_CORNER].c_idx = l_col_idx - KERNEL_SIZE;

l_corner[RIGHT_TOP_PADDING_CORNER].r_idx = l_row_idx - KERNEL_SIZE;
l_corner[RIGHT_TOP_PADDING_CORNER].c_idx = l_col_idx + BLOCK_SIZE;

l_corner[LEFT_BOTTOM_PADDING_CORNER].r_idx = l_row_idx + BLOCK_SIZE;
l_corner[LEFT_BOTTOM_PADDING_CORNER].c_idx = l_col_idx - KERNEL_SIZE;

l_corner[RIGHT_BOTTOM_PADDING_CORNER].r_idx = l_row_idx + BLOCK_SIZE;
l_corner[RIGHT_BOTTOM_PADDING_CORNER].c_idx = l_col_idx + BLOCK_SIZE;

/* Find indices of global memory whose data needs to be filled
into the left top, right top, left bottom and right bottom padding
corners of local memory */
g_corner[LEFT_TOP_PADDING_CORNER].r_idx = g_row_idx - KERNEL_SIZE;
g_corner[LEFT_TOP_PADDING_CORNER].c_idx = g_col_idx - KERNEL_SIZE;

g_corner[RIGHT_TOP_PADDING_CORNER].r_idx = g_row_idx - KERNEL_SIZE;
g_corner[RIGHT_TOP_PADDING_CORNER].c_idx = g_col_idx + BLOCK_SIZE;

g_corner[LEFT_BOTTOM_PADDING_CORNER].r_idx = g_row_idx + BLOCK_SIZE;
g_corner[LEFT_BOTTOM_PADDING_CORNER].c_idx = g_col_idx - KERNEL_SIZE;

g_corner[RIGHT_BOTTOM_PADDING_CORNER].r_idx = g_row_idx + BLOCK_SIZE;
g_corner[RIGHT_BOTTOM_PADDING_CORNER].c_idx = g_col_idx + BLOCK_SIZE;

for (int corner = LEFT_TOP_PADDING_CORNER; corner < NUM_OF_CORNERS; ++corner)
{
bool within_bounds = FALSE;

/* Check if the corner is within bounds of global matrix */
if (LEFT_TOP_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx >= 0) && (g_corner[corner].c_idx >= 0));
}

if (RIGHT_TOP_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx >= 0) && (g_corner[corner].c_idx < NUM_OF_GLOBAL_COLS));
}

if (LEFT_BOTTOM_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx < NUM_OF_GLOBAL_ROWS) && (g_corner[corner].c_idx >= 0));
}

if (RIGHT_BOTTOM_PADDING_CORNER == corner){
within_bounds = ((g_corner[corner].r_idx < NUM_OF_GLOBAL_ROWS) && (g_corner[corner].c_idx < NUM_OF_GLOBAL_COLS));
}

/* Copy corner into local memory if it is within the bounds of global matrix */
/* Convert from matrix indexing to array indexing */
int pad_l_idx = MATRIX_TO_ARRAY_INDEX(l_corner[corner].r_idx, l_corner[corner].c_idx, NUM_OF_LOCAL_COLS);
int pad_g_idx = MATRIX_TO_ARRAY_INDEX(g_corner[corner].r_idx, g_corner[corner].c_idx, NUM_OF_GLOBAL_COLS);
if (TRUE == within_bounds){
local[pad_l_idx] = in[pad_g_idx];
}
else {
local[pad_l_idx] = 0;
}
}
}

__syncthreads();

/* Apply convolution */
int result = 0;
for (int row_offset = -KERNEL_SIZE; row_offset <= KERNEL_SIZE; ++row_offset)
{
for (int col_offset = -KERNEL_SIZE; col_offset <= KERNEL_SIZE; ++col_offset)
{
/* Convert local matrix row and column to local element index */
int l_ele_idx = MATRIX_TO_ARRAY_INDEX((l_row_idx + row_offset), (l_col_idx + col_offset), NUM_OF_LOCAL_COLS);
result += local[l_ele_idx];
}
}

/* Store the result */
out[g_idx] = result;
}
}
	.text
	.file	"conv2DDevice.hip"
	.globl	_Z27__device_stub__conv2DDevicePKiPi # -- Begin function _Z27__device_stub__conv2DDevicePKiPi
	.type	_Z27__device_stub__conv2DDevicePKiPi,@function
_Z27__device_stub__conv2DDevicePKiPi:   # @_Z27__device_stub__conv2DDevicePKiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12conv2DDevicePKiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__conv2DDevicePKiPi, .Lfunc_end0-_Z27__device_stub__conv2DDevicePKiPi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12conv2DDevicePKiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12conv2DDevicePKiPi,@object   # @_Z12conv2DDevicePKiPi
	.section	.rodata,"a",@progbits
	.globl	_Z12conv2DDevicePKiPi
	.p2align	3, 0x0
_Z12conv2DDevicePKiPi:
	.quad	_Z27__device_stub__conv2DDevicePKiPi
	.size	_Z12conv2DDevicePKiPi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z12conv2DDevicePKiPi"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__conv2DDevicePKiPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12conv2DDevicePKiPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12conv2DDevicePKiPi   ; -- Begin function _Z12conv2DDevicePKiPi
	.globl	_Z12conv2DDevicePKiPi
	.p2align	8
	.type	_Z12conv2DDevicePKiPi,@function
_Z12conv2DDevicePKiPi:                  ; @_Z12conv2DDevicePKiPi
; %bb.0:
	s_load_b32 s4, s[2:3], 0x1c
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[13:14], null, s15, s5, v[5:6]
	v_mad_u64_u32 v[10:11], null, s14, s4, v[2:3]
	s_mov_b32 s4, exec_lo
	v_max_i32_e32 v1, v10, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x3e80, v1
	s_cbranch_execz .LBB0_21
; %bb.1:
	s_load_b128 s[4:7], s[2:3], 0x0
	s_delay_alu instid0(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, 0x3e80, v13, v[10:11]
	s_load_b64 s[0:1], s[0:1], 0x4
	v_add_nc_u32_e32 v1, 2, v5
	v_bfe_u32 v0, v0, 20, 10
	v_add_nc_u32_e32 v14, -2, v10
	v_add_nc_u32_e32 v16, 32, v10
	v_ashrrev_i32_e32 v4, 31, v3
	v_mul_u32_u24_e32 v7, 36, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[17:18], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v18, vcc_lo
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v6, s1, v5
	s_mul_i32 s0, s0, s1
	global_load_b32 v3, v[3:4], off
	v_mul_lo_u32 v4, s0, v2
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v4, v6, v0
	v_add_lshl_u32 v4, v7, v2, 2
	v_lshlrev_b32_e32 v19, 4, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3 offset:8
	v_cmpx_gt_u32_e32 2, v2
	s_cbranch_execz .LBB0_6
; %bb.2:
	v_cmp_gt_i32_e32 vcc_lo, 0x3e60, v10
	v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v6, 0x5440, v19
	v_add_nc_u32_e32 v7, 0x1440, v19
	v_or_b32_e32 v4, 34, v2
	v_cmp_lt_i32_e64 s0, 1, v10
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_mov_b32_e32 v15, v13
	s_mov_b32 s3, 0
	s_mov_b32 s8, 0
	s_mov_b32 s2, -1
	ds_store_b128 v19, v[1:4] offset:21568
	ds_store_b128 v19, v[13:16] offset:5184
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	v_lshl_add_u32 v0, s3, 3, v6
	s_and_b32 s9, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, 0, 1, s9
	ds_load_b64 v[0:1], v0
	v_cndmask_b32_e64 v3, v3, v8, s8
	v_and_b32_e32 v3, 1, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v3
	v_mov_b32_e32 v3, 0
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	v_lshl_add_u32 v3, s3, 3, v7
	ds_load_b64 v[3:4], v3
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[11:12], null, 0x3e80, v3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v11
	v_lshlrev_b64 v[3:4], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
.LBB0_5:                                ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v0, v0, 36
	s_xor_b32 s2, s2, -1
	s_mov_b32 s3, 1
	s_mov_b32 s8, -1
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v0, v0, v1, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v3
	s_cbranch_vccnz .LBB0_3
.LBB0_6:                                ; %Flow181
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v9, -2, v13
	v_add_nc_u32_e32 v11, 32, v13
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 2, v5
	s_cbranch_execz .LBB0_11
; %bb.7:
	v_add_nc_u32_e32 v6, 2, v2
	v_cmp_gt_i32_e32 vcc_lo, 0x3e60, v13
	v_dual_mov_b32 v12, v10 :: v_dual_add_nc_u32 v3, 0x9440, v19
	v_or_b32_e32 v7, 34, v5
	v_cmp_lt_i32_e64 s0, 1, v13
	v_mov_b32_e32 v8, v6
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_mov_b32 s3, 0
	s_mov_b32 s8, 0
	s_mov_b32 s2, -1
	ds_store_b128 v19, v[5:8] offset:37952
	scratch_store_b128 off, v[9:12], off offset:16
.LBB0_8:                                ; =>This Inner Loop Header: Depth=1
	v_lshl_add_u32 v0, s3, 3, v3
	s_and_b32 s9, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, 0, 1, s9
	ds_load_b64 v[0:1], v0
	v_cndmask_b32_e64 v6, v6, v4, s8
	v_and_b32_e32 v6, 1, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v6
	v_mov_b32_e32 v6, 0
	s_and_saveexec_b32 s8, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	s_lshl_b32 s3, s3, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_add_i32 s3, s3, 16
	scratch_load_b64 v[6:7], off, s3
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[19:20], null, 0x3e80, v6, v[7:8]
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[19:20]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
.LBB0_10:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v0, v0, 36
	s_xor_b32 s9, s2, -1
	s_mov_b32 s3, 1
	s_mov_b32 s8, -1
	s_mov_b32 s2, 0
	s_and_b32 vcc_lo, exec_lo, s9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_lshl_u32 v0, v0, v1, 2
	s_waitcnt vmcnt(0)
	ds_store_b32 v0, v6
	s_cbranch_vccz .LBB0_8
.LBB0_11:                               ; %Flow177
	s_or_b32 exec_lo, exec_lo, s1
	v_or_b32_e32 v0, v2, v5
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 2, v0
	s_cbranch_execz .LBB0_16
; %bb.12:
	v_cmp_lt_i32_e32 vcc_lo, 1, v13
	v_cmp_gt_i32_e64 s1, 0x3e60, v10
	v_cmp_lt_i32_e64 s0, 1, v10
	v_cmp_gt_i32_e64 s2, 0x3e60, v13
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v1, 34, v5
	v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v8, 34, v2
	s_and_b32 s8, s1, vcc_lo
	v_dual_mov_b32 v19, v9 :: v_dual_mov_b32 v20, v14
	v_dual_mov_b32 v21, v9 :: v_dual_mov_b32 v22, v16
	v_cndmask_b32_e64 v9, 0, 1, s8
	s_and_b32 s8, s0, s2
	s_and_b32 s1, s1, s2
	v_or_b32_e64 v12, 16, 4
	v_or_b32_e64 v15, 48, 4
	v_dual_mov_b32 v23, v11 :: v_dual_mov_b32 v24, v14
	v_dual_mov_b32 v25, v11 :: v_dual_mov_b32 v26, v16
	v_cndmask_b32_e64 v10, 0, 1, s8
	v_cndmask_b32_e64 v11, 0, 1, s1
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, v8
	s_mov_b32 s2, 0
	s_clause 0x3
	scratch_store_b128 off, v[5:8], off offset:16
	scratch_store_b128 off, v[1:4], off offset:32
	scratch_store_b128 off, v[19:22], off offset:48
	scratch_store_b128 off, v[23:26], off offset:64
.LBB0_13:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s2, 0
	v_add_nc_u32_e32 v0, s2, v12
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, vcc_lo, s1
	s_and_b32 s1, s1, s0
	s_cmp_eq_u32 s2, 8
	v_cndmask_b32_e64 v3, 0, 1, s1
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s2, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v9, s1
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s2, 24
	v_cndmask_b32_e64 v3, v3, v10, s1
	s_cselect_b32 s1, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v3, v3, v11, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 1, v3
	v_cmp_eq_u32_e64 s1, 1, v3
	v_mov_b32_e32 v3, 0
	scratch_load_b64 v[0:1], v0, off offset:-4
	s_and_saveexec_b32 s8, s1
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	v_add_nc_u32_e32 v3, s2, v15
	scratch_load_b64 v[3:4], v3, off offset:-4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[6:7], null, 0x3e80, v3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[3:4], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s1, s4, v3
	v_add_co_ci_u32_e64 v4, s1, s5, v4, s1
	global_load_b32 v3, v[3:4], off
.LBB0_15:                               ;   in Loop: Header=BB0_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_waitcnt vmcnt(0)
	v_mul_lo_u32 v0, v0, 36
	s_add_i32 s2, s2, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s2, 32
	v_add_lshl_u32 v0, v0, v1, 2
	ds_store_b32 v0, v3
	s_cbranch_scc0 .LBB0_13
.LBB0_16:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b32_e32 v0, 2, v2
	s_mov_b32 s0, -2
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_mad_u32_u24 v1, 0x90, v5, v0
	v_mov_b32_e32 v0, 0
.LBB0_17:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_18 Depth 2
	s_movk_i32 s1, 0xffec
.LBB0_18:                               ;   Parent Loop BB0_17 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s1, v1
	s_add_i32 s1, s1, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 0
	ds_load_b32 v2, v2 offset:20
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v2, v0
	s_cbranch_scc0 .LBB0_18
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=1
	v_add_nc_u32_e32 v1, 0x90, v1
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 3
	s_cbranch_scc0 .LBB0_17
; %bb.20:
	v_add_co_u32 v1, vcc_lo, s6, v17
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v18, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12conv2DDevicePKiPi
		.amdhsa_group_segment_fixed_size 54336
		.amdhsa_private_segment_fixed_size 80
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 27
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12conv2DDevicePKiPi, .Lfunc_end0-_Z12conv2DDevicePKiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1436
; NumSgprs: 18
; NumVgprs: 27
; ScratchSize: 80
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 54336 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 27
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 54336
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12conv2DDevicePKiPi
    .private_segment_fixed_size: 80
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12conv2DDevicePKiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     27
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
