#include <stdio.h>

////////////////////////////////////////////////////////////////////////////////
//! Matrix multiplication on the device: LHS = A * V
//! wA is A's width and wV is V's width
////////////////////////////////////////////////////////////////////////////////

__global__ void computeWireTempKernel(int maxPop,int numberOfVars,float* objT, float* objW,int* ids,float* dps,int* ls,
				      int* ws,bool* rotated,int* pos,int* couplings,int H,int L,int W){

	int i=blockIdx.x*blockDim.x+threadIdx.x;
	int j=blockIdx.y*blockDim.y+threadIdx.y;
	int index = i + j * blockDim.x;
	__shared__ int sids[61];
	__shared__ int sls[61];
	__shared__ int sws[61];
	__shared__ float sdps[61];
	__shared__ int spos[128*61];
	__shared__ bool scouplings[128*61];
	__shared__ bool srotated[128*61];
	if(index<61){
		sids[index] = ids[index];
		//__syncthreads();
	}
__syncthreads();
	if(index<61){
		sls[index] = ls[index];
		//__syncthreads();
	}
__syncthreads();
	if(index<61){
		sws[index] = ws[index];
		//__syncthreads();
	}
__syncthreads();
	if(index<61){
		sdps[index] = dps[index];
		//__syncthreads();
	}
__syncthreads();	
	for(int i=0;i<61;i++){
		spos[i*61 + index] = pos[i*61 + index];
		//__syncthreads();
	}
__syncthreads();
	for(int i=0;i<61;i++){
		scouplings[i*61 + index] = couplings[i*61 + index];
		//__syncthreads();
	}
__syncthreads();
	for(int i=0;i<61;i++){
		srotated[i*61 + index] = rotated[i*61 + index];
		//__syncthreads();
	}
__syncthreads();
	float tempObj = 0;
	float wireObj = 0;
	int CIz,CIy,CIx,CJz,CJy,CJx,CIid,posI,CIl,CIw,CIh,CJid,posJ,CJl,CJw,CJh;
        float CIdp,CJdp;
        int totalsize = L * W * H;
	int cellsPerLayer = totalsize / H;
        for (int i = 0; i < numberOfVars; ++i) {
            CIid = sids[i];
            CIdp = sdps[CIid-1];
	    posI = spos[index*numberOfVars + CIid-1];
	    if(!srotated[index*numberOfVars + CIid-1]){
	        CIl = sls[CIid-1];
        	CIw = sws[CIid-1];
	    }else{
		CIl = sws[CIid-1];
        	CIw = sls[CIid-1];
	    }
	    CIz = (posI / cellsPerLayer);
	    posI = posI - (cellsPerLayer * CIz);
	    CIx = posI % L;
	    posI = posI - CIx;
	    CIy = posI / L;
            CIh = 1;
            for (int j = 0; j < numberOfVars; ++j) {
                if (i < j) {
                    CJid = sids[j];
		    CJdp = sdps[CJid-1];		    
		    posJ = spos[index*numberOfVars + CJid-1];
		    if(!srotated[index*numberOfVars + CJid-1]){
		        CJl = sls[CJid-1];
	        	CJw = sws[CJid-1];
		    }else{
			CJl = sls[CJid-1];
	        	CJw = sws[CJid-1];
		    }		    
		    CJz = (posJ / cellsPerLayer);
		    posJ = posJ - (cellsPerLayer * CJz);
		    CJx = posJ % L;
		    posJ = posJ - CJx;
		    CJy = posJ / L;
                    CJh = 1;
                    
                    tempObj += (CIdp*CJdp) /
                                    (sqrtf(
                                          pow(abs(CIx + CIl / 2.0 - CJx - CJl / 2.0), 2)
                                        + pow(abs(CIy + CIw / 2.0 - CJy - CJw / 2.0), 2)
                                        + pow(abs(CIz + CIh / 2.0 - CJz - CJh / 2.0), 2)));
		    
                    if(scouplings[(CJid-1)*numberOfVars + CIid-1] == true){
		       wireObj += (fabsf(CIx+CIl/2.0-CJx-CJl/2.0) + fabsf(CIy+CIw/2.0-CJy-CJw/2.0) + (H+W)*fabsf(CIz+CIh/2.0-CJz-CJh/2.0));
  		    }
                }
		
            }
        }
	//__syncthreads();
	objT[index] = tempObj;
	objW[index] = index;	
}


	.file	"tmpxft_0029a288_00000000-6_computeWireTemp_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z66__device_stub__Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iiiiiPfS_PiS_S0_S0_PbS0_S0_iii
	.type	_Z66__device_stub__Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iiiiiPfS_PiS_S0_S0_PbS0_S0_iii, @function
_Z66__device_stub__Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iiiiiPfS_PiS_S0_S0_PbS0_S0_iii:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movl	%edi, 76(%rsp)
	leaq	104(%rsp), %rdi
	movl	%esi, 72(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 32(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 64(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rax, 24(%rsp)
	movq	304(%rsp), %rax
	movq	%rcx, 56(%rsp)
	leaq	96(%rsp), %rcx
	movq	%rax, 16(%rsp)
	movq	312(%rsp), %rax
	movq	%r8, 48(%rsp)
	movq	%rax, 8(%rsp)
	movq	320(%rsp), %rax
	movq	%r9, 40(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	76(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	movq	%rsp, %rax
	movq	%rax, 232(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 304
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L2:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z66__device_stub__Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iiiiiPfS_PiS_S0_S0_PbS0_S0_iii, .-_Z66__device_stub__Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iiiiiPfS_PiS_S0_S0_PbS0_S0_iii
	.globl	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.type	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii, @function
_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z66__device_stub__Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iiiiiPfS_PiS_S0_S0_PbS0_S0_iii
	.cfi_endproc
.LFE2052:
	.size	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii, .-_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

////////////////////////////////////////////////////////////////////////////////
//! Matrix multiplication on the device: LHS = A * V
//! wA is A's width and wV is V's width
////////////////////////////////////////////////////////////////////////////////

__global__ void computeWireTempKernel(int maxPop,int numberOfVars,float* objT, float* objW,int* ids,float* dps,int* ls,
				      int* ws,bool* rotated,int* pos,int* couplings,int H,int L,int W){

	int i=blockIdx.x*blockDim.x+threadIdx.x;
	int j=blockIdx.y*blockDim.y+threadIdx.y;
	int index = i + j * blockDim.x;
	__shared__ int sids[61];
	__shared__ int sls[61];
	__shared__ int sws[61];
	__shared__ float sdps[61];
	__shared__ int spos[128*61];
	__shared__ bool scouplings[128*61];
	__shared__ bool srotated[128*61];
	if(index<61){
		sids[index] = ids[index];
		//__syncthreads();
	}
__syncthreads();
	if(index<61){
		sls[index] = ls[index];
		//__syncthreads();
	}
__syncthreads();
	if(index<61){
		sws[index] = ws[index];
		//__syncthreads();
	}
__syncthreads();
	if(index<61){
		sdps[index] = dps[index];
		//__syncthreads();
	}
__syncthreads();	
	for(int i=0;i<61;i++){
		spos[i*61 + index] = pos[i*61 + index];
		//__syncthreads();
	}
__syncthreads();
	for(int i=0;i<61;i++){
		scouplings[i*61 + index] = couplings[i*61 + index];
		//__syncthreads();
	}
__syncthreads();
	for(int i=0;i<61;i++){
		srotated[i*61 + index] = rotated[i*61 + index];
		//__syncthreads();
	}
__syncthreads();
	float tempObj = 0;
	float wireObj = 0;
	int CIz,CIy,CIx,CJz,CJy,CJx,CIid,posI,CIl,CIw,CIh,CJid,posJ,CJl,CJw,CJh;
        float CIdp,CJdp;
        int totalsize = L * W * H;
	int cellsPerLayer = totalsize / H;
        for (int i = 0; i < numberOfVars; ++i) {
            CIid = sids[i];
            CIdp = sdps[CIid-1];
	    posI = spos[index*numberOfVars + CIid-1];
	    if(!srotated[index*numberOfVars + CIid-1]){
	        CIl = sls[CIid-1];
        	CIw = sws[CIid-1];
	    }else{
		CIl = sws[CIid-1];
        	CIw = sls[CIid-1];
	    }
	    CIz = (posI / cellsPerLayer);
	    posI = posI - (cellsPerLayer * CIz);
	    CIx = posI % L;
	    posI = posI - CIx;
	    CIy = posI / L;
            CIh = 1;
            for (int j = 0; j < numberOfVars; ++j) {
                if (i < j) {
                    CJid = sids[j];
		    CJdp = sdps[CJid-1];		    
		    posJ = spos[index*numberOfVars + CJid-1];
		    if(!srotated[index*numberOfVars + CJid-1]){
		        CJl = sls[CJid-1];
	        	CJw = sws[CJid-1];
		    }else{
			CJl = sls[CJid-1];
	        	CJw = sws[CJid-1];
		    }		    
		    CJz = (posJ / cellsPerLayer);
		    posJ = posJ - (cellsPerLayer * CJz);
		    CJx = posJ % L;
		    posJ = posJ - CJx;
		    CJy = posJ / L;
                    CJh = 1;
                    
                    tempObj += (CIdp*CJdp) /
                                    (sqrtf(
                                          pow(abs(CIx + CIl / 2.0 - CJx - CJl / 2.0), 2)
                                        + pow(abs(CIy + CIw / 2.0 - CJy - CJw / 2.0), 2)
                                        + pow(abs(CIz + CIh / 2.0 - CJz - CJh / 2.0), 2)));
		    
                    if(scouplings[(CJid-1)*numberOfVars + CIid-1] == true){
		       wireObj += (fabsf(CIx+CIl/2.0-CJx-CJl/2.0) + fabsf(CIy+CIw/2.0-CJy-CJw/2.0) + (H+W)*fabsf(CIz+CIh/2.0-CJz-CJh/2.0));
  		    }
                }
		
            }
        }
	//__syncthreads();
	objT[index] = tempObj;
	objW[index] = index;	
}


	.text
	.file	"computeWireTemp_kernel.hip"
	.globl	_Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii # -- Begin function _Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.type	_Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii,@function
_Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii: # @_Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$208, %rsp
	.cfi_def_cfa_offset 256
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	280(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$224, %rsp
	.cfi_adjust_cfa_offset -224
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii, .Lfunc_end0-_Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii,@object # @_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.section	.rodata,"a",@progbits
	.globl	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.p2align	3, 0x0
_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii:
	.quad	_Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.size	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii"
	.size	.L__unnamed_1, 53

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii ; -- Begin function _Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.globl	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
	.p2align	8
	.type	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii,@function
_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii: ; @_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x6c
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s15, s15, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v3, s15, s14, v1
	s_load_b512 s[8:23], s[0:1], 0x8
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v2, v0
	v_cmp_gt_i32_e32 vcc_lo, 61, v0
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b32_e32 v4, 2, v0
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, s2, s12, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s2, s13, v6, s2
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3 offset:39808
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s2, s16, v5
	v_add_co_ci_u32_e64 v6, s2, s17, v6, s2
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3 offset:39040
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v5, s2, s18, v5
	v_add_co_ci_u32_e64 v6, s2, s19, v6, s2
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3 offset:39296
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v6, vcc_lo
	global_load_b32 v3, v[5:6], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v3 offset:39552
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_9:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[5:6], 2, v[2:3]
	v_add_nc_u32_e32 v2, 61, v2
	v_add_co_u32 v5, vcc_lo, s22, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s23, v6, vcc_lo
	global_load_b32 v3, v[5:6], off
	v_add_nc_u32_e32 v5, s2, v4
	s_addk_i32 s2, 0xf4
	s_cmpk_eq_i32 s2, 0x3a24
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v3
	s_cbranch_scc0 .LBB0_9
; %bb.10:
	v_add_nc_u32_e32 v2, 0x7a00, v0
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_barrier
	buffer_gl0_inv
.LBB0_11:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v3, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_u8 v3, v[3:4], off
	v_add_nc_u32_e32 v4, s2, v2
	s_add_i32 s2, s2, 61
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s2, 0xe89
	s_waitcnt vmcnt(0)
	ds_store_b8 v4, v3
	s_cbranch_scc0 .LBB0_11
; %bb.12:
	s_load_b32 s33, s[0:1], 0x4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cmp_lt_i32 s33, 1
	s_cbranch_scc1 .LBB0_19
; %bb.13:                               ; %.lr.ph178
	s_load_b64 s[12:13], s[0:1], 0x54
	v_mul_lo_u32 v14, v0, s33
	v_dual_mov_b32 v15, 0 :: v_dual_mov_b32 v16, 0x9980
	s_mov_b32 s14, 0x55555555
	s_mov_b32 s16, 0x968915a9
	s_mov_b32 s18, 0x4222de17
	s_mov_b32 s20, 0x3abe935a
	s_mov_b32 s22, 0x47e6c9c2
	s_mov_b32 s24, 0xcfa74449
	s_mov_b32 s26, 0x71bf3c30
	s_mov_b32 s28, 0x1c7792ce
	s_mov_b32 s30, 0x924920da
	s_mov_b32 s34, 0x9999999c
	s_mov_b32 s36, 0xfefa39ef
	s_mov_b32 s38, 0x3b39803f
	s_mov_b32 s40, 0xd5df274d
	s_mov_b32 s42, 0x652b82fe
	s_mov_b32 s44, 0xfca7ab0c
	s_mov_b32 s46, 0x6a5dcb37
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s13, s13, s12
	s_ashr_i32 s71, s12, 31
	s_ashr_i32 s72, s13, 31
	s_add_i32 s0, s12, s71
	s_add_i32 s1, s13, s72
	s_xor_b32 s73, s0, s71
	s_xor_b32 s74, s1, s72
	v_cvt_f32_u32_e32 v2, s73
	v_cvt_f32_u32_e32 v3, s74
	s_sub_i32 s0, 0, s73
	s_sub_i32 s1, 0, s74
	s_mov_b32 s48, 0x623fde64
	v_rcp_iflag_f32_e32 v2, v2
	v_rcp_iflag_f32_e32 v3, v3
	s_mov_b32 s50, 0x7c89e6b0
	s_mov_b32 s52, 0x14761f6e
	s_mov_b32 s54, 0x1852b7b0
	s_mov_b32 s56, 0x11122322
	s_mov_b32 s58, 0x555502a1
	s_mov_b32 s60, 0x55555511
	s_mov_b32 s62, 11
	s_mov_b32 s70, 0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	s_mov_b32 s15, 0x3fe55555
	s_mov_b32 s17, 0x3fba6564
	s_mov_b32 s19, 0x3fbdee67
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v3, v3
	s_mov_b32 s21, 0x3fbe25e4
	s_mov_b32 s23, 0x3fc110ef
	s_mov_b32 s25, 0x3fc3b13b
	v_mul_lo_u32 v4, s0, v2
	v_mul_lo_u32 v5, s1, v3
	s_mov_b32 s27, 0x3fc745d1
	s_mov_b32 s29, 0x3fcc71c7
	s_mov_b32 s31, 0x3fd24924
	s_mov_b32 s35, 0x3fd99999
	s_mov_b32 s37, 0x3fe62e42
	s_mov_b32 s39, 0x3c7abc9e
	v_mul_hi_u32 v4, v2, v4
	v_mul_hi_u32 v5, v3, v5
	s_mov_b32 s41, 0x3c8543b0
	s_mov_b32 s43, 0x3ff71547
	s_mov_b32 s45, 0x3e928af3
	s_mov_b32 s47, 0x3e5ade15
	s_mov_b32 s49, 0x3ec71dee
	s_mov_b32 s51, 0x3efa0199
	v_add_nc_u32_e32 v17, v2, v4
	v_dual_mov_b32 v19, 0x9880 :: v_dual_add_nc_u32 v18, v3, v5
	s_mov_b32 s53, 0x3f2a01a0
	s_mov_b32 s55, 0x3f56c16c
	s_mov_b32 s57, 0x3f811111
	s_mov_b32 s59, 0x3fa55555
	s_mov_b32 s61, 0x3fc55555
	s_mov_b32 s63, 0x3fe00000
	s_mov_b32 s65, 0xbfe55555
	s_mov_b32 s67, 0xbfe62e42
	s_mov_b32 s69, 0xbc7abc9e
.LBB0_14:                               ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	s_lshl_b32 s0, s70, 2
	s_mov_b32 s75, 0x9b80
	v_mov_b32_e32 v2, s0
	s_mov_b32 s76, 0
	ds_load_b32 v2, v2 offset:39808
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v2, -1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v2, v14
	v_lshlrev_b32_e32 v4, 2, v3
	ds_load_b32 v4, v4
	ds_load_u8 v3, v3 offset:31232
	s_waitcnt lgkmcnt(1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v4, v5
	v_cndmask_b32_e64 v3, 0x9880, v16, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v6, v5
	v_xor_b32_e32 v5, s72, v5
	v_mul_hi_u32 v7, v6, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, v7, s74
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_nc_u32_e32 v8, 1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v9, s74, v6
	v_cmp_le_u32_e32 vcc_lo, s74, v6
	v_dual_cndmask_b32 v7, v7, v8 :: v_dual_cndmask_b32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s74, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_xor_b32_e32 v6, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v6, v5
	v_mul_lo_u32 v5, v10, s13
	v_cvt_f64_i32_e32 v[10:11], v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v5
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v4, v5
	v_xor_b32_e32 v6, v6, v5
	v_xor_b32_e32 v5, s71, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v7, v6, v17
	v_mul_lo_u32 v8, v7, s73
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v6, v8
	v_add_nc_u32_e32 v8, 1, v7
	v_cmp_le_u32_e32 vcc_lo, s73, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, v7, v8 :: v_dual_lshlrev_b32 v12, 2, v2
	v_subrev_nc_u32_e32 v2, s73, v6
	v_cndmask_b32_e64 v8, 0x9980, v19, s0
	v_dual_cndmask_b32 v2, v6, v2 :: v_dual_add_nc_u32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_add_nc_u32_e32 v6, 1, v7
	ds_load_b32 v20, v12 offset:39552
	ds_load_b32 v3, v3
	v_cmp_le_u32_e32 vcc_lo, s73, v2
	v_cndmask_b32_e32 v2, v7, v6, vcc_lo
	v_add_nc_u32_e32 v6, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v5
	ds_load_b32 v6, v6
	v_sub_nc_u32_e32 v7, v2, v5
	v_mul_lo_u32 v2, v7, s12
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v4, v2
	s_waitcnt lgkmcnt(1)
	v_cvt_f64_i32_e32 v[2:3], v3
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[4:5], v6
	v_cvt_f64_i32_e32 v[6:7], v7
	v_cvt_f64_i32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[2:3], 0.5, v[6:7]
	v_fma_f64 v[4:5], v[4:5], 0.5, v[8:9]
	v_add_f64 v[6:7], v[10:11], 0.5
.LBB0_15:                               ;   Parent Loop BB0_14 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_ge_u32 s70, s76
	s_cbranch_scc1 .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=2
	v_mov_b32_e32 v8, s75
	s_mov_b32 s64, s14
	s_mov_b32 s66, s36
	s_mov_b32 s68, s38
	ds_load_b32 v8, v8
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, -1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_lshl_u32 v8, v13, v14, 2
	ds_load_b32 v9, v8
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v8, 31, v9
	v_add_nc_u32_e32 v10, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, v10, v8
	v_xor_b32_e32 v8, s72, v8
	v_mul_hi_u32 v11, v10, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v12, v11, s74
	v_sub_nc_u32_e32 v10, v10, v12
	v_add_nc_u32_e32 v12, 1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v21, s74, v10
	v_cmp_le_u32_e32 vcc_lo, s74, v10
	v_dual_cndmask_b32 v11, v11, v12 :: v_dual_cndmask_b32 v10, v10, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, 1, v11
	v_cmp_le_u32_e32 vcc_lo, s74, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v11, v12, vcc_lo
	v_xor_b32_e32 v10, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v10, v8
	v_mul_lo_u32 v10, v8, s13
	v_cvt_f64_i32_e32 v[24:25], v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v9, v10
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, v9, v10
	v_xor_b32_e32 v11, v11, v10
	v_xor_b32_e32 v10, s71, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v12, v11, v17
	v_mul_lo_u32 v21, v12, s73
	v_add_f64 v[24:25], v[6:7], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v21
	v_add_nc_u32_e32 v21, 1, v12
	v_subrev_nc_u32_e32 v22, s73, v11
	v_cmp_le_u32_e32 vcc_lo, s73, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v12, v12, v21 :: v_dual_cndmask_b32 v11, v11, v22
	v_add_nc_u32_e32 v21, 1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s73, v11
	v_cndmask_b32_e32 v11, v12, v21, vcc_lo
	v_lshlrev_b32_e32 v21, 2, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v11, v11, v10
	v_add_nc_u32_e32 v13, 0x80, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v11, v10
	ds_load_2addr_stride64_b32 v[22:23], v13 offset0:152 offset1:153
	v_mul_lo_u32 v11, v10, s12
	v_sub_nc_u32_e32 v11, v9, v11
	v_cvt_f64_i32_e32 v[9:10], v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[11:12], v11
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[26:27], v23
	v_cvt_f64_i32_e32 v[22:23], v22
	v_add_f64 v[8:9], v[2:3], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[4:5], -v[11:12]
	v_fma_f64 v[12:13], v[26:27], -0.5, v[8:9]
	v_add_f64 v[8:9], v[24:25], -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[22:23], -0.5, v[10:11]
	v_frexp_mant_f64_e64 v[22:23], |v[12:13]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_frexp_mant_f64_e64 v[26:27], |v[8:9]|
	v_cmp_neq_f64_e64 s7, 0, v[8:9]
	v_frexp_mant_f64_e64 v[24:25], |v[10:11]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_f64_e64 s0, s[14:15], v[22:23]
	v_cmp_gt_f64_e32 vcc_lo, s[14:15], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e64 s1, s[14:15], v[24:25]
	v_cndmask_b32_e64 v28, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v29, 0, 1, s1
	v_ldexp_f64 v[22:23], v[22:23], v28
	v_cndmask_b32_e64 v28, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[24:25], v[24:25], v29
	v_ldexp_f64 v[26:27], v[26:27], v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[22:23], 1.0
	v_add_f64 v[46:47], v[22:23], -1.0
	v_add_f64 v[30:31], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[32:33], v[26:27], 1.0
	v_rcp_f64_e32 v[34:35], v[28:29]
	v_add_f64 v[52:53], v[28:29], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[36:37], v[30:31]
	v_add_f64 v[56:57], v[30:31], -1.0
	v_rcp_f64_e32 v[38:39], v[32:33]
	v_add_f64 v[60:61], v[32:33], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_add_f64 v[22:23], v[22:23], -v[52:53]
	v_fma_f64 v[40:41], -v[28:29], v[34:35], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[42:43], -v[30:31], v[36:37], 1.0
	v_fma_f64 v[44:45], -v[32:33], v[38:39], 1.0
	v_fma_f64 v[34:35], v[40:41], v[34:35], v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[42:43], v[36:37], v[36:37]
	v_fma_f64 v[38:39], v[44:45], v[38:39], v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[40:41], -v[28:29], v[34:35], 1.0
	v_fma_f64 v[42:43], -v[30:31], v[36:37], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], -v[32:33], v[38:39], 1.0
	v_fma_f64 v[34:35], v[40:41], v[34:35], v[34:35]
	v_add_f64 v[40:41], v[24:25], -1.0
	v_add_f64 v[24:25], v[24:25], -v[56:57]
	v_fma_f64 v[36:37], v[42:43], v[36:37], v[36:37]
	v_add_f64 v[42:43], v[26:27], -1.0
	v_fma_f64 v[38:39], v[44:45], v[38:39], v[38:39]
	v_add_f64 v[26:27], v[26:27], -v[60:61]
	v_mul_f64 v[44:45], v[46:47], v[34:35]
	v_mul_f64 v[48:49], v[40:41], v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[50:51], v[42:43], v[38:39]
	v_mul_f64 v[54:55], v[28:29], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[58:59], v[30:31], v[48:49]
	v_mul_f64 v[62:63], v[32:33], v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[44:45], v[28:29], -v[54:55]
	v_fma_f64 v[30:31], v[48:49], v[30:31], -v[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[50:51], v[32:33], -v[62:63]
	v_fma_f64 v[22:23], v[44:45], v[22:23], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[48:49], v[24:25], v[30:31]
	v_fma_f64 v[26:27], v[50:51], v[26:27], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[54:55], v[22:23]
	v_add_f64 v[30:31], v[58:59], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[62:63], v[26:27]
	v_add_f64 v[52:53], v[46:47], -v[28:29]
	v_add_f64 v[54:55], v[28:29], -v[54:55]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[56:57], v[40:41], -v[30:31]
	v_add_f64 v[58:59], v[30:31], -v[58:59]
	v_add_f64 v[60:61], v[42:43], -v[32:33]
	v_add_f64 v[62:63], v[32:33], -v[62:63]
	v_add_f64 v[46:47], v[46:47], -v[52:53]
	v_add_f64 v[22:23], v[54:55], -v[22:23]
	v_add_f64 v[40:41], v[40:41], -v[56:57]
	v_add_f64 v[24:25], v[58:59], -v[24:25]
	v_add_f64 v[42:43], v[42:43], -v[60:61]
	v_add_f64 v[26:27], v[62:63], -v[26:27]
	v_add_f64 v[28:29], v[46:47], -v[28:29]
	v_add_f64 v[30:31], v[40:41], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[42:43], -v[32:33]
	v_add_f64 v[22:23], v[22:23], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], v[30:31]
	v_add_f64 v[26:27], v[26:27], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[52:53], v[22:23]
	v_add_f64 v[24:25], v[56:57], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[60:61], v[26:27]
	v_mul_f64 v[22:23], v[34:35], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[24:25], v[36:37], v[24:25]
	v_mul_f64 v[26:27], v[38:39], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[44:45], v[22:23]
	v_add_f64 v[30:31], v[48:49], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[50:51], v[26:27]
	v_add_f64 v[34:35], v[28:29], -v[44:45]
	v_mul_f64 v[40:41], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[36:37], v[30:31], -v[48:49]
	v_add_f64 v[38:39], v[32:33], -v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[34:35]
	v_mul_f64 v[34:35], v[30:31], v[30:31]
	v_add_f64 v[24:25], v[24:25], -v[36:37]
	v_mul_f64 v[36:37], v[32:33], v[32:33]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	v_fma_f64 v[38:39], v[28:29], v[28:29], -v[40:41]
	v_add_f64 v[42:43], v[22:23], v[22:23]
	v_fma_f64 v[44:45], v[30:31], v[30:31], -v[34:35]
	v_add_f64 v[46:47], v[24:25], v[24:25]
	v_fma_f64 v[48:49], v[32:33], v[32:33], -v[36:37]
	v_add_f64 v[50:51], v[26:27], v[26:27]
	v_fma_f64 v[38:39], v[28:29], v[42:43], v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[30:31], v[46:47], v[44:45]
	v_fma_f64 v[44:45], v[32:33], v[50:51], v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[46:47], v[40:41], v[38:39]
	v_add_f64 v[48:49], v[34:35], v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[50:51], v[36:37], v[44:45]
	v_fma_f64 v[52:53], v[46:47], s[18:19], s[16:17]
	v_add_f64 v[40:41], v[46:47], -v[40:41]
	v_mul_f64 v[66:67], v[28:29], v[46:47]
	v_fma_f64 v[54:55], v[48:49], s[18:19], s[16:17]
	v_add_f64 v[34:35], v[48:49], -v[34:35]
	v_fma_f64 v[56:57], v[50:51], s[18:19], s[16:17]
	v_add_f64 v[36:37], v[50:51], -v[36:37]
	v_mul_f64 v[70:71], v[30:31], v[48:49]
	v_mul_f64 v[74:75], v[32:33], v[50:51]
	v_fma_f64 v[52:53], v[46:47], v[52:53], s[20:21]
	v_add_f64 v[38:39], v[38:39], -v[40:41]
	v_fma_f64 v[54:55], v[48:49], v[54:55], s[20:21]
	v_add_f64 v[34:35], v[42:43], -v[34:35]
	v_fma_f64 v[56:57], v[50:51], v[56:57], s[20:21]
	v_add_f64 v[36:37], v[44:45], -v[36:37]
	v_fma_f64 v[52:53], v[46:47], v[52:53], s[22:23]
	v_fma_f64 v[54:55], v[48:49], v[54:55], s[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[56:57], v[50:51], v[56:57], s[22:23]
	v_fma_f64 v[52:53], v[46:47], v[52:53], s[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[54:55], v[48:49], v[54:55], s[24:25]
	v_fma_f64 v[56:57], v[50:51], v[56:57], s[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[52:53], v[46:47], v[52:53], s[26:27]
	v_fma_f64 v[54:55], v[48:49], v[54:55], s[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[56:57], v[50:51], v[56:57], s[26:27]
	v_fma_f64 v[52:53], v[46:47], v[52:53], s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[54:55], v[48:49], v[54:55], s[28:29]
	v_fma_f64 v[56:57], v[50:51], v[56:57], s[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[52:53], v[46:47], v[52:53], s[30:31]
	v_fma_f64 v[54:55], v[48:49], v[54:55], s[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[56:57], v[50:51], v[56:57], s[30:31]
	v_fma_f64 v[52:53], v[46:47], v[52:53], s[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[54:55], v[48:49], v[54:55], s[34:35]
	v_fma_f64 v[56:57], v[50:51], v[56:57], s[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[58:59], v[46:47], v[52:53]
	v_mul_f64 v[60:61], v[48:49], v[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[62:63], v[50:51], v[56:57]
	v_fma_f64 v[40:41], v[46:47], v[52:53], -v[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[48:49], v[54:55], -v[60:61]
	v_fma_f64 v[44:45], v[50:51], v[56:57], -v[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[40:41], v[38:39], v[52:53], v[40:41]
	v_fma_f64 v[42:43], v[34:35], v[54:55], v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[44:45], v[36:37], v[56:57], v[44:45]
	v_add_f64 v[52:53], v[58:59], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[54:55], v[60:61], v[42:43]
	v_add_f64 v[56:57], v[62:63], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[64:65], v[52:53], s[14:15]
	v_add_f64 v[58:59], v[52:53], -v[58:59]
	v_add_f64 v[68:69], v[54:55], s[14:15]
	v_add_f64 v[60:61], v[54:55], -v[60:61]
	v_add_f64 v[72:73], v[56:57], s[14:15]
	v_add_f64 v[62:63], v[56:57], -v[62:63]
	v_add_f64 v[76:77], v[64:65], s[64:65]
	v_add_f64 v[40:41], v[40:41], -v[58:59]
	v_fma_f64 v[58:59], v[46:47], v[28:29], -v[66:67]
	v_add_f64 v[78:79], v[68:69], s[64:65]
	v_add_f64 v[42:43], v[42:43], -v[60:61]
	v_fma_f64 v[60:61], v[48:49], v[30:31], -v[70:71]
	v_add_f64 v[80:81], v[72:73], s[64:65]
	v_add_f64 v[44:45], v[44:45], -v[62:63]
	v_fma_f64 v[62:63], v[50:51], v[32:33], -v[74:75]
	v_add_f64 v[52:53], v[52:53], -v[76:77]
	v_add_f64 v[40:41], v[40:41], s[40:41]
	v_fma_f64 v[46:47], v[46:47], v[22:23], v[58:59]
	v_ldexp_f64 v[22:23], v[22:23], 1
	v_add_f64 v[54:55], v[54:55], -v[78:79]
	v_add_f64 v[42:43], v[42:43], s[40:41]
	v_fma_f64 v[48:49], v[48:49], v[24:25], v[60:61]
	v_add_f64 v[56:57], v[56:57], -v[80:81]
	v_add_f64 v[44:45], v[44:45], s[40:41]
	v_fma_f64 v[50:51], v[50:51], v[26:27], v[62:63]
	v_ldexp_f64 v[24:25], v[24:25], 1
	v_ldexp_f64 v[26:27], v[26:27], 1
	v_add_f64 v[40:41], v[40:41], v[52:53]
	v_fma_f64 v[38:39], v[38:39], v[28:29], v[46:47]
	v_ldexp_f64 v[28:29], v[28:29], 1
	v_add_f64 v[42:43], v[42:43], v[54:55]
	v_fma_f64 v[34:35], v[34:35], v[30:31], v[48:49]
	v_ldexp_f64 v[30:31], v[30:31], 1
	v_add_f64 v[44:45], v[44:45], v[56:57]
	v_fma_f64 v[36:37], v[36:37], v[32:33], v[50:51]
	v_ldexp_f64 v[32:33], v[32:33], 1
	v_add_f64 v[46:47], v[64:65], v[40:41]
	v_add_f64 v[48:49], v[66:67], v[38:39]
	v_add_f64 v[50:51], v[68:69], v[42:43]
	v_add_f64 v[52:53], v[70:71], v[34:35]
	v_add_f64 v[54:55], v[72:73], v[44:45]
	v_add_f64 v[56:57], v[74:75], v[36:37]
	v_add_f64 v[58:59], v[64:65], -v[46:47]
	v_mul_f64 v[60:61], v[48:49], v[46:47]
	v_add_f64 v[66:67], v[48:49], -v[66:67]
	v_add_f64 v[62:63], v[68:69], -v[50:51]
	v_mul_f64 v[64:65], v[52:53], v[50:51]
	v_add_f64 v[70:71], v[52:53], -v[70:71]
	v_add_f64 v[68:69], v[72:73], -v[54:55]
	v_mul_f64 v[72:73], v[56:57], v[54:55]
	v_add_f64 v[74:75], v[56:57], -v[74:75]
	v_add_f64 v[40:41], v[40:41], v[58:59]
	v_fma_f64 v[58:59], v[48:49], v[46:47], -v[60:61]
	v_add_f64 v[38:39], v[38:39], -v[66:67]
	v_add_f64 v[42:43], v[42:43], v[62:63]
	v_fma_f64 v[62:63], v[52:53], v[50:51], -v[64:65]
	v_add_f64 v[34:35], v[34:35], -v[70:71]
	v_add_f64 v[44:45], v[44:45], v[68:69]
	v_fma_f64 v[68:69], v[56:57], v[54:55], -v[72:73]
	v_add_f64 v[36:37], v[36:37], -v[74:75]
	v_fma_f64 v[40:41], v[48:49], v[40:41], v[58:59]
	v_frexp_exp_i32_f64_e32 v58, v[8:9]
	v_fma_f64 v[42:43], v[52:53], v[42:43], v[62:63]
	v_fma_f64 v[44:45], v[56:57], v[44:45], v[68:69]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[38:39], v[38:39], v[46:47], v[40:41]
	v_frexp_exp_i32_f64_e32 v46, v[12:13]
	v_frexp_exp_i32_f64_e32 v47, v[10:11]
	v_subrev_co_ci_u32_e32 v58, vcc_lo, 0, v58, vcc_lo
	v_fma_f64 v[34:35], v[34:35], v[50:51], v[42:43]
	v_fma_f64 v[36:37], v[36:37], v[54:55], v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[58:59], v58
	v_add_f64 v[40:41], v[60:61], v[38:39]
	v_subrev_co_ci_u32_e64 v44, s0, 0, v46, s0
	v_subrev_co_ci_u32_e64 v48, s0, 0, v47, s1
	v_add_f64 v[42:43], v[64:65], v[34:35]
	v_cvt_f64_i32_e32 v[44:45], v44
	v_add_f64 v[46:47], v[72:73], v[36:37]
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_f64_i32_e32 v[48:49], v48
	v_add_f64 v[50:51], v[28:29], v[40:41]
	v_add_f64 v[52:53], v[40:41], -v[60:61]
	v_add_f64 v[54:55], v[30:31], v[42:43]
	v_add_f64 v[56:57], v[42:43], -v[64:65]
	v_add_f64 v[62:63], v[32:33], v[46:47]
	v_add_f64 v[64:65], v[46:47], -v[72:73]
	v_mul_f64 v[66:67], v[48:49], s[36:37]
	v_mul_f64 v[60:61], v[44:45], s[36:37]
	v_add_f64 v[28:29], v[50:51], -v[28:29]
	v_add_f64 v[38:39], v[38:39], -v[52:53]
	v_mul_f64 v[52:53], v[58:59], s[36:37]
	v_add_f64 v[30:31], v[54:55], -v[30:31]
	v_add_f64 v[34:35], v[34:35], -v[56:57]
	v_add_f64 v[32:33], v[62:63], -v[32:33]
	v_add_f64 v[36:37], v[36:37], -v[64:65]
	v_fma_f64 v[56:57], v[44:45], s[36:37], -v[60:61]
	v_add_f64 v[28:29], v[40:41], -v[28:29]
	v_add_f64 v[22:23], v[22:23], v[38:39]
	v_fma_f64 v[38:39], v[48:49], s[36:37], -v[66:67]
	v_add_f64 v[30:31], v[42:43], -v[30:31]
	v_add_f64 v[24:25], v[24:25], v[34:35]
	v_fma_f64 v[34:35], v[58:59], s[36:37], -v[52:53]
	v_add_f64 v[32:33], v[46:47], -v[32:33]
	v_add_f64 v[26:27], v[26:27], v[36:37]
	v_fma_f64 v[36:37], v[44:45], s[38:39], v[56:57]
	v_add_f64 v[22:23], v[22:23], v[28:29]
	v_fma_f64 v[28:29], v[48:49], s[38:39], v[38:39]
	v_add_f64 v[24:25], v[24:25], v[30:31]
	v_fma_f64 v[30:31], v[58:59], s[38:39], v[34:35]
	v_add_f64 v[26:27], v[26:27], v[32:33]
	v_add_f64 v[32:33], v[60:61], v[36:37]
	v_add_f64 v[34:35], v[50:51], v[22:23]
	v_add_f64 v[38:39], v[66:67], v[28:29]
	v_add_f64 v[40:41], v[54:55], v[24:25]
	v_add_f64 v[42:43], v[52:53], v[30:31]
	v_add_f64 v[44:45], v[62:63], v[26:27]
	v_add_f64 v[60:61], v[32:33], -v[60:61]
	v_add_f64 v[46:47], v[32:33], v[34:35]
	v_add_f64 v[66:67], v[38:39], -v[66:67]
	v_add_f64 v[50:51], v[34:35], -v[50:51]
	v_add_f64 v[48:49], v[38:39], v[40:41]
	v_add_f64 v[52:53], v[42:43], -v[52:53]
	v_add_f64 v[54:55], v[40:41], -v[54:55]
	v_add_f64 v[56:57], v[42:43], v[44:45]
	v_add_f64 v[62:63], v[44:45], -v[62:63]
	v_add_f64 v[36:37], v[36:37], -v[60:61]
	v_add_f64 v[58:59], v[46:47], -v[32:33]
	v_add_f64 v[28:29], v[28:29], -v[66:67]
	v_add_f64 v[22:23], v[22:23], -v[50:51]
	v_add_f64 v[64:65], v[48:49], -v[38:39]
	v_add_f64 v[30:31], v[30:31], -v[52:53]
	v_add_f64 v[24:25], v[24:25], -v[54:55]
	v_add_f64 v[68:69], v[56:57], -v[42:43]
	v_add_f64 v[26:27], v[26:27], -v[62:63]
	v_add_f64 v[70:71], v[46:47], -v[58:59]
	v_add_f64 v[34:35], v[34:35], -v[58:59]
	v_add_f64 v[50:51], v[36:37], v[22:23]
	v_add_f64 v[72:73], v[48:49], -v[64:65]
	v_add_f64 v[40:41], v[40:41], -v[64:65]
	v_add_f64 v[60:61], v[56:57], -v[68:69]
	v_add_f64 v[44:45], v[44:45], -v[68:69]
	v_add_f64 v[32:33], v[32:33], -v[70:71]
	v_add_f64 v[38:39], v[38:39], -v[72:73]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[42:43], -v[60:61]
	v_add_f64 v[32:33], v[34:35], v[32:33]
	v_add_f64 v[34:35], v[28:29], v[24:25]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[38:39], v[40:41], v[38:39]
	v_add_f64 v[40:41], v[30:31], v[26:27]
	v_add_f64 v[42:43], v[44:45], v[42:43]
	v_add_f64 v[44:45], v[50:51], -v[36:37]
	v_add_f64 v[32:33], v[50:51], v[32:33]
	v_add_f64 v[52:53], v[34:35], -v[28:29]
	v_add_f64 v[38:39], v[34:35], v[38:39]
	v_add_f64 v[54:55], v[40:41], -v[30:31]
	v_add_f64 v[42:43], v[40:41], v[42:43]
	v_add_f64 v[50:51], v[50:51], -v[44:45]
	v_add_f64 v[22:23], v[22:23], -v[44:45]
	v_add_f64 v[58:59], v[46:47], v[32:33]
	v_add_f64 v[34:35], v[34:35], -v[52:53]
	v_add_f64 v[24:25], v[24:25], -v[52:53]
	v_add_f64 v[60:61], v[48:49], v[38:39]
	v_add_f64 v[40:41], v[40:41], -v[54:55]
	v_add_f64 v[26:27], v[26:27], -v[54:55]
	v_add_f64 v[62:63], v[56:57], v[42:43]
	v_add_f64 v[36:37], v[36:37], -v[50:51]
	v_add_f64 v[44:45], v[58:59], -v[46:47]
	v_add_f64 v[28:29], v[28:29], -v[34:35]
	v_add_f64 v[34:35], v[60:61], -v[48:49]
	v_add_f64 v[30:31], v[30:31], -v[40:41]
	v_add_f64 v[40:41], v[62:63], -v[56:57]
	v_add_f64 v[22:23], v[22:23], v[36:37]
	v_add_f64 v[32:33], v[32:33], -v[44:45]
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_add_f64 v[28:29], v[38:39], -v[34:35]
	v_add_f64 v[26:27], v[26:27], v[30:31]
	v_add_f64 v[30:31], v[42:43], -v[40:41]
	v_add_f64 v[22:23], v[22:23], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[24:25], v[28:29]
	v_add_f64 v[26:27], v[26:27], v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], v[58:59], v[22:23]
	v_add_f64 v[30:31], v[60:61], v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[62:63], v[26:27]
	v_add_f64 v[34:35], v[28:29], -v[58:59]
	v_add_f64 v[36:37], v[28:29], v[28:29]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[38:39], v[30:31], -v[60:61]
	v_add_f64 v[40:41], v[30:31], v[30:31]
	v_add_f64 v[42:43], v[32:33], -v[62:63]
	v_add_f64 v[44:45], v[32:33], v[32:33]
	v_add_f64 v[22:23], v[22:23], -v[34:35]
	v_fma_f64 v[28:29], v[28:29], 2.0, -v[36:37]
	v_cmp_class_f64_e64 vcc_lo, v[36:37], 0x204
	v_add_f64 v[24:25], v[24:25], -v[38:39]
	v_fma_f64 v[30:31], v[30:31], 2.0, -v[40:41]
	v_cmp_class_f64_e64 s0, v[40:41], 0x204
	v_add_f64 v[26:27], v[26:27], -v[42:43]
	v_fma_f64 v[32:33], v[32:33], 2.0, -v[44:45]
	v_cmp_class_f64_e64 s1, v[44:45], 0x204
	v_fma_f64 v[22:23], v[22:23], 2.0, v[28:29]
	v_fma_f64 v[24:25], v[24:25], 2.0, v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[26:27], v[26:27], 2.0, v[32:33]
	v_add_f64 v[28:29], v[36:37], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[40:41], v[24:25]
	v_add_f64 v[32:33], v[44:45], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v35, v29, v37 :: v_dual_cndmask_b32 v34, v28, v36
	v_add_f64 v[28:29], v[28:29], -v[36:37]
	v_cndmask_b32_e64 v39, v31, v41, s0
	v_cndmask_b32_e64 v38, v30, v40, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f64 v[42:43], v[34:35], s[42:43]
	v_cndmask_b32_e64 v49, v33, v45, s1
	v_cndmask_b32_e64 v48, v32, v44, s1
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[34:35]|
	v_mul_f64 v[46:47], v[38:39], s[42:43]
	v_add_f64 v[32:33], v[32:33], -v[44:45]
	v_add_f64 v[30:31], v[30:31], -v[40:41]
	v_mul_f64 v[50:51], v[48:49], s[42:43]
	v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[48:49]
	v_cmp_neq_f64_e64 s5, 0x7ff00000, |v[48:49]|
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[34:35]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[34:35]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[38:39]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[38:39]|
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[38:39]
	v_add_f64 v[22:23], v[22:23], -v[28:29]
	v_rndne_f64_e32 v[42:43], v[42:43]
	v_rndne_f64_e32 v[46:47], v[46:47]
	v_add_f64 v[26:27], v[26:27], -v[32:33]
	v_add_f64 v[24:25], v[24:25], -v[30:31]
	v_rndne_f64_e32 v[50:51], v[50:51]
	v_dual_cndmask_b32 v23, 0, v23 :: v_dual_cndmask_b32 v22, 0, v22
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[48:49]
	v_fma_f64 v[52:53], v[42:43], s[66:67], v[34:35]
	v_cvt_i32_f64_e32 v64, v[42:43]
	v_fma_f64 v[54:55], v[46:47], s[66:67], v[38:39]
	v_cndmask_b32_e64 v27, 0, v27, s5
	v_cndmask_b32_e64 v26, 0, v26, s5
	v_fma_f64 v[56:57], v[50:51], s[66:67], v[48:49]
	v_cndmask_b32_e64 v25, 0, v25, s0
	v_cndmask_b32_e64 v24, 0, v24, s0
	s_and_b32 s0, s2, s1
	v_fma_f64 v[52:53], v[42:43], s[68:69], v[52:53]
	v_fma_f64 v[54:55], v[46:47], s[68:69], v[54:55]
	v_fma_f64 v[56:57], v[50:51], s[68:69], v[56:57]
	v_cvt_i32_f64_e32 v50, v[50:51]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[58:59], v[52:53], s[46:47], s[44:45]
	v_fma_f64 v[60:61], v[54:55], s[46:47], s[44:45]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], s[46:47], s[44:45]
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[48:49]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[50:51]
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[50:51]
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[52:53]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[54:55]
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[54:55]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[54:55]
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[56:57]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[56:57]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[58:59]
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[58:59]
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[60:61]
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[58:59], v[52:53], v[58:59], s[62:63]
	v_fma_f64 v[60:61], v[54:55], v[60:61], s[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[62:63], v[56:57], v[62:63], s[62:63]
	v_fma_f64 v[58:59], v[52:53], v[58:59], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[60:61], v[54:55], v[60:61], 1.0
	v_fma_f64 v[62:63], v[56:57], v[62:63], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[42:43], v[52:53], v[58:59], 1.0
	v_cvt_i32_f64_e32 v52, v[46:47]
	v_fma_f64 v[46:47], v[54:55], v[60:61], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], v[56:57], v[62:63], 1.0
	v_ldexp_f64 v[40:41], v[42:43], v64
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[42:43], v[46:47], v52
	v_ldexp_f64 v[28:29], v[36:37], v50
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v30, 0x7ff00000, v41, s1
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[12:13]|
	v_cndmask_b32_e64 v31, 0x7ff00000, v43, s3
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v30, 0, v30, s2
	v_cmp_neq_f64_e64 s2, 0, v[12:13]
	v_cndmask_b32_e32 v33, 0x7ff00000, v29, vcc_lo
	s_and_b32 vcc_lo, s6, vcc_lo
	v_cndmask_b32_e64 v29, 0, v40, s0
	v_cndmask_b32_e64 v32, 0, v31, s4
	s_and_b32 s0, s4, s3
	v_cndmask_b32_e64 v34, 0, v33, s6
	v_cndmask_b32_e32 v33, 0, v28, vcc_lo
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[10:11]|
	v_cmp_neq_f64_e64 s4, 0, v[10:11]
	v_cndmask_b32_e64 v31, 0, v42, s0
	v_cmp_class_f64_e64 vcc_lo, v[29:30], 0x204
	v_fma_f64 v[26:27], v[33:34], v[26:27], v[33:34]
	v_cmp_class_f64_e64 s5, v[33:34], 0x204
	v_cmp_neq_f64_e64 s6, 0x7ff00000, |v[8:9]|
	v_fma_f64 v[24:25], v[31:32], v[24:25], v[31:32]
	v_cmp_class_f64_e64 s0, v[31:32], 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v27, v34, s5
	v_cndmask_b32_e64 v25, v25, v32, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_and_b32_e32 v10, 0x7fffffff, v10
	v_fma_f64 v[22:23], v[29:30], v[22:23], v[29:30]
	v_and_b32_e32 v25, 0x7fffffff, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, 0x7ff00000, v10, s6
	v_cndmask_b32_e64 v10, v24, v31, s0
	v_cndmask_b32_e64 v12, 0x7ff00000, v25, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v11, 0, v12, s4
	v_dual_cndmask_b32 v8, v22, v29 :: v_dual_cndmask_b32 v23, v23, v30
	s_and_b32 vcc_lo, s2, s1
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	s_and_b32 vcc_lo, s7, s6
	v_and_b32_e32 v23, 0x7fffffff, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, 0x7ff00000, v23, s1
	v_cndmask_b32_e64 v9, 0, v23, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[10:11], v[8:9]
	v_cndmask_b32_e64 v10, v26, v33, s5
	v_cndmask_b32_e64 v11, 0, v13, s7
	ds_load_b32 v13, v21 offset:39552
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
	v_add_f64 v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v8, v[8:9]
	v_mul_f32_e32 v9, 0x4f800000, v8
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, v8, v9, vcc_lo
	v_sqrt_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v10, -1, v9
	v_add_nc_u32_e32 v11, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v12, -v10, v9, v8
	v_fma_f32 v21, -v11, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v12
	v_cndmask_b32_e64 v9, v9, v10, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v21
	v_cndmask_b32_e64 v9, v9, v11, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, 0x37800000, v9
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x260
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v10, v20, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v8, v9, v8, vcc_lo
	v_div_scale_f32 v9, null, v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v9, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	v_div_scale_f32 v12, vcc_lo, v10, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v13, v12, v11
	v_fma_f32 v21, -v9, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, v21, v11
	v_fma_f32 v9, -v9, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v9, v9, v11, v13
	v_div_fixup_f32 v8, v9, v8, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v15, v15, v8
.LBB0_17:                               ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s76, s76, 1
	s_add_i32 s75, s75, 4
	s_cmp_eq_u32 s33, s76
	s_cbranch_scc0 .LBB0_15
; %bb.18:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_add_i32 s70, s70, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s70, s33
	s_cbranch_scc0 .LBB0_14
	s_branch .LBB0_20
.LBB0_19:
	v_mov_b32_e32 v15, 0
.LBB0_20:                               ; %Flow228
	v_lshlrev_b64 v[1:2], 2, v[0:1]
	v_cvt_f32_i32_e32 v5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
	v_add_co_u32 v0, vcc_lo, s10, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v2, vcc_lo
	global_store_b32 v[3:4], v15, off
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
		.amdhsa_group_segment_fixed_size 40052
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 82
		.amdhsa_next_free_sgpr 77
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii, .Lfunc_end0-_Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6468
; NumSgprs: 79
; NumVgprs: 82
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 40052 bytes/workgroup (compile time only)
; SGPRBlocks: 9
; VGPRBlocks: 10
; NumSGPRsForWavesPerEU: 79
; NumVGPRsForWavesPerEU: 82
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 40052
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     79
    .sgpr_spill_count: 0
    .symbol:         _Z21computeWireTempKerneliiPfS_PiS_S0_S0_PbS0_S0_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     82
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
