#include <stdio.h>
#include <cstdlib>
#include <time.h>
#include <stdlib.h>
#include <math.h>

/*
	Authors: Eric Sheeder, Gokul Natesan, Jacob Hollister
	Parallel Computing Final Project
	
	This code generates 2 large matrices and multiplies them, once on the GPU and once on the CPU
	It expects 3 variables on the command line, n, m, and p, where n and m are the dimensions of A and m and p are the dimensions of B
	This code currently only works accurately when n, m, and p are all multiples of 32
	
	Algorithm was learned and taken from this paper:
	https://webs.um.es/jmgarcia/miwiki/lib/exe/fetch.php?id=pubs&cache=cache&media=parco09.pdf
*/

// CUDA runtime
#include <cuda_runtime.h>

// Helper functions and utilities to work with CUDA
//#include <helper_functions.h>

//This function computes the final values for a single tile in the output matrix (C)
__global__ void compute_tile(int *d_A, int *d_B, int *d_C_gpu, int n, int m, int p) {
	// Block index
    int bx = blockIdx.x;
	int by = blockIdx.y;

    // Thread index
    int tx = threadIdx.x;
	int ty = threadIdx.y;
	
	//Chunk of 32x32 values loaded from A and B
	__shared__ float A[32][32];
	__shared__ float B[32][32];
	
	//Offset into A and B for each thread so it knows which piece of data to load into the shared arrays
	int indexA = by * (m*blockDim.y) + ty * m + tx;
	int indexB = bx*blockDim.x + ty*p + tx;
	
	//Each thread keeps track of its own sum in this variable
	int sum = 0;
		
	//Run through multiple tiles in A and B to compute our values for our tile in C
	for (int i = 0; i < p; i+=blockDim.x) {
		//Have each thread load a value into A and B
		A[ty][tx] = d_A[indexA];
		B[ty][tx] = d_B[indexB];
		//Synch threads so all threads wait until all data is loaded before we start calculating
		__syncthreads();
		//Have each thread run through the section of A and B we are at, doing 32 multiplications and summing them
		for (int j = 0; j < blockDim.x; j++) {
			sum += A[ty][j] * B[j][tx];
		}
		//Synch threads again so we know each thread is ready to move on to the next part of A and Block
		__syncthreads();
		indexA += blockDim.x;
		indexB += p*blockDim.x;
	}

	
	//Each thread should now have a complete value for its part in C, so figure out where it should go and store it
	int indexC = bx * blockDim.x + by * (p * blockDim.y) + p * ty + tx;
	d_C_gpu[indexC] = sum;
}

int main (int argc, char *argv[]) {
  int *A, *B, *C_cpu, *C_gpu; // matrices
  int n, m, p; // dimensions of matrices
  srand(time(NULL)); //random numbers each time
  clock_t cpu_start_time, cpu_end_time;
  cudaEvent_t gpu_start_time, gpu_end_time;
  double cpu_total_time;
  float gpu_total_time;
  
  //Make sure user puts in right parameters
  if (argc !=4) {
	printf("Usage: <./executable.exe n m p>, where n, m, and p are the dimensions of A (nxm) and B (mxp)");
	exit(1);
  }
  
  n = atoi(argv[1]);
  m = atoi(argv[2]);
  p = atoi(argv[3]);
  
  // Read number of rows (nr), number of columns (nc) and
  // number of elements and allocate memory for row_ptr, indices, data, b and c.
  unsigned int mem_size_A = (n*m)*sizeof(int);
  A = (int *) malloc (mem_size_A);
  unsigned int mem_size_B = (m*p)*sizeof(int);
  B = (int *) malloc (mem_size_B);
  unsigned int mem_size_C = (n*p)*sizeof(int);
  C_cpu = (int *) malloc (mem_size_C);
  C_gpu = (int *) malloc (mem_size_C);

  // Fill A with randomly generated data
  for (int i=0; i<n*m; i++) {
	int someInt = 1 + rand() % 10;
	A[i] = someInt;
  }
  
  // Fill B with randomly generated data
  for (int i=0; i<m*p; i++) {
	int someInt = 1 + rand() % 10;
	B[i] = someInt;
  }
  
  // Fill C with 0s
  for (int i=0; i<n*p; i++) {
	C_cpu[i] = 0;
	C_gpu[i] = 0;
  }
  
  // Allocate device memory
  int *d_A, *d_B, *d_C_gpu;
  
  cudaError_t error;

  error = cudaMalloc((void **) &d_A, mem_size_A);
  error = cudaMalloc((void **) &d_B, mem_size_B);
  error = cudaMalloc((void **) &d_C_gpu, mem_size_C);
  
  // copy host memory to device
  error = cudaMemcpy(d_A, A, mem_size_A, cudaMemcpyHostToDevice);
  error = cudaMemcpy(d_B, B, mem_size_B, cudaMemcpyHostToDevice);
  error = cudaMemcpy(d_C_gpu, C_gpu, mem_size_C, cudaMemcpyHostToDevice);
  
  // Setup execution parameters for parallel
  dim3 tile_size(32, 32);
  dim3 num_blocks(n/tile_size.x + (n % tile_size.x != 0), p/tile_size.y + (p % tile_size.y != 0));
  
  //Execute parallel code
  error = cudaEventCreate(&gpu_start_time);
  error = cudaEventCreate(&gpu_end_time);
  
  error = cudaEventRecord(gpu_start_time, NULL);
  //compute_tile<<<num_blocks, tile_size>>>(d_A, d_B, d_C_gpu, n, m, p);
  error = cudaEventRecord(gpu_end_time, NULL);
  error = cudaEventSynchronize(gpu_end_time);
  error = cudaEventElapsedTime(&gpu_total_time, gpu_start_time, gpu_end_time);
  
  cpu_start_time = clock();
  // MAIN COMPUTATION, SEQUENTIAL VERSION
  for (int row=0; row < n; row++) {
	for (int col = 0; col < p; col++) {
		int sum = 0;
		for (int i = 0; i < m; i++) {
			sum += A[row*m + i] * B[i*p + col];
		}
		C_cpu[row*p + col] = sum;
	}
  } 
  cpu_end_time = clock();
  
  cpu_total_time = ((double) (cpu_end_time - cpu_start_time)) / CLOCKS_PER_SEC;
  
  //Copy result from device to host
  error = cudaMemcpy(C_gpu, d_C_gpu, mem_size_C, cudaMemcpyDeviceToHost);
  
  cudaDeviceSynchronize();
  
  //Print values in our 2 c vectors to output.txt
  //Code taken from http://www.tutorialspoint.com/cprogramming/c_file_io.htm
  /*FILE *fpout;
  fpout = fopen("output.txt", "w+");
  fprintf(fpout, "index\tCPU\tGPU\tDifference\n");
  for (int i = 0; i < n; i++) {
	  int difference = A_cpu[i] - A_gpu[i];
	  fprintf(fpout, "%i\t%i\t%i\t%i\n", i, A_cpu[i], A_gpu[i], difference);
  }
  fclose(fpout);*/
  
  //Print out matrix A
  /*printf("Matrix A:\n");
  for (int row = 0; row < n; row++) {
	  for (int col = 0; col < m; col++) {
		  printf("%i ", A[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Print out matrix B
  /*printf("Matrix B:\n");
  for (int row = 0; row < m; row++) {
	  for (int col = 0; col < p; col++) {
		  printf("%i ", B[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Print out matrix C (CPU)
  /*printf("Matrix C (CPU):\n");
  for (int row = 0; row < n; row++) {
	  for (int col = 0; col < p; col++) {
		  printf("%i ", C_cpu[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Print out matrix C (GPU)
  /*printf("Matrix C (GPU):\n");
  for (int row = 0; row < n; row++) {
	  for (int col = 0; col < p; col++) {
		  printf("%i ", C_gpu[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Find discrepencies
  /*for (int row = 0; row < n; row++) {
	for (int col = 0; col < p; col++) {
	  if (C_gpu[row*n + col] != C_cpu[row*n + col]) {
		  printf("Error: C_gpu[%i] = %i, C_cpu[%i] = %i\n", row*n+col, C_gpu[row*n + col], row*n+col, C_cpu[row*n + col]);
	  }
	}
  }*/
  
  //Print performance time
  printf("CPU time was %f seconds\n", cpu_total_time);
  //printf("GPU time was %f milliseconds\n", gpu_total_time);
  
  // Clean up memory
  free(A);
  free(B);
  free(C_cpu);
  free(C_gpu);
  
  cudaFree(d_A);
  cudaFree(d_B);
  cudaFree(d_C_gpu);
  
  cudaDeviceReset();
  
  return 0;
}

	.file	"tmpxft_00269fe0_00000000-6_final_Eric_Sheeder.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Usage: <./executable.exe n m p>, where n, m, and p are the dimensions of A (nxm) and B (mxp)"
.LC2:
	.string	"CPU time was %f seconds\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%edi, %ebp
	xorl	%edi, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	cmpl	$4, %ebp
	je	.L3
	movl	$2, %edi
	leaq	.LC0(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L3:
	movq	8(%rbx), %rdi
	xorl	%r15d, %r15d
	call	atoi@PLT
	movq	16(%rbx), %rdi
	movl	%eax, 52(%rsp)
	call	atoi@PLT
	movq	24(%rbx), %rdi
	movl	%eax, %ebp
	call	atoi@PLT
	movl	52(%rsp), %r14d
	movl	%ebp, %r13d
	movl	%eax, %ebx
	imull	%ebp, %r14d
	imull	%ebx, %r13d
	leal	0(,%r14,4), %eax
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	call	malloc@PLT
	movq	%rax, 8(%rsp)
	leal	0(,%r13,4), %eax
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	call	malloc@PLT
	movl	52(%rsp), %r12d
	movq	%rax, 16(%rsp)
	imull	%ebx, %r12d
	leal	0(,%r12,4), %eax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rdi
	movq	%rax, 56(%rsp)
	call	malloc@PLT
	movq	%rax, 24(%rsp)
.L4:
	cmpl	%r15d, %r14d
	jle	.L19
	call	rand@PLT
	movl	$10, %ecx
	cltd
	idivl	%ecx
	movq	8(%rsp), %rax
	incl	%edx
	movl	%edx, (%rax,%r15,4)
	incq	%r15
	jmp	.L4
.L19:
	xorl	%r15d, %r15d
	movl	$10, %r14d
.L6:
	cmpl	%r15d, %r13d
	jle	.L20
	call	rand@PLT
	cltd
	idivl	%r14d
	movq	16(%rsp), %rax
	incl	%edx
	movl	%edx, (%rax,%r15,4)
	incq	%r15
	jmp	.L6
.L20:
	xorl	%eax, %eax
.L8:
	cmpl	%eax, %r12d
	jle	.L21
	movq	56(%rsp), %rcx
	xorl	%edx, %edx
	xorl	%esi, %esi
	movl	%edx, (%rcx,%rax,4)
	movq	24(%rsp), %rcx
	movl	%esi, (%rcx,%rax,4)
	incq	%rax
	jmp	.L8
.L21:
	movq	32(%rsp), %rsi
	leaq	96(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rsi
	leaq	104(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	112(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	96(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	104(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	112(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	80(%rsp), %rsi
	movq	88(%rsp), %rdx
	leaq	76(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	clock@PLT
	xorl	%ecx, %ecx
	xorl	%esi, %esi
	xorl	%edi, %edi
	movq	%rax, %r13
	movslq	%ebx, %rax
	leaq	0(,%rax,4), %r14
.L10:
	movl	52(%rsp), %eax
	cmpl	%eax, %edi
	jge	.L14
	movq	56(%rsp), %rdx
	movslq	%esi, %rax
	leaq	(%rdx,%rax,4), %r12
	movq	8(%rsp), %rdx
	movslq	%ecx, %rax
	leaq	(%rdx,%rax,4), %r11
	xorl	%eax, %eax
.L15:
	cmpl	%eax, %ebx
	jle	.L12
	movq	16(%rsp), %rdx
	xorl	%r8d, %r8d
	leaq	(%rdx,%rax,4), %r9
	xorl	%edx, %edx
.L13:
	cmpl	%edx, %ebp
	jle	.L22
	movl	(%r11,%rdx,4), %r10d
	imull	(%r9), %r10d
	incq	%rdx
	addq	%r14, %r9
	addl	%r10d, %r8d
	jmp	.L13
.L22:
	movl	%r8d, (%r12,%rax,4)
	incq	%rax
	jmp	.L15
.L12:
	incl	%edi
	addl	%ebx, %esi
	addl	%ebp, %ecx
	jmp	.L10
.L14:
	call	clock@PLT
	movq	(%rsp), %rdx
	movq	112(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	subq	%r13, %rax
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC1(%rip), %xmm0
	movsd	%xmm0, 32(%rsp)
	call	cudaMemcpy@PLT
	call	cudaDeviceSynchronize@PLT
	movsd	32(%rsp), %xmm0
	leaq	.LC2(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	56(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rdi
	call	free@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z39__device_stub__Z12compute_tilePiS_S_iiiPiS_S_iii
	.type	_Z39__device_stub__Z12compute_tilePiS_S_iiiPiS_S_iii, @function
_Z39__device_stub__Z12compute_tilePiS_S_iiiPiS_S_iii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12compute_tilePiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L23:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z39__device_stub__Z12compute_tilePiS_S_iiiPiS_S_iii, .-_Z39__device_stub__Z12compute_tilePiS_S_iiiPiS_S_iii
	.globl	_Z12compute_tilePiS_S_iii
	.type	_Z12compute_tilePiS_S_iii, @function
_Z12compute_tilePiS_S_iii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z12compute_tilePiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2053:
	.size	_Z12compute_tilePiS_S_iii, .-_Z12compute_tilePiS_S_iii
	.section	.rodata.str1.1
.LC3:
	.string	"_Z12compute_tilePiS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12compute_tilePiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <cstdlib>
#include <time.h>
#include <stdlib.h>
#include <math.h>

/*
	Authors: Eric Sheeder, Gokul Natesan, Jacob Hollister
	Parallel Computing Final Project
	
	This code generates 2 large matrices and multiplies them, once on the GPU and once on the CPU
	It expects 3 variables on the command line, n, m, and p, where n and m are the dimensions of A and m and p are the dimensions of B
	This code currently only works accurately when n, m, and p are all multiples of 32
	
	Algorithm was learned and taken from this paper:
	https://webs.um.es/jmgarcia/miwiki/lib/exe/fetch.php?id=pubs&cache=cache&media=parco09.pdf
*/

// CUDA runtime
#include <hip/hip_runtime.h>

// Helper functions and utilities to work with CUDA
//#include <helper_functions.h>

//This function computes the final values for a single tile in the output matrix (C)
__global__ void compute_tile(int *d_A, int *d_B, int *d_C_gpu, int n, int m, int p) {
	// Block index
    int bx = blockIdx.x;
	int by = blockIdx.y;

    // Thread index
    int tx = threadIdx.x;
	int ty = threadIdx.y;
	
	//Chunk of 32x32 values loaded from A and B
	__shared__ float A[32][32];
	__shared__ float B[32][32];
	
	//Offset into A and B for each thread so it knows which piece of data to load into the shared arrays
	int indexA = by * (m*blockDim.y) + ty * m + tx;
	int indexB = bx*blockDim.x + ty*p + tx;
	
	//Each thread keeps track of its own sum in this variable
	int sum = 0;
		
	//Run through multiple tiles in A and B to compute our values for our tile in C
	for (int i = 0; i < p; i+=blockDim.x) {
		//Have each thread load a value into A and B
		A[ty][tx] = d_A[indexA];
		B[ty][tx] = d_B[indexB];
		//Synch threads so all threads wait until all data is loaded before we start calculating
		__syncthreads();
		//Have each thread run through the section of A and B we are at, doing 32 multiplications and summing them
		for (int j = 0; j < blockDim.x; j++) {
			sum += A[ty][j] * B[j][tx];
		}
		//Synch threads again so we know each thread is ready to move on to the next part of A and Block
		__syncthreads();
		indexA += blockDim.x;
		indexB += p*blockDim.x;
	}

	
	//Each thread should now have a complete value for its part in C, so figure out where it should go and store it
	int indexC = bx * blockDim.x + by * (p * blockDim.y) + p * ty + tx;
	d_C_gpu[indexC] = sum;
}

int main (int argc, char *argv[]) {
  int *A, *B, *C_cpu, *C_gpu; // matrices
  int n, m, p; // dimensions of matrices
  srand(time(NULL)); //random numbers each time
  clock_t cpu_start_time, cpu_end_time;
  hipEvent_t gpu_start_time, gpu_end_time;
  double cpu_total_time;
  float gpu_total_time;
  
  //Make sure user puts in right parameters
  if (argc !=4) {
	printf("Usage: <./executable.exe n m p>, where n, m, and p are the dimensions of A (nxm) and B (mxp)");
	exit(1);
  }
  
  n = atoi(argv[1]);
  m = atoi(argv[2]);
  p = atoi(argv[3]);
  
  // Read number of rows (nr), number of columns (nc) and
  // number of elements and allocate memory for row_ptr, indices, data, b and c.
  unsigned int mem_size_A = (n*m)*sizeof(int);
  A = (int *) malloc (mem_size_A);
  unsigned int mem_size_B = (m*p)*sizeof(int);
  B = (int *) malloc (mem_size_B);
  unsigned int mem_size_C = (n*p)*sizeof(int);
  C_cpu = (int *) malloc (mem_size_C);
  C_gpu = (int *) malloc (mem_size_C);

  // Fill A with randomly generated data
  for (int i=0; i<n*m; i++) {
	int someInt = 1 + rand() % 10;
	A[i] = someInt;
  }
  
  // Fill B with randomly generated data
  for (int i=0; i<m*p; i++) {
	int someInt = 1 + rand() % 10;
	B[i] = someInt;
  }
  
  // Fill C with 0s
  for (int i=0; i<n*p; i++) {
	C_cpu[i] = 0;
	C_gpu[i] = 0;
  }
  
  // Allocate device memory
  int *d_A, *d_B, *d_C_gpu;
  
  hipError_t error;

  error = hipMalloc((void **) &d_A, mem_size_A);
  error = hipMalloc((void **) &d_B, mem_size_B);
  error = hipMalloc((void **) &d_C_gpu, mem_size_C);
  
  // copy host memory to device
  error = hipMemcpy(d_A, A, mem_size_A, hipMemcpyHostToDevice);
  error = hipMemcpy(d_B, B, mem_size_B, hipMemcpyHostToDevice);
  error = hipMemcpy(d_C_gpu, C_gpu, mem_size_C, hipMemcpyHostToDevice);
  
  // Setup execution parameters for parallel
  dim3 tile_size(32, 32);
  dim3 num_blocks(n/tile_size.x + (n % tile_size.x != 0), p/tile_size.y + (p % tile_size.y != 0));
  
  //Execute parallel code
  error = hipEventCreate(&gpu_start_time);
  error = hipEventCreate(&gpu_end_time);
  
  error = hipEventRecord(gpu_start_time, NULL);
  //compute_tile<<<num_blocks, tile_size>>>(d_A, d_B, d_C_gpu, n, m, p);
  error = hipEventRecord(gpu_end_time, NULL);
  error = hipEventSynchronize(gpu_end_time);
  error = hipEventElapsedTime(&gpu_total_time, gpu_start_time, gpu_end_time);
  
  cpu_start_time = clock();
  // MAIN COMPUTATION, SEQUENTIAL VERSION
  for (int row=0; row < n; row++) {
	for (int col = 0; col < p; col++) {
		int sum = 0;
		for (int i = 0; i < m; i++) {
			sum += A[row*m + i] * B[i*p + col];
		}
		C_cpu[row*p + col] = sum;
	}
  } 
  cpu_end_time = clock();
  
  cpu_total_time = ((double) (cpu_end_time - cpu_start_time)) / CLOCKS_PER_SEC;
  
  //Copy result from device to host
  error = hipMemcpy(C_gpu, d_C_gpu, mem_size_C, hipMemcpyDeviceToHost);
  
  hipDeviceSynchronize();
  
  //Print values in our 2 c vectors to output.txt
  //Code taken from http://www.tutorialspoint.com/cprogramming/c_file_io.htm
  /*FILE *fpout;
  fpout = fopen("output.txt", "w+");
  fprintf(fpout, "index\tCPU\tGPU\tDifference\n");
  for (int i = 0; i < n; i++) {
	  int difference = A_cpu[i] - A_gpu[i];
	  fprintf(fpout, "%i\t%i\t%i\t%i\n", i, A_cpu[i], A_gpu[i], difference);
  }
  fclose(fpout);*/
  
  //Print out matrix A
  /*printf("Matrix A:\n");
  for (int row = 0; row < n; row++) {
	  for (int col = 0; col < m; col++) {
		  printf("%i ", A[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Print out matrix B
  /*printf("Matrix B:\n");
  for (int row = 0; row < m; row++) {
	  for (int col = 0; col < p; col++) {
		  printf("%i ", B[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Print out matrix C (CPU)
  /*printf("Matrix C (CPU):\n");
  for (int row = 0; row < n; row++) {
	  for (int col = 0; col < p; col++) {
		  printf("%i ", C_cpu[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Print out matrix C (GPU)
  /*printf("Matrix C (GPU):\n");
  for (int row = 0; row < n; row++) {
	  for (int col = 0; col < p; col++) {
		  printf("%i ", C_gpu[row*n + col]);
	  }
	  printf("\n");
  }*/
  
  //Find discrepencies
  /*for (int row = 0; row < n; row++) {
	for (int col = 0; col < p; col++) {
	  if (C_gpu[row*n + col] != C_cpu[row*n + col]) {
		  printf("Error: C_gpu[%i] = %i, C_cpu[%i] = %i\n", row*n+col, C_gpu[row*n + col], row*n+col, C_cpu[row*n + col]);
	  }
	}
  }*/
  
  //Print performance time
  printf("CPU time was %f seconds\n", cpu_total_time);
  //printf("GPU time was %f milliseconds\n", gpu_total_time);
  
  // Clean up memory
  free(A);
  free(B);
  free(C_cpu);
  free(C_gpu);
  
  hipFree(d_A);
  hipFree(d_B);
  hipFree(d_C_gpu);
  
  hipDeviceReset();
  
  return 0;
}

	.text
	.file	"final_Eric_Sheeder.hip"
	.globl	_Z27__device_stub__compute_tilePiS_S_iii # -- Begin function _Z27__device_stub__compute_tilePiS_S_iii
	.type	_Z27__device_stub__compute_tilePiS_S_iii,@function
_Z27__device_stub__compute_tilePiS_S_iii: # @_Z27__device_stub__compute_tilePiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12compute_tilePiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__compute_tilePiS_S_iii, .Lfunc_end0-_Z27__device_stub__compute_tilePiS_S_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %ebp
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	cmpl	$4, %ebp
	jne	.LBB1_10
# %bb.1:
	movq	8(%rbx), %rdi
	callq	atoi
	movl	%eax, %r13d
	movq	16(%rbx), %rdi
	callq	atoi
	movl	%eax, %r12d
	movq	24(%rbx), %rdi
	callq	atoi
	movl	%eax, %r15d
	movl	%r12d, %ebp
	imull	%r13d, %ebp
	leal	(,%rbp,4), %edi
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	callq	malloc
	movq	%rax, %rbx
	imull	%r15d, %r12d
	leal	(,%r12,4), %edi
	movq	%rdi, 40(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, %r14
	imull	%r13d, %r15d
	leal	(,%r15,4), %edi
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	testl	%ebp, %ebp
	jle	.LBB1_4
# %bb.2:                                # %.lr.ph.preheader
	movl	%ebp, %r13d
	xorl	%ebp, %ebp
.LBB1_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%rbx,%rbp,4)
	incq	%rbp
	cmpq	%rbp, %r13
	jne	.LBB1_3
.LBB1_4:                                # %.preheader93
	testl	%r12d, %r12d
	jle	.LBB1_7
# %bb.5:                                # %.lr.ph96.preheader
	movl	%r12d, %r12d
	xorl	%r13d, %r13d
.LBB1_6:                                # %.lr.ph96
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltq
	imulq	$1717986919, %rax, %rcx         # imm = 0x66666667
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$34, %rcx
	addl	%edx, %ecx
	addl	%ecx, %ecx
	leal	(%rcx,%rcx,4), %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%r14,%r13,4)
	incq	%r13
	cmpq	%r13, %r12
	jne	.LBB1_6
.LBB1_7:                                # %.preheader92
	testl	%r15d, %r15d
	movq	56(%rsp), %rbp                  # 8-byte Reload
	jle	.LBB1_9
# %bb.8:                                # %.lr.ph98.preheader
	movl	%r15d, %edx
	shlq	$2, %rdx
	movq	%rbp, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.LBB1_9:                                # %._crit_edge
	leaq	32(%rsp), %rdi
	movq	8(%rsp), %r12                   # 8-byte Reload
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movq	40(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	48(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbp, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	80(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	72(%rsp), %r13
	movq	%r13, %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r13), %rdi
	callq	hipEventSynchronize
	movq	(%r12), %rsi
	movq	(%r13), %rdx
	leaq	68(%rsp), %rdi
	callq	hipEventElapsedTime
	callq	clock
	movq	%rax, %r12
	callq	clock
	subq	%r12, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	leaq	16(%rsp), %r12
	movq	(%r12), %rsi
	movq	%rbp, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipDeviceSynchronize
	movl	$.L.str.1, %edi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%rbp, %rdi
	callq	free
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	callq	hipFree
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	callq	hipFree
	movq	(%r12), %rdi
	callq	hipFree
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_10:
	.cfi_def_cfa_offset 144
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12compute_tilePiS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12compute_tilePiS_S_iii,@object # @_Z12compute_tilePiS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z12compute_tilePiS_S_iii
	.p2align	3, 0x0
_Z12compute_tilePiS_S_iii:
	.quad	_Z27__device_stub__compute_tilePiS_S_iii
	.size	_Z12compute_tilePiS_S_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Usage: <./executable.exe n m p>, where n, m, and p are the dimensions of A (nxm) and B (mxp)"
	.size	.L.str, 93

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"CPU time was %f seconds\n"
	.size	.L.str.1, 25

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12compute_tilePiS_S_iii"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__compute_tilePiS_S_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12compute_tilePiS_S_iii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12compute_tilePiS_S_iii ; -- Begin function _Z12compute_tilePiS_S_iii
	.globl	_Z12compute_tilePiS_S_iii
	.p2align	8
	.type	_Z12compute_tilePiS_S_iii,@function
_Z12compute_tilePiS_S_iii:              ; @_Z12compute_tilePiS_S_iii
; %bb.0:
	s_clause 0x3
	s_load_b64 s[8:9], s[0:1], 0x1c
	s_load_b32 s10, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v1, 0x3ff, v0
	s_mov_b32 s11, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v3, v2, s9
	s_lshr_b32 s0, s10, 16
	s_and_b32 s1, s10, 0xffff
	s_cmp_gt_i32 s9, 0
	s_cbranch_scc1 .LBB0_2
; %bb.1:                                ; %.._crit_edge62_crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v3, v1
	s_mul_i32 s10, s15, s0
	s_mov_b32 s12, 0
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s11, -1
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $sgpr10
                                        ; implicit-def: $vgpr4
.LBB0_3:                                ; %Flow89
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_mul_i32 s14, s14, s1
	s_cbranch_vccnz .LBB0_8
; %bb.4:                                ; %.lr.ph61
	s_mul_i32 s10, s15, s0
	v_lshlrev_b32_e32 v5, 2, v1
	s_cmp_lg_u32 s1, 0
	v_add_nc_u32_e32 v8, s10, v2
	s_cselect_b32 s0, -1, 0
	v_add_nc_u32_e32 v4, v3, v1
	v_lshlrev_b32_e32 v6, 7, v2
	v_or_b32_e32 v7, 0x1000, v5
	v_cndmask_b32_e64 v10, 0, 1, s0
	v_mad_u64_u32 v[2:3], null, v8, s8, v[1:2]
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v8, v6, v5
	v_add_nc_u32_e32 v0, s14, v4
	v_add_nc_u32_e32 v9, v7, v6
	v_cmp_ne_u32_e64 s0, 1, v10
	s_mov_b32 s8, 0
	s_mul_i32 s11, s1, s9
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_6 Depth 2
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s12, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_lshlrev_b64 v[12:13], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s4, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s0
	global_load_b32 v1, v[10:11], off
	global_load_b32 v3, v[12:13], off
	s_waitcnt vmcnt(1)
	v_cvt_f32_i32_e32 v10, v1
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v11, v3
	v_mov_b32_e32 v1, v7
	v_mov_b32_e32 v3, v6
	ds_store_b32 v8, v10
	ds_store_b32 v9, v11
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB0_7
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v10, v3
	ds_load_b32 v11, v1
	v_cvt_f32_i32_e32 v5, v5
	v_add_nc_u32_e32 v3, 4, v3
	v_add_nc_u32_e32 v1, 0x80, v1
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v10, v11
	v_cvt_i32_f32_e32 v5, v5
	s_cbranch_scc0 .LBB0_6
.LBB0_7:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_5 Depth=1
	v_add_nc_u32_e32 v2, s1, v2
	v_add_nc_u32_e32 v0, s11, v0
	s_add_i32 s8, s8, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s8, s9
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_5
	s_branch .LBB0_9
.LBB0_8:
	v_mov_b32_e32 v5, s12
.LBB0_9:                                ; %Flow90
	s_mul_i32 s0, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s14, s0, v4
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12compute_tilePiS_S_iii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12compute_tilePiS_S_iii, .Lfunc_end0-_Z12compute_tilePiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 18
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12compute_tilePiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12compute_tilePiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
