//blur cuda
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/time.h>

#define TY 32
#define TX 32


//this kernel does the regular blurring process
__global__
void blurKernel (int *R, int *G, int *B, int *Rnew, int *Gnew, int *Bnew, int rowsize, int colsize)
{
	int row = (blockIdx.y * blockDim.y) + threadIdx.y;
	int col = (blockIdx.x * blockDim.x) + threadIdx.x;
	int x = (row * colsize) + col;
	int xu = x - colsize;
	int xd = x + colsize;
	int xr = x + 1;
	int xl = x - 1;

	if((row < rowsize) && (col < colsize)) {
		if (row != 0 && row != (rowsize-1) && col != 0 && col != (colsize-1)){
			Rnew[x] = (R[xr]+R[xl]+R[xd]+R[xu])/4;
			Gnew[x] = (G[xr]+G[xl]+G[xd]+G[xu])/4;
			Bnew[x] = (B[xr]+B[xl]+B[xd]+B[xu])/4;
		}
		else if (row == 0 && col != 0 && col != (colsize-1)){
			Rnew[x] = (R[xr]+R[xd]+R[xl])/3;
			Gnew[x] = (G[xr]+G[xd]+G[xl])/3;
			Bnew[x] = (B[xr]+B[xd]+B[xl])/3;
		}
		else if (row == (rowsize-1) && col != 0 && col != (colsize-1)){
			Rnew[x] = (R[xl]+R[xr]+R[xu])/3;
			Gnew[x] = (G[xl]+G[xr]+G[xu])/3;
			Bnew[x] = (B[xl]+B[xr]+B[xu])/3;
		}
		else if (col == 0 && row != 0 && row != (rowsize-1)){
			Rnew[x] = (R[xr]+R[xu]+R[xd])/3;
			Gnew[x] = (G[xr]+G[xu]+G[xd])/3;
			Bnew[x] = (B[xr]+B[xu]+B[xd])/3;
		}
		else if (col == (colsize-1) && row != 0 && row != (rowsize-1)){
			Rnew[x] = (R[xd]+R[xl]+R[xu])/3;
			Gnew[x] = (G[xd]+G[xl]+G[xu])/3;
			Bnew[x] = (B[xd]+B[xl]+B[xu])/3;
		}
		else if (row==0 &&col==0){
			Rnew[x] = (R[xd]+R[xr])/2;
			Gnew[x] = (G[xd]+G[xr])/2;
			Bnew[x] = (B[xd]+B[xr])/2;
		}
		else if (row==0 &&col==(colsize-1)){
			Rnew[x] = (R[xd]+R[xl])/2;
			Gnew[x] = (G[xd]+G[xl])/2;
			Bnew[x] = (B[xd]+B[xl])/2;
		}
		else if (row==(rowsize-1) &&col==0){
			Rnew[x] = (R[xu]+R[xr])/2;
			Gnew[x] = (G[xu]+G[xr])/2;
			Bnew[x] = (B[xu]+B[xr])/2;
		}
		else if (row==(rowsize-1) &&col==(colsize-1)){
			Rnew[x] = (R[xu]+R[xl])/2;
			Gnew[x] = (G[xu]+G[xl])/2;
			Bnew[x] = (B[xu]+B[xl])/2;
		}
	}
}


__global__
void copyKernel(int *R, int *B, int *G, int *Rnew, int *Gnew, int *Bnew, int rowsize, int colsize)
{
	int row = (blockIdx.y * blockDim.y) + threadIdx.y;
	int col = (blockIdx.x * blockDim.x) + threadIdx.x;
	int x = (row * colsize) + col;

	if((col < colsize) && (row < rowsize)){
		R[x] = Rnew[x];
		G[x] = Gnew[x];
		B[x] = Bnew[x];
	}
}

int main (int argc, const char * argv[]) {
	static int const maxlen = 200, rowsize = 521, colsize = 428, linelen = 12;
	char str[maxlen], lines[5][maxlen];
	FILE *fp, *fout;
	int nlines = 0;
	unsigned int h1, h2, h3;
	char *sptr;
	int R[rowsize][colsize], G[rowsize][colsize], B[rowsize][colsize];
	int row = 0, col = 0, nblurs, lineno=0, k;
	struct timeval tim;
	
	// 5a. timing reading of image

	gettimeofday(&tim, NULL);
	double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
	fp = fopen ("David.ps", "r");

	while(! feof(fp))
	{
		fscanf(fp, "\n%[^\n]", str);
		if (nlines < 5) {strcpy((char *)lines[nlines++],(char *)str);}
		else{
			for (sptr=&str[0];*sptr != '\0';sptr+=6){
				sscanf(sptr,"%2x",&h1);
				sscanf(sptr+2,"%2x",&h2);
				sscanf(sptr+4,"%2x",&h3);
				
				if (col==colsize){
					col = 0;
					row++;
				}
				if (row < rowsize) {
					R[row][col] = h1;
					G[row][col] = h2;
					B[row][col] = h3;
				}
				col++;
			}
		}
	}
	fclose(fp);

	gettimeofday(&tim, NULL);
	double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5a Reading Image File took :%.6lf seconds elapsed\n", t2-t1);
	//printf("%.6lf,", t2-t1 ); easy csv output

	nblurs = 160;

	//5b :timing allocation of device memory
	gettimeofday(&tim, NULL);
	double t1b=tim.tv_sec+(tim.tv_usec/1000000.0);

	//intialise int variables
	int *d_R;
	int *d_G;
	int *d_B;

	int *d_Rnew , *d_Gnew , *d_Bnew;

	int sizei = sizeof(int) * (rowsize*colsize);

	//memory allocation

	cudaMalloc((void **)&d_R, sizei);
	cudaMalloc((void **)&d_G, sizei);
	cudaMalloc((void **)&d_B, sizei);
	cudaMalloc((void **)&d_Rnew, sizei);
	cudaMalloc((void **)&d_Gnew, sizei);
	cudaMalloc((void **)&d_Bnew, sizei);


	gettimeofday(&tim, NULL);
	double t2b=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5b Allocation of device memory took :%.6lf seconds elapsed\n", t2b-t1b);
	//printf("%.6lf,", t2b-t1b );


	//5c : timing Transferring data between host and device mem
	gettimeofday(&tim, NULL);
	double t3=tim.tv_sec+(tim.tv_usec/1000000.0);

	cudaMemcpy(d_R, R, sizei, cudaMemcpyHostToDevice);
	cudaMemcpy(d_G, G, sizei, cudaMemcpyHostToDevice);
	cudaMemcpy(d_B, B, sizei, cudaMemcpyHostToDevice);
	gettimeofday(&tim, NULL);
	double t4=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5c Transfer of data took :%.6lf seconds elapsed\n", t4-t3);
	//printf("%.6lf,", t4-t3 );


	//5d: time doing the blurring
	gettimeofday(&tim, NULL);
	double t5=tim.tv_sec+(tim.tv_usec/1000000.0);

	dim3 dimGrid(ceil(colsize/(float)TX), ceil(rowsize/(float)TY), 1);
	dim3 dimBlock(32, 32, 1);
	//run blurring
	for (k=0; k < nblurs; k++){
		blurKernel<<<dimGrid,dimBlock>>>(d_R, d_G, d_B, d_Rnew, d_Gnew, d_Bnew, rowsize, colsize);
		copyKernel<<<dimGrid,dimBlock>>>(d_R, d_G, d_B, d_Rnew, d_Gnew, d_Bnew, rowsize, colsize);
	}

	//return data back to host
	cudaMemcpy(R, d_R, sizei, cudaMemcpyDeviceToHost);
	cudaMemcpy(G, d_G, sizei, cudaMemcpyDeviceToHost);
	cudaMemcpy(B, d_B, sizei, cudaMemcpyDeviceToHost);

	cudaFree(d_R); cudaFree(d_G); cudaFree(d_B);
	cudaFree(d_Rnew); cudaFree(d_Gnew); cudaFree(d_Bnew);

	gettimeofday(&tim, NULL);
	double t6=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5d Blurring took :%.6lf seconds elapsed\n", t6-t5);
	//printf("%.6lf,", t6-t5 );
	


	//5e: time to output blurred image
	gettimeofday(&tim, NULL);
	double t7=tim.tv_sec+(tim.tv_usec/1000000.0);

	fout= fopen("DavidBlur.ps", "w");
	for (k=0;k<nlines;k++) fprintf(fout,"\n%s", lines[k]);
	fprintf(fout,"\n");
	for(row=0;row<rowsize;row++){
		for (col=0;col<colsize;col++){
			fprintf(fout,"%02x%02x%02x",R[row][col],G[row][col],B[row][col]);
			lineno++;
			if (lineno==linelen){
				fprintf(fout,"\n");
				lineno = 0;
			}
		}
	}
	fclose(fout);
    //return 0;


	gettimeofday(&tim, NULL);
	double t8=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5e Outputting blurre image took :%.6lf seconds elapsed\n", t8-t7);
	//printf("%.6lf,\n", t8-t7 );
	return 0;
}
	.file	"tmpxft_0020a0ab_00000000-6_blurCUDA.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z10blurKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	.type	_Z42__device_stub__Z10blurKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z42__device_stub__Z10blurKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10blurKernelPiS_S_S_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z42__device_stub__Z10blurKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z42__device_stub__Z10blurKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	.globl	_Z10blurKernelPiS_S_S_S_S_ii
	.type	_Z10blurKernelPiS_S_S_S_S_ii, @function
_Z10blurKernelPiS_S_S_S_S_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z10blurKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	.cfi_endproc
.LFE2053:
	.size	_Z10blurKernelPiS_S_S_S_S_ii, .-_Z10blurKernelPiS_S_S_S_S_ii
	.globl	_Z42__device_stub__Z10copyKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	.type	_Z42__device_stub__Z10copyKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii, @function
_Z42__device_stub__Z10copyKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10copyKernelPiS_S_S_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L8:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z42__device_stub__Z10copyKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii, .-_Z42__device_stub__Z10copyKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	.globl	_Z10copyKernelPiS_S_S_S_S_ii
	.type	_Z10copyKernelPiS_S_S_S_S_ii, @function
_Z10copyKernelPiS_S_S_S_S_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z10copyKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	.cfi_endproc
.LFE2055:
	.size	_Z10copyKernelPiS_S_S_S_S_ii, .-_Z10copyKernelPiS_S_S_S_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"r"
.LC2:
	.string	"David.ps"
.LC3:
	.string	"\n%[^\n]"
.LC4:
	.string	"%2x"
.LC5:
	.string	"part 5a Reading Image File took :%.6lf seconds elapsed\n"
.LC6:
	.string	"part 5b Allocation of device memory took :%.6lf seconds elapsed\n"
.LC7:
	.string	"part 5c Transfer of data took :%.6lf seconds elapsed\n"
.LC8:
	.string	"part 5d Blurring took :%.6lf seconds elapsed\n"
.LC9:
	.string	"w"
.LC10:
	.string	"DavidBlur.ps"
.LC11:
	.string	"\n%s"
.LC12:
	.string	"\n"
.LC13:
	.string	"%02x%02x%02x"
.LC14:
	.string	"part 5e Outputting blurre image took :%.6lf seconds elapsed\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	-2674688(%rsp), %r11
	.cfi_def_cfa 11, 2674744
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$2520, %rsp
	.cfi_def_cfa_offset 2677264
	xorl	%esi, %esi
	xorl	%r12d, %r12d
	xorl	%r13d, %r13d
	xorl	%ebx, %ebx
	leaq	.LC3(%rip), %r14
	movq	%fs:40, %rax
	movq	%rax, 2677192(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	leaq	.LC1(%rip), %rsi
	cvtsi2sdq	128(%rsp), %xmm0
	divsd	.LC0(%rip), %xmm0
	leaq	.LC2(%rip), %rdi
	addsd	%xmm1, %xmm0
	movsd	%xmm0, 24(%rsp)
	call	fopen@PLT
	movq	%rax, 16(%rsp)
.L14:
	movq	16(%rsp), %rdi
	call	feof@PLT
	testl	%eax, %eax
	jne	.L35
	leaq	2676992(%rsp), %rbp
	movq	16(%rsp), %rdi
	xorl	%eax, %eax
	movq	%r14, %rsi
	movq	%rbp, %rdx
	call	__isoc23_fscanf@PLT
	cmpl	$4, %ebx
	jg	.L31
	leal	1(%rbx), %r15d
	movl	$1000, %edx
	movq	%rbp, %rsi
	imulq	$200, %rbx, %rbx
	cmpq	%rdx, %rbx
	leaq	136(%rsp,%rbx), %rdi
	cmovnb	%rbx, %rdx
	subq	%rbx, %rdx
	movslq	%r15d, %rbx
	call	__strcpy_chk@PLT
	jmp	.L14
.L31:
	leaq	.LC4(%rip), %r15
.L15:
	cmpb	$0, 0(%rbp)
	je	.L14
	leaq	36(%rsp), %rdx
	movq	%r15, %rsi
	movq	%rbp, %rdi
	xorl	%eax, %eax
	call	__isoc23_sscanf@PLT
	leaq	40(%rsp), %rdx
	leaq	2(%rbp), %rdi
	xorl	%eax, %eax
	movq	%r15, %rsi
	call	__isoc23_sscanf@PLT
	xorl	%eax, %eax
	leaq	44(%rsp), %rdx
	leaq	4(%rbp), %rdi
	movq	%r15, %rsi
	call	__isoc23_sscanf@PLT
	cmpl	$428, %r12d
	jne	.L17
	incl	%r13d
	xorl	%r12d, %r12d
.L17:
	cmpl	$520, %r13d
	jg	.L18
	movslq	%r13d, %rax
	movslq	%r12d, %rdx
	imulq	$428, %rax, %rax
	addq	%rdx, %rax
	movl	36(%rsp), %edx
	movl	%edx, 1136(%rsp,%rax,4)
	movl	40(%rsp), %edx
	movl	%edx, 893088(%rsp,%rax,4)
	movl	44(%rsp), %edx
	movl	%edx, 1785040(%rsp,%rax,4)
.L18:
	incl	%r12d
	addq	$6, %rbp
	jmp	.L15
.L35:
	movq	16(%rsp), %rdi
	leaq	1136(%rsp), %r13
	leaq	893088(%rsp), %r14
	movl	$160, %r12d
	leaq	1785040(%rsp), %rbp
	call	fclose@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	leaq	.LC5(%rip), %rsi
	movb	$1, %al
	cvtsi2sdq	128(%rsp), %xmm0
	movl	$2, %edi
	divsd	.LC0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	24(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	leaq	48(%rsp), %rdi
	movl	$891952, %esi
	cvtsi2sdq	120(%rsp), %xmm1
	cvtsi2sdq	128(%rsp), %xmm0
	divsd	.LC0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movsd	%xmm0, 16(%rsp)
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$891952, %esi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movl	$891952, %esi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movl	$891952, %esi
	call	cudaMalloc@PLT
	leaq	80(%rsp), %rdi
	movl	$891952, %esi
	call	cudaMalloc@PLT
	leaq	88(%rsp), %rdi
	movl	$891952, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	leaq	.LC6(%rip), %rsi
	movb	$1, %al
	cvtsi2sdq	128(%rsp), %xmm0
	movl	$2, %edi
	divsd	.LC0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	16(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	movq	48(%rsp), %rdi
	movq	%r13, %rsi
	cvtsi2sdq	128(%rsp), %xmm0
	movl	$1, %ecx
	movl	$891952, %edx
	divsd	.LC0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	movsd	%xmm0, 16(%rsp)
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	$891952, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$891952, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	leaq	.LC7(%rip), %rsi
	movb	$1, %al
	cvtsi2sdq	128(%rsp), %xmm0
	movl	$2, %edi
	divsd	.LC0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	16(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	movabsq	$73014444046, %rax
	movl	$1, 104(%rsp)
	cvtsi2sdq	128(%rsp), %xmm0
	movq	%rax, 96(%rsp)
	divsd	.LC0(%rip), %xmm0
	movabsq	$137438953504, %rax
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	addsd	%xmm1, %xmm0
	movsd	%xmm0, 16(%rsp)
.L23:
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	$428
	.cfi_def_cfa_offset 2677272
	pushq	$521
	.cfi_def_cfa_offset 2677280
	movq	104(%rsp), %r9
	movq	96(%rsp), %r8
	movq	88(%rsp), %rcx
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z42__device_stub__Z10blurKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	popq	%rcx
	.cfi_def_cfa_offset 2677272
	popq	%rsi
	.cfi_def_cfa_offset 2677264
.L21:
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	pushq	$428
	.cfi_def_cfa_offset 2677272
	pushq	$521
	.cfi_def_cfa_offset 2677280
	movq	104(%rsp), %r9
	movq	96(%rsp), %r8
	movq	88(%rsp), %rcx
	movq	80(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z42__device_stub__Z10copyKernelPiS_S_S_S_S_iiPiS_S_S_S_S_ii
	popq	%rax
	.cfi_def_cfa_offset 2677272
	popq	%rdx
	.cfi_def_cfa_offset 2677264
.L22:
	decl	%r12d
	jne	.L23
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	xorl	%r15d, %r15d
	movl	$891952, %edx
	leaq	.LC11(%rip), %r12
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	movl	$891952, %edx
	call	cudaMemcpy@PLT
	movq	64(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$891952, %edx
	leaq	136(%rsp), %rbp
	call	cudaMemcpy@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	leaq	.LC8(%rip), %rsi
	movb	$1, %al
	cvtsi2sdq	128(%rsp), %xmm0
	movl	$2, %edi
	divsd	.LC0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	16(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	leaq	.LC9(%rip), %rsi
	cvtsi2sdq	128(%rsp), %xmm0
	divsd	.LC0(%rip), %xmm0
	leaq	.LC10(%rip), %rdi
	addsd	%xmm1, %xmm0
	movsd	%xmm0, 24(%rsp)
	call	fopen@PLT
	movq	%rax, 16(%rsp)
.L24:
	cmpl	%r15d, %ebx
	jle	.L36
	movq	16(%rsp), %rdi
	movq	%rbp, %rcx
	movq	%r12, %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	incl	%r15d
	addq	$200, %rbp
	call	__fprintf_chk@PLT
	jmp	.L24
.L36:
	movq	16(%rsp), %rdi
	leaq	.LC12(%rip), %rdx
	xorl	%eax, %eax
	xorl	%ebx, %ebx
	movl	$2, %esi
	xorl	%r15d, %r15d
	call	__fprintf_chk@PLT
.L26:
	movq	%rbx, %rbp
	movl	$428, %r12d
.L28:
	movl	0(%r13,%rbp), %ecx
	movl	(%r14,%rbp), %r8d
	movl	$2, %esi
	xorl	%eax, %eax
	movl	1785040(%rsp,%rbp), %r9d
	movq	16(%rsp), %rdi
	leaq	.LC13(%rip), %rdx
	incl	%r15d
	call	__fprintf_chk@PLT
	cmpl	$12, %r15d
	jne	.L27
	movq	16(%rsp), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	xorl	%r15d, %r15d
	leaq	.LC12(%rip), %rdx
	call	__fprintf_chk@PLT
.L27:
	addq	$4, %rbp
	decl	%r12d
	jne	.L28
	addq	$1712, %rbx
	cmpq	$891952, %rbx
	jne	.L26
	movq	16(%rsp), %rdi
	call	fclose@PLT
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	cvtsi2sdq	120(%rsp), %xmm1
	leaq	.LC14(%rip), %rsi
	movb	$1, %al
	cvtsi2sdq	128(%rsp), %xmm0
	movl	$2, %edi
	divsd	.LC0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	24(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	2677192(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$2677208, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC15:
	.string	"_Z10copyKernelPiS_S_S_S_S_ii"
.LC16:
	.string	"_Z10blurKernelPiS_S_S_S_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10copyKernelPiS_S_S_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10blurKernelPiS_S_S_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//blur cuda
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/time.h>

#define TY 32
#define TX 32


//this kernel does the regular blurring process
__global__
void blurKernel (int *R, int *G, int *B, int *Rnew, int *Gnew, int *Bnew, int rowsize, int colsize)
{
	int row = (blockIdx.y * blockDim.y) + threadIdx.y;
	int col = (blockIdx.x * blockDim.x) + threadIdx.x;
	int x = (row * colsize) + col;
	int xu = x - colsize;
	int xd = x + colsize;
	int xr = x + 1;
	int xl = x - 1;

	if((row < rowsize) && (col < colsize)) {
		if (row != 0 && row != (rowsize-1) && col != 0 && col != (colsize-1)){
			Rnew[x] = (R[xr]+R[xl]+R[xd]+R[xu])/4;
			Gnew[x] = (G[xr]+G[xl]+G[xd]+G[xu])/4;
			Bnew[x] = (B[xr]+B[xl]+B[xd]+B[xu])/4;
		}
		else if (row == 0 && col != 0 && col != (colsize-1)){
			Rnew[x] = (R[xr]+R[xd]+R[xl])/3;
			Gnew[x] = (G[xr]+G[xd]+G[xl])/3;
			Bnew[x] = (B[xr]+B[xd]+B[xl])/3;
		}
		else if (row == (rowsize-1) && col != 0 && col != (colsize-1)){
			Rnew[x] = (R[xl]+R[xr]+R[xu])/3;
			Gnew[x] = (G[xl]+G[xr]+G[xu])/3;
			Bnew[x] = (B[xl]+B[xr]+B[xu])/3;
		}
		else if (col == 0 && row != 0 && row != (rowsize-1)){
			Rnew[x] = (R[xr]+R[xu]+R[xd])/3;
			Gnew[x] = (G[xr]+G[xu]+G[xd])/3;
			Bnew[x] = (B[xr]+B[xu]+B[xd])/3;
		}
		else if (col == (colsize-1) && row != 0 && row != (rowsize-1)){
			Rnew[x] = (R[xd]+R[xl]+R[xu])/3;
			Gnew[x] = (G[xd]+G[xl]+G[xu])/3;
			Bnew[x] = (B[xd]+B[xl]+B[xu])/3;
		}
		else if (row==0 &&col==0){
			Rnew[x] = (R[xd]+R[xr])/2;
			Gnew[x] = (G[xd]+G[xr])/2;
			Bnew[x] = (B[xd]+B[xr])/2;
		}
		else if (row==0 &&col==(colsize-1)){
			Rnew[x] = (R[xd]+R[xl])/2;
			Gnew[x] = (G[xd]+G[xl])/2;
			Bnew[x] = (B[xd]+B[xl])/2;
		}
		else if (row==(rowsize-1) &&col==0){
			Rnew[x] = (R[xu]+R[xr])/2;
			Gnew[x] = (G[xu]+G[xr])/2;
			Bnew[x] = (B[xu]+B[xr])/2;
		}
		else if (row==(rowsize-1) &&col==(colsize-1)){
			Rnew[x] = (R[xu]+R[xl])/2;
			Gnew[x] = (G[xu]+G[xl])/2;
			Bnew[x] = (B[xu]+B[xl])/2;
		}
	}
}


__global__
void copyKernel(int *R, int *B, int *G, int *Rnew, int *Gnew, int *Bnew, int rowsize, int colsize)
{
	int row = (blockIdx.y * blockDim.y) + threadIdx.y;
	int col = (blockIdx.x * blockDim.x) + threadIdx.x;
	int x = (row * colsize) + col;

	if((col < colsize) && (row < rowsize)){
		R[x] = Rnew[x];
		G[x] = Gnew[x];
		B[x] = Bnew[x];
	}
}

int main (int argc, const char * argv[]) {
	static int const maxlen = 200, rowsize = 521, colsize = 428, linelen = 12;
	char str[maxlen], lines[5][maxlen];
	FILE *fp, *fout;
	int nlines = 0;
	unsigned int h1, h2, h3;
	char *sptr;
	int R[rowsize][colsize], G[rowsize][colsize], B[rowsize][colsize];
	int row = 0, col = 0, nblurs, lineno=0, k;
	struct timeval tim;
	
	// 5a. timing reading of image

	gettimeofday(&tim, NULL);
	double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
	fp = fopen ("David.ps", "r");

	while(! feof(fp))
	{
		fscanf(fp, "\n%[^\n]", str);
		if (nlines < 5) {strcpy((char *)lines[nlines++],(char *)str);}
		else{
			for (sptr=&str[0];*sptr != '\0';sptr+=6){
				sscanf(sptr,"%2x",&h1);
				sscanf(sptr+2,"%2x",&h2);
				sscanf(sptr+4,"%2x",&h3);
				
				if (col==colsize){
					col = 0;
					row++;
				}
				if (row < rowsize) {
					R[row][col] = h1;
					G[row][col] = h2;
					B[row][col] = h3;
				}
				col++;
			}
		}
	}
	fclose(fp);

	gettimeofday(&tim, NULL);
	double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5a Reading Image File took :%.6lf seconds elapsed\n", t2-t1);
	//printf("%.6lf,", t2-t1 ); easy csv output

	nblurs = 160;

	//5b :timing allocation of device memory
	gettimeofday(&tim, NULL);
	double t1b=tim.tv_sec+(tim.tv_usec/1000000.0);

	//intialise int variables
	int *d_R;
	int *d_G;
	int *d_B;

	int *d_Rnew , *d_Gnew , *d_Bnew;

	int sizei = sizeof(int) * (rowsize*colsize);

	//memory allocation

	hipMalloc((void **)&d_R, sizei);
	hipMalloc((void **)&d_G, sizei);
	hipMalloc((void **)&d_B, sizei);
	hipMalloc((void **)&d_Rnew, sizei);
	hipMalloc((void **)&d_Gnew, sizei);
	hipMalloc((void **)&d_Bnew, sizei);


	gettimeofday(&tim, NULL);
	double t2b=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5b Allocation of device memory took :%.6lf seconds elapsed\n", t2b-t1b);
	//printf("%.6lf,", t2b-t1b );


	//5c : timing Transferring data between host and device mem
	gettimeofday(&tim, NULL);
	double t3=tim.tv_sec+(tim.tv_usec/1000000.0);

	hipMemcpy(d_R, R, sizei, hipMemcpyHostToDevice);
	hipMemcpy(d_G, G, sizei, hipMemcpyHostToDevice);
	hipMemcpy(d_B, B, sizei, hipMemcpyHostToDevice);
	gettimeofday(&tim, NULL);
	double t4=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5c Transfer of data took :%.6lf seconds elapsed\n", t4-t3);
	//printf("%.6lf,", t4-t3 );


	//5d: time doing the blurring
	gettimeofday(&tim, NULL);
	double t5=tim.tv_sec+(tim.tv_usec/1000000.0);

	dim3 dimGrid(ceil(colsize/(float)TX), ceil(rowsize/(float)TY), 1);
	dim3 dimBlock(32, 32, 1);
	//run blurring
	for (k=0; k < nblurs; k++){
		blurKernel<<<dimGrid,dimBlock>>>(d_R, d_G, d_B, d_Rnew, d_Gnew, d_Bnew, rowsize, colsize);
		copyKernel<<<dimGrid,dimBlock>>>(d_R, d_G, d_B, d_Rnew, d_Gnew, d_Bnew, rowsize, colsize);
	}

	//return data back to host
	hipMemcpy(R, d_R, sizei, hipMemcpyDeviceToHost);
	hipMemcpy(G, d_G, sizei, hipMemcpyDeviceToHost);
	hipMemcpy(B, d_B, sizei, hipMemcpyDeviceToHost);

	hipFree(d_R); hipFree(d_G); hipFree(d_B);
	hipFree(d_Rnew); hipFree(d_Gnew); hipFree(d_Bnew);

	gettimeofday(&tim, NULL);
	double t6=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5d Blurring took :%.6lf seconds elapsed\n", t6-t5);
	//printf("%.6lf,", t6-t5 );
	


	//5e: time to output blurred image
	gettimeofday(&tim, NULL);
	double t7=tim.tv_sec+(tim.tv_usec/1000000.0);

	fout= fopen("DavidBlur.ps", "w");
	for (k=0;k<nlines;k++) fprintf(fout,"\n%s", lines[k]);
	fprintf(fout,"\n");
	for(row=0;row<rowsize;row++){
		for (col=0;col<colsize;col++){
			fprintf(fout,"%02x%02x%02x",R[row][col],G[row][col],B[row][col]);
			lineno++;
			if (lineno==linelen){
				fprintf(fout,"\n");
				lineno = 0;
			}
		}
	}
	fclose(fout);
    //return 0;


	gettimeofday(&tim, NULL);
	double t8=tim.tv_sec+(tim.tv_usec/1000000.0);
	printf("part 5e Outputting blurre image took :%.6lf seconds elapsed\n", t8-t7);
	//printf("%.6lf,\n", t8-t7 );
	return 0;
}
	.text
	.file	"blurCUDA.hip"
	.globl	_Z25__device_stub__blurKernelPiS_S_S_S_S_ii # -- Begin function _Z25__device_stub__blurKernelPiS_S_S_S_S_ii
	.type	_Z25__device_stub__blurKernelPiS_S_S_S_S_ii,@function
_Z25__device_stub__blurKernelPiS_S_S_S_S_ii: # @_Z25__device_stub__blurKernelPiS_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10blurKernelPiS_S_S_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__blurKernelPiS_S_S_S_S_ii, .Lfunc_end0-_Z25__device_stub__blurKernelPiS_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__copyKernelPiS_S_S_S_S_ii # -- Begin function _Z25__device_stub__copyKernelPiS_S_S_S_S_ii
	.type	_Z25__device_stub__copyKernelPiS_S_S_S_S_ii,@function
_Z25__device_stub__copyKernelPiS_S_S_S_S_ii: # @_Z25__device_stub__copyKernelPiS_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10copyKernelPiS_S_S_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__copyKernelPiS_S_S_S_S_ii, .Lfunc_end1-_Z25__device_stub__copyKernelPiS_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI2_0:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$2677192, %rsp                  # imm = 0x28D9C8
	.cfi_def_cfa_offset 2677248
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	leaq	96(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	cvtsi2sdq	(%rbx), %xmm0
	cvtsi2sdq	8(%rbx), %xmm1
	divsd	.LCPI2_0(%rip), %xmm1
	addsd	%xmm0, %xmm1
	movsd	%xmm1, 48(%rsp)                 # 8-byte Spill
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	movq	%rax, %r14
	movq	%rax, %rdi
	callq	feof
	testl	%eax, %eax
	jne	.LBB2_12
# %bb.1:                                # %.lr.ph114.preheader
	leaq	112(%rsp), %rbp
	leaq	84(%rsp), %r13
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
	xorl	%r15d, %r15d
	movq	%r14, 8(%rsp)                   # 8-byte Spill
.LBB2_2:                                # %.lr.ph114
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_7 Depth 2
	movl	$.L.str.2, %esi
	movq	%r14, %r12
	movq	%r14, %rdi
	movq	%rbp, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movq	16(%rsp), %rcx                  # 8-byte Reload
	cmpl	$5, %ecx
	jge	.LBB2_3
# %bb.5:                                #   in Loop: Header=BB2_2 Depth=1
	movslq	%ecx, %rax
	incl	%ecx
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	imulq	$200, %rax, %rax
	leaq	(%rsp,%rax), %rdi
	addq	$320, %rdi                      # imm = 0x140
	movq	%rbp, %rsi
	callq	strcpy
	jmp	.LBB2_4
.LBB2_3:                                # %.preheader104
                                        #   in Loop: Header=BB2_2 Depth=1
	cmpb	$0, 112(%rsp)
	je	.LBB2_4
# %bb.6:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB2_2 Depth=1
	leaq	112(%rsp), %rbp
	leaq	88(%rsp), %r12
.LBB2_7:                                # %.lr.ph
                                        #   Parent Loop BB2_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%ebx, %r14d
	movl	$.L.str.3, %esi
	movq	%rbp, %rdi
	leaq	92(%rsp), %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	leaq	2(%rbp), %rdi
	movl	$.L.str.3, %esi
	movq	%r12, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	addq	$4, %rbp
	movl	$.L.str.3, %esi
	movq	%rbp, %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	__isoc23_sscanf
	xorl	%ebx, %ebx
	cmpl	$428, %r15d                     # imm = 0x1AC
	sete	%bl
	movl	$0, %eax
	cmovel	%eax, %r15d
	addl	%r14d, %ebx
	cmpl	$520, %ebx                      # imm = 0x208
	jg	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_7 Depth=2
	movl	92(%rsp), %eax
	movslq	%ebx, %rcx
	movslq	%r15d, %rdx
	imulq	$1712, %rcx, %rcx               # imm = 0x6B0
	leaq	(%rsp,%rcx), %rsi
	addq	$1785232, %rsi                  # imm = 0x1B3D90
	movl	%eax, (%rsi,%rdx,4)
	movl	88(%rsp), %eax
	leaq	893280(%rsp,%rcx), %rsi
	movl	%eax, (%rsi,%rdx,4)
	movl	84(%rsp), %eax
	addq	%rsp, %rcx
	addq	$1328, %rcx                     # imm = 0x530
	movl	%eax, (%rcx,%rdx,4)
.LBB2_9:                                #   in Loop: Header=BB2_7 Depth=2
	incl	%r15d
	cmpb	$0, 2(%rbp)
	leaq	2(%rbp), %rbp
	jne	.LBB2_7
# %bb.10:                               #   in Loop: Header=BB2_2 Depth=1
	movq	8(%rsp), %r14                   # 8-byte Reload
	jmp	.LBB2_11
.LBB2_4:                                #   in Loop: Header=BB2_2 Depth=1
	movq	%r12, %r14
.LBB2_11:                               # %.loopexit
                                        #   in Loop: Header=BB2_2 Depth=1
	movq	%r14, %rdi
	callq	feof
	testl	%eax, %eax
	leaq	112(%rsp), %rbp
	je	.LBB2_2
.LBB2_12:                               # %._crit_edge
	movabsq	$137438953504, %rbx             # imm = 0x2000000020
	movabsq	$73014444046, %r13              # imm = 0x110000000E
	movq	%r14, %rdi
	callq	fclose
	leaq	96(%rsp), %r15
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm1, %xmm1
	cvtsi2sdq	(%r15), %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2sdq	8(%r15), %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	48(%rsp), %xmm0                 # 8-byte Folded Reload
	movl	$.L.str.4, %edi
	movb	$1, %al
	callq	printf
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm0, %xmm0
	cvtsi2sdq	(%r15), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2sdq	8(%r15), %xmm1
	divsd	.LCPI2_0(%rip), %xmm1
	addsd	%xmm0, %xmm1
	movsd	%xmm1, 8(%rsp)                  # 8-byte Spill
	leaq	40(%rsp), %rbp
	movl	$891952, %esi                   # imm = 0xD9C30
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r14
	movl	$891952, %esi                   # imm = 0xD9C30
	movq	%r14, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %r12
	movl	$891952, %esi                   # imm = 0xD9C30
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	72(%rsp), %rdi
	movl	$891952, %esi                   # imm = 0xD9C30
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movl	$891952, %esi                   # imm = 0xD9C30
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movl	$891952, %esi                   # imm = 0xD9C30
	callq	hipMalloc
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm1, %xmm1
	cvtsi2sdq	(%r15), %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2sdq	8(%r15), %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	8(%rsp), %xmm0                  # 8-byte Folded Reload
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm0, %xmm0
	cvtsi2sdq	(%r15), %xmm0
	xorps	%xmm1, %xmm1
	cvtsi2sdq	8(%r15), %xmm1
	divsd	.LCPI2_0(%rip), %xmm1
	addsd	%xmm0, %xmm1
	movsd	%xmm1, 8(%rsp)                  # 8-byte Spill
	movq	(%rbp), %rdi
	leaq	1785232(%rsp), %rsi
	movl	$891952, %edx                   # imm = 0xD9C30
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r14), %rdi
	leaq	893280(%rsp), %rsi
	movl	$891952, %edx                   # imm = 0xD9C30
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	1328(%rsp), %rsi
	movl	$891952, %edx                   # imm = 0xD9C30
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm1, %xmm1
	cvtsi2sdq	(%r15), %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2sdq	8(%r15), %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	8(%rsp), %xmm0                  # 8-byte Folded Reload
	movl	$.L.str.6, %edi
	movb	$1, %al
	callq	printf
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r15), %r12
	xorps	%xmm0, %xmm0
	cvtsi2sdq	8(%r15), %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	$160, %ebp
.LBB2_13:                               # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_15
# %bb.14:                               #   in Loop: Header=BB2_13 Depth=1
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	72(%rsp), %rcx
	movq	64(%rsp), %r8
	movq	56(%rsp), %r9
	pushq	$428                            # imm = 0x1AC
	.cfi_adjust_cfa_offset 8
	pushq	$521                            # imm = 0x209
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__blurKernelPiS_S_S_S_S_ii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB2_15:                               #   in Loop: Header=BB2_13 Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_17
# %bb.16:                               #   in Loop: Header=BB2_13 Depth=1
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	72(%rsp), %rcx
	movq	64(%rsp), %r8
	movq	56(%rsp), %r9
	pushq	$428                            # imm = 0x1AC
	.cfi_adjust_cfa_offset 8
	pushq	$521                            # imm = 0x209
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__copyKernelPiS_S_S_S_S_ii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB2_17:                               #   in Loop: Header=BB2_13 Depth=1
	decl	%ebp
	jne	.LBB2_13
# %bb.18:
	xorps	%xmm0, %xmm0
	cvtsi2sd	%r12, %xmm0
	movsd	8(%rsp), %xmm1                  # 8-byte Reload
                                        # xmm1 = mem[0],zero
	addsd	%xmm0, %xmm1
	movsd	%xmm1, 8(%rsp)                  # 8-byte Spill
	movq	40(%rsp), %rsi
	leaq	1785232(%rsp), %rbx
	movl	$891952, %edx                   # imm = 0xD9C30
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	leaq	893280(%rsp), %r14
	movl	$891952, %edx                   # imm = 0xD9C30
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	leaq	1328(%rsp), %r15
	movl	$891952, %edx                   # imm = 0xD9C30
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	leaq	96(%rsp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm1, %xmm1
	cvtsi2sdq	(%r12), %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2sdq	8(%r12), %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	8(%rsp), %xmm0                  # 8-byte Folded Reload
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%r12), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	8(%r12), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movl	$.L.str.8, %edi
	movl	$.L.str.9, %esi
	callq	fopen
	movq	%rax, %r12
	movq	16(%rsp), %rax                  # 8-byte Reload
	testl	%eax, %eax
	jle	.LBB2_21
# %bb.19:                               # %.lr.ph119.preheader
	movl	%eax, %ebp
	leaq	320(%rsp), %r13
.LBB2_20:                               # %.lr.ph119
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.10, %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	fprintf
	addq	$200, %r13
	decq	%rbp
	jne	.LBB2_20
.LBB2_21:                               # %._crit_edge120
	movl	$10, %edi
	movq	%r12, %rsi
	callq	fputc@PLT
	xorl	%ecx, %ecx
	xorl	%r13d, %r13d
.LBB2_22:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_23 Depth 2
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	xorl	%ebp, %ebp
.LBB2_23:                               #   Parent Loop BB2_22 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rbx,%rbp,4), %edx
	movl	(%r14,%rbp,4), %ecx
	movl	(%r15,%rbp,4), %r8d
	movl	$.L.str.12, %esi
	movq	%r12, %rdi
	xorl	%eax, %eax
	callq	fprintf
	incl	%r13d
	cmpl	$12, %r13d
	jne	.LBB2_25
# %bb.24:                               #   in Loop: Header=BB2_23 Depth=2
	movl	$10, %edi
	movq	%r12, %rsi
	callq	fputc@PLT
	xorl	%r13d, %r13d
.LBB2_25:                               #   in Loop: Header=BB2_23 Depth=2
	incq	%rbp
	cmpq	$428, %rbp                      # imm = 0x1AC
	jne	.LBB2_23
# %bb.26:                               #   in Loop: Header=BB2_22 Depth=1
	movq	16(%rsp), %rcx                  # 8-byte Reload
	incq	%rcx
	movl	$1712, %eax                     # imm = 0x6B0
	addq	%rax, %rbx
	addq	%rax, %r14
	addq	%rax, %r15
	cmpq	$521, %rcx                      # imm = 0x209
	jne	.LBB2_22
# %bb.27:
	xorps	%xmm0, %xmm0
	cvtsi2sdq	8(%rsp), %xmm0          # 8-byte Folded Reload
	cvtsi2sdq	48(%rsp), %xmm2         # 8-byte Folded Reload
	movsd	.LCPI2_0(%rip), %xmm1           # xmm1 = mem[0],zero
	divsd	%xmm1, %xmm2
	addsd	%xmm0, %xmm2
	movsd	%xmm2, 16(%rsp)                 # 8-byte Spill
	movq	%r12, %rdi
	callq	fclose
	leaq	96(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	xorps	%xmm1, %xmm1
	cvtsi2sdq	(%rbx), %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2sdq	8(%rbx), %xmm0
	divsd	.LCPI2_0(%rip), %xmm0
	addsd	%xmm1, %xmm0
	subsd	16(%rsp), %xmm0                 # 8-byte Folded Reload
	movl	$.L.str.13, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$2677192, %rsp                  # imm = 0x28D9C8
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10blurKernelPiS_S_S_S_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10copyKernelPiS_S_S_S_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10blurKernelPiS_S_S_S_S_ii,@object # @_Z10blurKernelPiS_S_S_S_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z10blurKernelPiS_S_S_S_S_ii
	.p2align	3, 0x0
_Z10blurKernelPiS_S_S_S_S_ii:
	.quad	_Z25__device_stub__blurKernelPiS_S_S_S_S_ii
	.size	_Z10blurKernelPiS_S_S_S_S_ii, 8

	.type	_Z10copyKernelPiS_S_S_S_S_ii,@object # @_Z10copyKernelPiS_S_S_S_S_ii
	.globl	_Z10copyKernelPiS_S_S_S_S_ii
	.p2align	3, 0x0
_Z10copyKernelPiS_S_S_S_S_ii:
	.quad	_Z25__device_stub__copyKernelPiS_S_S_S_S_ii
	.size	_Z10copyKernelPiS_S_S_S_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"David.ps"
	.size	.L.str, 9

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"r"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\n%[^\n]"
	.size	.L.str.2, 7

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%2x"
	.size	.L.str.3, 4

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"part 5a Reading Image File took :%.6lf seconds elapsed\n"
	.size	.L.str.4, 56

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"part 5b Allocation of device memory took :%.6lf seconds elapsed\n"
	.size	.L.str.5, 65

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"part 5c Transfer of data took :%.6lf seconds elapsed\n"
	.size	.L.str.6, 54

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"part 5d Blurring took :%.6lf seconds elapsed\n"
	.size	.L.str.7, 46

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"DavidBlur.ps"
	.size	.L.str.8, 13

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"w"
	.size	.L.str.9, 2

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"\n%s"
	.size	.L.str.10, 4

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"%02x%02x%02x"
	.size	.L.str.12, 13

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"part 5e Outputting blurre image took :%.6lf seconds elapsed\n"
	.size	.L.str.13, 61

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10blurKernelPiS_S_S_S_S_ii"
	.size	.L__unnamed_1, 29

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10copyKernelPiS_S_S_S_S_ii"
	.size	.L__unnamed_2, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__blurKernelPiS_S_S_S_S_ii
	.addrsig_sym _Z25__device_stub__copyKernelPiS_S_S_S_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10blurKernelPiS_S_S_S_S_ii
	.addrsig_sym _Z10copyKernelPiS_S_S_S_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10blurKernelPiS_S_S_S_S_ii ; -- Begin function _Z10blurKernelPiS_S_S_S_S_ii
	.globl	_Z10blurKernelPiS_S_S_S_S_ii
	.p2align	8
	.type	_Z10blurKernelPiS_S_S_S_S_ii,@function
_Z10blurKernelPiS_S_S_S_S_ii:           ; @_Z10blurKernelPiS_S_S_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b64 s[4:5], s[0:1], 0x30
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[7:8], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[5:6], null, s14, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v7
	v_cmp_gt_i32_e64 s2, s5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_41
; %bb.1:
	s_clause 0x1
	s_load_b256 s[8:15], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	v_mad_u64_u32 v[0:1], null, v7, s5, v[5:6]
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	v_cmp_eq_u32_e64 s0, 0, v7
	s_mov_b32 s6, 0
	s_mov_b32 s3, 0
                                        ; implicit-def: $sgpr1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s0
	s_xor_b32 s0, exec_lo, s2
; %bb.2:                                ; %._crit_edge
	s_mov_b32 s3, exec_lo
	s_add_i32 s1, s5, -1
; %bb.3:                                ; %Flow
	s_or_saveexec_b32 s7, s0
	v_subrev_nc_u32_e32 v2, s5, v0
	v_mov_b32_e32 v8, s1
                                        ; implicit-def: $sgpr0
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_xor_b32 exec_lo, exec_lo, s7
	s_cbranch_execz .LBB0_7
; %bb.4:
	s_add_i32 s1, s4, -1
	v_cmp_ne_u32_e64 s0, 0, v5
	v_cmp_ne_u32_e64 s1, s1, v7
	s_add_i32 s6, s5, -1
	s_mov_b32 s20, -1
	v_cmp_ne_u32_e64 s2, s6, v5
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_and_b32 s0, s1, s0
	s_mov_b32 s1, 0
	s_and_b32 s21, s0, s2
                                        ; implicit-def: $sgpr0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s21
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_ashr_i32 s21, s5, 31
	s_mov_b32 s20, s5
	s_mov_b32 s1, exec_lo
	v_lshlrev_b64 v[8:9], 2, v[0:1]
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	s_lshl_b64 s[20:21], s[20:21], 2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s8, v8
	v_add_co_ci_u32_e64 v11, s0, s9, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s0, v10, s20
	v_add_co_ci_u32_e64 v13, s0, s21, v11, s0
	v_add_co_u32 v14, s0, s8, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v15, s0, s9, v4, s0
	s_clause 0x3
	global_load_b32 v6, v[12:13], off
	global_load_b32 v12, v[14:15], off
	global_load_b32 v13, v[10:11], off offset:4
	global_load_b32 v10, v[10:11], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v10, v6, v12
	v_add_co_u32 v10, s0, s14, v8
	v_add_co_ci_u32_e64 v11, s0, s15, v9, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v12, 31, v6
	v_lshrrev_b32_e32 v14, 30, v12
	v_add_co_u32 v12, s0, s10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v13, s0, s11, v9, s0
	v_add_nc_u32_e32 v6, v6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s0, v12, s20
	v_add_co_ci_u32_e64 v15, s0, s21, v13, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 2, v6
	v_add_co_u32 v16, s0, s10, v3
	v_add_co_ci_u32_e64 v17, s0, s11, v4, s0
	global_store_b32 v[10:11], v6, off
	s_clause 0x3
	global_load_b32 v6, v[14:15], off
	global_load_b32 v10, v[16:17], off
	global_load_b32 v11, v[12:13], off offset:4
	global_load_b32 v12, v[12:13], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v11, v6, v10
	v_ashrrev_i32_e32 v10, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v12, 30, v10
	v_add_co_u32 v10, s0, s16, v8
	v_add_co_ci_u32_e64 v11, s0, s17, v9, s0
	v_add_co_u32 v8, s0, s12, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v6, v12
	v_add_co_ci_u32_e64 v9, s0, s13, v9, s0
	v_add_co_u32 v12, s0, v8, s20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 2, v6
	v_add_co_ci_u32_e64 v13, s0, s21, v9, s0
	v_add_co_u32 v3, s0, s12, v3
	global_store_b32 v[10:11], v6, off
	s_clause 0x2
	global_load_b32 v6, v[12:13], off
	global_load_b32 v10, v[8:9], off offset:4
	global_load_b32 v8, v[8:9], off offset:-4
	v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
	s_mov_b32 s0, 4
	s_xor_b32 s20, exec_lo, -1
	s_waitcnt vmcnt(0)
	v_add3_u32 v10, v8, v10, v6
.LBB0_6:                                ; %Flow318
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v8, s6
	s_and_not1_b32 s2, s3, exec_lo
	s_and_b32 s3, s20, exec_lo
	s_and_b32 s6, s1, exec_lo
	s_or_b32 s3, s2, s3
.LBB0_7:                                ; %Flow317
	s_or_b32 exec_lo, exec_lo, s7
	v_mov_b32_e32 v6, s0
	s_and_saveexec_b32 s7, s3
	s_cbranch_execz .LBB0_39
; %bb.8:
	v_cmp_eq_u32_e64 s1, 0, v7
	v_cmp_ne_u32_e64 s3, 0, v5
	v_cmp_eq_u32_e64 s0, v5, v8
	s_mov_b32 s20, s6
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s1, s3
	s_xor_b32 s2, s2, -1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s21, s2, -1
                                        ; implicit-def: $sgpr2
	s_and_saveexec_b32 s22, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s22
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_ashrrev_i32_e32 v1, 31, v0
	s_ashr_i32 s23, s5, 31
	s_mov_b32 s22, s5
	s_or_b32 s20, s6, exec_lo
	s_lshl_b64 s[22:23], s[22:23], 2
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s2, s8, v2
	v_add_co_ci_u32_e64 v5, s2, s9, v3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s2, v4, s22
	v_add_co_ci_u32_e64 v7, s2, s23, v5, s2
	s_clause 0x2
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[4:5], off offset:4
	global_load_b32 v4, v[4:5], off offset:-4
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v6, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v8, 0x55555556, v4
	v_add_co_u32 v4, s2, s14, v2
	v_add_co_ci_u32_e64 v5, s2, s15, v3, s2
	v_add_co_u32 v6, s2, s10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s2, s11, v3, s2
	v_lshrrev_b32_e32 v9, 31, v8
	v_add_nc_u32_e32 v10, v8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s2, v6, s22
	v_add_co_ci_u32_e64 v9, s2, s23, v7, s2
	global_store_b32 v[4:5], v10, off
	s_clause 0x2
	global_load_b32 v4, v[8:9], off
	global_load_b32 v5, v[6:7], off offset:4
	global_load_b32 v6, v[6:7], off offset:-4
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v4, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v8, 0x55555556, v4
	v_add_co_u32 v4, s2, s16, v2
	v_add_co_ci_u32_e64 v5, s2, s17, v3, s2
	v_add_co_u32 v6, s2, s12, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v7, s2, s13, v3, s2
	v_lshrrev_b32_e32 v9, 31, v8
	v_add_co_u32 v2, s2, v6, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, s2, s23, v7, s2
	v_add_nc_u32_e32 v8, v8, v9
	global_store_b32 v[4:5], v8, off
	s_clause 0x1
	global_load_b32 v4, v[6:7], off offset:4
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v3, s2, v6, -4
                                        ; implicit-def: $vgpr5_vgpr6
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, v2, v4
	v_add_co_ci_u32_e64 v4, s2, -1, v7, s2
	s_mov_b32 s2, 3
                                        ; implicit-def: $vgpr7_vgpr8
                                        ; implicit-def: $vgpr2
.LBB0_10:                               ; %Flow320
	s_or_saveexec_b32 s21, s21
	v_mov_b32_e32 v6, s2
	s_xor_b32 exec_lo, exec_lo, s21
	s_cbranch_execz .LBB0_38
; %bb.11:
	s_add_i32 s2, s4, -1
	s_mov_b32 s22, s20
	v_cmp_eq_u32_e64 s2, s2, v7
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, s2, s3
	s_xor_b32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, s0
	s_xor_b32 s4, s3, -1
                                        ; implicit-def: $sgpr3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s23, s4
	s_xor_b32 s4, exec_lo, s23
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_or_b32 s22, s20, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s8, v4
	v_add_co_ci_u32_e64 v3, s3, s9, v5, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s3, s8, v6
	v_add_co_ci_u32_e64 v9, s3, s9, v7, s3
	s_clause 0x2
	global_load_b32 v10, v[2:3], off offset:-4
	global_load_b32 v2, v[2:3], off offset:4
	global_load_b32 v3, v[8:9], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v2, v2, v10, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v10, 0x55555556, v2
	v_add_co_u32 v2, s3, s14, v4
	v_add_co_ci_u32_e64 v3, s3, s15, v5, s3
	v_add_co_u32 v8, s3, s10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s3, s11, v5, s3
	v_lshrrev_b32_e32 v11, 31, v10
	v_add_nc_u32_e32 v12, v10, v11
	v_add_co_u32 v10, s3, s10, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s3, s11, v7, s3
	global_store_b32 v[2:3], v12, off
	s_clause 0x2
	global_load_b32 v2, v[8:9], off offset:-4
	global_load_b32 v3, v[8:9], off offset:4
	global_load_b32 v8, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v2, v3, v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v8, 0x55555556, v2
	v_add_co_u32 v2, s3, s16, v4
	v_add_co_ci_u32_e64 v3, s3, s17, v5, s3
	v_add_co_u32 v4, s3, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s3, s13, v5, s3
	v_lshrrev_b32_e32 v9, 31, v8
	v_add_nc_u32_e32 v8, v8, v9
	global_store_b32 v[2:3], v8, off
	s_clause 0x1
	global_load_b32 v2, v[4:5], off offset:-4
	global_load_b32 v3, v[4:5], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, v3, v2
	v_add_co_u32 v3, s3, s12, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s3, s13, v7, s3
	s_mov_b32 s3, 3
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr7_vgpr8
.LBB0_13:                               ; %Flow322
	s_or_saveexec_b32 s23, s4
	v_mov_b32_e32 v6, s3
	s_xor_b32 exec_lo, exec_lo, s23
	s_cbranch_execz .LBB0_37
; %bb.14:
	v_cmp_eq_u32_e64 s3, 0, v5
                                        ; implicit-def: $sgpr25
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, vcc_lo, s3
	s_xor_b32 s4, s4, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s2, s4
	s_xor_b32 s24, s4, -1
	s_mov_b32 s4, s22
	s_and_saveexec_b32 s26, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s24, exec_lo, s26
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_ashr_i32 s27, s5, 31
	s_mov_b32 s26, s5
	s_mov_b32 s25, 3
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_lshl_b64 s[26:27], s[26:27], 2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v6, s4, s8, v4
	v_add_co_ci_u32_e64 v7, s4, s9, v5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s4, s8, v2
	v_add_co_ci_u32_e64 v9, s4, s9, v3, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s4, v6, s26
	v_add_co_ci_u32_e64 v11, s4, s27, v7, s4
	s_clause 0x2
	global_load_b32 v6, v[6:7], off offset:4
	global_load_b32 v7, v[8:9], off
	global_load_b32 v8, v[10:11], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v6, v7, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v12, 0x55555556, v6
	v_add_co_u32 v6, s4, s14, v4
	v_add_co_ci_u32_e64 v7, s4, s15, v5, s4
	v_add_co_u32 v8, s4, s10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s4, s11, v5, s4
	v_lshrrev_b32_e32 v13, 31, v12
	v_add_co_u32 v10, s4, s10, v2
	v_add_co_ci_u32_e64 v11, s4, s11, v3, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v12, v13
	v_add_co_u32 v12, s4, v8, s26
	v_add_co_ci_u32_e64 v13, s4, s27, v9, s4
	global_store_b32 v[6:7], v14, off
	s_clause 0x2
	global_load_b32 v6, v[8:9], off offset:4
	global_load_b32 v7, v[10:11], off
	global_load_b32 v8, v[12:13], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v6, v7, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_hi_i32 v8, 0x55555556, v6
	v_add_co_u32 v6, s4, s16, v4
	v_add_co_ci_u32_e64 v7, s4, s17, v5, s4
	v_add_co_u32 v4, s4, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s4, s13, v5, s4
	v_lshrrev_b32_e32 v9, 31, v8
	v_add_co_u32 v2, s4, s12, v2
	v_add_co_ci_u32_e64 v3, s4, s13, v3, s4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v8, v9
	global_store_b32 v[6:7], v8, off
	s_clause 0x1
	global_load_b32 v6, v[4:5], off offset:4
	global_load_b32 v2, v[2:3], off
	v_add_co_u32 v3, s4, v4, s26
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, s4, s27, v5, s4
	s_or_b32 s4, s22, exec_lo
                                        ; implicit-def: $vgpr7_vgpr8
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, v2, v6
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr5_vgpr6
.LBB0_16:                               ; %Flow324
	s_or_saveexec_b32 s24, s24
	v_mov_b32_e32 v6, s25
	s_xor_b32 exec_lo, exec_lo, s24
	s_cbranch_execz .LBB0_36
; %bb.17:
	s_and_b32 s25, vcc_lo, s0
	v_add_nc_u32_e32 v9, s5, v0
	s_xor_b32 s25, s25, -1
                                        ; implicit-def: $sgpr26
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s5, s2, s25
	s_xor_b32 s25, s5, -1
	s_mov_b32 s5, s4
	s_and_saveexec_b32 s27, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, s27
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_ashrrev_i32_e32 v10, 31, v9
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s26, 3
	s_or_b32 s5, s4, exec_lo
	v_lshlrev_b64 v[4:5], 2, v[9:10]
	v_lshlrev_b64 v[6:7], 2, v[0:1]
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v7, vcc_lo
	v_add_co_u32 v12, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v9, vcc_lo
	s_clause 0x2
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[10:11], off offset:-4
	global_load_b32 v10, v[12:13], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v2, v3, v2, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_hi_i32 v14, 0x55555556, v2
	v_add_co_u32 v2, vcc_lo, s14, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v7, vcc_lo
	v_add_co_u32 v10, vcc_lo, s10, v4
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v5, vcc_lo
	v_lshrrev_b32_e32 v15, 31, v14
	v_add_co_u32 v12, vcc_lo, s10, v6
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v16, v14, v15
	v_add_co_u32 v14, vcc_lo, s10, v8
	v_add_co_ci_u32_e32 v15, vcc_lo, s11, v9, vcc_lo
	global_store_b32 v[2:3], v16, off
	s_clause 0x2
	global_load_b32 v2, v[10:11], off
	global_load_b32 v3, v[12:13], off offset:-4
	global_load_b32 v10, v[14:15], off
	s_waitcnt vmcnt(0)
	v_add3_u32 v2, v3, v2, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_hi_i32 v10, 0x55555556, v2
	v_add_co_u32 v2, vcc_lo, s16, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v7, vcc_lo
	v_add_co_u32 v4, vcc_lo, s12, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
	v_lshrrev_b32_e32 v11, 31, v10
	v_add_co_u32 v6, vcc_lo, s12, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v10, v10, v11
	global_store_b32 v[2:3], v10, off
	s_clause 0x1
	global_load_b32 v2, v[4:5], off
	global_load_b32 v3, v[6:7], off offset:-4
                                        ; implicit-def: $vgpr5_vgpr6
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, v3, v2
	v_add_co_u32 v3, vcc_lo, s12, v8
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v9, vcc_lo
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr7_vgpr8
                                        ; implicit-def: $vgpr2
.LBB0_19:                               ; %Flow326
	s_or_saveexec_b32 s25, s25
	v_mov_b32_e32 v6, s26
	s_xor_b32 exec_lo, exec_lo, s25
	s_cbranch_execz .LBB0_35
; %bb.20:
	v_or_b32_e32 v1, v5, v7
	s_mov_b32 s27, s5
	s_mov_b32 s26, exec_lo
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s26, exec_lo, s26
	s_cbranch_execz .LBB0_32
; %bb.21:
	s_and_b32 s1, s1, s0
	s_mov_b32 s27, s5
	s_xor_b32 s1, s1, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s28, s1
	s_xor_b32 s1, exec_lo, s28
	s_cbranch_execz .LBB0_29
; %bb.22:
	s_and_b32 s3, s2, s3
                                        ; implicit-def: $sgpr28
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s27, s3, -1
	s_mov_b32 s3, s5
	s_and_saveexec_b32 s29, s27
	s_xor_b32 s27, exec_lo, s29
	s_cbranch_execz .LBB0_26
; %bb.23:
	s_and_b32 s0, s2, s0
	s_mov_b32 s2, s5
                                        ; implicit-def: $sgpr28
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr3_vgpr4
	s_and_saveexec_b32 s3, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s3
	s_cbranch_execz .LBB0_25
; %bb.24:
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_mov_b32 s28, 2
	s_or_b32 s2, s5, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[7:8], off
	global_load_b32 v7, v[9:10], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	v_add_co_u32 v7, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v9, 31, v2
	v_add_nc_u32_e32 v2, v2, v9
	v_add_co_u32 v9, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_u32 v11, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v6, vcc_lo
	global_store_b32 v[7:8], v2, off
	s_clause 0x1
	global_load_b32 v2, v[9:10], off
	global_load_b32 v7, v[11:12], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 31, v2
	v_add_nc_u32_e32 v2, v2, v7
	v_add_co_u32 v7, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s12, v3
	global_store_b32 v[7:8], v2, off
	global_load_b32 v10, v[5:6], off offset:-4
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
.LBB0_25:                               ; %Flow331
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s5, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr2
	s_or_b32 s3, s0, s2
.LBB0_26:                               ; %Flow330
	s_or_saveexec_b32 s0, s27
	v_mov_b32_e32 v6, s28
	s_xor_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_ashrrev_i32_e32 v3, 31, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_or_b32 s3, s3, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s8, v5
	s_waitcnt vmcnt(0)
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[7:8], off
	global_load_b32 v7, v[9:10], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	v_add_co_u32 v7, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v9, 31, v2
	v_add_nc_u32_e32 v2, v2, v9
	v_add_co_u32 v9, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_u32 v11, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v6, vcc_lo
	global_store_b32 v[7:8], v2, off
	s_clause 0x1
	global_load_b32 v2, v[9:10], off
	global_load_b32 v7, v[11:12], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 31, v2
	v_add_nc_u32_e32 v2, v2, v7
	v_add_co_u32 v7, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s12, v3
	global_store_b32 v[7:8], v2, off
	global_load_b32 v10, v[5:6], off offset:4
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	v_mov_b32_e32 v6, 2
.LBB0_28:                               ; %Flow332
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s5, exec_lo
	s_and_b32 s2, s3, exec_lo
                                        ; implicit-def: $vgpr9
	s_or_b32 s27, s0, s2
.LBB0_29:                               ; %Flow329
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_31
; %bb.30:
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	v_ashrrev_i32_e32 v1, 31, v0
	s_or_b32 s27, s27, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[9:10]
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[7:8], off
	global_load_b32 v7, v[9:10], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	v_add_co_u32 v7, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v9, 31, v2
	v_add_nc_u32_e32 v2, v2, v9
	v_add_co_u32 v9, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_u32 v11, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v6, vcc_lo
	global_store_b32 v[7:8], v2, off
	s_clause 0x1
	global_load_b32 v2, v[9:10], off
	global_load_b32 v7, v[11:12], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 31, v2
	v_add_nc_u32_e32 v2, v2, v7
	v_add_co_u32 v7, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s12, v3
	global_store_b32 v[7:8], v2, off
	global_load_b32 v10, v[5:6], off offset:-4
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	v_mov_b32_e32 v6, 2
.LBB0_31:                               ; %Flow333
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s5, exec_lo
	s_and_b32 s1, s27, exec_lo
                                        ; implicit-def: $vgpr9
	s_or_b32 s27, s0, s1
.LBB0_32:                               ; %Flow328
	s_and_not1_saveexec_b32 s0, s26
	s_cbranch_execz .LBB0_34
; %bb.33:
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v10, 31, v9
	v_ashrrev_i32_e32 v1, 31, v0
	s_or_b32 s27, s27, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[9:10]
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v6, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[7:8], off
	global_load_b32 v7, v[9:10], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	v_add_co_u32 v7, vcc_lo, s14, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v9, 31, v2
	v_add_nc_u32_e32 v2, v2, v9
	v_add_co_u32 v9, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_u32 v11, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v6, vcc_lo
	global_store_b32 v[7:8], v2, off
	s_clause 0x1
	global_load_b32 v2, v[9:10], off
	global_load_b32 v7, v[11:12], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v7, 31, v2
	v_add_nc_u32_e32 v2, v2, v7
	v_add_co_u32 v7, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, s17, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_ashrrev_i32_e32 v2, 1, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s13, v6, vcc_lo
	v_add_co_u32 v3, vcc_lo, s12, v3
	global_store_b32 v[7:8], v2, off
	global_load_b32 v10, v[5:6], off offset:4
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	v_mov_b32_e32 v6, 2
.LBB0_34:                               ; %Flow334
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s5, exec_lo
	s_and_b32 s1, s27, exec_lo
	s_or_b32 s5, s0, s1
.LBB0_35:                               ; %Flow327
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s4, exec_lo
	s_and_b32 s1, s5, exec_lo
	s_or_b32 s4, s0, s1
.LBB0_36:                               ; %Flow325
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s22, exec_lo
	s_and_b32 s1, s4, exec_lo
	s_or_b32 s22, s0, s1
.LBB0_37:                               ; %Flow323
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s20, exec_lo
	s_and_b32 s1, s22, exec_lo
	s_or_b32 s20, s0, s1
.LBB0_38:                               ; %Flow321
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s6, exec_lo
	s_and_b32 s1, s20, exec_lo
	s_or_b32 s6, s0, s1
.LBB0_39:                               ; %Flow319
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s6
	s_cbranch_execz .LBB0_41
; %bb.40:                               ; %.sink.split
	global_load_b32 v2, v[3:4], off
	v_cvt_f32_u32_e32 v3, v6
	v_sub_nc_u32_e32 v4, 0, v6
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt vmcnt(0)
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v2, v10, v2
	v_cvt_u32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v2
	v_mul_lo_u32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v5
	v_mul_hi_u32 v4, v3, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v5
	v_add_nc_u32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v2, v3
	v_mul_lo_u32 v4, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v2, v4
	v_add_nc_u32_e32 v4, 1, v3
	v_sub_nc_u32_e32 v7, v2, v6
	v_cmp_ge_u32_e32 vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v2, v7 :: v_dual_cndmask_b32 v3, v3, v4
	v_cmp_ge_u32_e32 vcc_lo, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v3
	v_cndmask_b32_e32 v2, v3, v4, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v5
	v_sub_nc_u32_e32 v2, v2, v5
	global_store_b32 v[0:1], v2, off
.LBB0_41:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10blurKernelPiS_S_S_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10blurKernelPiS_S_S_S_S_ii, .Lfunc_end0-_Z10blurKernelPiS_S_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 4184
; NumSgprs: 32
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10copyKernelPiS_S_S_S_S_ii ; -- Begin function _Z10copyKernelPiS_S_S_S_S_ii
	.globl	_Z10copyKernelPiS_S_S_S_S_ii
	.p2align	8
	.type	_Z10copyKernelPiS_S_S_S_S_ii,@function
_Z10copyKernelPiS_S_S_S_S_ii:           ; @_Z10copyKernelPiS_S_S_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x44
	s_load_b64 s[2:3], s[0:1], 0x30
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s3, v0
	v_cmp_gt_i32_e64 s2, s2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	global_load_b32 v6, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v6, off
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10copyKernelPiS_S_S_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10copyKernelPiS_S_S_S_S_ii, .Lfunc_end1-_Z10copyKernelPiS_S_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 296
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10blurKernelPiS_S_S_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z10blurKernelPiS_S_S_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10copyKernelPiS_S_S_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10copyKernelPiS_S_S_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
