#include "includes.h"
__global__ void simKernel(int N_stgy, int N_batch, double *alpha, double *mid, double *gap, int *late, int *pos, int *rest_lag, double *prof, double *last_prc, int *cnt, double fee){
int global_i = blockIdx.x*blockDim.x + threadIdx.x;
if( global_i >= N_stgy) return;
int start = global_i*N_batch + rest_lag[global_i], end = global_i*N_batch + N_batch, i;
for(i = start; i<end; ++i) if(alpha[i]*mid[i%N_batch]>gap[i%N_batch] + fee || alpha[i]*mid[i%N_batch]<-gap[i%N_batch] - fee){
if(alpha[i]*mid[i%N_batch]>gap[i%N_batch]+fee && pos[global_i]<1){
last_prc[global_i] = mid[i%N_batch] + gap[i%N_batch] + fee;
prof[global_i] -= (1-pos[global_i])*last_prc[global_i];
cnt[global_i] += 1-pos[global_i];
pos[global_i] = 1;
i += late[i%N_batch];
}
else if(alpha[i]*mid[i%N_batch]<-gap[i%N_batch]-fee && pos[global_i]>-1){
last_prc[global_i] = mid[i%N_batch] - gap[i%N_batch] - fee;
prof[global_i] += (pos[global_i]+1)*last_prc[global_i];
cnt[global_i] += pos[global_i]+1;
pos[global_i] = -1;
i += late[i%N_batch];
}
}
rest_lag[global_i] = i-end;
}
	.file	"tmpxft_002cae23_00000000-6_simKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z50__device_stub__Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_diiPdS_S_PiS0_S0_S_S_S0_d
	.type	_Z50__device_stub__Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_diiPdS_S_PiS0_S0_S_S_S0_d, @function
_Z50__device_stub__Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_diiPdS_S_PiS0_S0_S_S_S0_d:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	288(%rsp), %rax
	movl	%edi, 92(%rsp)
	leaq	120(%rsp), %rdi
	movl	%esi, 88(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rax, 48(%rsp)
	movq	296(%rsp), %rax
	movq	%rdx, 80(%rsp)
	leaq	104(%rsp), %rdx
	movq	%rax, 40(%rsp)
	movq	304(%rsp), %rax
	movq	%rcx, 72(%rsp)
	leaq	112(%rsp), %rcx
	movq	%rax, 32(%rsp)
	movq	312(%rsp), %rax
	movq	%r8, 64(%rsp)
	movq	%rax, 24(%rsp)
	movq	320(%rsp), %rax
	movq	%r9, 56(%rsp)
	movq	%rax, 16(%rsp)
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	92(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movl	$1, 128(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L2:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z50__device_stub__Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_diiPdS_S_PiS0_S0_S_S_S0_d, .-_Z50__device_stub__Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_diiPdS_S_PiS0_S0_S_S_S0_d
	.globl	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.type	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d, @function
_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_diiPdS_S_PiS0_S0_S_S_S0_d
	.cfi_endproc
.LFE2033:
	.size	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d, .-_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void simKernel(int N_stgy, int N_batch, double *alpha, double *mid, double *gap, int *late, int *pos, int *rest_lag, double *prof, double *last_prc, int *cnt, double fee){
int global_i = blockIdx.x*blockDim.x + threadIdx.x;
if( global_i >= N_stgy) return;
int start = global_i*N_batch + rest_lag[global_i], end = global_i*N_batch + N_batch, i;
for(i = start; i<end; ++i) if(alpha[i]*mid[i%N_batch]>gap[i%N_batch] + fee || alpha[i]*mid[i%N_batch]<-gap[i%N_batch] - fee){
if(alpha[i]*mid[i%N_batch]>gap[i%N_batch]+fee && pos[global_i]<1){
last_prc[global_i] = mid[i%N_batch] + gap[i%N_batch] + fee;
prof[global_i] -= (1-pos[global_i])*last_prc[global_i];
cnt[global_i] += 1-pos[global_i];
pos[global_i] = 1;
i += late[i%N_batch];
}
else if(alpha[i]*mid[i%N_batch]<-gap[i%N_batch]-fee && pos[global_i]>-1){
last_prc[global_i] = mid[i%N_batch] - gap[i%N_batch] - fee;
prof[global_i] += (pos[global_i]+1)*last_prc[global_i];
cnt[global_i] += pos[global_i]+1;
pos[global_i] = -1;
i += late[i%N_batch];
}
}
rest_lag[global_i] = i-end;
}
	.text
	.file	"simKernel.hip"
	.globl	_Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d # -- Begin function _Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.type	_Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d,@function
_Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d: # @_Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	movq	%rsp, %rdi
	movl	%esi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	24(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	movq	%r9, 88(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d, .Lfunc_end0-_Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d,@object # @_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.section	.rodata,"a",@progbits
	.globl	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.p2align	3, 0x0
_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d:
	.quad	_Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.size	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d"
	.size	.L__unnamed_1, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d ; -- Begin function _Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.globl	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
	.p2align	8
	.type	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d,@function
_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d:   ; @_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x64
	s_load_b64 s[2:3], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s2, v3
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_20
; %bb.1:
	s_load_b512 s[4:19], s[0:1], 0x8
	v_ashrrev_i32_e32 v4, 31, v3
	v_mul_lo_u32 v2, v3, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_add_nc_u32_e32 v18, s3, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s14, v10
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v11, vcc_lo
	s_mov_b32 s14, exec_lo
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v5, v2
	v_cmpx_gt_i32_e64 s3, v5
	s_cbranch_execz .LBB0_19
; %bb.2:                                ; %.lr.ph
	s_ashr_i32 s2, s3, 31
	v_lshlrev_b64 v[8:9], 3, v[3:4]
	s_add_i32 s3, s3, s2
	v_add_co_u32 v4, vcc_lo, s12, v10
	s_xor_b32 s15, s3, s2
	s_load_b128 s[0:3], s[0:1], 0x48
	v_cvt_f32_u32_e32 v5, s15
	s_sub_i32 s20, 0, s15
                                        ; implicit-def: $vgpr20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v12, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v11, vcc_lo
	v_add_co_u32 v6, vcc_lo, s18, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v3, s20, v12
	v_add_co_ci_u32_e32 v7, vcc_lo, s19, v9, vcc_lo
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_mul_hi_u32 v3, v12, v3
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	s_mov_b32 s1, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v12, v3
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v2, v3
	v_lshlrev_b64 v[14:15], 3, v[2:3]
	v_xor_b32_e32 v12, v12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v13, v12, v19
	v_mul_lo_u32 v13, v13, s15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, v12, v13
	v_subrev_nc_u32_e32 v13, s15, v12
	v_cmp_le_u32_e32 vcc_lo, s15, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v12, v12, v13, vcc_lo
	v_subrev_nc_u32_e32 v13, s15, v12
	v_cmp_le_u32_e32 vcc_lo, s15, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v12, v13, vcc_lo
	v_add_co_u32 v14, vcc_lo, s4, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
	v_xor_b32_e32 v12, v12, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v12, v12, v3
	v_ashrrev_i32_e32 v13, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[16:17], 3, v[12:13]
	v_add_co_u32 v21, vcc_lo, s6, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v22, vcc_lo, s7, v17, vcc_lo
	v_add_co_u32 v16, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
	global_load_b64 v[23:24], v[14:15], off
	global_load_b64 v[14:15], v[21:22], off
	global_load_b64 v[16:17], v[16:17], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[21:22], v[23:24], v[14:15]
	s_waitcnt vmcnt(0)
	v_add_f64 v[23:24], v[16:17], s[2:3]
	v_add_f64 v[25:26], -v[16:17], -s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e64 s0, v[21:22], v[23:24]
	v_cmp_lt_f64_e32 vcc_lo, v[21:22], v[25:26]
	v_cmp_ngt_f64_e64 s18, v[21:22], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s13, s0, vcc_lo
	s_and_saveexec_b32 s12, s13
	s_cbranch_execz .LBB0_17
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s16, 0
	s_mov_b32 s13, 0
	s_and_saveexec_b32 s17, s0
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v20, v[4:5], off
	s_and_not1_b32 s18, s18, exec_lo
	s_mov_b32 s13, exec_lo
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e64 s0, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s18, s18, s0
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s0, s18
	s_cbranch_execz .LBB0_12
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=1
	s_mov_b32 s18, 0
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s16, vcc_lo
	s_cbranch_execz .LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=1
	global_load_b32 v21, v[4:5], off
	s_mov_b32 s19, exec_lo
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $vgpr3
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 -1, v21
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=1
	v_add_f64 v[22:23], v[14:15], -v[16:17]
	v_add_nc_u32_e32 v28, 1, v21
	s_mov_b32 s18, exec_lo
	s_mov_b32 s17, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[26:27], v28
	v_add_f64 v[22:23], v[22:23], -s[2:3]
	global_store_b64 v[6:7], v[22:23], off
	global_load_b64 v[24:25], v[8:9], off
	global_load_b32 v3, v[10:11], off
	s_waitcnt vmcnt(1)
	v_fma_f64 v[21:22], v[22:23], v[26:27], v[24:25]
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, v3, v28
	global_store_b64 v[8:9], v[21:22], off
.LBB0_10:                               ; %Flow162
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s18, s18, exec_lo
.LBB0_11:                               ; %Flow161
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s16, s18, exec_lo
	s_and_not1_b32 s13, s13, exec_lo
.LBB0_12:                               ; %Flow160
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v21, s17
	s_and_saveexec_b32 s0, s13
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_3 Depth=1
	v_add_f64 v[14:15], v[14:15], v[16:17]
	v_sub_nc_u32_e32 v21, 1, v20
	s_or_b32 s16, s16, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[21:22], v21
	v_add_f64 v[14:15], v[14:15], s[2:3]
	global_store_b64 v[6:7], v[14:15], off
	global_load_b64 v[16:17], v[8:9], off
	global_load_b32 v3, v[10:11], off
	s_waitcnt vmcnt(1)
	v_fma_f64 v[14:15], -v[14:15], v[21:22], v[16:17]
	s_waitcnt vmcnt(0)
	v_sub_nc_u32_e32 v3, v3, v20
	v_mov_b32_e32 v21, 1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v3, 1, v3
	global_store_b64 v[8:9], v[14:15], off
.LBB0_14:                               ; %Flow163
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_and_saveexec_b32 s0, s16
	s_cbranch_execz .LBB0_16
; %bb.15:                               ; %.sink.split
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	global_store_b32 v[10:11], v3, off
	global_store_b32 v[4:5], v21, off
	v_add_co_u32 v12, vcc_lo, s10, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v13, vcc_lo
	global_load_b32 v3, v[12:13], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
.LBB0_16:                               ; %Flow164
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_17:                               ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v2, v18
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_3
; %bb.18:                               ; %Flow165
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_19:                               ; %Flow166
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s14
	v_sub_nc_u32_e32 v2, v2, v18
	global_store_b32 v[0:1], v2, off
.LBB0_20:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 29
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d, .Lfunc_end0-_Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1012
; NumSgprs: 23
; NumVgprs: 29
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 29
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z9simKerneliiPdS_S_PiS0_S0_S_S_S0_d.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     29
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
