#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>

#define THREADS 64
#define WARP_SIZE 32
#define WARPS ((THREADS+WARP_SIZE-1)/WARP_SIZE)
#define IP 4
#define OP 4
#define INBUFFERS 4
#define OUTBUFFERS (((WARP_SIZE/IP)*INBUFFERS+(WARP_SIZE/OP)-1)/(WARP_SIZE/OP))

__global__ void BSMAD(int *buffer, int *synapse, int *output) {
	volatile int tid = threadIdx.x;
	volatile int result = 0;
	asm("/*");
	asm("CPTX_BEGIN");
	asm("bsmad.s32 %0, %1, %2, %3, %4, %5, %6, %7, %8;" : "=r"(result) : "r"(IP), "r"(OP), "r"(buffer[tid*INBUFFERS]), "r"(buffer[tid*INBUFFERS+1]), "r"(buffer[tid*INBUFFERS+2]), "r"(buffer[tid*INBUFFERS+3]), "r"(synapse[tid]), "r"(output[(tid%WARP_SIZE)%OUTBUFFERS + OUTBUFFERS*(tid/WARP_SIZE)]));
	asm("CPTX_END");
	asm("*/");
	if (tid%WARP_SIZE < OUTBUFFERS) output[tid%WARP_SIZE + OUTBUFFERS*(tid/WARP_SIZE)] = result;
}

int main(int argc, char** argv) {
	int *h_buffer = (int*)malloc(INBUFFERS*THREADS*sizeof(int));
	int *h_synapse = (int*)malloc(THREADS*sizeof(int));
	int *h_output = (int*)calloc(WARPS*OUTBUFFERS,sizeof(int));

	for (int i = 0; i < INBUFFERS*THREADS; i++) { h_buffer[i] = 0xFDB97531; }
	for (int i = 0; i < THREADS; i++) { h_synapse[i] = 1 + 2*(i/WARP_SIZE); }
	for (int i = 0; i < WARPS*OUTBUFFERS; i++) { h_output[i] = 0x87654321; }

	int *d_buffer, *d_synapse, *d_output;
	cudaMalloc(&d_buffer, INBUFFERS*THREADS*sizeof(int));
	cudaMalloc(&d_synapse, THREADS*sizeof(int));
	cudaMalloc(&d_output, WARPS*OUTBUFFERS*sizeof(int));
	cudaMemcpy(d_buffer, h_buffer, INBUFFERS*THREADS*sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_synapse, h_synapse, THREADS*sizeof(int), cudaMemcpyHostToDevice);
	cudaMemcpy(d_output, h_output, WARPS*OUTBUFFERS*sizeof(int), cudaMemcpyHostToDevice);
	
	BSMAD<<<1, THREADS>>>(d_buffer, d_synapse, d_output);
	
	cudaMemcpy(h_output, d_output, WARPS*OUTBUFFERS*sizeof(int), cudaMemcpyDeviceToHost);

	for (int i = 0; i < WARPS*OUTBUFFERS; i++) {
		if (i % OUTBUFFERS == 0) printf("\nWarp %d:\n", i/OUTBUFFERS);
		printf("%d: %08x\n", i, h_output[i]);
	}

	cudaFree(d_buffer); cudaFree(d_synapse); cudaFree(d_output);
	free(h_buffer); free(h_synapse); free(h_output);

	return 0;
}

	.file	"tmpxft_0027558f_00000000-6_bsmad_simple.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z5BSMADPiS_S_PiS_S_
	.type	_Z28__device_stub__Z5BSMADPiS_S_PiS_S_, @function
_Z28__device_stub__Z5BSMADPiS_S_PiS_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z5BSMADPiS_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z28__device_stub__Z5BSMADPiS_S_PiS_S_, .-_Z28__device_stub__Z5BSMADPiS_S_PiS_S_
	.globl	_Z5BSMADPiS_S_
	.type	_Z5BSMADPiS_S_, @function
_Z5BSMADPiS_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z5BSMADPiS_S_PiS_S_
	.cfi_endproc
.LFE2053:
	.size	_Z5BSMADPiS_S_, .-_Z5BSMADPiS_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\nWarp %d:\n"
.LC1:
	.string	"%d: %08x\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1024, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$256, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movl	$4, %esi
	movl	$8, %edi
	movq	%rax, %r12
	call	calloc@PLT
	movq	%rax, %rbx
	xorl	%eax, %eax
.L9:
	movl	$-38177487, 0(%r13,%rax,4)
	incq	%rax
	cmpq	$256, %rax
	jne	.L9
	xorl	%eax, %eax
.L10:
	movl	%eax, %edx
	sarl	$5, %edx
	leal	1(%rdx,%rdx), %edx
	movl	%edx, (%r12,%rax,4)
	incq	%rax
	cmpq	$64, %rax
	jne	.L10
	xorl	%eax, %eax
.L11:
	movl	$-2023406815, (%rbx,%rax,4)
	incq	%rax
	cmpq	$8, %rax
	jne	.L11
	leaq	8(%rsp), %rdi
	movl	$1024, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$32, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$1024, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$32, %edx
	call	cudaMemcpy@PLT
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z28__device_stub__Z5BSMADPiS_S_PiS_S_
.L12:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%ebp, %ebp
	movl	$32, %edx
	leaq	.LC0(%rip), %r14
	call	cudaMemcpy@PLT
.L14:
	movl	%ebp, %r15d
	testl	$3, %ebp
	jne	.L13
	movl	%ebp, %edx
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	sarl	$2, %edx
	call	__printf_chk@PLT
.L13:
	movl	(%rbx,%rbp,4), %ecx
	movl	%r15d, %edx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$8, %rbp
	jne	.L14
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z5BSMADPiS_S_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5BSMADPiS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>

#define THREADS 64
#define WARP_SIZE 32
#define WARPS ((THREADS+WARP_SIZE-1)/WARP_SIZE)
#define IP 4
#define OP 4
#define INBUFFERS 4
#define OUTBUFFERS (((WARP_SIZE/IP)*INBUFFERS+(WARP_SIZE/OP)-1)/(WARP_SIZE/OP))

__global__ void BSMAD(int *buffer, int *synapse, int *output) {
	volatile int tid = threadIdx.x;
	volatile int result = 0;
	asm("/*");
	asm("CPTX_BEGIN");
	asm("bsmad.s32 %0, %1, %2, %3, %4, %5, %6, %7, %8;" : "=r"(result) : "r"(IP), "r"(OP), "r"(buffer[tid*INBUFFERS]), "r"(buffer[tid*INBUFFERS+1]), "r"(buffer[tid*INBUFFERS+2]), "r"(buffer[tid*INBUFFERS+3]), "r"(synapse[tid]), "r"(output[(tid%WARP_SIZE)%OUTBUFFERS + OUTBUFFERS*(tid/WARP_SIZE)]));
	asm("CPTX_END");
	asm("*/");
	if (tid%WARP_SIZE < OUTBUFFERS) output[tid%WARP_SIZE + OUTBUFFERS*(tid/WARP_SIZE)] = result;
}

int main(int argc, char** argv) {
	int *h_buffer = (int*)malloc(INBUFFERS*THREADS*sizeof(int));
	int *h_synapse = (int*)malloc(THREADS*sizeof(int));
	int *h_output = (int*)calloc(WARPS*OUTBUFFERS,sizeof(int));

	for (int i = 0; i < INBUFFERS*THREADS; i++) { h_buffer[i] = 0xFDB97531; }
	for (int i = 0; i < THREADS; i++) { h_synapse[i] = 1 + 2*(i/WARP_SIZE); }
	for (int i = 0; i < WARPS*OUTBUFFERS; i++) { h_output[i] = 0x87654321; }

	int *d_buffer, *d_synapse, *d_output;
	hipMalloc(&d_buffer, INBUFFERS*THREADS*sizeof(int));
	hipMalloc(&d_synapse, THREADS*sizeof(int));
	hipMalloc(&d_output, WARPS*OUTBUFFERS*sizeof(int));
	hipMemcpy(d_buffer, h_buffer, INBUFFERS*THREADS*sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_synapse, h_synapse, THREADS*sizeof(int), hipMemcpyHostToDevice);
	hipMemcpy(d_output, h_output, WARPS*OUTBUFFERS*sizeof(int), hipMemcpyHostToDevice);
	
	BSMAD<<<1, THREADS>>>(d_buffer, d_synapse, d_output);
	
	hipMemcpy(h_output, d_output, WARPS*OUTBUFFERS*sizeof(int), hipMemcpyDeviceToHost);

	for (int i = 0; i < WARPS*OUTBUFFERS; i++) {
		if (i % OUTBUFFERS == 0) printf("\nWarp %d:\n", i/OUTBUFFERS);
		printf("%d: %08x\n", i, h_output[i]);
	}

	hipFree(d_buffer); hipFree(d_synapse); hipFree(d_output);
	free(h_buffer); free(h_synapse); free(h_output);

	return 0;
}

	.text
	.file	"bsmad_simple.hip"
	.globl	_Z20__device_stub__BSMADPiS_S_  # -- Begin function _Z20__device_stub__BSMADPiS_S_
	.type	_Z20__device_stub__BSMADPiS_S_,@function
_Z20__device_stub__BSMADPiS_S_:         # @_Z20__device_stub__BSMADPiS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5BSMADPiS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__BSMADPiS_S_, .Lfunc_end0-_Z20__device_stub__BSMADPiS_S_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1024, %edi                     # imm = 0x400
	callq	malloc
	movq	%rax, %rbx
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, %r14
	movl	$8, %edi
	movl	$4, %esi
	callq	calloc
	movq	%rax, %r15
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$-38177487, (%rbx,%rax,4)       # imm = 0xFDB97531
	incq	%rax
	cmpq	$256, %rax                      # imm = 0x100
	jne	.LBB1_1
# %bb.2:                                # %.preheader34.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader34
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %ecx
	shrl	$4, %ecx
	orl	$1, %ecx
	movl	%ecx, (%r14,%rax,4)
	incq	%rax
	cmpq	$64, %rax
	jne	.LBB1_3
# %bb.4:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_5:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	$-2023406815, (%r15,%rax,4)     # imm = 0x87654321
	incq	%rax
	cmpq	$8, %rax
	jne	.LBB1_5
# %bb.6:
	leaq	16(%rsp), %r12
	movl	$1024, %esi                     # imm = 0x400
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r13
	movl	$256, %esi                      # imm = 0x100
	movq	%r13, %rdi
	callq	hipMalloc
	movq	%rsp, %rbp
	movl	$32, %esi
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$1024, %edx                     # imm = 0x400
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r13), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$32, %edx
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	63(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	callq	_Z20__device_stub__BSMADPiS_S_
.LBB1_8:
	movq	(%rsp), %rsi
	movl	$32, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
.LBB1_9:                                # =>This Inner Loop Header: Depth=1
	testb	$3, %r12b
	jne	.LBB1_11
# %bb.10:                               #   in Loop: Header=BB1_9 Depth=1
	movl	%r12d, %esi
	shrl	$2, %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
.LBB1_11:                               #   in Loop: Header=BB1_9 Depth=1
	movl	(%r15,%r12,4), %edx
	movl	$.L.str.1, %edi
	movl	%r12d, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%r12
	cmpq	$8, %r12
	jne	.LBB1_9
# %bb.12:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5BSMADPiS_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5BSMADPiS_S_,@object          # @_Z5BSMADPiS_S_
	.section	.rodata,"a",@progbits
	.globl	_Z5BSMADPiS_S_
	.p2align	3, 0x0
_Z5BSMADPiS_S_:
	.quad	_Z20__device_stub__BSMADPiS_S_
	.size	_Z5BSMADPiS_S_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\nWarp %d:\n"
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d: %08x\n"
	.size	.L.str.1, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5BSMADPiS_S_"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__BSMADPiS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5BSMADPiS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5BSMADPiS_S_          ; -- Begin function _Z5BSMADPiS_S_
	.globl	_Z5BSMADPiS_S_
	.p2align	8
	.type	_Z5BSMADPiS_S_,@function
_Z5BSMADPiS_S_:                         ; @_Z5BSMADPiS_S_
; %bb.0:
	s_mov_b64 s[2:3], src_private_base
	s_mov_b32 s2, 4
	s_mov_b32 s8, 8
	s_mov_b32 s9, s3
	v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
	v_mov_b32_e32 v3, s8
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
	flat_store_b32 v[1:2], v0 dlc
	s_waitcnt_vscnt null, 0x0
	flat_store_b32 v[3:4], v5 dlc
	s_waitcnt_vscnt null, 0x0
	;;#ASMSTART
	/*
	;;#ASMEND
	;;#ASMSTART
	CPTX_BEGIN
	;;#ASMEND
	flat_load_b32 v0, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v5, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v0, v[5:6], off
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_lshlrev_b32_e32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v7, v[5:6], off offset:4
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_lshlrev_b32_e32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v8, v[5:6], off offset:8
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_lshlrev_b32_e32 v5, 2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	global_load_b32 v9, v[5:6], off offset:12
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	s_mov_b32 s4, 4
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v10, v[5:6], off
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(1)
	v_ashrrev_i32_e32 v11, 31, v5
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v12, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v11, 27, v11
	v_lshrrev_b32_e32 v12, 27, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, v5, v11
	v_add_nc_u32_e32 v6, v6, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v11, 0xffe0, v11
	v_ashrrev_i32_e32 v6, 5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v5, v11
	v_bfe_i32 v11, v5, 0, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b16 v11, 13, v11
	v_and_b32_e32 v11, 3, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u16 v11, v5, v11
	v_and_b32_e32 v11, 0xfc, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u16 v5, v5, v11
	v_bfe_i32 v5, v5, 0, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v5, v6, 2, v5
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s0, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	;;#ASMSTART
	bsmad.s32 s4, s4, s4, v0, v7, v8, v9, v10, v5;
	;;#ASMEND
	v_mov_b32_e32 v0, s4
	s_mov_b32 s4, exec_lo
	flat_store_b32 v[3:4], v0 dlc
	s_waitcnt_vscnt null, 0x0
	;;#ASMSTART
	CPTX_END
	;;#ASMEND
	;;#ASMSTART
	*/
	;;#ASMEND
	flat_load_b32 v0, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 27, v1
	v_add_nc_u32_e32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, 0xffffffe0, v1
	v_sub_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 4, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	flat_load_b32 v4, v[0:1] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v0, v[2:3] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v1, v[2:3] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(1)
	v_ashrrev_i32_e32 v2, 31, v0
	s_waitcnt lgkmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v2, 27, v2
	v_lshrrev_b32_e32 v3, 27, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v0, v2
	v_add_nc_u32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, 0xffffffe0, v2
	v_ashrrev_i32_e32 v1, 5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v2
	v_lshl_add_u32 v0, v1, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v4, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5BSMADPiS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 12
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 10
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5BSMADPiS_S_, .Lfunc_end0-_Z5BSMADPiS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 920
; NumSgprs: 12
; NumVgprs: 13
; ScratchSize: 12
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5BSMADPiS_S_
    .private_segment_fixed_size: 12
    .sgpr_count:     12
    .sgpr_spill_count: 0
    .symbol:         _Z5BSMADPiS_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
