/***************************************************************************//**
 * \file LHS2.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the left hand side for the poission solve
 */

#include "LHS2.h"

namespace kernels
{
__global__
void LHS2_mid_iter(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt,
					int *count, double *ns_rhs, double *interp_rhs, int *hybridTagsP, int *ghostTagsP,
					double *alpha, double *dpdn,
					int *index1, int *index2, int *index3, int *index4,
					double *q1coef, double *q2coef, double *q3coef, double *q4coef,
					double *q1, double *q2, double *q3, double *q4, int timeStep)
{
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x;
	if (ip >= nx*ny)
		return;
	int	I	= ip % nx,
		J	= ip / nx;

	if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
		return;

	int numE = nx*4-2 + (J-1)*(nx*5-2) + I*5-1;
	double temp = 0;


	if (hybridTagsP[ip]>0)//if were at hybrid node
	{
		int interp_index[4] = {index1[ip], index2[ip], index3[ip], index4[ip]};
		//int nx_index[5] = {ip+nx, ip+1, ip-nx, ip-1, ip};//n e s w p
		double CInterp[4];
		double Cns[5];
		double q[4] = {q1[ip], q2[ip], q3[ip], q4[ip]};

		//calculate the pressure coefficients for the stencil pressure calculation
		Cns[0] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5); //N
		Cns[1] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5); //E
		Cns[2] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5); //s
		Cns[3] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5); //w
		Cns[4] = -Cns[0] - Cns[1] - Cns[2] - Cns[3]; //P

		//set pressure coefficients for the interpolation pressure calculation
		CInterp[0] = q1coef[ip];
		CInterp[1] = q2coef[ip];
		CInterp[2] = q3coef[ip];
		CInterp[3] = q4coef[ip];

		//multiply by alpha
		for (int i=0;i<4;i++)
		{
			Cns[i] = (1-alpha[ip])*Cns[i]/Cns[4];
			CInterp[i] = alpha[ip]*CInterp[i];
		}

		/*   0  1  2		NW  N   NE
		 *   3  4  5		W   P   E
		 *   6  7  8		SW  S   SE
		 */
		int stencil_index[9]    = {ip + nx - 1, ip + nx, ip + nx + 1,
								   ip - 1     , ip     , ip + 1,
								   ip - nx - 1, ip - nx, ip - nx + 1};
		double stencil[9] = {0, Cns[0], 0, Cns[3], 1, Cns[1], 0, Cns[2], 0};
		//combine ns and interp stencils
		bool stencil_used[9] = {false, true, false, true, true, true, false, true, false};
		for (int n=0;n<4;n++)
		{
			for (int m=0;m<9;m++)
			{
				if (stencil_index[m] == interp_index[n] && m != 4)
				{
					stencil[m] -= CInterp[n]; //this should be minus
				}
			}
		}
		//add ns to sparse matrix
		for (int m = 0; m<9; m++)
		{
			if (stencil_used[m])
			{
				row[numE] = ip;
				col[numE] = stencil_index[m];
				val[numE] = stencil[m];
				numE++;
			}
		}
		ns_rhs[ip] = (1-alpha[ip])/Cns[4];
		interp_rhs[ip] = 0;
		//calc new numE
		numE = ny*nx*5 - ny*2 - nx*2 + count[ip]-1;
		//add interp corner to sparse matrix
		for (int n=0;n<4;n++)
		{
			for (int m=0;m<9;m++)
			{
				if (stencil_index[m] == interp_index[n] && !stencil_used[m])
				{
					row[numE] = ip;
					col[numE] = interp_index[n];
					val[numE] = -CInterp[n];//this should also be minus
				}
				else if(stencil_index[m] == ip && interp_index[n] == ip)
					interp_rhs[ip] += CInterp[n]*q[n]; //this should be addition

			}
		}
	}
	else if (ghostTagsP[ip]>0)
	{
		int interp_index[4] = {index1[ip], index2[ip], index3[ip], index4[ip]};
		bool interp_in[4] = {false, false, false, false};
		int ns_index[5] = {ip + nx, ip + 1, ip - nx, ip -1, ip}; //n e s w p
		bool ns_overlap[5] = {false, false, false, false, true};
		double q[4] = {q1[ip], q2[ip], q3[ip], q4[ip]};
		double CInterp[4];
		CInterp[0] = q1coef[ip];
		CInterp[1] = q2coef[ip];
		CInterp[2] = q3coef[ip];
		CInterp[3] = q4coef[ip];
		//count the number of nodes the interp is using
		//find how which ns nodes are occupied
		int counter = 0;
		temp = 0;
		for (int l=0; l<4; l++)
		{
			if (ghostTagsP[interp_index[l]]>0)
			{
				counter +=1;
				interp_in[l] = true;
			}
			for (int n=0; n<5; n++)
			{
				if (interp_index[l] == ns_index[n])
					ns_overlap[n] = true;
			}
		}
		//add center to matrix
		row[numE] = ip;
		col[numE] = ip;
		val[numE] = 1;
		numE++;
		//add real interp values to matrix
		for (int i=0; i<4; i++)
		{
			if (!interp_in[i] && interp_index[i] != ip)
			{
				row[numE] = ip;
				col[numE] = interp_index[i];
				val[numE] = -CInterp[i];
				numE++;
			}
			else
			{
				temp += CInterp[i] * q[i];
			}
		}
		//fill remainder of values
		int counter2 = 0;
		for (int i=0; i<5; i++)
		{
			if (counter2>=counter)
				break;
			if (ns_overlap[i]==false)
			{
				row[numE] = ip;
				col[numE] = ns_index[i];
				val[numE] = 0;
				numE++;
				counter2++;
			}
		}
		ns_rhs[ip] = 0;
		interp_rhs[ip] = dpdn[ip] + temp;
	}
	else //if were not at a hybrid node
	{
		//temp = dt/(dx[I]*(dx[I]+dx[I+1])*0.5) + dt/(dx[I]*(dx[I]+dx[I-1])*0.5) + dt/(dy[J]*(dy[J]+dy[J+1])*0.5) + dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		temp = 0;
		//EAST
		row[numE] = ip;
		col[numE] = ip + 1;
		//val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5)/temp;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
		temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
		numE++;

		//WEST
		row[numE] = ip;
		col[numE] = ip - 1;
		//val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5)/temp;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		temp +=dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		numE++;

		//NORTH
		row[numE] = ip;
		col[numE] = ip + nx;
		//val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5)/temp;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		numE++;

		//SOUTH
		row[numE] = ip;
		col[numE] = ip - nx;
		//val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5)/temp;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		numE++;
		//MID
		row[numE] = ip;
		col[numE] = ip;
		//val[numE] = 1;
		val[numE] = temp;
		ns_rhs[ip] = 1;
		interp_rhs[ip] = 0;
		//ns_rhs[ip] = 1/temp;
		//interp_rhs[ip] = 0;
	}
}
}

	.file	"tmpxft_0020e7f0_00000000-6_LHS2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z115__device_stub__ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_iPiS_PdS0_S0_iidS_S0_S0_S_S_S0_S0_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S0_i
	.type	_Z115__device_stub__ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_iPiS_PdS0_S0_iidS_S0_S0_S_S_S0_S0_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S0_i, @function
_Z115__device_stub__ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_iPiS_PdS0_S0_iidS_S0_S0_S_S_S0_S0_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S0_i:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$520, %rsp
	.cfi_def_cfa_offset 528
	movq	536(%rsp), %rax
	movq	%rdi, 200(%rsp)
	leaq	232(%rsp), %rdi
	movq	%rsi, 192(%rsp)
	leaq	244(%rsp), %rsi
	movq	%rax, 144(%rsp)
	movq	544(%rsp), %rax
	movq	%rdx, 184(%rsp)
	leaq	216(%rsp), %rdx
	movq	%rax, 136(%rsp)
	movq	552(%rsp), %rax
	movq	%rcx, 176(%rsp)
	leaq	224(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movq	560(%rsp), %rax
	movq	%r8, 168(%rsp)
	movq	%rax, 120(%rsp)
	movq	568(%rsp), %rax
	movl	%r9d, 164(%rsp)
	movq	%rax, 112(%rsp)
	movq	576(%rsp), %rax
	movsd	%xmm0, 152(%rsp)
	movq	%rax, 104(%rsp)
	movq	584(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	592(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	600(%rsp), %rax
	movq	%rax, 80(%rsp)
	movq	608(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	616(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	624(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	632(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	640(%rsp), %rax
	movq	%rax, 40(%rsp)
	movq	648(%rsp), %rax
	movq	%rax, 32(%rsp)
	movq	656(%rsp), %rax
	movq	%rax, 24(%rsp)
	movq	664(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	672(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	680(%rsp), %rax
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 504(%rsp)
	xorl	%eax, %eax
	leaq	200(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	184(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	168(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	164(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	528(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	152(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 376(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 384(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 392(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 400(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 408(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 416(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 424(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 432(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 440(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 448(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 456(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 464(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 472(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 480(%rsp)
	movq	%rsp, %rax
	movq	%rax, 488(%rsp)
	leaq	688(%rsp), %rax
	movq	%rax, 496(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 232(%rsp)
	movl	$1, 240(%rsp)
	movq	%rax, 244(%rsp)
	movl	$1, 252(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	224(%rsp)
	.cfi_def_cfa_offset 536
	leaq	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i(%rip), %rdi
	pushq	224(%rsp)
	.cfi_def_cfa_offset 544
	movq	260(%rsp), %rcx
	movl	268(%rsp), %r8d
	movq	248(%rsp), %rsi
	movl	256(%rsp), %edx
	leaq	296(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 536
	popq	%rdx
	.cfi_def_cfa_offset 528
.L2:
	movq	504(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$520, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z115__device_stub__ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_iPiS_PdS0_S0_iidS_S0_S0_S_S_S0_S0_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S0_i, .-_Z115__device_stub__ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_iPiS_PdS0_S0_iidS_S0_S0_S_S_S0_S0_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S0_i
	.globl	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.type	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i, @function
_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z115__device_stub__ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_iPiS_PdS0_S0_iidS_S0_S0_S_S_S0_S0_S_S_S_S_S0_S0_S0_S0_S0_S0_S0_S0_i
	.cfi_endproc
.LFE2033:
	.size	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i, .-_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/***************************************************************************//**
 * \file LHS2.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 * \brief kernels to generate the left hand side for the poission solve
 */


#include <hip/hip_runtime.h>
#include "LHS2.h"

namespace kernels
{
__global__
void LHS2_mid_iter(int *row, int *col, double *val, double *dx, double *dy, int nx, int ny, double dt,
					int *count, double *ns_rhs, double *interp_rhs, int *hybridTagsP, int *ghostTagsP,
					double *alpha, double *dpdn,
					int *index1, int *index2, int *index3, int *index4,
					double *q1coef, double *q2coef, double *q3coef, double *q4coef,
					double *q1, double *q2, double *q3, double *q4, int timeStep)
{
	int ip 	= threadIdx.x + blockDim.x * blockIdx.x;
	if (ip >= nx*ny)
		return;
	int	I	= ip % nx,
		J	= ip / nx;

	if (I == 0 || I == nx-1 || J == 0 || J == ny-1)
		return;

	int numE = nx*4-2 + (J-1)*(nx*5-2) + I*5-1;
	double temp = 0;


	if (hybridTagsP[ip]>0)//if were at hybrid node
	{
		int interp_index[4] = {index1[ip], index2[ip], index3[ip], index4[ip]};
		//int nx_index[5] = {ip+nx, ip+1, ip-nx, ip-1, ip};//n e s w p
		double CInterp[4];
		double Cns[5];
		double q[4] = {q1[ip], q2[ip], q3[ip], q4[ip]};

		//calculate the pressure coefficients for the stencil pressure calculation
		Cns[0] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5); //N
		Cns[1] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5); //E
		Cns[2] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5); //s
		Cns[3] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5); //w
		Cns[4] = -Cns[0] - Cns[1] - Cns[2] - Cns[3]; //P

		//set pressure coefficients for the interpolation pressure calculation
		CInterp[0] = q1coef[ip];
		CInterp[1] = q2coef[ip];
		CInterp[2] = q3coef[ip];
		CInterp[3] = q4coef[ip];

		//multiply by alpha
		for (int i=0;i<4;i++)
		{
			Cns[i] = (1-alpha[ip])*Cns[i]/Cns[4];
			CInterp[i] = alpha[ip]*CInterp[i];
		}

		/*   0  1  2		NW  N   NE
		 *   3  4  5		W   P   E
		 *   6  7  8		SW  S   SE
		 */
		int stencil_index[9]    = {ip + nx - 1, ip + nx, ip + nx + 1,
								   ip - 1     , ip     , ip + 1,
								   ip - nx - 1, ip - nx, ip - nx + 1};
		double stencil[9] = {0, Cns[0], 0, Cns[3], 1, Cns[1], 0, Cns[2], 0};
		//combine ns and interp stencils
		bool stencil_used[9] = {false, true, false, true, true, true, false, true, false};
		for (int n=0;n<4;n++)
		{
			for (int m=0;m<9;m++)
			{
				if (stencil_index[m] == interp_index[n] && m != 4)
				{
					stencil[m] -= CInterp[n]; //this should be minus
				}
			}
		}
		//add ns to sparse matrix
		for (int m = 0; m<9; m++)
		{
			if (stencil_used[m])
			{
				row[numE] = ip;
				col[numE] = stencil_index[m];
				val[numE] = stencil[m];
				numE++;
			}
		}
		ns_rhs[ip] = (1-alpha[ip])/Cns[4];
		interp_rhs[ip] = 0;
		//calc new numE
		numE = ny*nx*5 - ny*2 - nx*2 + count[ip]-1;
		//add interp corner to sparse matrix
		for (int n=0;n<4;n++)
		{
			for (int m=0;m<9;m++)
			{
				if (stencil_index[m] == interp_index[n] && !stencil_used[m])
				{
					row[numE] = ip;
					col[numE] = interp_index[n];
					val[numE] = -CInterp[n];//this should also be minus
				}
				else if(stencil_index[m] == ip && interp_index[n] == ip)
					interp_rhs[ip] += CInterp[n]*q[n]; //this should be addition

			}
		}
	}
	else if (ghostTagsP[ip]>0)
	{
		int interp_index[4] = {index1[ip], index2[ip], index3[ip], index4[ip]};
		bool interp_in[4] = {false, false, false, false};
		int ns_index[5] = {ip + nx, ip + 1, ip - nx, ip -1, ip}; //n e s w p
		bool ns_overlap[5] = {false, false, false, false, true};
		double q[4] = {q1[ip], q2[ip], q3[ip], q4[ip]};
		double CInterp[4];
		CInterp[0] = q1coef[ip];
		CInterp[1] = q2coef[ip];
		CInterp[2] = q3coef[ip];
		CInterp[3] = q4coef[ip];
		//count the number of nodes the interp is using
		//find how which ns nodes are occupied
		int counter = 0;
		temp = 0;
		for (int l=0; l<4; l++)
		{
			if (ghostTagsP[interp_index[l]]>0)
			{
				counter +=1;
				interp_in[l] = true;
			}
			for (int n=0; n<5; n++)
			{
				if (interp_index[l] == ns_index[n])
					ns_overlap[n] = true;
			}
		}
		//add center to matrix
		row[numE] = ip;
		col[numE] = ip;
		val[numE] = 1;
		numE++;
		//add real interp values to matrix
		for (int i=0; i<4; i++)
		{
			if (!interp_in[i] && interp_index[i] != ip)
			{
				row[numE] = ip;
				col[numE] = interp_index[i];
				val[numE] = -CInterp[i];
				numE++;
			}
			else
			{
				temp += CInterp[i] * q[i];
			}
		}
		//fill remainder of values
		int counter2 = 0;
		for (int i=0; i<5; i++)
		{
			if (counter2>=counter)
				break;
			if (ns_overlap[i]==false)
			{
				row[numE] = ip;
				col[numE] = ns_index[i];
				val[numE] = 0;
				numE++;
				counter2++;
			}
		}
		ns_rhs[ip] = 0;
		interp_rhs[ip] = dpdn[ip] + temp;
	}
	else //if were not at a hybrid node
	{
		//temp = dt/(dx[I]*(dx[I]+dx[I+1])*0.5) + dt/(dx[I]*(dx[I]+dx[I-1])*0.5) + dt/(dy[J]*(dy[J]+dy[J+1])*0.5) + dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		temp = 0;
		//EAST
		row[numE] = ip;
		col[numE] = ip + 1;
		//val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5)/temp;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
		temp += dt/(dx[I]*(dx[I]+dx[I+1])*0.5);
		numE++;

		//WEST
		row[numE] = ip;
		col[numE] = ip - 1;
		//val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5)/temp;
		val[numE] = -dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		temp +=dt/(dx[I]*(dx[I]+dx[I-1])*0.5);
		numE++;

		//NORTH
		row[numE] = ip;
		col[numE] = ip + nx;
		//val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5)/temp;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J+1])*0.5);
		numE++;

		//SOUTH
		row[numE] = ip;
		col[numE] = ip - nx;
		//val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5)/temp;
		val[numE] = -dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		temp += dt/(dy[J]*(dy[J]+dy[J-1])*0.5);
		numE++;
		//MID
		row[numE] = ip;
		col[numE] = ip;
		//val[numE] = 1;
		val[numE] = temp;
		ns_rhs[ip] = 1;
		interp_rhs[ip] = 0;
		//ns_rhs[ip] = 1/temp;
		//interp_rhs[ip] = 0;
	}
}
}

	.text
	.file	"LHS2.hip"
	.globl	_ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i # -- Begin function _ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.type	_ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i,@function
_ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i: # @_ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$336, %rsp                      # imm = 0x150
	.cfi_def_cfa_offset 384
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	32(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	480(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	488(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	496(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	504(%rsp), %rax
	movq	%rax, 176(%rbx)
	leaq	512(%rsp), %rax
	movq	%rax, 184(%rbx)
	leaq	520(%rsp), %rax
	movq	%rax, 192(%rbx)
	leaq	528(%rsp), %rax
	movq	%rax, 200(%rbx)
	leaq	536(%rsp), %rax
	movq	%rax, 208(%rbx)
	leaq	544(%rsp), %rax
	movq	%rax, 216(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$352, %rsp                      # imm = 0x160
	.cfi_adjust_cfa_offset -352
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i, .Lfunc_end0-_ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i,@object # @_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.section	.rodata,"a",@progbits
	.globl	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.p2align	3, 0x0
_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i:
	.quad	_ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.size	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i"
	.size	.L__unnamed_1, 102

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN7kernels28__device_stub__LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i ; -- Begin function _ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.globl	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
	.p2align	8
	.type	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i,@function
_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i: ; @_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0xe4
	s_load_b64 s[28:29], s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s30, s29, s28
	v_mad_u64_u32 v[36:37], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s30, v36
	s_cbranch_execz .LBB0_50
; %bb.1:
	s_ashr_i32 s2, s28, 31
	v_ashrrev_i32_e32 v37, 31, v36
	s_add_i32 s3, s28, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s3, s3, s2
	v_add_nc_u32_e32 v2, v36, v37
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s4, 0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v37
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v2, v0
	v_mul_lo_u32 v1, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v2, v1
	v_add_nc_u32_e32 v2, 1, v0
	v_subrev_nc_u32_e32 v3, s3, v1
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2
	v_xor_b32_e32 v3, s2, v37
	v_cmp_le_u32_e32 vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, 1, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v3
	v_sub_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v0, s28
	v_sub_nc_u32_e32 v2, v36, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_50
; %bb.2:
	s_add_i32 s2, s28, -1
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cmp_ne_u32_e64 s2, s2, v2
	s_add_i32 s3, s29, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e64 s3, s3, v0
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_50
; %bb.3:
	s_load_b512 s[4:19], s[0:1], 0x30
	v_lshlrev_b64 v[43:44], 2, v[36:37]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s12, v43
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v44, vcc_lo
	global_load_b32 v1, v[3:4], off
	s_clause 0x3
	s_load_b256 s[20:27], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x20
	s_load_b512 s[36:51], s[0:1], 0x70
	s_load_b256 s[52:59], s[0:1], 0xb0
	s_lshl_b32 s0, s28, 2
	v_add_nc_u32_e32 v3, -1, v0
	s_add_i32 s0, s0, -2
	v_lshl_add_u32 v4, v2, 2, v2
	s_add_i32 s1, s0, s28
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v3, v3, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v41, s0, v4, v3
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e32 1, v1
	s_xor_b32 s12, exec_lo, s0
	s_cbranch_execz .LBB0_27
; %bb.4:
	v_add_co_u32 v3, vcc_lo, s14, v43
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v44, vcc_lo
	v_ashrrev_i32_e32 v42, 31, v41
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $sgpr0_sgpr1
	global_load_b32 v1, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e32 1, v1
	s_xor_b32 s13, exec_lo, s13
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_nc_u32_e32 v15, 1, v36
                                        ; implicit-def: $vgpr43_vgpr44
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s26, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, s27, v2, vcc_lo
	global_load_b128 v[1:4], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[1:2], v[3:4]
	v_mul_f64 v[1:2], v[1:2], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[1:2], v[1:2], 0.5
	v_div_scale_f64 v[3:4], null, v[1:2], v[1:2], -s[4:5]
	v_div_scale_f64 v[11:12], vcc_lo, -s[4:5], v[1:2], -s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[3:4], -v[3:4], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[3:4], v[3:4], v[7:8], v[9:10]
	v_lshlrev_b64 v[7:8], 3, v[41:42]
	v_div_fixup_f64 v[1:2], v[3:4], v[1:2], -s[4:5]
	v_lshlrev_b64 v[3:4], 2, v[41:42]
                                        ; implicit-def: $vgpr41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v4, vcc_lo
	v_add_co_u32 v11, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v12, vcc_lo, s23, v4, vcc_lo
	v_add_co_u32 v13, vcc_lo, s24, v7
	v_add_co_ci_u32_e32 v14, vcc_lo, s25, v8, vcc_lo
	global_store_b32 v[9:10], v36, off offset:-4
	global_store_b32 v[11:12], v15, off offset:-4
	global_store_b64 v[13:14], v[1:2], off offset:-8
	s_clause 0x1
	global_load_b64 v[7:8], v[5:6], off offset:8
	global_load_b128 v[1:4], v[5:6], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[7:8], v[3:4], v[7:8]
	v_add_f64 v[1:2], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[7:8], v[3:4], v[7:8]
	v_mul_f64 v[1:2], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[15:16], v[7:8], 0.5
	v_mul_f64 v[1:2], v[1:2], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[3:4], null, v[15:16], v[15:16], s[4:5]
	v_div_scale_f64 v[7:8], null, v[1:2], v[1:2], -s[4:5]
	v_div_scale_f64 v[25:26], vcc_lo, s[4:5], v[15:16], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[17:18], v[3:4]
	v_rcp_f64_e32 v[19:20], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[3:4], v[17:18], 1.0
	v_fma_f64 v[23:24], -v[7:8], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], -v[3:4], v[17:18], 1.0
	v_fma_f64 v[23:24], -v[7:8], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[17:18], v[21:22], v[17:18]
	v_div_scale_f64 v[21:22], s0, -s[4:5], v[1:2], -s[4:5]
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[23:24], v[25:26], v[17:18]
	v_mul_f64 v[27:28], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[3:4], -v[3:4], v[23:24], v[25:26]
	v_fma_f64 v[7:8], -v[7:8], v[27:28], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[17:18], v[3:4], v[17:18], v[23:24]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[3:4], v[7:8], v[19:20], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[15:16], v[17:18], v[15:16], s[4:5]
	v_div_fixup_f64 v[2:3], v[3:4], v[1:2], -s[4:5]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v19, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v20, vcc_lo, s3, v1, vcc_lo
	v_add_f64 v[15:16], v[15:16], 0
	global_store_b64 v[13:14], v[2:3], off
	global_load_b128 v[0:3], v[5:6], off offset:-8
	global_load_b128 v[4:7], v[19:20], off
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_mul_f64 v[2:3], v[4:5], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[4:5], v[0:1], 0.5
	v_mul_f64 v[0:1], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[4:5], v[4:5], s[4:5]
	v_div_scale_f64 v[6:7], null, v[0:1], v[0:1], -s[4:5]
	v_div_scale_f64 v[29:30], vcc_lo, s[4:5], v[4:5], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[21:22], v[2:3]
	v_rcp_f64_e32 v[23:24], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[2:3], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[6:7], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], -v[2:3], v[21:22], 1.0
	v_fma_f64 v[27:28], -v[6:7], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[21:22], v[25:26], v[21:22]
	v_div_scale_f64 v[25:26], s0, -s[4:5], v[0:1], -s[4:5]
	v_fma_f64 v[23:24], v[23:24], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[27:28], v[29:30], v[21:22]
	v_mul_f64 v[31:32], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], -v[2:3], v[27:28], v[29:30]
	v_fma_f64 v[6:7], -v[6:7], v[31:32], v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[21:22], v[2:3], v[21:22], v[27:28]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[2:3], v[6:7], v[23:24], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[4:5], v[21:22], v[4:5], s[4:5]
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], -s[4:5]
	v_add_nc_u32_e32 v2, -1, v36
	v_add_nc_u32_e32 v3, s28, v36
	global_store_b32 v[9:10], v36, off
	global_store_b32 v[11:12], v2, off
	global_store_b32 v[9:10], v36, off offset:4
	global_store_b32 v[11:12], v3, off offset:4
	global_store_b64 v[13:14], v[0:1], off offset:8
	s_clause 0x1
	global_load_b64 v[6:7], v[19:20], off offset:8
	global_load_b128 v[0:3], v[19:20], off offset:-8
	v_add_f64 v[4:5], v[15:16], v[4:5]
	s_waitcnt vmcnt(0)
	v_add_f64 v[6:7], v[2:3], v[6:7]
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[2:3], v[6:7]
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[6:7], v[6:7], 0.5
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[6:7], v[6:7], s[4:5]
	v_div_scale_f64 v[23:24], null, v[0:1], v[0:1], -s[4:5]
	v_div_scale_f64 v[33:34], vcc_lo, s[4:5], v[6:7], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[25:26], v[2:3]
	v_rcp_f64_e32 v[27:28], v[23:24]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[29:30], -v[2:3], v[25:26], 1.0
	v_fma_f64 v[31:32], -v[23:24], v[27:28], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], v[25:26], v[29:30], v[25:26]
	v_fma_f64 v[27:28], v[27:28], v[31:32], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], -v[2:3], v[25:26], 1.0
	v_fma_f64 v[31:32], -v[23:24], v[27:28], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[25:26], v[29:30], v[25:26]
	v_div_scale_f64 v[29:30], s0, -s[4:5], v[0:1], -s[4:5]
	v_fma_f64 v[27:28], v[27:28], v[31:32], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[31:32], v[33:34], v[25:26]
	v_mul_f64 v[38:39], v[29:30], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], -v[2:3], v[31:32], v[33:34]
	v_fma_f64 v[23:24], -v[23:24], v[38:39], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[25:26], v[2:3], v[25:26], v[31:32]
	s_mov_b32 vcc_lo, s0
	s_mov_b64 s[0:1], 0
	v_div_fmas_f64 v[2:3], v[23:24], v[27:28], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[6:7], v[25:26], v[6:7], s[4:5]
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], -s[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_subrev_nc_u32_e32 v6, s28, v36
	global_store_b64 v[13:14], v[0:1], off offset:16
	global_load_b128 v[0:3], v[19:20], off offset:-8
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_mul_f64 v[0:1], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], s[4:5]
	v_div_scale_f64 v[27:28], vcc_lo, s[4:5], v[0:1], s[4:5]
	v_rcp_f64_e32 v[19:20], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[2:3], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	v_fma_f64 v[23:24], -v[2:3], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[19:20], v[23:24], v[19:20]
	v_mul_f64 v[17:18], v[27:28], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[17:18], v[27:28]
	v_div_fmas_f64 v[2:3], v[2:3], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], s[4:5]
	v_lshlrev_b64 v[2:3], 3, v[36:37]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_add_f64 v[0:1], v[4:5], v[0:1]
	v_dual_mov_b32 v5, 0x3ff00000 :: v_dual_mov_b32 v4, 0
	global_store_b32 v[9:10], v36, off offset:8
	global_store_b32 v[11:12], v6, off offset:8
	global_store_b32 v[9:10], v36, off offset:12
	global_store_b32 v[11:12], v36, off offset:12
	global_store_b64 v[13:14], v[0:1], off offset:24
	global_store_b64 v[2:3], v[4:5], off
.LBB0_6:                                ; %Flow586
	s_or_saveexec_b32 s13, s13
	v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
	s_xor_b32 exec_lo, exec_lo, s13
	s_cbranch_execz .LBB0_26
; %bb.7:
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s36, v43
	v_add_co_ci_u32_e32 v1, vcc_lo, s37, v44, vcc_lo
	v_add_co_u32 v2, vcc_lo, s38, v43
	v_add_co_ci_u32_e32 v3, vcc_lo, s39, v44, vcc_lo
	v_dual_mov_b32 v20, 0 :: v_dual_add_nc_u32 v25, s28, v36
	global_load_b32 v24, v[0:1], off
	global_load_b32 v30, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s40, v43
	v_lshlrev_b64 v[0:1], 3, v[36:37]
	v_add_co_ci_u32_e32 v3, vcc_lo, s41, v44, vcc_lo
	v_add_co_u32 v4, vcc_lo, s42, v43
	v_add_co_ci_u32_e32 v5, vcc_lo, s43, v44, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s52, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s53, v1, vcc_lo
	v_add_co_u32 v8, vcc_lo, s54, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s55, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, s56, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s57, v1, vcc_lo
	global_load_b32 v31, v[2:3], off
	global_load_b32 v32, v[4:5], off
	global_load_b64 v[2:3], v[6:7], off
	global_load_b64 v[4:5], v[8:9], off
	global_load_b64 v[6:7], v[10:11], off
	v_add_co_u32 v8, vcc_lo, s58, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s59, v1, vcc_lo
	v_add_co_u32 v10, vcc_lo, s44, v0
	v_add_co_ci_u32_e32 v11, vcc_lo, s45, v1, vcc_lo
	v_add_co_u32 v12, vcc_lo, s46, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s47, v1, vcc_lo
	v_add_co_u32 v14, vcc_lo, s48, v0
	v_add_co_ci_u32_e32 v15, vcc_lo, s49, v1, vcc_lo
	v_add_co_u32 v16, vcc_lo, s50, v0
	v_add_co_ci_u32_e32 v17, vcc_lo, s51, v1, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[14:15], v[14:15], off
	global_load_b64 v[16:17], v[16:17], off
	v_dual_mov_b32 v29, 0 :: v_dual_add_nc_u32 v26, 1, v36
	v_subrev_nc_u32_e32 v27, s28, v36
	v_dual_mov_b32 v35, 0 :: v_dual_add_nc_u32 v28, -1, v36
	v_dual_mov_b32 v19, 1 :: v_dual_mov_b32 v40, 0
	v_dual_mov_b32 v39, 0 :: v_dual_mov_b32 v38, 0
	v_dual_mov_b32 v18, 0 :: v_dual_mov_b32 v33, 0
	v_mov_b32_e32 v34, 0
	s_mov_b32 s31, 0
.LBB0_8:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_9 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s31, 1
	s_mov_b64 s[0:1], 0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s31, 2
	s_waitcnt vmcnt(10)
	v_cndmask_b32_e32 v21, v24, v30, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s31, 3
	s_waitcnt vmcnt(9)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v21, v21, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_waitcnt vmcnt(8)
	v_cndmask_b32_e32 v22, v21, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v23, 31, v22
	v_lshlrev_b64 v[43:44], 2, v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v43, vcc_lo, s14, v43
	v_add_co_ci_u32_e32 v44, vcc_lo, s15, v44, vcc_lo
	global_load_b32 v23, v[43:44], off
.LBB0_9:                                ;   Parent Loop BB0_8 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s0, 1
	v_lshlrev_b16 v21, 8, v34
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_dual_cndmask_b32 v34, v25, v26 :: v_dual_and_b32 v33, 0xff, v33
	v_lshlrev_b16 v20, 8, v20
	s_cselect_b32 vcc_lo, -1, 0
	v_and_b32_e32 v18, 0xff, v18
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v20, v33, v20
	v_or_b32_e32 v18, v18, v21
	v_cndmask_b32_e32 v21, v34, v27, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v20, 16, v20
	s_cmp_eq_u32 s0, 4
	v_dual_cndmask_b32 v21, v21, v28 :: v_dual_and_b32 v18, 0xffff, v18
	s_cselect_b32 vcc_lo, -1, 0
	s_lshl_b32 s33, s0, 3
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v18, v18, v20
	s_lshl_b64 s[34:35], 0xff, s33
	v_cndmask_b32_e32 v21, v21, v36, vcc_lo
	s_not_b64 s[60:61], s[34:35]
	s_and_b32 s34, s34, 0x1010101
	v_and_b32_e32 v33, s60, v18
	s_and_b32 s33, s35, 0x1010101
	v_cmp_eq_u32_e32 vcc_lo, v22, v21
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	v_or_b32_e32 v33, s34, v33
	v_and_b32_e32 v19, 0xff, v19
	s_cmp_eq_u32 s0, 5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v18, v18, v33 :: v_dual_and_b32 v19, 0xffff, v19
	v_lshrrev_b32_e32 v33, 16, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v20, s61, v19
	v_lshrrev_b32_e32 v34, 8, v18
	v_or_b32_e32 v20, s33, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v19, v19, v20, vcc_lo
	v_lshrrev_b64 v[20:21], 24, v[18:19]
	s_cbranch_scc0 .LBB0_9
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=1
	v_and_b32_e32 v21, 0xff, v35
	v_lshlrev_b16 v22, 8, v40
	v_and_b32_e32 v35, 0xff, v39
	v_lshlrev_b16 v38, 8, v38
	s_lshl_b32 s0, s31, 3
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, 0, v23
	v_or_b32_e32 v21, v21, v22
	s_lshl_b32 s0, 0xff, s0
	v_or_b32_e32 v22, v35, v38
	s_add_i32 s31, s31, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v21, 0xffff, v21
	s_cmp_eq_u32 s31, 4
	v_lshlrev_b32_e32 v22, 16, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v21, v21, v22
	v_bfi_b32 v22, s0, 0x1010101, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v35, v21, v22, vcc_lo
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v29, vcc_lo
	v_lshrrev_b32_e32 v38, 24, v35
	v_lshrrev_b32_e32 v39, 16, v35
	v_lshrrev_b32_e32 v40, 8, v35
	s_cbranch_scc0 .LBB0_8
; %bb.11:
	v_dual_mov_b32 v46, 0 :: v_dual_and_b32 v23, 0xff, v35
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b16 v35, 8, v40
	v_and_b32_e32 v40, 0xff, v39
	v_lshlrev_b16 v44, 8, v38
	v_lshlrev_b64 v[21:22], 2, v[41:42]
	v_lshlrev_b64 v[42:43], 3, v[41:42]
	v_or_b32_e32 v23, v23, v35
	v_mov_b32_e32 v47, 0x3ff00000
	v_or_b32_e32 v35, v40, v44
	s_mov_b64 s[0:1], 0
	v_add_co_u32 v38, vcc_lo, s20, v21
	v_add_co_ci_u32_e32 v39, vcc_lo, s21, v22, vcc_lo
	v_add_co_u32 v44, vcc_lo, s22, v21
	v_and_b32_e32 v23, 0xffff, v23
	v_lshlrev_b32_e32 v35, 16, v35
	v_add_co_ci_u32_e32 v45, vcc_lo, s23, v22, vcc_lo
	v_add_co_u32 v42, vcc_lo, s24, v42
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	v_add_co_ci_u32_e32 v43, vcc_lo, s25, v43, vcc_lo
	v_or_b32_e32 v35, v23, v35
	global_store_b32 v[38:39], v36, off offset:-4
	global_store_b32 v[44:45], v36, off offset:-4
	global_store_b64 v[42:43], v[46:47], off offset:-8
.LBB0_12:                               ; =>This Inner Loop Header: Depth=1
	s_lshl_b32 s14, s0, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v23, s14, v35
	v_and_b32_e32 v23, 0xff, v23
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u16_e64 s14, 0, v23
	v_cmp_eq_u16_e32 vcc_lo, 0, v23
                                        ; implicit-def: $vgpr23
	s_and_saveexec_b32 s15, vcc_lo
	s_cbranch_execz .LBB0_16
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=1
	s_cmp_eq_u32 s0, 1
	s_mov_b32 s33, -1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v23, v24, v30, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_mov_b32 s31, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v23, v23, v31, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v38, v23, v32, vcc_lo
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e64 v38, v36
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_12 Depth=1
	v_ashrrev_i32_e32 v42, 31, v41
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[39:40], 2, v[41:42]
	v_cndmask_b32_e32 v45, v11, v13, vcc_lo
	v_cndmask_b32_e32 v23, v10, v12, vcc_lo
	v_add_co_u32 v43, vcc_lo, s20, v39
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v44, vcc_lo, s21, v40, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	v_cndmask_b32_e32 v48, v45, v15, vcc_lo
	v_lshlrev_b64 v[45:46], 3, v[41:42]
	v_cndmask_b32_e32 v23, v23, v14, vcc_lo
	v_add_co_u32 v39, vcc_lo, s22, v39
	v_add_co_ci_u32_e32 v40, vcc_lo, s23, v40, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_xor_b32 s33, exec_lo, -1
	v_cndmask_b32_e32 v47, v23, v16, vcc_lo
	v_cndmask_b32_e64 v48, -v48, -v17, vcc_lo
	v_add_co_u32 v45, vcc_lo, s24, v45
	v_add_co_ci_u32_e32 v46, vcc_lo, s25, v46, vcc_lo
	v_add_nc_u32_e32 v23, 1, v41
	global_store_b32 v[43:44], v36, off
	global_store_b32 v[39:40], v38, off
	global_store_b64 v[45:46], v[47:48], off
.LBB0_15:                               ; %Flow585
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s14, s14, exec_lo
	s_and_b32 s31, s33, exec_lo
	s_or_b32 s14, s14, s31
.LBB0_16:                               ; %Flow584
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_and_saveexec_b32 s15, s14
	s_cbranch_execz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_12 Depth=1
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_dual_cndmask_b32 v23, v11, v13 :: v_dual_cndmask_b32 v38, v10, v12
	v_dual_cndmask_b32 v39, v3, v5 :: v_dual_cndmask_b32 v40, v2, v4
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v23, v23, v15 :: v_dual_cndmask_b32 v38, v38, v14
	v_cndmask_b32_e32 v42, v39, v7, vcc_lo
	v_cndmask_b32_e32 v40, v40, v6, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v39, v23, v17 :: v_dual_cndmask_b32 v38, v38, v16
	v_mov_b32_e32 v23, v41
	v_dual_cndmask_b32 v43, v42, v9 :: v_dual_cndmask_b32 v42, v40, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[21:22], v[38:39], v[42:43], v[21:22]
.LBB0_18:                               ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 4
	s_cbranch_scc1 .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mov_b32_e32 v41, v23
	s_branch .LBB0_12
.LBB0_20:                               ; %.preheader431
	s_mov_b32 s15, 0
	s_mov_b32 s14, exec_lo
	v_cmpx_ne_u32_e32 0, v29
	s_cbranch_execz .LBB0_25
; %bb.21:                               ; %.lr.ph.preheader
	v_and_b32_e32 v2, 0xff, v18
	v_lshlrev_b16 v3, 8, v34
	v_and_b32_e32 v4, 0xff, v33
	v_lshlrev_b16 v5, 8, v20
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v2, v2, v3
	v_or_b32_e32 v3, v4, v5
	v_and_b32_e32 v4, 0xff, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v6, 0xffff, v2
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, 0xffff, v4
	v_or_b32_e32 v4, v6, v3
	v_mov_b32_e32 v6, 0
.LBB0_22:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_lshl_b32 s31, s0, 3
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_lshrrev_b64 v[7:8], s31, v[4:5]
	s_mov_b32 s31, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, 0xff, v7
	v_cmpx_eq_u16_e32 0, v3
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
	s_cmp_eq_u32 s0, 1
	v_ashrrev_i32_e32 v24, 31, v23
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	v_cndmask_b32_e32 v3, v25, v26, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_lshlrev_b64 v[7:8], 2, v[23:24]
	s_cmp_eq_u32 s0, 3
	v_lshlrev_b64 v[11:12], 3, v[23:24]
	v_dual_cndmask_b32 v3, v3, v27 :: v_dual_add_nc_u32 v6, 1, v6
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 4
	v_add_nc_u32_e32 v23, 1, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v28, vcc_lo
	v_add_co_u32 v9, vcc_lo, s20, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, s21, v8, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v13, v3, v36, vcc_lo
	v_add_co_u32 v7, vcc_lo, s22, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s23, v8, vcc_lo
	v_add_co_u32 v11, vcc_lo, s24, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s25, v12, vcc_lo
	v_mov_b32_e32 v3, v2
	global_store_b32 v[9:10], v36, off
	global_store_b32 v[7:8], v13, off
	global_store_b64 v[11:12], v[2:3], off
.LBB0_24:                               ;   in Loop: Header=BB0_22 Depth=1
	s_or_b32 exec_lo, exec_lo, s31
	v_cmp_ge_i32_e32 vcc_lo, v6, v29
	s_cmp_gt_u32 s0, 3
	s_cselect_b32 s31, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 s31, s31, vcc_lo
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_and_b32 s31, exec_lo, s31
	s_or_b32 s15, s31, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB0_22
.LBB0_25:                               ; %Flow583
	s_or_b32 exec_lo, exec_lo, s14
	v_mov_b32_e32 v2, 0
	v_add_co_u32 v4, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s18, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v3, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	global_store_b64 v[4:5], v[2:3], off
	global_load_b64 v[0:1], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[21:22], v[0:1]
.LBB0_26:                               ; %Flow587
	s_or_b32 exec_lo, exec_lo, s13
	v_lshlrev_b64 v[2:3], 3, v[36:37]
                                        ; implicit-def: $vgpr36_vgpr37
                                        ; implicit-def: $vgpr43_vgpr44
                                        ; implicit-def: $vgpr41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr2
.LBB0_27:                               ; %Flow591
	s_and_not1_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_50
; %bb.28:
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[61:62], 3, v[36:37]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s26, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s27, v3, vcc_lo
	s_clause 0x1
	global_load_b64 v[8:9], v[0:1], off offset:8
	global_load_b128 v[0:3], v[0:1], off offset:-8
	s_clause 0x1
	global_load_b64 v[10:11], v[4:5], off offset:8
	global_load_b128 v[4:7], v[4:5], off offset:-8
	v_add_co_u32 v28, vcc_lo, s36, v43
	v_add_co_ci_u32_e32 v29, vcc_lo, s37, v44, vcc_lo
	s_waitcnt vmcnt(2)
	v_add_f64 v[8:9], v[2:3], v[8:9]
	v_add_f64 v[0:1], v[2:3], v[0:1]
	s_waitcnt vmcnt(0)
	v_add_f64 v[10:11], v[6:7], v[10:11]
	v_add_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[8:9], v[2:3], v[8:9]
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[10:11], v[6:7], v[10:11]
	v_mul_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[2:3], v[8:9], 0.5
	v_mul_f64 v[6:7], v[0:1], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[8:9], v[10:11], 0.5
	v_mul_f64 v[4:5], v[4:5], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f64 v[10:11], null, v[2:3], v[2:3], -s[4:5]
	v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], -s[4:5]
	v_div_scale_f64 v[14:15], null, v[6:7], v[6:7], -s[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[18:19], null, v[4:5], v[4:5], -s[4:5]
	v_rcp_f64_e32 v[0:1], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[16:17], v[12:13]
	v_rcp_f64_e32 v[20:21], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_rcp_f64_e32 v[26:27], v[18:19]
	v_fma_f64 v[22:23], -v[10:11], v[0:1], 1.0
	v_fma_f64 v[24:25], -v[12:13], v[16:17], 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[30:31], -v[14:15], v[20:21], 1.0
	v_fma_f64 v[34:35], -v[18:19], v[26:27], 1.0
	v_fma_f64 v[22:23], v[0:1], v[22:23], v[0:1]
	v_add_co_u32 v0, vcc_lo, s38, v43
	v_fma_f64 v[16:17], v[16:17], v[24:25], v[16:17]
	v_add_co_ci_u32_e32 v1, vcc_lo, s39, v44, vcc_lo
	v_add_co_u32 v24, vcc_lo, s40, v43
	v_add_co_ci_u32_e32 v25, vcc_lo, s41, v44, vcc_lo
	v_add_co_u32 v32, vcc_lo, s42, v43
	v_add_co_ci_u32_e32 v33, vcc_lo, s43, v44, vcc_lo
	v_add_co_u32 v63, vcc_lo, s16, v61
	v_add_co_ci_u32_e32 v64, vcc_lo, s17, v62, vcc_lo
	global_load_b32 v69, v[28:29], off
	global_load_b32 v70, v[0:1], off
	global_load_b32 v71, v[24:25], off
	global_load_b32 v72, v[32:33], off
	v_add_co_u32 v24, vcc_lo, s52, v61
	global_load_b64 v[0:1], v[63:64], off
	v_add_co_ci_u32_e32 v25, vcc_lo, s53, v62, vcc_lo
	v_add_co_u32 v28, vcc_lo, s54, v61
	v_add_co_ci_u32_e32 v29, vcc_lo, s55, v62, vcc_lo
	v_add_co_u32 v32, vcc_lo, s56, v61
	v_fma_f64 v[20:21], v[20:21], v[30:31], v[20:21]
	v_add_co_ci_u32_e32 v33, vcc_lo, s57, v62, vcc_lo
	v_add_co_u32 v37, vcc_lo, s58, v61
	v_add_co_ci_u32_e32 v38, vcc_lo, s59, v62, vcc_lo
	v_add_co_u32 v53, vcc_lo, s44, v61
	v_fma_f64 v[30:31], -v[10:11], v[22:23], 1.0
	v_add_co_ci_u32_e32 v54, vcc_lo, s45, v62, vcc_lo
	v_fma_f64 v[39:40], -v[12:13], v[16:17], 1.0
	v_add_co_u32 v55, vcc_lo, s46, v61
	v_add_co_ci_u32_e32 v56, vcc_lo, s47, v62, vcc_lo
	v_add_co_u32 v57, vcc_lo, s48, v61
	v_add_co_ci_u32_e32 v58, vcc_lo, s49, v62, vcc_lo
	v_add_co_u32 v59, vcc_lo, s50, v61
	v_add_co_ci_u32_e32 v60, vcc_lo, s51, v62, vcc_lo
	global_load_b64 v[45:46], v[24:25], off
	global_load_b64 v[47:48], v[28:29], off
	global_load_b64 v[49:50], v[32:33], off
	global_load_b64 v[51:52], v[37:38], off
	global_load_b64 v[53:54], v[53:54], off
	global_load_b64 v[55:56], v[55:56], off
	global_load_b64 v[57:58], v[57:58], off
	global_load_b64 v[59:60], v[59:60], off
	v_fma_f64 v[24:25], v[26:27], v[34:35], v[26:27]
	v_div_scale_f64 v[28:29], vcc_lo, -s[4:5], v[2:3], -s[4:5]
	v_div_scale_f64 v[32:33], s1, -s[4:5], v[6:7], -s[4:5]
	v_fma_f64 v[26:27], -v[14:15], v[20:21], 1.0
	v_fma_f64 v[22:23], v[22:23], v[30:31], v[22:23]
	v_div_scale_f64 v[30:31], s0, -s[4:5], v[8:9], -s[4:5]
	v_fma_f64 v[16:17], v[16:17], v[39:40], v[16:17]
	v_div_scale_f64 v[39:40], s2, -s[4:5], v[4:5], -s[4:5]
	v_fma_f64 v[34:35], -v[18:19], v[24:25], 1.0
	v_fma_f64 v[20:21], v[20:21], v[26:27], v[20:21]
	v_mul_f64 v[26:27], v[28:29], v[22:23]
	v_mul_f64 v[37:38], v[30:31], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[24:25], v[34:35], v[24:25]
	v_mul_f64 v[34:35], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[10:11], -v[10:11], v[26:27], v[28:29]
	v_fma_f64 v[12:13], -v[12:13], v[37:38], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[28:29], v[39:40], v[24:25]
	v_fma_f64 v[14:15], -v[14:15], v[34:35], v[32:33]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[10:11], v[10:11], v[22:23], v[26:27]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[37:38]
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[16:17], -v[18:19], v[28:29], v[39:40]
	v_div_fmas_f64 v[14:15], v[14:15], v[20:21], v[34:35]
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[2:3], v[10:11], v[2:3], -s[4:5]
	v_div_fixup_f64 v[10:11], v[12:13], v[8:9], -s[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f64 v[8:9], v[16:17], v[24:25], v[28:29]
	v_div_fixup_f64 v[14:15], v[14:15], v[6:7], -s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], -v[2:3], -v[10:11]
	v_div_fixup_f64 v[6:7], v[8:9], v[4:5], -s[4:5]
	s_mov_b64 s[4:5], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[12:13], -v[14:15]
	v_add_f64 v[65:66], v[4:5], -v[6:7]
	s_waitcnt vmcnt(8)
	v_add_f64 v[4:5], -v[0:1], 1.0
.LBB0_29:                               ; =>This Inner Loop Header: Depth=1
	s_cmp_eq_u32 s4, 1
	s_cselect_b32 s0, -1, 0
	s_cmp_eq_u32 s4, 2
	v_cndmask_b32_e64 v8, v3, v11, s0
	v_cndmask_b32_e64 v9, v2, v10, s0
	s_cselect_b32 s1, -1, 0
	s_cmp_eq_u32 s4, 3
	s_cselect_b32 s2, -1, 0
	v_cndmask_b32_e64 v8, v8, v15, s1
	v_cndmask_b32_e64 v9, v9, v14, s1
	s_cmp_eq_u32 s4, 4
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, v8, v7, s2
	v_cndmask_b32_e64 v12, v9, v6, s2
	s_cmp_eq_u32 s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, v8, v66, s3
	v_cndmask_b32_e64 v8, v12, v65, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], v[4:5]
	v_div_scale_f64 v[12:13], null, v[65:66], v[65:66], v[8:9]
	v_div_scale_f64 v[20:21], vcc_lo, v[8:9], v[65:66], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[16:17], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
	v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[20:21], v[16:17]
	v_fma_f64 v[12:13], -v[12:13], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[18:19]
	s_waitcnt vmcnt(2)
	v_cndmask_b32_e64 v16, v54, v56, s0
	v_cndmask_b32_e64 v17, v53, v55, s0
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_waitcnt vmcnt(1)
	v_cndmask_b32_e64 v16, v16, v58, s1
	v_cndmask_b32_e64 v18, v17, v57, s1
	s_cmp_eq_u32 s4, 4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v17, v16, v60, s2
	v_cndmask_b32_e64 v16, v18, v59, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[16:17], v[0:1]
	v_div_fixup_f64 v[8:9], v[12:13], v[65:66], v[8:9]
	v_cndmask_b32_e64 v60, v60, v17, s2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v59, v59, v16, s2
	v_cndmask_b32_e64 v58, v58, v17, s1
	v_cndmask_b32_e64 v57, v57, v16, s1
	v_cndmask_b32_e64 v56, v56, v17, s0
	v_cndmask_b32_e64 v55, v55, v16, s0
	v_dual_cndmask_b32 v54, v54, v17 :: v_dual_cndmask_b32 v53, v53, v16
	v_cndmask_b32_e64 v66, v66, v9, s3
	v_cndmask_b32_e64 v65, v65, v8, s3
	v_cndmask_b32_e64 v7, v7, v9, s2
	v_cndmask_b32_e64 v6, v6, v8, s2
	v_cndmask_b32_e64 v15, v15, v9, s1
	v_cndmask_b32_e64 v14, v14, v8, s1
	v_cndmask_b32_e64 v11, v11, v9, s0
	v_cndmask_b32_e64 v10, v10, v8, s0
	v_dual_cndmask_b32 v3, v3, v9 :: v_dual_cndmask_b32 v2, v2, v8
	s_cbranch_scc0 .LBB0_29
; %bb.30:
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v33, s28, v36
	v_subrev_nc_u32_e32 v39, s28, v36
	v_add_nc_u32_e32 v35, -1, v36
	v_add_nc_u32_e32 v37, 1, v36
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v9, 0x3ff00000 :: v_dual_add_nc_u32 v32, -1, v33
	v_dual_mov_b32 v1, v0 :: v_dual_add_nc_u32 v34, 1, v33
	v_dual_mov_b32 v5, v0 :: v_dual_add_nc_u32 v38, -1, v39
	v_dual_mov_b32 v13, v0 :: v_dual_add_nc_u32 v40, 1, v39
	v_mov_b32_e32 v4, v0
	v_mov_b32_e32 v8, v0
	v_mov_b32_e32 v12, v0
	v_mov_b32_e32 v16, v0
	v_mov_b32_e32 v17, v0
	s_mov_b32 s2, 0
.LBB0_31:                               ; %.preheader430
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_32 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 1
	s_mov_b64 s[0:1], 0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 2
	v_dual_cndmask_b32 v42, v69, v70 :: v_dual_cndmask_b32 v67, v54, v56
	v_cndmask_b32_e32 v68, v53, v55, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v67, v67, v58 :: v_dual_cndmask_b32 v42, v42, v71
	v_cndmask_b32_e32 v73, v68, v57, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v68, v67, v60, vcc_lo
	v_dual_cndmask_b32 v42, v42, v72 :: v_dual_cndmask_b32 v67, v73, v59
.LBB0_32:                               ;   Parent Loop BB0_31 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 m0, s0
	s_cmp_lg_u32 s0, 4
	v_movrels_b32_e32 v73, v32
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, v73, v42
	s_and_b32 s4, s3, vcc_lo
	s_and_saveexec_b32 s3, s4
; %bb.33:                               ;   in Loop: Header=BB0_32 Depth=2
	s_lshl_b32 s4, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s4
	v_movrels_b32_e32 v74, v1
	v_movrels_b32_e32 v73, v0
	v_add_f64 v[73:74], v[73:74], -v[67:68]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_movreld_b32_e32 v0, v73
	v_movreld_b32_e32 v1, v74
; %bb.34:                               ;   in Loop: Header=BB0_32 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 9
	s_cbranch_scc0 .LBB0_32
; %bb.35:                               ;   in Loop: Header=BB0_31 Depth=1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 4
	s_cbranch_scc1 .LBB0_31
; %bb.36:                               ; %.preheader429.preheader
	v_add_nc_u32_e32 v41, -1, v41
	s_mov_b64 s[0:1], 0
.LBB0_37:                               ; %.preheader429
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 2
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 1
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s0, 3
	v_cndmask_b32_e64 v42, 0, 1, s2
	s_cselect_b32 s2, -1, 0
	s_cmp_lg_u32 s0, 4
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e32 v42, 0, v42, vcc_lo
	s_and_b32 s2, s3, s2
	s_cmp_lg_u32 s0, 5
	s_cselect_b32 s3, -1, 0
	s_and_b32 vcc_lo, s3, s2
	s_cmp_lg_u32 s0, 6
	v_cndmask_b32_e32 v42, 1, v42, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s0, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v42, 0, v42, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_lg_u32 s0, 8
	v_cndmask_b32_e32 v42, 1, v42, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v42, 0, v42, vcc_lo
	v_cmp_eq_u16_e32 vcc_lo, 0, v42
	s_cbranch_vccnz .LBB0_39
; %bb.38:                               ;   in Loop: Header=BB0_37 Depth=1
	v_ashrrev_i32_e32 v42, 31, v41
	s_mov_b32 m0, s0
	s_lshl_b32 s2, s0, 1
	v_movrels_b32_e32 v79, v32
	s_mov_b32 m0, s2
	v_lshlrev_b64 v[67:68], 2, v[41:42]
	v_lshlrev_b64 v[75:76], 3, v[41:42]
	v_add_nc_u32_e32 v41, 1, v41
	v_movrels_b32_e32 v78, v1
	v_movrels_b32_e32 v77, v0
	v_add_co_u32 v73, vcc_lo, s20, v67
	v_add_co_ci_u32_e32 v74, vcc_lo, s21, v68, vcc_lo
	v_add_co_u32 v67, vcc_lo, s22, v67
	v_add_co_ci_u32_e32 v68, vcc_lo, s23, v68, vcc_lo
	v_add_co_u32 v75, vcc_lo, s24, v75
	v_add_co_ci_u32_e32 v76, vcc_lo, s25, v76, vcc_lo
	global_store_b32 v[73:74], v36, off
	global_store_b32 v[67:68], v79, off
	global_store_b64 v[75:76], v[77:78], off
.LBB0_39:                               ;   in Loop: Header=BB0_37 Depth=1
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 9
	s_cbranch_scc0 .LBB0_37
; %bb.40:
	global_load_b64 v[0:1], v[63:64], off
	v_add_co_u32 v4, vcc_lo, s6, v43
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v44, vcc_lo
	s_add_i32 s0, s29, s28
	s_mul_i32 s30, s30, 5
	s_lshl_b32 s0, s0, 1
	global_load_b32 v10, v[4:5], off
	s_not_b32 s0, s0
	v_mov_b32_e32 v12, 0
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v13, v12
	s_waitcnt vmcnt(1)
	v_add_f64 v[0:1], -v[0:1], 1.0
	v_div_scale_f64 v[2:3], null, v[65:66], v[65:66], v[0:1]
	v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[65:66], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[6:7], v[8:9], v[4:5]
	v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	v_div_fixup_f64 v[8:9], v[2:3], v[65:66], v[0:1]
	s_waitcnt vmcnt(0)
	v_add3_u32 v2, s30, s0, v10
	v_add_co_u32 v10, vcc_lo, s8, v61
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v62, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v3, 31, v2
	v_add_co_u32 v0, vcc_lo, s10, v61
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v62, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	global_store_b64 v[10:11], v[8:9], off
	global_store_b64 v[0:1], v[12:13], off
	v_add_co_u32 v2, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s21, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s22, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s23, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
.LBB0_41:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_42 Depth 2
	s_cmp_eq_u32 s4, 1
	s_mov_b64 s[2:3], 0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s4, 2
	v_dual_cndmask_b32 v8, v69, v70 :: v_dual_cndmask_b32 v9, v54, v56
	s_cselect_b32 s0, -1, 0
	v_dual_cndmask_b32 v10, v53, v55 :: v_dual_cndmask_b32 v11, v46, v48
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v71, s0
	v_cndmask_b32_e64 v9, v9, v58, s0
	v_cndmask_b32_e32 v13, v45, v47, vcc_lo
	s_cmp_eq_u32 s4, 3
	s_cselect_b32 vcc_lo, -1, 0
	v_cndmask_b32_e32 v12, v8, v72, vcc_lo
	v_cndmask_b32_e64 v8, v10, v57, s0
	v_cndmask_b32_e64 v10, v11, v50, s0
	v_cndmask_b32_e64 v13, v13, v49, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v9, v9, v60 :: v_dual_cndmask_b32 v8, v8, v59
	v_dual_cndmask_b32 v11, v10, v52 :: v_dual_cndmask_b32 v10, v13, v51
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, 0x80000000, v9
	v_cmp_eq_u32_e32 vcc_lo, v12, v36
	v_mul_f64 v[10:11], -v[8:9], v[10:11]
.LBB0_42:                               ;   Parent Loop BB0_41 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s2, 1
	s_mov_b32 m0, s2
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s2, 2
	v_cndmask_b32_e64 v13, 0, 1, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s2, 3
	s_cselect_b32 s1, -1, 0
	s_cmp_lg_u32 s2, 4
	v_cndmask_b32_e64 v13, 0, v13, s0
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, s5, s1
	s_cmp_lg_u32 s2, 5
	s_cselect_b32 s1, -1, 0
	s_and_b32 s0, s1, s0
	s_cmp_lg_u32 s2, 6
	v_cndmask_b32_e64 v13, 1, v13, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s2, 7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0, v13, s0
	s_cselect_b32 s0, -1, 0
	s_cmp_lg_u32 s2, 8
	v_cndmask_b32_e64 v14, 1, v13, s0
	s_cselect_b32 s0, -1, 0
	v_movrels_b32_e32 v13, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, 0, v14, s0
	v_cmp_ne_u32_e64 s0, v13, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ne_u16_e64 s1, 0, v14
	s_or_b32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_46
; %bb.43:                               ;   in Loop: Header=BB0_42 Depth=2
	v_cmp_eq_u32_e64 s0, v13, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s5, vcc_lo, s0
	s_and_saveexec_b32 s0, s5
	s_cbranch_execz .LBB0_45
; %bb.44:                               ;   in Loop: Header=BB0_42 Depth=2
	global_load_b64 v[13:14], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[13:14], v[10:11], v[13:14]
	global_store_b64 v[0:1], v[13:14], off
.LBB0_45:                               ; %Flow588
                                        ;   in Loop: Header=BB0_42 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_46:                               ; %Flow589
                                        ;   in Loop: Header=BB0_42 Depth=2
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_48
; %bb.47:                               ;   in Loop: Header=BB0_42 Depth=2
	global_store_b32 v[2:3], v36, off
	global_store_b32 v[4:5], v12, off
	global_store_b64 v[6:7], v[8:9], off
.LBB0_48:                               ;   in Loop: Header=BB0_42 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_cmp_eq_u32 s2, 9
	s_cbranch_scc0 .LBB0_42
; %bb.49:                               ;   in Loop: Header=BB0_41 Depth=1
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 4
	s_cbranch_scc0 .LBB0_41
.LBB0_50:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 472
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 80
		.amdhsa_next_free_sgpr 62
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i, .Lfunc_end0-_ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6520
; NumSgprs: 64
; NumVgprs: 80
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 7
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 64
; NumVGPRsForWavesPerEU: 80
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
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    .kernarg_segment_align: 8
    .kernarg_segment_size: 472
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i
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    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels13LHS2_mid_iterEPiS0_PdS1_S1_iidS0_S1_S1_S0_S0_S1_S1_S0_S0_S0_S0_S1_S1_S1_S1_S1_S1_S1_S1_i.kd
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    .vgpr_count:     80
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
