#define bidx (blockIdx.x)
#define bidy (blockIdx.y)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define COALESCED_NUM 16
#define blockDimX 128
#define blockDimY 1
#define idx (bidx*blockDimX+tidx)
#define idy (bidy*blockDimY+tidy)
#define merger_y 32
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define A(y,x) A[(y)*WIDTH_A+(x)]
#define B(y,x) B[(y)*WIDTH_B+(x)]
#define C(y,x) C[(y)*WIDTH_C+(x)]
#define WIDTH_C 2048
#define WIDTH_B 2048
#define WIDTH_A 2048
__global__ void matmul(float * A, float * B, float * C, int width, int height)
{
	__shared__ float shared_0[16][33];
	int i;
	float sum_0;
	float sum_1;
	float sum_2;
	float sum_3;
	float sum_4;
	float sum_5;
	float sum_6;
	float sum_7;
	float sum_8;
	float sum_9;
	float sum_10;
	float sum_11;
	float sum_12;
	float sum_13;
	float sum_14;
	float sum_15;
	float sum_16;
	float sum_17;
	float sum_18;
	float sum_19;
	float sum_20;
	float sum_21;
	float sum_22;
	float sum_23;
	float sum_24;
	float sum_25;
	float sum_26;
	float sum_27;
	float sum_28;
	float sum_29;
	float sum_30;
	float sum_31;
	sum_0=0;
	sum_1=0;
	sum_2=0;
	sum_3=0;
	sum_4=0;
	sum_5=0;
	sum_6=0;
	sum_7=0;
	sum_8=0;
	sum_9=0;
	sum_10=0;
	sum_11=0;
	sum_12=0;
	sum_13=0;
	sum_14=0;
	sum_15=0;
	sum_16=0;
	sum_17=0;
	sum_18=0;
	sum_19=0;
	sum_20=0;
	sum_21=0;
	sum_22=0;
	sum_23=0;
	sum_24=0;
	sum_25=0;
	sum_26=0;
	sum_27=0;
	sum_28=0;
	sum_29=0;
	sum_30=0;
	sum_31=0;
	for (i=0; i<width; i=(i+16))
	{
		int it_1;
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+0), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+8), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+16), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+24), (i+(tidx%16)));
		__syncthreads();
		#pragma unroll 
		for (it_1=0; it_1<16; it_1=(it_1+1))
		{
			float a_0;
			float a_1;
			float a_2;
			float a_3;
			float a_4;
			float a_5;
			float a_6;
			float a_7;
			float a_8;
			float a_9;
			float a_10;
			float a_11;
			float a_12;
			float a_13;
			float a_14;
			float a_15;
			float a_16;
			float a_17;
			float a_18;
			float a_19;
			float a_20;
			float a_21;
			float a_22;
			float a_23;
			float a_24;
			float a_25;
			float a_26;
			float a_27;
			float a_28;
			float a_29;
			float a_30;
			float a_31;
			float b;
			a_0=shared_0[it_1][0];
			a_1=shared_0[it_1][1];
			a_2=shared_0[it_1][2];
			a_3=shared_0[it_1][3];
			a_4=shared_0[it_1][4];
			a_5=shared_0[it_1][5];
			a_6=shared_0[it_1][6];
			a_7=shared_0[it_1][7];
			a_8=shared_0[it_1][8];
			a_9=shared_0[it_1][9];
			a_10=shared_0[it_1][10];
			a_11=shared_0[it_1][11];
			a_12=shared_0[it_1][12];
			a_13=shared_0[it_1][13];
			a_14=shared_0[it_1][14];
			a_15=shared_0[it_1][15];
			a_16=shared_0[it_1][16];
			a_17=shared_0[it_1][17];
			a_18=shared_0[it_1][18];
			a_19=shared_0[it_1][19];
			a_20=shared_0[it_1][20];
			a_21=shared_0[it_1][21];
			a_22=shared_0[it_1][22];
			a_23=shared_0[it_1][23];
			a_24=shared_0[it_1][24];
			a_25=shared_0[it_1][25];
			a_26=shared_0[it_1][26];
			a_27=shared_0[it_1][27];
			a_28=shared_0[it_1][28];
			a_29=shared_0[it_1][29];
			a_30=shared_0[it_1][30];
			a_31=shared_0[it_1][31];
			b=B((it_1+i), idx);
			sum_0+=(a_0*b);
			sum_1+=(a_1*b);
			sum_2+=(a_2*b);
			sum_3+=(a_3*b);
			sum_4+=(a_4*b);
			sum_5+=(a_5*b);
			sum_6+=(a_6*b);
			sum_7+=(a_7*b);
			sum_8+=(a_8*b);
			sum_9+=(a_9*b);
			sum_10+=(a_10*b);
			sum_11+=(a_11*b);
			sum_12+=(a_12*b);
			sum_13+=(a_13*b);
			sum_14+=(a_14*b);
			sum_15+=(a_15*b);
			sum_16+=(a_16*b);
			sum_17+=(a_17*b);
			sum_18+=(a_18*b);
			sum_19+=(a_19*b);
			sum_20+=(a_20*b);
			sum_21+=(a_21*b);
			sum_22+=(a_22*b);
			sum_23+=(a_23*b);
			sum_24+=(a_24*b);
			sum_25+=(a_25*b);
			sum_26+=(a_26*b);
			sum_27+=(a_27*b);
			sum_28+=(a_28*b);
			sum_29+=(a_29*b);
			sum_30+=(a_30*b);
			sum_31+=(a_31*b);
		}
		__syncthreads();
	}
	{
		C((((bidy*32)+tidy)+0), idx)=sum_0;
	}
	{
		C((((bidy*32)+tidy)+1), idx)=sum_1;
	}
	{
		C((((bidy*32)+tidy)+2), idx)=sum_2;
	}
	{
		C((((bidy*32)+tidy)+3), idx)=sum_3;
	}
	{
		C((((bidy*32)+tidy)+4), idx)=sum_4;
	}
	{
		C((((bidy*32)+tidy)+5), idx)=sum_5;
	}
	{
		C((((bidy*32)+tidy)+6), idx)=sum_6;
	}
	{
		C((((bidy*32)+tidy)+7), idx)=sum_7;
	}
	{
		C((((bidy*32)+tidy)+8), idx)=sum_8;
	}
	{
		C((((bidy*32)+tidy)+9), idx)=sum_9;
	}
	{
		C((((bidy*32)+tidy)+10), idx)=sum_10;
	}
	{
		C((((bidy*32)+tidy)+11), idx)=sum_11;
	}
	{
		C((((bidy*32)+tidy)+12), idx)=sum_12;
	}
	{
		C((((bidy*32)+tidy)+13), idx)=sum_13;
	}
	{
		C((((bidy*32)+tidy)+14), idx)=sum_14;
	}
	{
		C((((bidy*32)+tidy)+15), idx)=sum_15;
	}
	{
		C((((bidy*32)+tidy)+16), idx)=sum_16;
	}
	{
		C((((bidy*32)+tidy)+17), idx)=sum_17;
	}
	{
		C((((bidy*32)+tidy)+18), idx)=sum_18;
	}
	{
		C((((bidy*32)+tidy)+19), idx)=sum_19;
	}
	{
		C((((bidy*32)+tidy)+20), idx)=sum_20;
	}
	{
		C((((bidy*32)+tidy)+21), idx)=sum_21;
	}
	{
		C((((bidy*32)+tidy)+22), idx)=sum_22;
	}
	{
		C((((bidy*32)+tidy)+23), idx)=sum_23;
	}
	{
		C((((bidy*32)+tidy)+24), idx)=sum_24;
	}
	{
		C((((bidy*32)+tidy)+25), idx)=sum_25;
	}
	{
		C((((bidy*32)+tidy)+26), idx)=sum_26;
	}
	{
		C((((bidy*32)+tidy)+27), idx)=sum_27;
	}
	{
		C((((bidy*32)+tidy)+28), idx)=sum_28;
	}
	{
		C((((bidy*32)+tidy)+29), idx)=sum_29;
	}
	{
		C((((bidy*32)+tidy)+30), idx)=sum_30;
	}
	{
		C((((bidy*32)+tidy)+31), idx)=sum_31;
	}
}

	.file	"tmpxft_002d8fb9_00000000-6_gcompiler_matmul_THREADBLOCK_X_8__THREAD_Y_32_.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii
	.type	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii, @function
_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6matmulPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii, .-_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii
	.globl	_Z6matmulPfS_S_ii
	.type	_Z6matmulPfS_S_ii, @function
_Z6matmulPfS_S_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z6matmulPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2033:
	.size	_Z6matmulPfS_S_ii, .-_Z6matmulPfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6matmulPfS_S_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6matmulPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#define bidx (blockIdx.x)
#define bidy (blockIdx.y)
#define tidx (threadIdx.x)
#define tidy (threadIdx.y)
#define gridDimX (gridDim.x)
#define gridDimY (gridDim.y)
#define COALESCED_NUM 16
#define blockDimX 128
#define blockDimY 1
#define idx (bidx*blockDimX+tidx)
#define idy (bidy*blockDimY+tidy)
#define merger_y 32
#define coalesced_idy (bidy/(COALESCED_NUM/(merger_y*blockDimY))*COALESCED_NUM)
#define A(y,x) A[(y)*WIDTH_A+(x)]
#define B(y,x) B[(y)*WIDTH_B+(x)]
#define C(y,x) C[(y)*WIDTH_C+(x)]
#define WIDTH_C 2048
#define WIDTH_B 2048
#define WIDTH_A 2048
__global__ void matmul(float * A, float * B, float * C, int width, int height)
{
	__shared__ float shared_0[16][33];
	int i;
	float sum_0;
	float sum_1;
	float sum_2;
	float sum_3;
	float sum_4;
	float sum_5;
	float sum_6;
	float sum_7;
	float sum_8;
	float sum_9;
	float sum_10;
	float sum_11;
	float sum_12;
	float sum_13;
	float sum_14;
	float sum_15;
	float sum_16;
	float sum_17;
	float sum_18;
	float sum_19;
	float sum_20;
	float sum_21;
	float sum_22;
	float sum_23;
	float sum_24;
	float sum_25;
	float sum_26;
	float sum_27;
	float sum_28;
	float sum_29;
	float sum_30;
	float sum_31;
	sum_0=0;
	sum_1=0;
	sum_2=0;
	sum_3=0;
	sum_4=0;
	sum_5=0;
	sum_6=0;
	sum_7=0;
	sum_8=0;
	sum_9=0;
	sum_10=0;
	sum_11=0;
	sum_12=0;
	sum_13=0;
	sum_14=0;
	sum_15=0;
	sum_16=0;
	sum_17=0;
	sum_18=0;
	sum_19=0;
	sum_20=0;
	sum_21=0;
	sum_22=0;
	sum_23=0;
	sum_24=0;
	sum_25=0;
	sum_26=0;
	sum_27=0;
	sum_28=0;
	sum_29=0;
	sum_30=0;
	sum_31=0;
	for (i=0; i<width; i=(i+16))
	{
		int it_1;
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+0), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+8), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+16), (i+(tidx%16)));
		shared_0[((tidx%16)+0)][(tidx/16)]=A(((((bidy*32)+tidy)+(tidx/16))+24), (i+(tidx%16)));
		__syncthreads();
		#pragma unroll 
		for (it_1=0; it_1<16; it_1=(it_1+1))
		{
			float a_0;
			float a_1;
			float a_2;
			float a_3;
			float a_4;
			float a_5;
			float a_6;
			float a_7;
			float a_8;
			float a_9;
			float a_10;
			float a_11;
			float a_12;
			float a_13;
			float a_14;
			float a_15;
			float a_16;
			float a_17;
			float a_18;
			float a_19;
			float a_20;
			float a_21;
			float a_22;
			float a_23;
			float a_24;
			float a_25;
			float a_26;
			float a_27;
			float a_28;
			float a_29;
			float a_30;
			float a_31;
			float b;
			a_0=shared_0[it_1][0];
			a_1=shared_0[it_1][1];
			a_2=shared_0[it_1][2];
			a_3=shared_0[it_1][3];
			a_4=shared_0[it_1][4];
			a_5=shared_0[it_1][5];
			a_6=shared_0[it_1][6];
			a_7=shared_0[it_1][7];
			a_8=shared_0[it_1][8];
			a_9=shared_0[it_1][9];
			a_10=shared_0[it_1][10];
			a_11=shared_0[it_1][11];
			a_12=shared_0[it_1][12];
			a_13=shared_0[it_1][13];
			a_14=shared_0[it_1][14];
			a_15=shared_0[it_1][15];
			a_16=shared_0[it_1][16];
			a_17=shared_0[it_1][17];
			a_18=shared_0[it_1][18];
			a_19=shared_0[it_1][19];
			a_20=shared_0[it_1][20];
			a_21=shared_0[it_1][21];
			a_22=shared_0[it_1][22];
			a_23=shared_0[it_1][23];
			a_24=shared_0[it_1][24];
			a_25=shared_0[it_1][25];
			a_26=shared_0[it_1][26];
			a_27=shared_0[it_1][27];
			a_28=shared_0[it_1][28];
			a_29=shared_0[it_1][29];
			a_30=shared_0[it_1][30];
			a_31=shared_0[it_1][31];
			b=B((it_1+i), idx);
			sum_0+=(a_0*b);
			sum_1+=(a_1*b);
			sum_2+=(a_2*b);
			sum_3+=(a_3*b);
			sum_4+=(a_4*b);
			sum_5+=(a_5*b);
			sum_6+=(a_6*b);
			sum_7+=(a_7*b);
			sum_8+=(a_8*b);
			sum_9+=(a_9*b);
			sum_10+=(a_10*b);
			sum_11+=(a_11*b);
			sum_12+=(a_12*b);
			sum_13+=(a_13*b);
			sum_14+=(a_14*b);
			sum_15+=(a_15*b);
			sum_16+=(a_16*b);
			sum_17+=(a_17*b);
			sum_18+=(a_18*b);
			sum_19+=(a_19*b);
			sum_20+=(a_20*b);
			sum_21+=(a_21*b);
			sum_22+=(a_22*b);
			sum_23+=(a_23*b);
			sum_24+=(a_24*b);
			sum_25+=(a_25*b);
			sum_26+=(a_26*b);
			sum_27+=(a_27*b);
			sum_28+=(a_28*b);
			sum_29+=(a_29*b);
			sum_30+=(a_30*b);
			sum_31+=(a_31*b);
		}
		__syncthreads();
	}
	{
		C((((bidy*32)+tidy)+0), idx)=sum_0;
	}
	{
		C((((bidy*32)+tidy)+1), idx)=sum_1;
	}
	{
		C((((bidy*32)+tidy)+2), idx)=sum_2;
	}
	{
		C((((bidy*32)+tidy)+3), idx)=sum_3;
	}
	{
		C((((bidy*32)+tidy)+4), idx)=sum_4;
	}
	{
		C((((bidy*32)+tidy)+5), idx)=sum_5;
	}
	{
		C((((bidy*32)+tidy)+6), idx)=sum_6;
	}
	{
		C((((bidy*32)+tidy)+7), idx)=sum_7;
	}
	{
		C((((bidy*32)+tidy)+8), idx)=sum_8;
	}
	{
		C((((bidy*32)+tidy)+9), idx)=sum_9;
	}
	{
		C((((bidy*32)+tidy)+10), idx)=sum_10;
	}
	{
		C((((bidy*32)+tidy)+11), idx)=sum_11;
	}
	{
		C((((bidy*32)+tidy)+12), idx)=sum_12;
	}
	{
		C((((bidy*32)+tidy)+13), idx)=sum_13;
	}
	{
		C((((bidy*32)+tidy)+14), idx)=sum_14;
	}
	{
		C((((bidy*32)+tidy)+15), idx)=sum_15;
	}
	{
		C((((bidy*32)+tidy)+16), idx)=sum_16;
	}
	{
		C((((bidy*32)+tidy)+17), idx)=sum_17;
	}
	{
		C((((bidy*32)+tidy)+18), idx)=sum_18;
	}
	{
		C((((bidy*32)+tidy)+19), idx)=sum_19;
	}
	{
		C((((bidy*32)+tidy)+20), idx)=sum_20;
	}
	{
		C((((bidy*32)+tidy)+21), idx)=sum_21;
	}
	{
		C((((bidy*32)+tidy)+22), idx)=sum_22;
	}
	{
		C((((bidy*32)+tidy)+23), idx)=sum_23;
	}
	{
		C((((bidy*32)+tidy)+24), idx)=sum_24;
	}
	{
		C((((bidy*32)+tidy)+25), idx)=sum_25;
	}
	{
		C((((bidy*32)+tidy)+26), idx)=sum_26;
	}
	{
		C((((bidy*32)+tidy)+27), idx)=sum_27;
	}
	{
		C((((bidy*32)+tidy)+28), idx)=sum_28;
	}
	{
		C((((bidy*32)+tidy)+29), idx)=sum_29;
	}
	{
		C((((bidy*32)+tidy)+30), idx)=sum_30;
	}
	{
		C((((bidy*32)+tidy)+31), idx)=sum_31;
	}
}

	.text
	.file	"gcompiler_matmul_THREADBLOCK_X_8__THREAD_Y_32_.hip"
	.globl	_Z21__device_stub__matmulPfS_S_ii # -- Begin function _Z21__device_stub__matmulPfS_S_ii
	.type	_Z21__device_stub__matmulPfS_S_ii,@function
_Z21__device_stub__matmulPfS_S_ii:      # @_Z21__device_stub__matmulPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6matmulPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__matmulPfS_S_ii, .Lfunc_end0-_Z21__device_stub__matmulPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6matmulPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6matmulPfS_S_ii,@object       # @_Z6matmulPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z6matmulPfS_S_ii
	.p2align	3, 0x0
_Z6matmulPfS_S_ii:
	.quad	_Z21__device_stub__matmulPfS_S_ii
	.size	_Z6matmulPfS_S_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6matmulPfS_S_ii"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__matmulPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6matmulPfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6matmulPfS_S_ii       ; -- Begin function _Z6matmulPfS_S_ii
	.globl	_Z6matmulPfS_S_ii
	.p2align	8
	.type	_Z6matmulPfS_S_ii,@function
_Z6matmulPfS_S_ii:                      ; @_Z6matmulPfS_S_ii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v35, v0, 10, 10
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v36, s14, 7, v2
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s2, 0
	s_cbranch_scc1 .LBB0_2
; %bb.1:                                ; %.._crit_edge_crit_edge
	v_bfe_u32 v1, v0, 10, 10
	v_lshl_add_u32 v0, s14, 7, v2
	s_mov_b32 s8, 0
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr8
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr0
.LBB0_3:                                ; %Flow577
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_7
; %bb.4:                                ; %.lr.ph
	v_lshrrev_b32_e32 v0, 4, v2
	s_lshl_b32 s3, s15, 5
	v_dual_mov_b32 v38, 0x3fc :: v_dual_and_b32 v1, 15, v2
	v_mov_b32_e32 v39, 0x404
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add3_u32 v2, s3, v35, v0
	v_dual_mov_b32 v37, 0 :: v_dual_lshlrev_b32 v0, 2, v0
	v_mov_b32_e32 v40, 0x40c
	v_dual_mov_b32 v41, 0x414 :: v_dual_mov_b32 v28, 0
	v_lshl_or_b32 v2, v2, 11, v1
	v_dual_mov_b32 v42, 0x4a4 :: v_dual_mov_b32 v27, 0
	v_dual_mov_b32 v43, 0x4ac :: v_dual_mov_b32 v30, 0
	v_dual_mov_b32 v44, 0x4b4 :: v_dual_mov_b32 v29, 0
	v_mad_u32_u24 v45, 0x84, v1, v0
	v_dual_mov_b32 v31, 0 :: v_dual_add_nc_u32 v46, 0xc000, v2
	v_dual_mov_b32 v47, 0x4bc :: v_dual_mov_b32 v32, 0
	v_dual_mov_b32 v48, 0x4c4 :: v_dual_mov_b32 v33, 0
	v_dual_mov_b32 v49, 0x4cc :: v_dual_mov_b32 v34, 0
	v_dual_mov_b32 v50, 0x4d4 :: v_dual_mov_b32 v19, 0
	v_dual_mov_b32 v51, 0x4dc :: v_dual_mov_b32 v20, 0
	v_dual_mov_b32 v52, 0x4e4 :: v_dual_mov_b32 v21, 0
	v_dual_mov_b32 v53, 0x4ec :: v_dual_mov_b32 v22, 0
	v_dual_mov_b32 v54, 0x4f4 :: v_dual_mov_b32 v23, 0
	v_dual_mov_b32 v55, 0x4fc :: v_dual_mov_b32 v24, 0
	v_dual_mov_b32 v56, 0x504 :: v_dual_mov_b32 v25, 0
	v_dual_mov_b32 v57, 0x50c :: v_dual_mov_b32 v26, 0
	v_dual_mov_b32 v58, 0x514 :: v_dual_mov_b32 v11, 0
	v_dual_mov_b32 v59, 0x51c :: v_dual_mov_b32 v12, 0
	v_dual_mov_b32 v60, 0x5ac :: v_dual_mov_b32 v13, 0
	v_dual_mov_b32 v61, 0x5b4 :: v_dual_mov_b32 v14, 0
	v_dual_mov_b32 v62, 0x5bc :: v_dual_mov_b32 v15, 0
	v_dual_mov_b32 v63, 0x5c4 :: v_dual_mov_b32 v16, 0
	v_dual_mov_b32 v64, 0x5cc :: v_dual_mov_b32 v17, 0
	v_dual_mov_b32 v65, 0x5d4 :: v_dual_mov_b32 v18, 0
	v_dual_mov_b32 v66, 0x5dc :: v_dual_mov_b32 v3, 0
	v_dual_mov_b32 v67, 0x5e4 :: v_dual_mov_b32 v4, 0
	v_dual_mov_b32 v68, 0x5ec :: v_dual_mov_b32 v5, 0
	v_dual_mov_b32 v69, 0x5f4 :: v_dual_mov_b32 v6, 0
	v_dual_mov_b32 v70, 0x5fc :: v_dual_mov_b32 v7, 0
	v_dual_mov_b32 v71, 0x604 :: v_dual_mov_b32 v8, 0
	v_dual_mov_b32 v72, 0x60c :: v_dual_mov_b32 v9, 0
	v_dual_mov_b32 v73, 0x614 :: v_dual_mov_b32 v10, 0
	v_mov_b32_e32 v74, 0x61c
	v_dual_mov_b32 v75, 0x624 :: v_dual_mov_b32 v2, 0
	v_mov_b32_e32 v76, 0x6b4
	v_mov_b32_e32 v77, 0x6bc
	v_mov_b32_e32 v78, 0x6c4
	v_mov_b32_e32 v79, 0x6cc
	v_mov_b32_e32 v80, 0x6d4
	v_mov_b32_e32 v81, 0x6dc
	v_mov_b32_e32 v82, 0x6e4
	v_mov_b32_e32 v83, 0x6ec
	v_mov_b32_e32 v84, 0x6f4
	v_mov_b32_e32 v85, 0x6fc
	v_mov_b32_e32 v86, 0x704
	v_mov_b32_e32 v87, 0x70c
	v_mov_b32_e32 v88, 0x714
	v_mov_b32_e32 v89, 0x71c
	v_mov_b32_e32 v90, 0x724
	v_mov_b32_e32 v91, 0x72c
	v_mov_b32_e32 v92, 0x7bc
	v_mov_b32_e32 v93, 0x7c4
	v_mov_b32_e32 v94, 0x7cc
	v_mov_b32_e32 v95, 0x7d4
	v_mov_b32_e32 v96, 0x7dc
	v_mov_b32_e32 v97, 0x7e4
	v_mov_b32_e32 v98, 0x7ec
	v_mov_b32_e32 v99, 0x7f4
	v_mov_b32_e32 v100, 0x7fc
	v_mov_b32_e32 v101, 0x804
	v_mov_b32_e32 v102, 0x80c
	v_mov_b32_e32 v103, 0x814
	v_mov_b32_e32 v104, 0x81c
	v_mov_b32_e32 v105, 0x824
	v_mov_b32_e32 v106, 0x82c
	v_mov_b32_e32 v107, 0x834
	v_add_nc_u32_e32 v0, 0x7800, v36
	s_mov_b32 s3, 0
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s3, v46
	s_add_i32 s3, s3, 16
	s_cmp_lt_i32 s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xffff8800, v0
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v108, vcc_lo, s4, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s5, v109, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v110, vcc_lo, s6, v110
	global_load_b32 v1, v[108:109], off
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	s_waitcnt vmcnt(0)
	ds_store_b32 v45, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	global_load_b32 v1, v[110:111], off
	ds_load_b128 v[108:111], v37
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	v_fmac_f32_e32 v29, v110, v1
	v_fmac_f32_e32 v30, v111, v1
	ds_load_b128 v[108:111], v37 offset:16
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	v_fmac_f32_e32 v33, v110, v1
	v_fmac_f32_e32 v34, v111, v1
	ds_load_b128 v[108:111], v37 offset:32
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	v_fmac_f32_e32 v21, v110, v1
	v_fmac_f32_e32 v22, v111, v1
	ds_load_b128 v[108:111], v37 offset:48
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	v_fmac_f32_e32 v25, v110, v1
	v_fmac_f32_e32 v26, v111, v1
	ds_load_b128 v[108:111], v37 offset:64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	v_fmac_f32_e32 v13, v110, v1
	v_fmac_f32_e32 v14, v111, v1
	ds_load_b128 v[108:111], v37 offset:80
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	v_fmac_f32_e32 v17, v110, v1
	v_fmac_f32_e32 v18, v111, v1
	ds_load_b128 v[108:111], v37 offset:96
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	v_fmac_f32_e32 v5, v110, v1
	v_fmac_f32_e32 v6, v111, v1
	ds_load_b128 v[108:111], v37 offset:112
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	v_fmac_f32_e32 v10, v110, v1
	v_fmac_f32_e32 v9, v111, v1
	v_add_nc_u32_e32 v1, 0xffff9000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xffff9800, v0
	v_add_co_u32 v108, vcc_lo, s6, v108
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	global_load_b32 v1, v[108:109], off
	v_add_co_u32 v110, vcc_lo, s6, v110
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	global_load_b32 v112, v[110:111], off
	ds_load_2addr_b32 v[108:109], v37 offset0:33 offset1:34
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:35 offset1:36
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	v_fmac_f32_e32 v30, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:33 offset1:34
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v112
	v_fmac_f32_e32 v28, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:37 offset1:38
	v_fmac_f32_e32 v29, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v30, v111, v112 :: v_dual_fmac_f32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:39 offset1:40
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v108, v1
	v_fmac_f32_e32 v34, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:35 offset1:36
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v112
	v_fmac_f32_e32 v32, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:41 offset1:42
	v_fmac_f32_e32 v33, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v34, v111, v112 :: v_dual_fmac_f32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:43 offset1:44
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v108, v1
	v_fmac_f32_e32 v22, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:37 offset1:38
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v112
	v_fmac_f32_e32 v20, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:45 offset1:46
	v_fmac_f32_e32 v21, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v22, v111, v112 :: v_dual_fmac_f32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:47 offset1:48
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v108, v1
	v_fmac_f32_e32 v26, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:39 offset1:40
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v112
	v_fmac_f32_e32 v24, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:49 offset1:50
	v_fmac_f32_e32 v25, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v26, v111, v112 :: v_dual_fmac_f32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:51 offset1:52
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v108, v1
	v_fmac_f32_e32 v14, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:41 offset1:42
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v112
	v_fmac_f32_e32 v12, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:53 offset1:54
	v_fmac_f32_e32 v13, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v14, v111, v112 :: v_dual_fmac_f32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:55 offset1:56
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v108, v1
	v_fmac_f32_e32 v18, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:43 offset1:44
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v112
	v_fmac_f32_e32 v16, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:57 offset1:58
	v_fmac_f32_e32 v17, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v18, v111, v112 :: v_dual_fmac_f32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:59 offset1:60
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v108, v1
	v_fmac_f32_e32 v6, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:45 offset1:46
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v112
	v_fmac_f32_e32 v4, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:61 offset1:62
	v_fmac_f32_e32 v5, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v111, v112 :: v_dual_fmac_f32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:63 offset1:64
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v108, v1
	v_fmac_f32_e32 v9, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:47 offset1:48
	v_add_nc_u32_e32 v1, 0xffffa000, v0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v112
	v_fmac_f32_e32 v8, v109, v112
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xffffa800, v0
	v_fmac_f32_e32 v10, v110, v112
	v_fmac_f32_e32 v9, v111, v112
	v_add_co_u32 v108, vcc_lo, s6, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	global_load_b32 v1, v[108:109], off
	v_add_co_u32 v110, vcc_lo, s6, v110
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	global_load_b32 v112, v[110:111], off
	ds_load_2addr_b32 v[108:109], v37 offset0:99 offset1:100
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:101 offset1:102
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	v_fmac_f32_e32 v30, v109, v1
	ds_load_b128 v[108:111], v37 offset:528
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v112
	v_fmac_f32_e32 v28, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:103 offset1:104
	v_fmac_f32_e32 v29, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v30, v111, v112 :: v_dual_fmac_f32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:105 offset1:106
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v108, v1
	v_fmac_f32_e32 v34, v109, v1
	ds_load_b128 v[108:111], v37 offset:544
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v112
	v_fmac_f32_e32 v32, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:107 offset1:108
	v_fmac_f32_e32 v33, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v34, v111, v112 :: v_dual_fmac_f32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:109 offset1:110
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v108, v1
	v_fmac_f32_e32 v22, v109, v1
	ds_load_b128 v[108:111], v37 offset:560
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v112
	v_fmac_f32_e32 v20, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:111 offset1:112
	v_fmac_f32_e32 v21, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v22, v111, v112 :: v_dual_fmac_f32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:113 offset1:114
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v108, v1
	v_fmac_f32_e32 v26, v109, v1
	ds_load_b128 v[108:111], v37 offset:576
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v112
	v_fmac_f32_e32 v24, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:115 offset1:116
	v_fmac_f32_e32 v25, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v26, v111, v112 :: v_dual_fmac_f32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:117 offset1:118
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v108, v1
	v_fmac_f32_e32 v14, v109, v1
	ds_load_b128 v[108:111], v37 offset:592
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v112
	v_fmac_f32_e32 v12, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:119 offset1:120
	v_fmac_f32_e32 v13, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v14, v111, v112 :: v_dual_fmac_f32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:121 offset1:122
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v108, v1
	v_fmac_f32_e32 v18, v109, v1
	ds_load_b128 v[108:111], v37 offset:608
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v112
	v_fmac_f32_e32 v16, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:123 offset1:124
	v_fmac_f32_e32 v17, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v18, v111, v112 :: v_dual_fmac_f32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:125 offset1:126
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v108, v1
	v_fmac_f32_e32 v6, v109, v1
	ds_load_b128 v[108:111], v37 offset:624
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v112
	v_fmac_f32_e32 v4, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:127 offset1:128
	v_fmac_f32_e32 v5, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v111, v112 :: v_dual_fmac_f32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:129 offset1:130
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v108, v1
	v_fmac_f32_e32 v9, v109, v1
	ds_load_b128 v[108:111], v37 offset:640
	v_add_nc_u32_e32 v1, 0xffffb000, v0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v112
	v_fmac_f32_e32 v8, v109, v112
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xffffb800, v0
	v_fmac_f32_e32 v10, v110, v112
	v_fmac_f32_e32 v9, v111, v112
	v_add_co_u32 v108, vcc_lo, s6, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	global_load_b32 v1, v[108:109], off
	ds_load_2addr_b32 v[108:109], v37 offset0:165 offset1:166
	v_add_co_u32 v110, vcc_lo, s6, v110
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:167 offset1:168
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	global_load_b32 v108, v[110:111], off
	v_fmac_f32_e32 v30, v109, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:99 offset1:100
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v109, v108
	v_fmac_f32_e32 v28, v110, v108
	ds_load_2addr_b32 v[109:110], v37 offset0:169 offset1:170
	v_fmac_f32_e32 v29, v111, v108
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v30, v112, v108 :: v_dual_fmac_f32 v31, v109, v1
	v_fmac_f32_e32 v32, v110, v1
	ds_load_2addr_b32 v[109:110], v37 offset0:171 offset1:172
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v109, v1
	v_fmac_f32_e32 v34, v110, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:101 offset1:102
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v34, v112, v108
	v_fmac_f32_e32 v31, v109, v108
	v_fmac_f32_e32 v32, v110, v108
	ds_load_2addr_b32 v[109:110], v37 offset0:173 offset1:174
	v_fmac_f32_e32 v33, v111, v108
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v109, v1
	v_fmac_f32_e32 v20, v110, v1
	ds_load_2addr_b32 v[109:110], v37 offset0:175 offset1:176
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v109, v1
	v_fmac_f32_e32 v22, v110, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:103 offset1:104
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v109, v108
	v_fmac_f32_e32 v20, v110, v108
	ds_load_2addr_b32 v[109:110], v37 offset0:177 offset1:178
	v_fmac_f32_e32 v21, v111, v108
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v22, v112, v108 :: v_dual_fmac_f32 v23, v109, v1
	v_fmac_f32_e32 v24, v110, v1
	ds_load_2addr_b32 v[109:110], v37 offset0:179 offset1:180
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v109, v1
	v_fmac_f32_e32 v26, v110, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:105 offset1:106
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v109, v108
	v_fmac_f32_e32 v24, v110, v108
	ds_load_2addr_b32 v[109:110], v37 offset0:181 offset1:182
	v_fmac_f32_e32 v25, v111, v108
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v26, v112, v108 :: v_dual_fmac_f32 v11, v109, v1
	v_fmac_f32_e32 v12, v110, v1
	ds_load_2addr_b32 v[109:110], v37 offset0:183 offset1:184
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v109, v1
	v_fmac_f32_e32 v14, v110, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:107 offset1:108
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v109, v108
	v_fmac_f32_e32 v12, v110, v108
	ds_load_2addr_b32 v[109:110], v37 offset0:185 offset1:186
	v_fmac_f32_e32 v13, v111, v108
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v14, v112, v108 :: v_dual_fmac_f32 v15, v109, v1
	v_fmac_f32_e32 v16, v110, v1
	ds_load_2addr_b32 v[109:110], v37 offset0:187 offset1:188
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v109, v1
	v_fmac_f32_e32 v18, v110, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:109 offset1:110
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v109, v108
	v_fmac_f32_e32 v16, v110, v108
	ds_load_2addr_b32 v[109:110], v37 offset0:189 offset1:190
	v_fmac_f32_e32 v17, v111, v108
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v18, v112, v108 :: v_dual_fmac_f32 v3, v109, v1
	v_fmac_f32_e32 v4, v110, v1
	ds_load_2addr_b32 v[109:110], v37 offset0:191 offset1:192
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v109, v1
	v_fmac_f32_e32 v6, v110, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:111 offset1:112
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v109, v108
	v_fmac_f32_e32 v4, v110, v108
	ds_load_2addr_b32 v[109:110], v37 offset0:193 offset1:194
	v_fmac_f32_e32 v5, v111, v108
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v112, v108 :: v_dual_fmac_f32 v7, v109, v1
	v_fmac_f32_e32 v8, v110, v1
	ds_load_2addr_b32 v[109:110], v37 offset0:195 offset1:196
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v109, v1
	v_fmac_f32_e32 v9, v110, v1
	ds_load_2addr_b64 v[109:112], v37 offset0:113 offset1:114
	v_add_nc_u32_e32 v1, 0xffffc000, v0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v109, v108
	v_fmac_f32_e32 v8, v110, v108
	v_fmac_f32_e32 v10, v111, v108
	v_fmac_f32_e32 v9, v112, v108
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xffffc800, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v108, vcc_lo, s6, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	global_load_b32 v1, v[108:109], off
	v_add_co_u32 v110, vcc_lo, s6, v110
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	global_load_b32 v112, v[110:111], off
	ds_load_2addr_b32 v[108:109], v37 offset0:231 offset1:232
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:233 offset1:234
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	v_fmac_f32_e32 v30, v109, v1
	ds_load_b128 v[108:111], v37 offset:1056
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v112
	v_fmac_f32_e32 v28, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:235 offset1:236
	v_fmac_f32_e32 v29, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v30, v111, v112 :: v_dual_fmac_f32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:237 offset1:238
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v108, v1
	v_fmac_f32_e32 v34, v109, v1
	ds_load_b128 v[108:111], v37 offset:1072
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v112
	v_fmac_f32_e32 v32, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:239 offset1:240
	v_fmac_f32_e32 v33, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v34, v111, v112 :: v_dual_fmac_f32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:241 offset1:242
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v108, v1
	v_fmac_f32_e32 v22, v109, v1
	ds_load_b128 v[108:111], v37 offset:1088
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v112
	v_fmac_f32_e32 v20, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:243 offset1:244
	v_fmac_f32_e32 v21, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v22, v111, v112 :: v_dual_fmac_f32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:245 offset1:246
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v108, v1
	v_fmac_f32_e32 v26, v109, v1
	ds_load_b128 v[108:111], v37 offset:1104
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v112
	v_fmac_f32_e32 v24, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:247 offset1:248
	v_fmac_f32_e32 v25, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v26, v111, v112 :: v_dual_fmac_f32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:249 offset1:250
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v108, v1
	v_fmac_f32_e32 v14, v109, v1
	ds_load_b128 v[108:111], v37 offset:1120
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v112
	v_fmac_f32_e32 v12, v109, v112
	ds_load_2addr_b32 v[108:109], v37 offset0:251 offset1:252
	v_fmac_f32_e32 v13, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v14, v111, v112 :: v_dual_fmac_f32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	ds_load_2addr_b32 v[108:109], v37 offset0:253 offset1:254
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v108, v1
	v_fmac_f32_e32 v18, v109, v1
	ds_load_b128 v[108:111], v37 offset:1136
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v112
	v_fmac_f32_e32 v16, v109, v112
	ds_load_2addr_b32 v[108:109], v38 offset1:1
	v_fmac_f32_e32 v17, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v18, v111, v112 :: v_dual_fmac_f32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	ds_load_2addr_b32 v[108:109], v39 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v108, v1
	v_fmac_f32_e32 v6, v109, v1
	ds_load_b128 v[108:111], v37 offset:1152
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v112
	v_fmac_f32_e32 v4, v109, v112
	ds_load_2addr_b32 v[108:109], v40 offset1:1
	v_fmac_f32_e32 v5, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v111, v112 :: v_dual_fmac_f32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	ds_load_2addr_b32 v[108:109], v41 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v108, v1
	v_fmac_f32_e32 v9, v109, v1
	ds_load_b128 v[108:111], v37 offset:1168
	v_add_nc_u32_e32 v1, 0xffffd000, v0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v112
	v_fmac_f32_e32 v8, v109, v112
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xffffd800, v0
	v_fmac_f32_e32 v10, v110, v112
	v_fmac_f32_e32 v9, v111, v112
	v_add_co_u32 v108, vcc_lo, s6, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	global_load_b32 v1, v[108:109], off
	v_add_co_u32 v110, vcc_lo, s6, v110
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	global_load_b32 v112, v[110:111], off
	ds_load_2addr_b32 v[108:109], v42 offset1:1
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v43 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	v_fmac_f32_e32 v30, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:165 offset1:166
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v112
	v_fmac_f32_e32 v28, v109, v112
	ds_load_2addr_b32 v[108:109], v44 offset1:1
	v_fmac_f32_e32 v29, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v30, v111, v112 :: v_dual_fmac_f32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	ds_load_2addr_b32 v[108:109], v47 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v108, v1
	v_fmac_f32_e32 v34, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:167 offset1:168
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v112
	v_fmac_f32_e32 v32, v109, v112
	ds_load_2addr_b32 v[108:109], v48 offset1:1
	v_fmac_f32_e32 v33, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v34, v111, v112 :: v_dual_fmac_f32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	ds_load_2addr_b32 v[108:109], v49 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v108, v1
	v_fmac_f32_e32 v22, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:169 offset1:170
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v112
	v_fmac_f32_e32 v20, v109, v112
	ds_load_2addr_b32 v[108:109], v50 offset1:1
	v_fmac_f32_e32 v21, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v22, v111, v112 :: v_dual_fmac_f32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	ds_load_2addr_b32 v[108:109], v51 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v108, v1
	v_fmac_f32_e32 v26, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:171 offset1:172
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v112
	v_fmac_f32_e32 v24, v109, v112
	ds_load_2addr_b32 v[108:109], v52 offset1:1
	v_fmac_f32_e32 v25, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v26, v111, v112 :: v_dual_fmac_f32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	ds_load_2addr_b32 v[108:109], v53 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v108, v1
	v_fmac_f32_e32 v14, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:173 offset1:174
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v112
	v_fmac_f32_e32 v12, v109, v112
	ds_load_2addr_b32 v[108:109], v54 offset1:1
	v_fmac_f32_e32 v13, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v14, v111, v112 :: v_dual_fmac_f32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	ds_load_2addr_b32 v[108:109], v55 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v108, v1
	v_fmac_f32_e32 v18, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:175 offset1:176
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v112
	v_fmac_f32_e32 v16, v109, v112
	ds_load_2addr_b32 v[108:109], v56 offset1:1
	v_fmac_f32_e32 v17, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v18, v111, v112 :: v_dual_fmac_f32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	ds_load_2addr_b32 v[108:109], v57 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v108, v1
	v_fmac_f32_e32 v6, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:177 offset1:178
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v112
	v_fmac_f32_e32 v4, v109, v112
	ds_load_2addr_b32 v[108:109], v58 offset1:1
	v_fmac_f32_e32 v5, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v111, v112 :: v_dual_fmac_f32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	ds_load_2addr_b32 v[108:109], v59 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v108, v1
	v_fmac_f32_e32 v9, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:179 offset1:180
	v_add_nc_u32_e32 v1, 0xffffe000, v0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v112
	v_fmac_f32_e32 v8, v109, v112
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xffffe800, v0
	v_fmac_f32_e32 v10, v110, v112
	v_fmac_f32_e32 v9, v111, v112
	v_add_co_u32 v108, vcc_lo, s6, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	global_load_b32 v1, v[108:109], off
	v_add_co_u32 v110, vcc_lo, s6, v110
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	global_load_b32 v112, v[110:111], off
	ds_load_2addr_b32 v[108:109], v60 offset1:1
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v61 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	v_fmac_f32_e32 v30, v109, v1
	ds_load_b128 v[108:111], v37 offset:1584
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v112
	v_fmac_f32_e32 v28, v109, v112
	ds_load_2addr_b32 v[108:109], v62 offset1:1
	v_fmac_f32_e32 v29, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v30, v111, v112 :: v_dual_fmac_f32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	ds_load_2addr_b32 v[108:109], v63 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v108, v1
	v_fmac_f32_e32 v34, v109, v1
	ds_load_b128 v[108:111], v37 offset:1600
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v112
	v_fmac_f32_e32 v32, v109, v112
	ds_load_2addr_b32 v[108:109], v64 offset1:1
	v_fmac_f32_e32 v33, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v34, v111, v112 :: v_dual_fmac_f32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	ds_load_2addr_b32 v[108:109], v65 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v108, v1
	v_fmac_f32_e32 v22, v109, v1
	ds_load_b128 v[108:111], v37 offset:1616
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v112
	v_fmac_f32_e32 v20, v109, v112
	ds_load_2addr_b32 v[108:109], v66 offset1:1
	v_fmac_f32_e32 v21, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v22, v111, v112 :: v_dual_fmac_f32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	ds_load_2addr_b32 v[108:109], v67 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v108, v1
	v_fmac_f32_e32 v26, v109, v1
	ds_load_b128 v[108:111], v37 offset:1632
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v112
	v_fmac_f32_e32 v24, v109, v112
	ds_load_2addr_b32 v[108:109], v68 offset1:1
	v_fmac_f32_e32 v25, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v26, v111, v112 :: v_dual_fmac_f32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	ds_load_2addr_b32 v[108:109], v69 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v108, v1
	v_fmac_f32_e32 v14, v109, v1
	ds_load_b128 v[108:111], v37 offset:1648
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v112
	v_fmac_f32_e32 v12, v109, v112
	ds_load_2addr_b32 v[108:109], v70 offset1:1
	v_fmac_f32_e32 v13, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v14, v111, v112 :: v_dual_fmac_f32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	ds_load_2addr_b32 v[108:109], v71 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v108, v1
	v_fmac_f32_e32 v18, v109, v1
	ds_load_b128 v[108:111], v37 offset:1664
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v112
	v_fmac_f32_e32 v16, v109, v112
	ds_load_2addr_b32 v[108:109], v72 offset1:1
	v_fmac_f32_e32 v17, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v18, v111, v112 :: v_dual_fmac_f32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	ds_load_2addr_b32 v[108:109], v73 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v108, v1
	v_fmac_f32_e32 v6, v109, v1
	ds_load_b128 v[108:111], v37 offset:1680
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v112
	v_fmac_f32_e32 v4, v109, v112
	ds_load_2addr_b32 v[108:109], v74 offset1:1
	v_fmac_f32_e32 v5, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v111, v112 :: v_dual_fmac_f32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	ds_load_2addr_b32 v[108:109], v75 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v108, v1
	v_fmac_f32_e32 v9, v109, v1
	ds_load_b128 v[108:111], v37 offset:1696
	v_add_nc_u32_e32 v1, 0xfffff000, v0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v112
	v_fmac_f32_e32 v8, v109, v112
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[108:109], 2, v[1:2]
	v_add_nc_u32_e32 v1, 0xfffff800, v0
	v_fmac_f32_e32 v10, v110, v112
	v_fmac_f32_e32 v9, v111, v112
	v_add_co_u32 v108, vcc_lo, s6, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	v_lshlrev_b64 v[110:111], 2, v[1:2]
	global_load_b32 v1, v[108:109], off
	v_add_co_u32 v110, vcc_lo, s6, v110
	v_add_co_ci_u32_e32 v111, vcc_lo, s7, v111, vcc_lo
	global_load_b32 v112, v[110:111], off
	ds_load_2addr_b32 v[108:109], v76 offset1:1
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v77 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	v_fmac_f32_e32 v30, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:231 offset1:232
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v112
	v_fmac_f32_e32 v28, v109, v112
	ds_load_2addr_b32 v[108:109], v78 offset1:1
	v_fmac_f32_e32 v29, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v30, v111, v112 :: v_dual_fmac_f32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	ds_load_2addr_b32 v[108:109], v79 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v108, v1
	v_fmac_f32_e32 v34, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:233 offset1:234
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v112
	v_fmac_f32_e32 v32, v109, v112
	ds_load_2addr_b32 v[108:109], v80 offset1:1
	v_fmac_f32_e32 v33, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v34, v111, v112 :: v_dual_fmac_f32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	ds_load_2addr_b32 v[108:109], v81 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v108, v1
	v_fmac_f32_e32 v22, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:235 offset1:236
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v112
	v_fmac_f32_e32 v20, v109, v112
	ds_load_2addr_b32 v[108:109], v82 offset1:1
	v_fmac_f32_e32 v21, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v22, v111, v112 :: v_dual_fmac_f32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	ds_load_2addr_b32 v[108:109], v83 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v108, v1
	v_fmac_f32_e32 v26, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:237 offset1:238
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v112
	v_fmac_f32_e32 v24, v109, v112
	ds_load_2addr_b32 v[108:109], v84 offset1:1
	v_fmac_f32_e32 v25, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v26, v111, v112 :: v_dual_fmac_f32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	ds_load_2addr_b32 v[108:109], v85 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v108, v1
	v_fmac_f32_e32 v14, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:239 offset1:240
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v112
	v_fmac_f32_e32 v12, v109, v112
	ds_load_2addr_b32 v[108:109], v86 offset1:1
	v_fmac_f32_e32 v13, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v14, v111, v112 :: v_dual_fmac_f32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	ds_load_2addr_b32 v[108:109], v87 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v108, v1
	v_fmac_f32_e32 v18, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:241 offset1:242
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v112
	v_fmac_f32_e32 v16, v109, v112
	ds_load_2addr_b32 v[108:109], v88 offset1:1
	v_fmac_f32_e32 v17, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v18, v111, v112 :: v_dual_fmac_f32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	ds_load_2addr_b32 v[108:109], v89 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v108, v1
	v_fmac_f32_e32 v6, v109, v1
	ds_load_2addr_b64 v[108:111], v37 offset0:243 offset1:244
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v112
	v_fmac_f32_e32 v4, v109, v112
	ds_load_2addr_b32 v[108:109], v90 offset1:1
	v_fmac_f32_e32 v5, v110, v112
	s_waitcnt lgkmcnt(0)
	v_dual_fmac_f32 v6, v111, v112 :: v_dual_fmac_f32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	ds_load_2addr_b32 v[108:109], v91 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v108, v1
	v_fmac_f32_e32 v9, v109, v1
	v_mov_b32_e32 v1, v2
	ds_load_2addr_b64 v[108:111], v37 offset0:245 offset1:246
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v112
	v_fmac_f32_e32 v8, v109, v112
	v_lshlrev_b64 v[108:109], 2, v[0:1]
	v_fmac_f32_e32 v10, v110, v112
	v_fmac_f32_e32 v9, v111, v112
	v_add_nc_u32_e32 v0, 0x8000, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v108, vcc_lo, s6, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, s7, v109, vcc_lo
	global_load_b32 v1, v[108:109], off
	ds_load_2addr_b32 v[108:109], v92 offset1:1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v27, v108, v1
	v_fmac_f32_e32 v28, v109, v1
	ds_load_2addr_b32 v[108:109], v93 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v29, v108, v1
	v_fmac_f32_e32 v30, v109, v1
	ds_load_2addr_b32 v[108:109], v94 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v31, v108, v1
	v_fmac_f32_e32 v32, v109, v1
	ds_load_2addr_b32 v[108:109], v95 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v33, v108, v1
	v_fmac_f32_e32 v34, v109, v1
	ds_load_2addr_b32 v[108:109], v96 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v19, v108, v1
	v_fmac_f32_e32 v20, v109, v1
	ds_load_2addr_b32 v[108:109], v97 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v21, v108, v1
	v_fmac_f32_e32 v22, v109, v1
	ds_load_2addr_b32 v[108:109], v98 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v23, v108, v1
	v_fmac_f32_e32 v24, v109, v1
	ds_load_2addr_b32 v[108:109], v99 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v25, v108, v1
	v_fmac_f32_e32 v26, v109, v1
	ds_load_2addr_b32 v[108:109], v100 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v11, v108, v1
	v_fmac_f32_e32 v12, v109, v1
	ds_load_2addr_b32 v[108:109], v101 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v13, v108, v1
	v_fmac_f32_e32 v14, v109, v1
	ds_load_2addr_b32 v[108:109], v102 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v15, v108, v1
	v_fmac_f32_e32 v16, v109, v1
	ds_load_2addr_b32 v[108:109], v103 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v17, v108, v1
	v_fmac_f32_e32 v18, v109, v1
	ds_load_2addr_b32 v[108:109], v104 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v3, v108, v1
	v_fmac_f32_e32 v4, v109, v1
	ds_load_2addr_b32 v[108:109], v105 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v108, v1
	v_fmac_f32_e32 v6, v109, v1
	ds_load_2addr_b32 v[108:109], v106 offset1:1
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v7, v108, v1
	v_fmac_f32_e32 v8, v109, v1
	ds_load_2addr_b32 v[108:109], v107 offset1:1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_fmac_f32_e32 v10, v108, v1
	v_fmac_f32_e32 v9, v109, v1
	s_cbranch_scc1 .LBB0_5
; %bb.6:                                ; %Flow
	v_dual_mov_b32 v1, v35 :: v_dual_mov_b32 v0, v36
	s_branch .LBB0_8
.LBB0_7:
	v_dual_mov_b32 v27, s8 :: v_dual_mov_b32 v28, s8
	v_dual_mov_b32 v29, s8 :: v_dual_mov_b32 v30, s8
	v_dual_mov_b32 v31, s8 :: v_dual_mov_b32 v32, s8
	v_dual_mov_b32 v33, s8 :: v_dual_mov_b32 v34, s8
	v_dual_mov_b32 v19, s8 :: v_dual_mov_b32 v20, s8
	v_dual_mov_b32 v21, s8 :: v_dual_mov_b32 v22, s8
	v_dual_mov_b32 v23, s8 :: v_dual_mov_b32 v24, s8
	v_dual_mov_b32 v25, s8 :: v_dual_mov_b32 v26, s8
	v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v12, s8
	v_dual_mov_b32 v13, s8 :: v_dual_mov_b32 v14, s8
	v_dual_mov_b32 v15, s8 :: v_dual_mov_b32 v16, s8
	v_dual_mov_b32 v17, s8 :: v_dual_mov_b32 v18, s8
	v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s8
	v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s8
	v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, s8
	v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v9, s8
.LBB0_8:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 11, v1
	s_lshl_b32 s2, s15, 16
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add3_u32 v0, s2, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v36, v1
	v_mov_b32_e32 v38, v1
	v_mov_b32_e32 v40, v1
	v_dual_mov_b32 v44, v1 :: v_dual_add_nc_u32 v39, 0x1800, v0
	v_add_nc_u32_e32 v35, 0x800, v0
	v_lshlrev_b64 v[41:42], 2, v[0:1]
	v_add_nc_u32_e32 v37, 0x1000, v0
	v_add_nc_u32_e32 v43, 0x2000, v0
	v_lshlrev_b64 v[39:40], 2, v[39:40]
	v_lshlrev_b64 v[35:36], 2, v[35:36]
	v_dual_mov_b32 v46, v1 :: v_dual_add_nc_u32 v45, 0x2800, v0
	v_lshlrev_b64 v[37:38], 2, v[37:38]
	v_add_co_u32 v41, vcc_lo, s0, v41
	v_add_co_ci_u32_e32 v42, vcc_lo, s1, v42, vcc_lo
	v_add_co_u32 v35, vcc_lo, s0, v35
	v_add_co_ci_u32_e32 v36, vcc_lo, s1, v36, vcc_lo
	v_add_co_u32 v37, vcc_lo, s0, v37
	v_lshlrev_b64 v[43:44], 2, v[43:44]
	v_dual_mov_b32 v48, v1 :: v_dual_add_nc_u32 v47, 0x3000, v0
	v_add_co_ci_u32_e32 v38, vcc_lo, s1, v38, vcc_lo
	v_add_co_u32 v39, vcc_lo, s0, v39
	v_lshlrev_b64 v[45:46], 2, v[45:46]
	v_dual_mov_b32 v50, v1 :: v_dual_add_nc_u32 v49, 0x3800, v0
	v_add_co_ci_u32_e32 v40, vcc_lo, s1, v40, vcc_lo
	v_add_co_u32 v43, vcc_lo, s0, v43
	v_lshlrev_b64 v[47:48], 2, v[47:48]
	v_add_co_ci_u32_e32 v44, vcc_lo, s1, v44, vcc_lo
	v_add_co_u32 v45, vcc_lo, s0, v45
	v_lshlrev_b64 v[49:50], 2, v[49:50]
	v_add_co_ci_u32_e32 v46, vcc_lo, s1, v46, vcc_lo
	v_dual_mov_b32 v52, v1 :: v_dual_add_nc_u32 v51, 0x4000, v0
	v_add_co_u32 v47, vcc_lo, s0, v47
	v_add_co_ci_u32_e32 v48, vcc_lo, s1, v48, vcc_lo
	v_dual_mov_b32 v54, v1 :: v_dual_add_nc_u32 v53, 0x4800, v0
	v_add_co_u32 v49, vcc_lo, s0, v49
	v_lshlrev_b64 v[51:52], 2, v[51:52]
	v_add_co_ci_u32_e32 v50, vcc_lo, s1, v50, vcc_lo
	s_clause 0x7
	global_store_b32 v[41:42], v27, off
	global_store_b32 v[35:36], v28, off
	global_store_b32 v[37:38], v29, off
	global_store_b32 v[39:40], v30, off
	global_store_b32 v[43:44], v31, off
	global_store_b32 v[45:46], v32, off
	global_store_b32 v[47:48], v33, off
	global_store_b32 v[49:50], v34, off
	v_dual_mov_b32 v30, v1 :: v_dual_add_nc_u32 v29, 0x5000, v0
	v_lshlrev_b64 v[27:28], 2, v[53:54]
	v_dual_mov_b32 v34, v1 :: v_dual_add_nc_u32 v33, 0x5800, v0
	v_add_co_u32 v31, vcc_lo, s0, v51
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_dual_mov_b32 v36, v1 :: v_dual_add_nc_u32 v35, 0x6000, v0
	v_add_co_ci_u32_e32 v32, vcc_lo, s1, v52, vcc_lo
	v_add_co_u32 v27, vcc_lo, s0, v27
	v_lshlrev_b64 v[33:34], 2, v[33:34]
	v_dual_mov_b32 v38, v1 :: v_dual_add_nc_u32 v37, 0x6800, v0
	v_add_co_ci_u32_e32 v28, vcc_lo, s1, v28, vcc_lo
	v_add_co_u32 v29, vcc_lo, s0, v29
	v_lshlrev_b64 v[35:36], 2, v[35:36]
	v_dual_mov_b32 v40, v1 :: v_dual_add_nc_u32 v39, 0x7000, v0
	v_add_co_ci_u32_e32 v30, vcc_lo, s1, v30, vcc_lo
	v_add_co_u32 v33, vcc_lo, s0, v33
	v_lshlrev_b64 v[37:38], 2, v[37:38]
	v_dual_mov_b32 v42, v1 :: v_dual_add_nc_u32 v41, 0x7800, v0
	v_add_co_ci_u32_e32 v34, vcc_lo, s1, v34, vcc_lo
	v_add_co_u32 v35, vcc_lo, s0, v35
	v_lshlrev_b64 v[39:40], 2, v[39:40]
	v_add_co_ci_u32_e32 v36, vcc_lo, s1, v36, vcc_lo
	v_add_co_u32 v37, vcc_lo, s0, v37
	v_lshlrev_b64 v[41:42], 2, v[41:42]
	v_add_co_ci_u32_e32 v38, vcc_lo, s1, v38, vcc_lo
	v_dual_mov_b32 v44, v1 :: v_dual_add_nc_u32 v43, 0x8000, v0
	v_add_co_u32 v39, vcc_lo, s0, v39
	v_add_co_ci_u32_e32 v40, vcc_lo, s1, v40, vcc_lo
	v_dual_mov_b32 v46, v1 :: v_dual_add_nc_u32 v45, 0x8800, v0
	v_add_co_u32 v41, vcc_lo, s0, v41
	v_lshlrev_b64 v[43:44], 2, v[43:44]
	v_add_co_ci_u32_e32 v42, vcc_lo, s1, v42, vcc_lo
	s_clause 0x7
	global_store_b32 v[31:32], v19, off
	global_store_b32 v[27:28], v20, off
	global_store_b32 v[29:30], v21, off
	global_store_b32 v[33:34], v22, off
	global_store_b32 v[35:36], v23, off
	global_store_b32 v[37:38], v24, off
	global_store_b32 v[39:40], v25, off
	global_store_b32 v[41:42], v26, off
	v_dual_mov_b32 v22, v1 :: v_dual_add_nc_u32 v21, 0x9000, v0
	v_lshlrev_b64 v[19:20], 2, v[45:46]
	v_dual_mov_b32 v26, v1 :: v_dual_add_nc_u32 v25, 0x9800, v0
	v_add_co_u32 v23, vcc_lo, s0, v43
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	v_dual_mov_b32 v28, v1 :: v_dual_add_nc_u32 v27, 0xa000, v0
	v_add_co_ci_u32_e32 v24, vcc_lo, s1, v44, vcc_lo
	v_add_co_u32 v19, vcc_lo, s0, v19
	v_lshlrev_b64 v[25:26], 2, v[25:26]
	v_dual_mov_b32 v30, v1 :: v_dual_add_nc_u32 v29, 0xa800, v0
	v_add_co_ci_u32_e32 v20, vcc_lo, s1, v20, vcc_lo
	v_add_co_u32 v21, vcc_lo, s0, v21
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	v_dual_mov_b32 v32, v1 :: v_dual_add_nc_u32 v31, 0xb000, v0
	v_add_co_ci_u32_e32 v22, vcc_lo, s1, v22, vcc_lo
	v_add_co_u32 v25, vcc_lo, s0, v25
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_dual_mov_b32 v34, v1 :: v_dual_add_nc_u32 v33, 0xb800, v0
	v_add_co_ci_u32_e32 v26, vcc_lo, s1, v26, vcc_lo
	v_add_co_u32 v27, vcc_lo, s0, v27
	v_lshlrev_b64 v[31:32], 2, v[31:32]
	v_add_co_ci_u32_e32 v28, vcc_lo, s1, v28, vcc_lo
	v_add_co_u32 v29, vcc_lo, s0, v29
	v_lshlrev_b64 v[33:34], 2, v[33:34]
	v_add_co_ci_u32_e32 v30, vcc_lo, s1, v30, vcc_lo
	v_dual_mov_b32 v36, v1 :: v_dual_add_nc_u32 v35, 0xc000, v0
	v_add_co_u32 v31, vcc_lo, s0, v31
	v_add_co_ci_u32_e32 v32, vcc_lo, s1, v32, vcc_lo
	v_dual_mov_b32 v38, v1 :: v_dual_add_nc_u32 v37, 0xc800, v0
	v_add_co_u32 v33, vcc_lo, s0, v33
	v_lshlrev_b64 v[35:36], 2, v[35:36]
	v_add_co_ci_u32_e32 v34, vcc_lo, s1, v34, vcc_lo
	s_clause 0x7
	global_store_b32 v[23:24], v11, off
	global_store_b32 v[19:20], v12, off
	global_store_b32 v[21:22], v13, off
	global_store_b32 v[25:26], v14, off
	global_store_b32 v[27:28], v15, off
	global_store_b32 v[29:30], v16, off
	global_store_b32 v[31:32], v17, off
	global_store_b32 v[33:34], v18, off
	v_dual_mov_b32 v14, v1 :: v_dual_add_nc_u32 v13, 0xd000, v0
	v_lshlrev_b64 v[11:12], 2, v[37:38]
	v_dual_mov_b32 v18, v1 :: v_dual_add_nc_u32 v17, 0xd800, v0
	v_add_co_u32 v15, vcc_lo, s0, v35
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_dual_mov_b32 v20, v1 :: v_dual_add_nc_u32 v19, 0xe000, v0
	v_add_co_ci_u32_e32 v16, vcc_lo, s1, v36, vcc_lo
	v_add_co_u32 v11, vcc_lo, s0, v11
	v_lshlrev_b64 v[17:18], 2, v[17:18]
	v_dual_mov_b32 v22, v1 :: v_dual_add_nc_u32 v21, 0xe800, v0
	v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
	v_add_co_u32 v13, vcc_lo, s0, v13
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	v_dual_mov_b32 v24, v1 :: v_dual_add_nc_u32 v23, 0xf000, v0
	v_add_co_ci_u32_e32 v14, vcc_lo, s1, v14, vcc_lo
	v_add_co_u32 v17, vcc_lo, s0, v17
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	v_add_nc_u32_e32 v0, 0xf800, v0
	v_add_co_ci_u32_e32 v18, vcc_lo, s1, v18, vcc_lo
	v_add_co_u32 v19, vcc_lo, s0, v19
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_ci_u32_e32 v20, vcc_lo, s1, v20, vcc_lo
	v_add_co_u32 v21, vcc_lo, s0, v21
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_ci_u32_e32 v22, vcc_lo, s1, v22, vcc_lo
	v_add_co_u32 v23, vcc_lo, s0, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s1, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_clause 0x7
	global_store_b32 v[15:16], v3, off
	global_store_b32 v[11:12], v4, off
	global_store_b32 v[13:14], v5, off
	global_store_b32 v[17:18], v6, off
	global_store_b32 v[19:20], v7, off
	global_store_b32 v[21:22], v8, off
	global_store_b32 v[23:24], v10, off
	global_store_b32 v[0:1], v9, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6matmulPfS_S_ii
		.amdhsa_group_segment_fixed_size 2112
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 113
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6matmulPfS_S_ii, .Lfunc_end0-_Z6matmulPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7412
; NumSgprs: 18
; NumVgprs: 113
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2112 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 14
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 113
; Occupancy: 12
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2112
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6matmulPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6matmulPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     113
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
