#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	cudaError_t error = cudaGetLastError ();
	if (error != cudaSuccess) {
		printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
		exit(-1);
	}
}

__global__ void hypterm (double * __restrict__ flux_in_0, double * __restrict__ flux_in_1, double * __restrict__ flux_in_2, double * __restrict__ flux_in_3, double * __restrict__ flux_in_4, double * __restrict__ cons_in_1, double * __restrict__ cons_in_2, double * __restrict__ cons_in_3, double * __restrict__ cons_in_4, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.z);

	double (*flux_0)[308][308] = (double (*)[308][308])flux_in_0;
	double (*flux_1)[308][308] = (double (*)[308][308])flux_in_1;
	double (*flux_2)[308][308] = (double (*)[308][308])flux_in_2;
	double (*flux_3)[308][308] = (double (*)[308][308])flux_in_3;
	double (*flux_4)[308][308] = (double (*)[308][308])flux_in_4;
	double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
	double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
	double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
	double (*q_4)[308][308] = (double (*)[308][308])q_in_4;
	double (*cons_1)[308][308] = (double (*)[308][308])cons_in_1;
	double (*cons_2)[308][308] = (double (*)[308][308])cons_in_2;
	double (*cons_3)[308][308] = (double (*)[308][308])cons_in_3;
	double (*cons_4)[308][308] = (double (*)[308][308])cons_in_4;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
double _t_1_ = cons_1[k][j][i+1];
_t_1_ -= cons_1[k][j][i-1];
double flux_0kc0jc0ic0 = dxinv0 * 0.8 * _t_1_;
double _t_2_ = cons_1[k][j][i+2];
_t_2_ -= cons_1[k][j][i-2];
flux_0kc0jc0ic0 -= dxinv0 * 0.2 * _t_2_;
double _t_3_ = cons_1[k][j][i+3];
_t_3_ -= cons_1[k][j][i-3];
flux_0kc0jc0ic0 += dxinv0 * 0.038 * _t_3_;
double _t_4_ = cons_1[k][j][i+4];
_t_4_ -= cons_1[k][j][i-4];
flux_0kc0jc0ic0 -= dxinv0 * 0.0035 * _t_4_;

double _t_6_ = cons_1[k][j][i+1] * q_1[k][j][i+1];
_t_6_ -= cons_1[k][j][i-1] * q_1[k][j][i-1];
_t_6_ += q_4[k][j][i+1];
_t_6_ -= q_4[k][j][i-1];
double flux_1kc0jc0ic0 = dxinv0 * 0.8 * _t_6_;
double _t_7_ = cons_1[k][j][i+2] * q_1[k][j][i+2];
_t_7_ -= cons_1[k][j][i-2] * q_1[k][j][i-2];
_t_7_ += q_4[k][j][i+2];
_t_7_ -= q_4[k][j][i-2];
flux_1kc0jc0ic0 -= dxinv0 * 0.2 * _t_7_;
double _t_8_ = cons_1[k][j][i+3] * q_1[k][j][i+3];
_t_8_ -= cons_1[k][j][i-3] * q_1[k][j][i-3];
_t_8_ += q_4[k][j][i+3];
_t_8_ -= q_4[k][j][i-3];
flux_1kc0jc0ic0 += dxinv0 * 0.038 * _t_8_;
double _t_9_ = cons_1[k][j][i+4] * q_1[k][j][i+4];
_t_9_ -= cons_1[k][j][i-4] * q_1[k][j][i-4];
_t_9_ += q_4[k][j][i+4];
_t_9_ -= q_4[k][j][i-4];
flux_1kc0jc0ic0 -= dxinv0 * 0.0035 * _t_9_;

double _t_11_ = cons_2[k][j][i+1] * q_1[k][j][i+1];
_t_11_ -= cons_2[k][j][i-1] * q_1[k][j][i-1];
double flux_2kc0jc0ic0 = dxinv0 * 0.8 * _t_11_;
double _t_12_ = cons_2[k][j][i+2] * q_1[k][j][i+2];
_t_12_ -= cons_2[k][j][i-2] * q_1[k][j][i-2];
flux_2kc0jc0ic0 -= dxinv0 * 0.2 * _t_12_;
double _t_13_ = cons_2[k][j][i+3] * q_1[k][j][i+3];
_t_13_ -= cons_2[k][j][i-3] * q_1[k][j][i-3];
flux_2kc0jc0ic0 += dxinv0 * 0.038 * _t_13_;
double _t_14_ = cons_2[k][j][i+4] * q_1[k][j][i+4];
_t_14_ -= cons_2[k][j][i-4] * q_1[k][j][i-4];
flux_2kc0jc0ic0 -= dxinv0 * 0.0035 * _t_14_;

double _t_16_ = cons_3[k][j][i+1] * q_1[k][j][i+1];
_t_16_ -= cons_3[k][j][i-1] * q_1[k][j][i-1];
double flux_3kc0jc0ic0 = dxinv0 * 0.8 * _t_16_;
double _t_17_ = cons_3[k][j][i+2] * q_1[k][j][i+2];
_t_17_ -= cons_3[k][j][i-2] * q_1[k][j][i-2];
flux_3kc0jc0ic0 -= dxinv0 * 0.2 * _t_17_;
double _t_18_ = cons_3[k][j][i+3] * q_1[k][j][i+3];
_t_18_ -= cons_3[k][j][i-3] * q_1[k][j][i-3];
flux_3kc0jc0ic0 += dxinv0 * 0.038 * _t_18_;
double _t_19_ = cons_3[k][j][i+4] * q_1[k][j][i+4];
_t_19_ -= cons_3[k][j][i-4] * q_1[k][j][i-4];
flux_3kc0jc0ic0 -= dxinv0 * 0.0035 * _t_19_;

double _t_21_ = q_4[k][j][i+1] * q_1[k][j][i+1];
double _v_24_ = cons_4[k][j][i+1] * q_1[k][j][i+1];
_t_21_ += _v_24_;
_t_21_ -= cons_4[k][j][i-1] * q_1[k][j][i-1];
double _v_27_ = q_4[k][j][i-1] * q_1[k][j][i-1];
_t_21_ -= _v_27_;
double flux_4kc0jc0ic0 = dxinv0 * 0.8 * _t_21_;
double _t_22_ = q_4[k][j][i+2] * q_1[k][j][i+2];
double _v_28_ = cons_4[k][j][i+2] * q_1[k][j][i+2];
_t_22_ += _v_28_;
_t_22_ -= cons_4[k][j][i-2] * q_1[k][j][i-2];
double _v_31_ = q_4[k][j][i-2] * q_1[k][j][i-2];
_t_22_ -= _v_31_;
flux_4kc0jc0ic0 -= dxinv0 * 0.2 * _t_22_;
double _t_23_ = q_4[k][j][i+3] * q_1[k][j][i+3];
double _v_32_ = cons_4[k][j][i+3] * q_1[k][j][i+3];
_t_23_ += _v_32_;
_t_23_ -= cons_4[k][j][i-3] * q_1[k][j][i-3];
double _v_35_ = q_4[k][j][i-3] * q_1[k][j][i-3];
_t_23_ -= _v_35_;
flux_4kc0jc0ic0 += dxinv0 * 0.038 * _t_23_;
double _t_24_ = q_4[k][j][i+4] * q_1[k][j][i+4];
double _v_36_ = cons_4[k][j][i+4] * q_1[k][j][i+4];
_t_24_ += _v_36_;
_t_24_ -= cons_4[k][j][i-4] * q_1[k][j][i-4];
double _v_39_ = q_4[k][j][i-4] * q_1[k][j][i-4];
_t_24_ -= _v_39_;
flux_4kc0jc0ic0 -= dxinv0 * 0.0035 * _t_24_;

double _t_27_ = cons_2[k][j+1][i];
_t_27_ -= cons_2[k][j-1][i];
double _t_25_ = dxinv1 * 0.8 * _t_27_;
double _t_28_ = cons_2[k][j+2][i];
_t_28_ -= cons_2[k][j-2][i];
_t_25_ -= dxinv1 * 0.2 * _t_28_;
double _t_29_ = cons_2[k][j+3][i];
_t_29_ -= cons_2[k][j-3][i];
_t_25_ += dxinv1 * 0.038 * _t_29_;
double _t_30_ = cons_2[k][j+4][i];
_t_30_ -= cons_2[k][j-4][i];
_t_25_ -= dxinv1 * 0.0035 * _t_30_;
flux_0kc0jc0ic0 -= _t_25_;

double _t_33_ = cons_1[k][j+1][i] * q_2[k][j+1][i];
_t_33_ -= cons_1[k][j-1][i] * q_2[k][j-1][i];
double _t_31_ = dxinv1 * 0.8 * _t_33_;
double _t_34_ = cons_1[k][j+2][i] * q_2[k][j+2][i];
_t_34_ -= cons_1[k][j-2][i] * q_2[k][j-2][i];
_t_31_ -= dxinv1 * 0.2 * _t_34_;
double _t_35_ = cons_1[k][j+3][i] * q_2[k][j+3][i];
_t_35_ -= cons_1[k][j-3][i] * q_2[k][j-3][i];
_t_31_ += dxinv1 * 0.038 * _t_35_;
double _t_36_ = cons_1[k][j+4][i] * q_2[k][j+4][i];
_t_36_ -= cons_1[k][j-4][i] * q_2[k][j-4][i];
_t_31_ -= dxinv1 * 0.0035 * _t_36_;
flux_1kc0jc0ic0 -= _t_31_;

double _t_39_ = cons_2[k][j+1][i] * q_2[k][j+1][i];
_t_39_ -= cons_2[k][j-1][i] * q_2[k][j-1][i];
_t_39_ += q_4[k][j+1][i];
_t_39_ -= q_4[k][j-1][i];
double _t_37_ = dxinv1 * 0.8 * _t_39_;
double _t_40_ = cons_2[k][j+2][i] * q_2[k][j+2][i];
_t_40_ -= cons_2[k][j-2][i] * q_2[k][j-2][i];
_t_40_ += q_4[k][j+2][i];
_t_40_ -= q_4[k][j-2][i];
_t_37_ -= dxinv1 * 0.2 * _t_40_;
double _t_41_ = cons_2[k][j+3][i] * q_2[k][j+3][i];
_t_41_ -= cons_2[k][j-3][i] * q_2[k][j-3][i];
_t_41_ += q_4[k][j+3][i];
_t_41_ -= q_4[k][j-3][i];
_t_37_ += dxinv1 * 0.038 * _t_41_;
double _t_42_ = cons_2[k][j+4][i] * q_2[k][j+4][i];
_t_42_ -= cons_2[k][j-4][i] * q_2[k][j-4][i];
_t_42_ += q_4[k][j+4][i];
_t_42_ -= q_4[k][j-4][i];
_t_37_ -= dxinv1 * 0.0035 * _t_42_;
flux_2kc0jc0ic0 -= _t_37_;

double _t_45_ = cons_3[k][j+1][i] * q_2[k][j+1][i];
_t_45_ -= cons_3[k][j-1][i] * q_2[k][j-1][i];
double _t_43_ = dxinv1 * 0.8 * _t_45_;
double _t_46_ = cons_3[k][j+2][i] * q_2[k][j+2][i];
_t_46_ -= cons_3[k][j-2][i] * q_2[k][j-2][i];
_t_43_ -= dxinv1 * 0.2 * _t_46_;
double _t_47_ = cons_3[k][j+3][i] * q_2[k][j+3][i];
_t_47_ -= cons_3[k][j-3][i] * q_2[k][j-3][i];
_t_43_ += dxinv1 * 0.038 * _t_47_;
double _t_48_ = cons_3[k][j+4][i] * q_2[k][j+4][i];
_t_48_ -= cons_3[k][j-4][i] * q_2[k][j-4][i];
_t_43_ -= dxinv1 * 0.0035 * _t_48_;
flux_3kc0jc0ic0 -= _t_43_;

double _t_51_ = q_4[k][j+1][i] * q_2[k][j+1][i];
double _v_64_ = cons_4[k][j+1][i] * q_2[k][j+1][i];
_t_51_ += _v_64_;
_t_51_ -= cons_4[k][j-1][i] * q_2[k][j-1][i];
double _v_67_ = q_4[k][j-1][i] * q_2[k][j-1][i];
_t_51_ -= _v_67_;
double _t_49_ = dxinv1 * 0.8 * _t_51_;
double _t_52_ = q_4[k][j+2][i] * q_2[k][j+2][i];
double _v_68_ = cons_4[k][j+2][i] * q_2[k][j+2][i];
_t_52_ += _v_68_;
_t_52_ -= cons_4[k][j-2][i] * q_2[k][j-2][i];
double _v_71_ = q_4[k][j-2][i] * q_2[k][j-2][i];
_t_52_ -= _v_71_;
_t_49_ -= dxinv1 * 0.2 * _t_52_;
double _t_53_ = q_4[k][j+3][i] * q_2[k][j+3][i];
double _v_72_ = cons_4[k][j+3][i] * q_2[k][j+3][i];
_t_53_ += _v_72_;
_t_53_ -= cons_4[k][j-3][i] * q_2[k][j-3][i];
double _v_75_ = q_4[k][j-3][i] * q_2[k][j-3][i];
_t_53_ -= _v_75_;
_t_49_ += dxinv1 * 0.038 * _t_53_;
double _t_54_ = q_4[k][j+4][i] * q_2[k][j+4][i];
double _v_76_ = cons_4[k][j+4][i] * q_2[k][j+4][i];
_t_54_ += _v_76_;
_t_54_ -= cons_4[k][j-4][i] * q_2[k][j-4][i];
double _v_79_ = q_4[k][j-4][i] * q_2[k][j-4][i];
_t_54_ -= _v_79_;
_t_49_ -= dxinv1 * 0.0035 * _t_54_;
flux_4kc0jc0ic0 -= _t_49_;

double _t_57_ = cons_3[k+1][j][i];
_t_57_ -= cons_3[k-1][j][i];
double _t_55_ = dxinv2 * 0.8 * _t_57_;
double _t_58_ = cons_3[k+2][j][i];
_t_58_ -= cons_3[k-2][j][i];
_t_55_ -= dxinv2 * 0.2 * _t_58_;
double _t_59_ = cons_3[k+3][j][i];
_t_59_ -= cons_3[k-3][j][i];
_t_55_ += dxinv2 * 0.038 * _t_59_;
double _t_60_ = cons_3[k+4][j][i];
_t_60_ -= cons_3[k-4][j][i];
_t_55_ -= dxinv2 * 0.0035 * _t_60_;
flux_0kc0jc0ic0 -= _t_55_;

double _t_63_ = cons_1[k+1][j][i] * q_3[k+1][j][i];
_t_63_ -= cons_1[k-1][j][i] * q_3[k-1][j][i];
double _t_61_ = dxinv2 * 0.8 * _t_63_;
double _t_64_ = cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_64_ -= cons_1[k-2][j][i] * q_3[k-2][j][i];
_t_61_ -= dxinv2 * 0.2 * _t_64_;
double _t_65_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_65_ -= cons_1[k-3][j][i] * q_3[k-3][j][i];
_t_61_ += dxinv2 * 0.038 * _t_65_;
double _t_66_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_66_ -= cons_1[k-4][j][i] * q_3[k-4][j][i];
_t_61_ -= dxinv2 * 0.0035 * _t_66_;
flux_1kc0jc0ic0 -= _t_61_;

double _t_69_ = cons_2[k+1][j][i] * q_3[k+1][j][i];
_t_69_ -= cons_2[k-1][j][i] * q_3[k-1][j][i];
double _t_67_ = dxinv2 * 0.8 * _t_69_;
double _t_70_ = cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_70_ -= cons_2[k-2][j][i] * q_3[k-2][j][i];
_t_67_ -= dxinv2 * 0.2 * _t_70_;
double _t_71_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_71_ -= cons_2[k-3][j][i] * q_3[k-3][j][i];
_t_67_ += dxinv2 * 0.038 * _t_71_;
double _t_72_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_72_ -= cons_2[k-4][j][i] * q_3[k-4][j][i];
_t_67_ -= dxinv2 * 0.0035 * _t_72_;
flux_2kc0jc0ic0 -= _t_67_;

double _t_75_ = cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_75_ -= cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_75_ += q_4[k+1][j][i];
_t_75_ -= q_4[k-1][j][i];
double _t_73_ = dxinv2 * 0.8 * _t_75_;
double _t_76_ = cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_76_ -= cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_76_ += q_4[k+2][j][i];
_t_76_ -= q_4[k-2][j][i];
_t_73_ -= dxinv2 * 0.2 * _t_76_;
double _t_77_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_77_ -= cons_3[k-3][j][i] * q_3[k-3][j][i];
_t_77_ += q_4[k+3][j][i];
_t_77_ -= q_4[k-3][j][i];
_t_73_ += dxinv2 * 0.038 * _t_77_;
double _t_78_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_78_ -= cons_3[k-4][j][i] * q_3[k-4][j][i];
_t_78_ += q_4[k+4][j][i];
_t_78_ -= q_4[k-4][j][i];
_t_73_ -= dxinv2 * 0.0035 * _t_78_;
flux_3kc0jc0ic0 -= _t_73_;

double _t_81_ = q_4[k+1][j][i] * q_3[k+1][j][i];
double _v_104_ = cons_4[k+1][j][i] * q_3[k+1][j][i];
_t_81_ += _v_104_;
_t_81_ -= cons_4[k-1][j][i] * q_3[k-1][j][i];
double _v_107_ = q_4[k-1][j][i] * q_3[k-1][j][i];
_t_81_ -= _v_107_;
double _t_79_ = dxinv2 * 0.8 * _t_81_;
double _t_82_ = q_4[k+2][j][i] * q_3[k+2][j][i];
double _v_108_ = cons_4[k+2][j][i] * q_3[k+2][j][i];
_t_82_ += _v_108_;
_t_82_ -= cons_4[k-2][j][i] * q_3[k-2][j][i];
double _v_111_ = q_4[k-2][j][i] * q_3[k-2][j][i];
_t_82_ -= _v_111_;
_t_79_ -= dxinv2 * 0.2 * _t_82_;
double _t_83_ = q_4[k+3][j][i] * q_3[k+3][j][i];
double _v_112_ = cons_4[k+3][j][i] * q_3[k+3][j][i];
_t_83_ += _v_112_;
_t_83_ -= cons_4[k-3][j][i] * q_3[k-3][j][i];
double _v_115_ = q_4[k-3][j][i] * q_3[k-3][j][i];
_t_83_ -= _v_115_;
_t_79_ += dxinv2 * 0.038 * _t_83_;
double _t_84_ = q_4[k+4][j][i] * q_3[k+4][j][i];
double _v_116_ = cons_4[k+4][j][i] * q_3[k+4][j][i];
_t_84_ += _v_116_;
_t_84_ -= cons_4[k-4][j][i] * q_3[k-4][j][i];
double _v_119_ = q_4[k-4][j][i] * q_3[k-4][j][i];
_t_84_ -= _v_119_;
_t_79_ -= dxinv2 * 0.0035 * _t_84_;
flux_4kc0jc0ic0 -= _t_79_;

flux_0[k][j][i] = flux_0kc0jc0ic0;
flux_1[k][j][i] = flux_1kc0jc0ic0;
flux_2[k][j][i] = flux_2kc0jc0ic0;
flux_3[k][j][i] = flux_3kc0jc0ic0;
flux_4[k][j][i] = flux_4kc0jc0ic0;
	} 
}

extern "C" void host_code (double *h_flux_0, double *h_flux_1, double *h_flux_2, double *h_flux_3, double *h_flux_4, double *h_cons_1, double *h_cons_2, double *h_cons_3, double *h_cons_4, double *h_q_1, double *h_q_2, double *h_q_3, double *h_q_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	double *flux_0;
	cudaMalloc (&flux_0, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_0\n");
	cudaMemcpy (flux_0, h_flux_0, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_1;
	cudaMalloc (&flux_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_1\n");
	cudaMemcpy (flux_1, h_flux_1, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_2;
	cudaMalloc (&flux_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_2\n");
	cudaMemcpy (flux_2, h_flux_2, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_3;
	cudaMalloc (&flux_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_3\n");
	cudaMemcpy (flux_3, h_flux_3, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *flux_4;
	cudaMalloc (&flux_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_4\n");
	cudaMemcpy (flux_4, h_flux_4, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_1;
	cudaMalloc (&cons_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_1\n");
	cudaMemcpy (cons_1, h_cons_1, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_2;
	cudaMalloc (&cons_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_2\n");
	cudaMemcpy (cons_2, h_cons_2, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_3;
	cudaMalloc (&cons_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_3\n");
	cudaMemcpy (cons_3, h_cons_3, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *cons_4;
	cudaMalloc (&cons_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_4\n");
	cudaMemcpy (cons_4, h_cons_4, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_1;
	cudaMalloc (&q_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_1\n");
	cudaMemcpy (q_1, h_q_1, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_2;
	cudaMalloc (&q_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_2\n");
	cudaMemcpy (q_2, h_q_2, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_3;
	cudaMalloc (&q_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_3\n");
	cudaMemcpy (q_3, h_q_3, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);
	double *q_4;
	cudaMalloc (&q_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_4\n");
	cudaMemcpy (q_4, h_q_4, sizeof(double)*L*M*N, cudaMemcpyHostToDevice);

	dim3 blockconfig (16, 4, 4);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, blockconfig.z));
	hypterm <<<gridconfig, blockconfig>>> (flux_0, flux_1, flux_2, flux_3, flux_4, cons_1, cons_2, cons_3, cons_4, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);

	cudaMemcpy (h_flux_0, flux_0, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_1, flux_1, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_3, flux_3, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_4, flux_4, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
	cudaMemcpy (h_flux_2, flux_2, sizeof(double)*L*M*N, cudaMemcpyDeviceToHost);
}

	.file	"tmpxft_002c2e88_00000000-6_max-reordered-b.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0:
.LFB2173:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2173:
	.size	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L3
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L3:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z56__device_stub__Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z56__device_stub__Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, @function
_Z56__device_stub__Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$376, %rsp
	.cfi_def_cfa_offset 384
	movsd	%xmm0, 24(%rsp)
	movsd	%xmm1, 16(%rsp)
	movsd	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	160(%rsp), %rdi
	movq	%rax, 208(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	384(%rsp), %rax
	movq	%rsi, 48(%rsp)
	leaq	172(%rsp), %rsi
	movq	%rax, 88(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 256(%rsp)
	movq	392(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	144(%rsp), %rdx
	movq	%rax, 96(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	400(%rsp), %rax
	movq	%rcx, 64(%rsp)
	leaq	152(%rsp), %rcx
	movq	%rax, 104(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 272(%rsp)
	movq	408(%rsp), %rax
	movq	%r8, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 280(%rsp)
	movq	416(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 288(%rsp)
	movq	424(%rsp), %rax
	movl	$1, 168(%rsp)
	movq	%rax, 128(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 296(%rsp)
	movq	432(%rsp), %rax
	movl	$1, 180(%rsp)
	movq	%rax, 136(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	448(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 352(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 160(%rsp)
	movq	%rax, 172(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	152(%rsp)
	.cfi_def_cfa_offset 392
	leaq	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii(%rip), %rdi
	pushq	152(%rsp)
	.cfi_def_cfa_offset 400
	movq	188(%rsp), %rcx
	movl	196(%rsp), %r8d
	movq	176(%rsp), %rsi
	movl	184(%rsp), %edx
	leaq	224(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 392
	popq	%rdx
	.cfi_def_cfa_offset 384
.L7:
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$376, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z56__device_stub__Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, .-_Z56__device_stub__Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, @function
_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_endproc
.LFE2054:
	.size	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, .-_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for flux_0\n"
.LC2:
	.string	"Failed to allocate device memory for flux_1\n"
.LC3:
	.string	"Failed to allocate device memory for flux_2\n"
.LC4:
	.string	"Failed to allocate device memory for flux_3\n"
.LC5:
	.string	"Failed to allocate device memory for flux_4\n"
.LC6:
	.string	"Failed to allocate device memory for cons_1\n"
.LC7:
	.string	"Failed to allocate device memory for cons_2\n"
.LC8:
	.string	"Failed to allocate device memory for cons_3\n"
.LC9:
	.string	"Failed to allocate device memory for cons_4\n"
.LC10:
	.string	"Failed to allocate device memory for q_1\n"
.LC11:
	.string	"Failed to allocate device memory for q_2\n"
.LC12:
	.string	"Failed to allocate device memory for q_3\n"
.LC13:
	.string	"Failed to allocate device memory for q_4\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r9, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$264, %rsp
	.cfi_def_cfa_offset 320
	movq	336(%rsp), %rax
	movq	%r8, 40(%rsp)
	movsd	%xmm0, 104(%rsp)
	movq	320(%rsp), %r15
	movq	328(%rsp), %r14
	movq	%rax, 48(%rsp)
	movq	344(%rsp), %rax
	movq	%rcx, 32(%rsp)
	movq	%rax, 56(%rsp)
	movq	352(%rsp), %rax
	movq	%rdi, 8(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rax, 64(%rsp)
	movq	360(%rsp), %rax
	movq	%rsi, 16(%rsp)
	movq	%rax, 72(%rsp)
	movq	368(%rsp), %rax
	movq	%rdx, 24(%rsp)
	movq	%rax, 80(%rsp)
	movsd	%xmm1, 96(%rsp)
	movl	384(%rsp), %ebp
	movslq	392(%rsp), %rdx
	movsd	%xmm2, 88(%rsp)
	movl	376(%rsp), %ebx
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	movslq	%ebp, %rax
	movq	%rdx, %r12
	imulq	%rdx, %rax
	movslq	%ebx, %rdx
	imulq	%rdx, %rax
	salq	$3, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	120(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	128(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	128(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	136(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC3(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	136(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	144(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC4(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	152(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC5(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	152(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	160(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC6(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%r13, %rsi
	movq	160(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	168(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC7(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%r15, %rsi
	movq	168(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	176(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC8(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%r14, %rsi
	movq	176(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	184(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC9(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	184(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	192(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC10(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	192(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	200(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC11(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$1, %ecx
	movq	200(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	208(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC12(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$1, %ecx
	movq	208(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	216(%rsp), %rdi
	call	_Z10cudaMallocIdE9cudaErrorPPT_m.isra.0
	leaq	.LC13(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$1, %ecx
	movq	216(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%ebx, %eax
	movl	%ebx, %esi
	movl	%ebp, %edx
	andl	$3, %eax
	shrl	$2, %esi
	movl	%r12d, %ecx
	cmpl	$1, %eax
	movl	%ebp, %eax
	sbbl	$-1, %esi
	andl	$3, %edx
	shrl	$2, %eax
	cmpl	$1, %edx
	movl	%r12d, %edx
	sbbl	$-1, %eax
	andl	$15, %ecx
	shrl	$4, %edx
	cmpl	$1, %ecx
	movl	%eax, 240(%rsp)
	movl	$4, %ecx
	sbbl	$-1, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%edx, 236(%rsp)
	movl	$1073741825, %edx
	movq	236(%rsp), %rdi
	salq	$4, %rdx
	call	__cudaPushCallConfiguration@PLT
	movsd	88(%rsp), %xmm2
	movsd	96(%rsp), %xmm1
	testl	%eax, %eax
	movsd	104(%rsp), %xmm0
	jne	.L16
	pushq	%r12
	.cfi_def_cfa_offset 328
	xorps	.LC14(%rip), %xmm0
	pushq	%rbp
	.cfi_def_cfa_offset 336
	pushq	%rbx
	.cfi_def_cfa_offset 344
	pushq	240(%rsp)
	.cfi_def_cfa_offset 352
	pushq	240(%rsp)
	.cfi_def_cfa_offset 360
	pushq	240(%rsp)
	.cfi_def_cfa_offset 368
	pushq	240(%rsp)
	.cfi_def_cfa_offset 376
	pushq	240(%rsp)
	.cfi_def_cfa_offset 384
	pushq	240(%rsp)
	.cfi_def_cfa_offset 392
	pushq	240(%rsp)
	.cfi_def_cfa_offset 400
	movq	240(%rsp), %r9
	movq	232(%rsp), %r8
	movq	224(%rsp), %rcx
	movq	216(%rsp), %rdx
	movq	208(%rsp), %rsi
	movq	200(%rsp), %rdi
	call	_Z56__device_stub__Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiiiPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	addq	$80, %rsp
	.cfi_def_cfa_offset 320
.L16:
	movq	(%rsp), %rdx
	movq	120(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movq	128(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	32(%rsp), %rdi
	movl	$2, %ecx
	movq	144(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	40(%rsp), %rdi
	movl	$2, %ecx
	movq	152(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movq	136(%rsp), %rsi
	call	cudaMemcpy@PLT
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$264, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC15:
	.string	"_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC14:
	.long	0
	.long	-2147483648
	.long	0
	.long	0
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	hipError_t error = hipGetLastError ();
	if (error != hipSuccess) {
		printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
		exit(-1);
	}
}

__global__ void hypterm (double * __restrict__ flux_in_0, double * __restrict__ flux_in_1, double * __restrict__ flux_in_2, double * __restrict__ flux_in_3, double * __restrict__ flux_in_4, double * __restrict__ cons_in_1, double * __restrict__ cons_in_2, double * __restrict__ cons_in_3, double * __restrict__ cons_in_4, double * __restrict__ q_in_1, double * __restrict__ q_in_2, double * __restrict__ q_in_3, double * __restrict__ q_in_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	//Determing the block's indices
	int blockdim_i= (int)(blockDim.x);
	int i0 = (int)(blockIdx.x)*(blockdim_i);
	int i = max (i0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);
	int blockdim_k= (int)(blockDim.z);
	int k0 = (int)(blockIdx.z)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.z);

	double (*flux_0)[308][308] = (double (*)[308][308])flux_in_0;
	double (*flux_1)[308][308] = (double (*)[308][308])flux_in_1;
	double (*flux_2)[308][308] = (double (*)[308][308])flux_in_2;
	double (*flux_3)[308][308] = (double (*)[308][308])flux_in_3;
	double (*flux_4)[308][308] = (double (*)[308][308])flux_in_4;
	double (*q_1)[308][308] = (double (*)[308][308])q_in_1;
	double (*q_2)[308][308] = (double (*)[308][308])q_in_2;
	double (*q_3)[308][308] = (double (*)[308][308])q_in_3;
	double (*q_4)[308][308] = (double (*)[308][308])q_in_4;
	double (*cons_1)[308][308] = (double (*)[308][308])cons_in_1;
	double (*cons_2)[308][308] = (double (*)[308][308])cons_in_2;
	double (*cons_3)[308][308] = (double (*)[308][308])cons_in_3;
	double (*cons_4)[308][308] = (double (*)[308][308])cons_in_4;

	if (i>=4 & j>=4 & k>=4 & i<=N-5 & j<=N-5 & k<=N-5) {
double _t_1_ = cons_1[k][j][i+1];
_t_1_ -= cons_1[k][j][i-1];
double flux_0kc0jc0ic0 = dxinv0 * 0.8 * _t_1_;
double _t_2_ = cons_1[k][j][i+2];
_t_2_ -= cons_1[k][j][i-2];
flux_0kc0jc0ic0 -= dxinv0 * 0.2 * _t_2_;
double _t_3_ = cons_1[k][j][i+3];
_t_3_ -= cons_1[k][j][i-3];
flux_0kc0jc0ic0 += dxinv0 * 0.038 * _t_3_;
double _t_4_ = cons_1[k][j][i+4];
_t_4_ -= cons_1[k][j][i-4];
flux_0kc0jc0ic0 -= dxinv0 * 0.0035 * _t_4_;

double _t_6_ = cons_1[k][j][i+1] * q_1[k][j][i+1];
_t_6_ -= cons_1[k][j][i-1] * q_1[k][j][i-1];
_t_6_ += q_4[k][j][i+1];
_t_6_ -= q_4[k][j][i-1];
double flux_1kc0jc0ic0 = dxinv0 * 0.8 * _t_6_;
double _t_7_ = cons_1[k][j][i+2] * q_1[k][j][i+2];
_t_7_ -= cons_1[k][j][i-2] * q_1[k][j][i-2];
_t_7_ += q_4[k][j][i+2];
_t_7_ -= q_4[k][j][i-2];
flux_1kc0jc0ic0 -= dxinv0 * 0.2 * _t_7_;
double _t_8_ = cons_1[k][j][i+3] * q_1[k][j][i+3];
_t_8_ -= cons_1[k][j][i-3] * q_1[k][j][i-3];
_t_8_ += q_4[k][j][i+3];
_t_8_ -= q_4[k][j][i-3];
flux_1kc0jc0ic0 += dxinv0 * 0.038 * _t_8_;
double _t_9_ = cons_1[k][j][i+4] * q_1[k][j][i+4];
_t_9_ -= cons_1[k][j][i-4] * q_1[k][j][i-4];
_t_9_ += q_4[k][j][i+4];
_t_9_ -= q_4[k][j][i-4];
flux_1kc0jc0ic0 -= dxinv0 * 0.0035 * _t_9_;

double _t_11_ = cons_2[k][j][i+1] * q_1[k][j][i+1];
_t_11_ -= cons_2[k][j][i-1] * q_1[k][j][i-1];
double flux_2kc0jc0ic0 = dxinv0 * 0.8 * _t_11_;
double _t_12_ = cons_2[k][j][i+2] * q_1[k][j][i+2];
_t_12_ -= cons_2[k][j][i-2] * q_1[k][j][i-2];
flux_2kc0jc0ic0 -= dxinv0 * 0.2 * _t_12_;
double _t_13_ = cons_2[k][j][i+3] * q_1[k][j][i+3];
_t_13_ -= cons_2[k][j][i-3] * q_1[k][j][i-3];
flux_2kc0jc0ic0 += dxinv0 * 0.038 * _t_13_;
double _t_14_ = cons_2[k][j][i+4] * q_1[k][j][i+4];
_t_14_ -= cons_2[k][j][i-4] * q_1[k][j][i-4];
flux_2kc0jc0ic0 -= dxinv0 * 0.0035 * _t_14_;

double _t_16_ = cons_3[k][j][i+1] * q_1[k][j][i+1];
_t_16_ -= cons_3[k][j][i-1] * q_1[k][j][i-1];
double flux_3kc0jc0ic0 = dxinv0 * 0.8 * _t_16_;
double _t_17_ = cons_3[k][j][i+2] * q_1[k][j][i+2];
_t_17_ -= cons_3[k][j][i-2] * q_1[k][j][i-2];
flux_3kc0jc0ic0 -= dxinv0 * 0.2 * _t_17_;
double _t_18_ = cons_3[k][j][i+3] * q_1[k][j][i+3];
_t_18_ -= cons_3[k][j][i-3] * q_1[k][j][i-3];
flux_3kc0jc0ic0 += dxinv0 * 0.038 * _t_18_;
double _t_19_ = cons_3[k][j][i+4] * q_1[k][j][i+4];
_t_19_ -= cons_3[k][j][i-4] * q_1[k][j][i-4];
flux_3kc0jc0ic0 -= dxinv0 * 0.0035 * _t_19_;

double _t_21_ = q_4[k][j][i+1] * q_1[k][j][i+1];
double _v_24_ = cons_4[k][j][i+1] * q_1[k][j][i+1];
_t_21_ += _v_24_;
_t_21_ -= cons_4[k][j][i-1] * q_1[k][j][i-1];
double _v_27_ = q_4[k][j][i-1] * q_1[k][j][i-1];
_t_21_ -= _v_27_;
double flux_4kc0jc0ic0 = dxinv0 * 0.8 * _t_21_;
double _t_22_ = q_4[k][j][i+2] * q_1[k][j][i+2];
double _v_28_ = cons_4[k][j][i+2] * q_1[k][j][i+2];
_t_22_ += _v_28_;
_t_22_ -= cons_4[k][j][i-2] * q_1[k][j][i-2];
double _v_31_ = q_4[k][j][i-2] * q_1[k][j][i-2];
_t_22_ -= _v_31_;
flux_4kc0jc0ic0 -= dxinv0 * 0.2 * _t_22_;
double _t_23_ = q_4[k][j][i+3] * q_1[k][j][i+3];
double _v_32_ = cons_4[k][j][i+3] * q_1[k][j][i+3];
_t_23_ += _v_32_;
_t_23_ -= cons_4[k][j][i-3] * q_1[k][j][i-3];
double _v_35_ = q_4[k][j][i-3] * q_1[k][j][i-3];
_t_23_ -= _v_35_;
flux_4kc0jc0ic0 += dxinv0 * 0.038 * _t_23_;
double _t_24_ = q_4[k][j][i+4] * q_1[k][j][i+4];
double _v_36_ = cons_4[k][j][i+4] * q_1[k][j][i+4];
_t_24_ += _v_36_;
_t_24_ -= cons_4[k][j][i-4] * q_1[k][j][i-4];
double _v_39_ = q_4[k][j][i-4] * q_1[k][j][i-4];
_t_24_ -= _v_39_;
flux_4kc0jc0ic0 -= dxinv0 * 0.0035 * _t_24_;

double _t_27_ = cons_2[k][j+1][i];
_t_27_ -= cons_2[k][j-1][i];
double _t_25_ = dxinv1 * 0.8 * _t_27_;
double _t_28_ = cons_2[k][j+2][i];
_t_28_ -= cons_2[k][j-2][i];
_t_25_ -= dxinv1 * 0.2 * _t_28_;
double _t_29_ = cons_2[k][j+3][i];
_t_29_ -= cons_2[k][j-3][i];
_t_25_ += dxinv1 * 0.038 * _t_29_;
double _t_30_ = cons_2[k][j+4][i];
_t_30_ -= cons_2[k][j-4][i];
_t_25_ -= dxinv1 * 0.0035 * _t_30_;
flux_0kc0jc0ic0 -= _t_25_;

double _t_33_ = cons_1[k][j+1][i] * q_2[k][j+1][i];
_t_33_ -= cons_1[k][j-1][i] * q_2[k][j-1][i];
double _t_31_ = dxinv1 * 0.8 * _t_33_;
double _t_34_ = cons_1[k][j+2][i] * q_2[k][j+2][i];
_t_34_ -= cons_1[k][j-2][i] * q_2[k][j-2][i];
_t_31_ -= dxinv1 * 0.2 * _t_34_;
double _t_35_ = cons_1[k][j+3][i] * q_2[k][j+3][i];
_t_35_ -= cons_1[k][j-3][i] * q_2[k][j-3][i];
_t_31_ += dxinv1 * 0.038 * _t_35_;
double _t_36_ = cons_1[k][j+4][i] * q_2[k][j+4][i];
_t_36_ -= cons_1[k][j-4][i] * q_2[k][j-4][i];
_t_31_ -= dxinv1 * 0.0035 * _t_36_;
flux_1kc0jc0ic0 -= _t_31_;

double _t_39_ = cons_2[k][j+1][i] * q_2[k][j+1][i];
_t_39_ -= cons_2[k][j-1][i] * q_2[k][j-1][i];
_t_39_ += q_4[k][j+1][i];
_t_39_ -= q_4[k][j-1][i];
double _t_37_ = dxinv1 * 0.8 * _t_39_;
double _t_40_ = cons_2[k][j+2][i] * q_2[k][j+2][i];
_t_40_ -= cons_2[k][j-2][i] * q_2[k][j-2][i];
_t_40_ += q_4[k][j+2][i];
_t_40_ -= q_4[k][j-2][i];
_t_37_ -= dxinv1 * 0.2 * _t_40_;
double _t_41_ = cons_2[k][j+3][i] * q_2[k][j+3][i];
_t_41_ -= cons_2[k][j-3][i] * q_2[k][j-3][i];
_t_41_ += q_4[k][j+3][i];
_t_41_ -= q_4[k][j-3][i];
_t_37_ += dxinv1 * 0.038 * _t_41_;
double _t_42_ = cons_2[k][j+4][i] * q_2[k][j+4][i];
_t_42_ -= cons_2[k][j-4][i] * q_2[k][j-4][i];
_t_42_ += q_4[k][j+4][i];
_t_42_ -= q_4[k][j-4][i];
_t_37_ -= dxinv1 * 0.0035 * _t_42_;
flux_2kc0jc0ic0 -= _t_37_;

double _t_45_ = cons_3[k][j+1][i] * q_2[k][j+1][i];
_t_45_ -= cons_3[k][j-1][i] * q_2[k][j-1][i];
double _t_43_ = dxinv1 * 0.8 * _t_45_;
double _t_46_ = cons_3[k][j+2][i] * q_2[k][j+2][i];
_t_46_ -= cons_3[k][j-2][i] * q_2[k][j-2][i];
_t_43_ -= dxinv1 * 0.2 * _t_46_;
double _t_47_ = cons_3[k][j+3][i] * q_2[k][j+3][i];
_t_47_ -= cons_3[k][j-3][i] * q_2[k][j-3][i];
_t_43_ += dxinv1 * 0.038 * _t_47_;
double _t_48_ = cons_3[k][j+4][i] * q_2[k][j+4][i];
_t_48_ -= cons_3[k][j-4][i] * q_2[k][j-4][i];
_t_43_ -= dxinv1 * 0.0035 * _t_48_;
flux_3kc0jc0ic0 -= _t_43_;

double _t_51_ = q_4[k][j+1][i] * q_2[k][j+1][i];
double _v_64_ = cons_4[k][j+1][i] * q_2[k][j+1][i];
_t_51_ += _v_64_;
_t_51_ -= cons_4[k][j-1][i] * q_2[k][j-1][i];
double _v_67_ = q_4[k][j-1][i] * q_2[k][j-1][i];
_t_51_ -= _v_67_;
double _t_49_ = dxinv1 * 0.8 * _t_51_;
double _t_52_ = q_4[k][j+2][i] * q_2[k][j+2][i];
double _v_68_ = cons_4[k][j+2][i] * q_2[k][j+2][i];
_t_52_ += _v_68_;
_t_52_ -= cons_4[k][j-2][i] * q_2[k][j-2][i];
double _v_71_ = q_4[k][j-2][i] * q_2[k][j-2][i];
_t_52_ -= _v_71_;
_t_49_ -= dxinv1 * 0.2 * _t_52_;
double _t_53_ = q_4[k][j+3][i] * q_2[k][j+3][i];
double _v_72_ = cons_4[k][j+3][i] * q_2[k][j+3][i];
_t_53_ += _v_72_;
_t_53_ -= cons_4[k][j-3][i] * q_2[k][j-3][i];
double _v_75_ = q_4[k][j-3][i] * q_2[k][j-3][i];
_t_53_ -= _v_75_;
_t_49_ += dxinv1 * 0.038 * _t_53_;
double _t_54_ = q_4[k][j+4][i] * q_2[k][j+4][i];
double _v_76_ = cons_4[k][j+4][i] * q_2[k][j+4][i];
_t_54_ += _v_76_;
_t_54_ -= cons_4[k][j-4][i] * q_2[k][j-4][i];
double _v_79_ = q_4[k][j-4][i] * q_2[k][j-4][i];
_t_54_ -= _v_79_;
_t_49_ -= dxinv1 * 0.0035 * _t_54_;
flux_4kc0jc0ic0 -= _t_49_;

double _t_57_ = cons_3[k+1][j][i];
_t_57_ -= cons_3[k-1][j][i];
double _t_55_ = dxinv2 * 0.8 * _t_57_;
double _t_58_ = cons_3[k+2][j][i];
_t_58_ -= cons_3[k-2][j][i];
_t_55_ -= dxinv2 * 0.2 * _t_58_;
double _t_59_ = cons_3[k+3][j][i];
_t_59_ -= cons_3[k-3][j][i];
_t_55_ += dxinv2 * 0.038 * _t_59_;
double _t_60_ = cons_3[k+4][j][i];
_t_60_ -= cons_3[k-4][j][i];
_t_55_ -= dxinv2 * 0.0035 * _t_60_;
flux_0kc0jc0ic0 -= _t_55_;

double _t_63_ = cons_1[k+1][j][i] * q_3[k+1][j][i];
_t_63_ -= cons_1[k-1][j][i] * q_3[k-1][j][i];
double _t_61_ = dxinv2 * 0.8 * _t_63_;
double _t_64_ = cons_1[k+2][j][i] * q_3[k+2][j][i];
_t_64_ -= cons_1[k-2][j][i] * q_3[k-2][j][i];
_t_61_ -= dxinv2 * 0.2 * _t_64_;
double _t_65_ = cons_1[k+3][j][i] * q_3[k+3][j][i];
_t_65_ -= cons_1[k-3][j][i] * q_3[k-3][j][i];
_t_61_ += dxinv2 * 0.038 * _t_65_;
double _t_66_ = cons_1[k+4][j][i] * q_3[k+4][j][i];
_t_66_ -= cons_1[k-4][j][i] * q_3[k-4][j][i];
_t_61_ -= dxinv2 * 0.0035 * _t_66_;
flux_1kc0jc0ic0 -= _t_61_;

double _t_69_ = cons_2[k+1][j][i] * q_3[k+1][j][i];
_t_69_ -= cons_2[k-1][j][i] * q_3[k-1][j][i];
double _t_67_ = dxinv2 * 0.8 * _t_69_;
double _t_70_ = cons_2[k+2][j][i] * q_3[k+2][j][i];
_t_70_ -= cons_2[k-2][j][i] * q_3[k-2][j][i];
_t_67_ -= dxinv2 * 0.2 * _t_70_;
double _t_71_ = cons_2[k+3][j][i] * q_3[k+3][j][i];
_t_71_ -= cons_2[k-3][j][i] * q_3[k-3][j][i];
_t_67_ += dxinv2 * 0.038 * _t_71_;
double _t_72_ = cons_2[k+4][j][i] * q_3[k+4][j][i];
_t_72_ -= cons_2[k-4][j][i] * q_3[k-4][j][i];
_t_67_ -= dxinv2 * 0.0035 * _t_72_;
flux_2kc0jc0ic0 -= _t_67_;

double _t_75_ = cons_3[k+1][j][i] * q_3[k+1][j][i];
_t_75_ -= cons_3[k-1][j][i] * q_3[k-1][j][i];
_t_75_ += q_4[k+1][j][i];
_t_75_ -= q_4[k-1][j][i];
double _t_73_ = dxinv2 * 0.8 * _t_75_;
double _t_76_ = cons_3[k+2][j][i] * q_3[k+2][j][i];
_t_76_ -= cons_3[k-2][j][i] * q_3[k-2][j][i];
_t_76_ += q_4[k+2][j][i];
_t_76_ -= q_4[k-2][j][i];
_t_73_ -= dxinv2 * 0.2 * _t_76_;
double _t_77_ = cons_3[k+3][j][i] * q_3[k+3][j][i];
_t_77_ -= cons_3[k-3][j][i] * q_3[k-3][j][i];
_t_77_ += q_4[k+3][j][i];
_t_77_ -= q_4[k-3][j][i];
_t_73_ += dxinv2 * 0.038 * _t_77_;
double _t_78_ = cons_3[k+4][j][i] * q_3[k+4][j][i];
_t_78_ -= cons_3[k-4][j][i] * q_3[k-4][j][i];
_t_78_ += q_4[k+4][j][i];
_t_78_ -= q_4[k-4][j][i];
_t_73_ -= dxinv2 * 0.0035 * _t_78_;
flux_3kc0jc0ic0 -= _t_73_;

double _t_81_ = q_4[k+1][j][i] * q_3[k+1][j][i];
double _v_104_ = cons_4[k+1][j][i] * q_3[k+1][j][i];
_t_81_ += _v_104_;
_t_81_ -= cons_4[k-1][j][i] * q_3[k-1][j][i];
double _v_107_ = q_4[k-1][j][i] * q_3[k-1][j][i];
_t_81_ -= _v_107_;
double _t_79_ = dxinv2 * 0.8 * _t_81_;
double _t_82_ = q_4[k+2][j][i] * q_3[k+2][j][i];
double _v_108_ = cons_4[k+2][j][i] * q_3[k+2][j][i];
_t_82_ += _v_108_;
_t_82_ -= cons_4[k-2][j][i] * q_3[k-2][j][i];
double _v_111_ = q_4[k-2][j][i] * q_3[k-2][j][i];
_t_82_ -= _v_111_;
_t_79_ -= dxinv2 * 0.2 * _t_82_;
double _t_83_ = q_4[k+3][j][i] * q_3[k+3][j][i];
double _v_112_ = cons_4[k+3][j][i] * q_3[k+3][j][i];
_t_83_ += _v_112_;
_t_83_ -= cons_4[k-3][j][i] * q_3[k-3][j][i];
double _v_115_ = q_4[k-3][j][i] * q_3[k-3][j][i];
_t_83_ -= _v_115_;
_t_79_ += dxinv2 * 0.038 * _t_83_;
double _t_84_ = q_4[k+4][j][i] * q_3[k+4][j][i];
double _v_116_ = cons_4[k+4][j][i] * q_3[k+4][j][i];
_t_84_ += _v_116_;
_t_84_ -= cons_4[k-4][j][i] * q_3[k-4][j][i];
double _v_119_ = q_4[k-4][j][i] * q_3[k-4][j][i];
_t_84_ -= _v_119_;
_t_79_ -= dxinv2 * 0.0035 * _t_84_;
flux_4kc0jc0ic0 -= _t_79_;

flux_0[k][j][i] = flux_0kc0jc0ic0;
flux_1[k][j][i] = flux_1kc0jc0ic0;
flux_2[k][j][i] = flux_2kc0jc0ic0;
flux_3[k][j][i] = flux_3kc0jc0ic0;
flux_4[k][j][i] = flux_4kc0jc0ic0;
	} 
}

extern "C" void host_code (double *h_flux_0, double *h_flux_1, double *h_flux_2, double *h_flux_3, double *h_flux_4, double *h_cons_1, double *h_cons_2, double *h_cons_3, double *h_cons_4, double *h_q_1, double *h_q_2, double *h_q_3, double *h_q_4, double dxinv0, double dxinv1, double dxinv2, int L, int M, int N) {
	double *flux_0;
	hipMalloc (&flux_0, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_0\n");
	hipMemcpy (flux_0, h_flux_0, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_1;
	hipMalloc (&flux_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_1\n");
	hipMemcpy (flux_1, h_flux_1, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_2;
	hipMalloc (&flux_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_2\n");
	hipMemcpy (flux_2, h_flux_2, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_3;
	hipMalloc (&flux_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_3\n");
	hipMemcpy (flux_3, h_flux_3, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *flux_4;
	hipMalloc (&flux_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for flux_4\n");
	hipMemcpy (flux_4, h_flux_4, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_1;
	hipMalloc (&cons_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_1\n");
	hipMemcpy (cons_1, h_cons_1, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_2;
	hipMalloc (&cons_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_2\n");
	hipMemcpy (cons_2, h_cons_2, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_3;
	hipMalloc (&cons_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_3\n");
	hipMemcpy (cons_3, h_cons_3, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *cons_4;
	hipMalloc (&cons_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for cons_4\n");
	hipMemcpy (cons_4, h_cons_4, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_1;
	hipMalloc (&q_1, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_1\n");
	hipMemcpy (q_1, h_q_1, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_2;
	hipMalloc (&q_2, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_2\n");
	hipMemcpy (q_2, h_q_2, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_3;
	hipMalloc (&q_3, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_3\n");
	hipMemcpy (q_3, h_q_3, sizeof(double)*L*M*N, hipMemcpyHostToDevice);
	double *q_4;
	hipMalloc (&q_4, sizeof(double)*L*M*N);
	check_error ("Failed to allocate device memory for q_4\n");
	hipMemcpy (q_4, h_q_4, sizeof(double)*L*M*N, hipMemcpyHostToDevice);

	dim3 blockconfig (16, 4, 4);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(M, blockconfig.y), ceil(L, blockconfig.z));
	hypterm <<<gridconfig, blockconfig>>> (flux_0, flux_1, flux_2, flux_3, flux_4, cons_1, cons_2, cons_3, cons_4, q_1, q_2, q_3, q_4, -dxinv0, dxinv1, dxinv2, L, M, N);

	hipMemcpy (h_flux_0, flux_0, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_1, flux_1, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_3, flux_3, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_4, flux_4, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
	hipMemcpy (h_flux_2, flux_2, sizeof(double)*L*M*N, hipMemcpyDeviceToHost);
}

	.text
	.file	"max-reordered-b.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii # -- Begin function _Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.type	_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii,@function
_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii: # @_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$288, %rsp                      # imm = 0x120
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	64(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	40(%rsp), %r9
	movsd	%xmm0, (%r9)
	leaq	32(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	24(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	368(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	376(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	384(%rsp), %rax
	movq	%rax, 96(%rbx)
	movq	%r9, 104(%rbx)
	movq	%r10, 112(%rbx)
	movq	%r11, 120(%rbx)
	leaq	392(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$304, %rsp                      # imm = 0x130
	.cfi_adjust_cfa_offset -304
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, .Lfunc_end1-_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function host_code
.LCPI2_0:
	.quad	0x8000000000000000              # double -0
	.quad	0x8000000000000000              # double -0
	.text
	.globl	host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movsd	%xmm2, 56(%rsp)                 # 8-byte Spill
	movsd	%xmm1, 48(%rsp)                 # 8-byte Spill
	movaps	%xmm0, 192(%rsp)                # 16-byte Spill
	movq	%r9, 88(%rsp)                   # 8-byte Spill
	movq	%r8, 72(%rsp)                   # 8-byte Spill
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	movq	%rdx, %r12
	movq	%rsi, %rbp
	movq	%rdi, %rbx
	movslq	328(%rsp), %r15
	movq	%r15, 96(%rsp)                  # 8-byte Spill
	movslq	336(%rsp), %rax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movslq	344(%rsp), %r13
	imulq	%rax, %r15
	imulq	%r13, %r15
	shlq	$3, %r15
	leaq	40(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r14), %rdi
	movq	%rbx, 104(%rsp)                 # 8-byte Spill
	movq	%rbx, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	movq	(%r14), %rdi
	movq	%rbp, 112(%rsp)                 # 8-byte Spill
	movq	%rbp, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %edi
	callq	_Z11check_errorPKc
	movq	(%r14), %rdi
	movq	%r12, 120(%rsp)                 # 8-byte Spill
	movq	%r12, %rsi
	movq	72(%rsp), %r12                  # 8-byte Reload
	movq	64(%rsp), %rbp                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %edi
	callq	_Z11check_errorPKc
	movq	(%r14), %rdi
	movq	%rbp, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.5, %edi
	callq	_Z11check_errorPKc
	movq	(%r14), %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	184(%rsp), %r14
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.6, %edi
	callq	_Z11check_errorPKc
	movq	(%r14), %rdi
	movq	80(%rsp), %r14                  # 8-byte Reload
	movq	88(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	176(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.7, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	272(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	168(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.8, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	280(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	160(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.9, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	288(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	152(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.10, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	296(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	144(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.11, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	304(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	136(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.12, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	312(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	128(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movl	$.L.str.13, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	96(%rsp), %rbx                  # 8-byte Reload
	movq	320(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r13d, %eax
	andl	$15, %eax
	movl	%r13d, %ecx
	shrl	$4, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movl	%r14d, %eax
	andl	$3, %eax
	movl	%r14d, %edi
	shrl	$2, %edi
	cmpl	$1, %eax
	sbbl	$-1, %edi
	movl	%ebx, %eax
	andl	$3, %eax
	movl	%ebx, %esi
	shrl	$2, %esi
	cmpl	$1, %eax
	sbbl	$-1, %esi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$17179869200, %rdx              # imm = 0x400000010
	movl	$4, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movq	184(%rsp), %r9
	movaps	192(%rsp), %xmm0                # 16-byte Reload
	xorps	.LCPI2_0(%rip), %xmm0
	movsd	48(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	56(%rsp), %xmm2                 # 8-byte Reload
                                        # xmm2 = mem[0],zero
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	152(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	184(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	200(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	216(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	232(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	248(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
.LBB2_2:
	movq	40(%rsp), %rsi
	movq	104(%rsp), %rdi                 # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movq	112(%rsp), %rdi                 # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	%rbp, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	%r12, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rsi
	movq	120(%rsp), %rdi                 # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii,@object # @_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.section	.rodata,"a",@progbits
	.globl	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.p2align	3, 0x0
_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii:
	.quad	_Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.size	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for flux_0\n"
	.size	.L.str.1, 45

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for flux_1\n"
	.size	.L.str.2, 45

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate device memory for flux_2\n"
	.size	.L.str.3, 45

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate device memory for flux_3\n"
	.size	.L.str.4, 45

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to allocate device memory for flux_4\n"
	.size	.L.str.5, 45

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to allocate device memory for cons_1\n"
	.size	.L.str.6, 45

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to allocate device memory for cons_2\n"
	.size	.L.str.7, 45

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate device memory for cons_3\n"
	.size	.L.str.8, 45

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to allocate device memory for cons_4\n"
	.size	.L.str.9, 45

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Failed to allocate device memory for q_1\n"
	.size	.L.str.10, 42

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Failed to allocate device memory for q_2\n"
	.size	.L.str.11, 42

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Failed to allocate device memory for q_3\n"
	.size	.L.str.12, 42

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"Failed to allocate device memory for q_4\n"
	.size	.L.str.13, 42

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii"
	.size	.L__unnamed_1, 43

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii ; -- Begin function _Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.globl	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
	.p2align	8
	.type	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii,@function
_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii: ; @_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x9c
	s_load_b32 s4, s[0:1], 0x88
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v3, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_and_b32 s5, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s13, s13, s5
	s_mul_i32 s14, s14, s2
	s_mul_i32 s15, s15, s3
	s_max_i32 s2, s13, 0
	s_max_i32 s3, s14, 0
	s_max_i32 s5, s15, 0
	v_add_nc_u32_e32 v0, s2, v1
	v_add_nc_u32_e32 v2, s3, v2
	v_add_nc_u32_e32 v100, s5, v3
	s_add_i32 s4, s4, -5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min3_u32 v1, v0, v2, v100
	v_max3_i32 v3, v0, v2, v100
	v_cmp_lt_u32_e32 vcc_lo, 3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s4, v3
	s_and_b32 s2, s2, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x20
	s_load_b256 s[12:19], s[0:1], 0x40
	v_mad_u64_u32 v[22:23], null, 0xb9480, v100, 0
	v_mov_b32_e32 v1, 0
	v_mad_u64_u32 v[20:21], null, 0x9a0, v2, 0
	s_load_b64 s[2:3], s[0:1], 0x60
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[24:25], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s6, v22
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v23, vcc_lo
	v_add_co_u32 v2, vcc_lo, s14, v22
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v23, vcc_lo
	v_add_co_u32 v4, vcc_lo, s8, v22
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v23, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v20
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v21, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v20
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v21, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v20
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v34, vcc_lo, v2, v24
	v_add_co_ci_u32_e32 v35, vcc_lo, v3, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v28, vcc_lo, v4, v24
	v_add_co_ci_u32_e32 v29, vcc_lo, v5, v25, vcc_lo
	v_add_co_u32 v26, vcc_lo, v0, v24
	v_add_co_ci_u32_e32 v27, vcc_lo, v1, v25, vcc_lo
	v_add_co_u32 v8, vcc_lo, s10, v22
	v_add_co_ci_u32_e32 v9, vcc_lo, s11, v23, vcc_lo
	s_load_b128 s[8:11], s[0:1], 0x68
	v_add_co_u32 v10, vcc_lo, s12, v22
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v23, vcc_lo
	v_add_co_u32 v8, vcc_lo, v8, v20
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v10, vcc_lo, v10, v20
	v_add_co_ci_u32_e32 v11, vcc_lo, v11, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v32, vcc_lo, v8, v24
	v_add_co_ci_u32_e32 v33, vcc_lo, v9, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v30, vcc_lo, v10, v24
	v_add_co_ci_u32_e32 v31, vcc_lo, v11, v25, vcc_lo
	s_clause 0x1
	global_load_b128 v[4:7], v[34:35], off offset:-16
	global_load_b128 v[0:3], v[34:35], off offset:-32
	s_clause 0x1
	global_load_b128 v[12:15], v[28:29], off offset:-16
	global_load_b128 v[16:19], v[28:29], off offset:-32
	global_load_b128 v[36:39], v[32:33], off offset:-16
	global_load_b128 v[8:11], v[26:27], off offset:-16
	global_load_b128 v[40:43], v[30:31], off offset:8
	global_load_b128 v[44:47], v[34:35], off offset:8
	global_load_b128 v[48:51], v[26:27], off offset:-32
	global_load_b128 v[52:55], v[32:33], off offset:-32
	global_load_b128 v[56:59], v[34:35], off offset:24
	global_load_b128 v[60:63], v[30:31], off offset:24
	global_load_b128 v[64:67], v[28:29], off offset:8
	v_add_co_u32 v34, vcc_lo, s2, v22
	v_add_co_ci_u32_e32 v35, vcc_lo, s3, v23, vcc_lo
	global_load_b128 v[68:71], v[28:29], off offset:24
	v_add_co_u32 v34, vcc_lo, v34, v20
	v_add_co_ci_u32_e32 v35, vcc_lo, v35, v21, vcc_lo
	s_mov_b32 s6, 0x9999999a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v34, vcc_lo, v34, v24
	v_add_co_ci_u32_e32 v35, vcc_lo, v35, v25, vcc_lo
	global_load_b128 v[72:75], v[32:33], off offset:8
	global_load_b128 v[76:79], v[26:27], off offset:8
	global_load_b128 v[80:83], v[34:35], off offset:8
	global_load_b128 v[84:87], v[32:33], off offset:24
	global_load_b128 v[101:104], v[26:27], off offset:24
	global_load_b128 v[92:95], v[34:35], off offset:24
	global_load_b128 v[88:91], v[30:31], off offset:-16
	global_load_b64 v[105:106], v[28:29], off offset:-2464
	global_load_b64 v[111:112], v[26:27], off offset:-2464
	global_load_b64 v[113:114], v[32:33], off offset:-2464
	global_load_b64 v[115:116], v[30:31], off offset:2464
	global_load_b64 v[123:124], v[28:29], off offset:2464
	s_mov_b32 s7, 0x3fe99999
	s_mov_b32 s13, 0x3fc99999
	s_mov_b32 s12, s6
	s_mov_b32 s2, 0x6a7ef9db
	s_mov_b32 s3, 0x3fa374bc
	s_load_b64 s[14:15], s[0:1], 0x78
	s_waitcnt vmcnt(17)
	v_mul_f64 v[119:120], v[50:51], v[2:3]
	v_mul_f64 v[14:15], v[6:7], v[14:15]
	v_mul_f64 v[12:13], v[4:5], v[12:13]
	v_mul_f64 v[18:19], v[2:3], v[18:19]
	v_mul_f64 v[96:97], v[0:1], v[16:17]
	v_mul_f64 v[38:39], v[6:7], v[38:39]
	v_mul_f64 v[36:37], v[4:5], v[36:37]
	v_mul_f64 v[98:99], v[10:11], v[6:7]
	v_mul_f64 v[107:108], v[8:9], v[4:5]
	v_mul_f64 v[109:110], v[44:45], v[40:41]
	v_mul_f64 v[42:43], v[46:47], v[42:43]
	s_waitcnt vmcnt(16)
	v_mul_f64 v[117:118], v[2:3], v[54:55]
	s_waitcnt vmcnt(14)
	v_mul_f64 v[121:122], v[56:57], v[60:61]
	v_mul_f64 v[52:53], v[0:1], v[52:53]
	v_mul_f64 v[62:63], v[58:59], v[62:63]
	s_waitcnt vmcnt(13)
	v_fma_f64 v[40:41], v[44:45], v[64:65], -v[14:15]
	v_fma_f64 v[54:55], v[46:47], v[66:67], -v[12:13]
	s_waitcnt vmcnt(12)
	v_fma_f64 v[16:17], v[56:57], v[68:69], -v[18:19]
	v_fma_f64 v[12:13], v[58:59], v[70:71], -v[96:97]
	s_waitcnt vmcnt(11)
	v_fma_f64 v[60:61], v[44:45], v[72:73], -v[38:39]
	v_fma_f64 v[64:65], v[46:47], v[74:75], -v[36:37]
	s_waitcnt vmcnt(10)
	v_fma_f64 v[70:71], v[76:77], v[44:45], -v[98:99]
	v_fma_f64 v[96:97], v[78:79], v[46:47], -v[107:108]
	s_waitcnt vmcnt(9)
	v_fma_f64 v[68:69], v[44:45], v[80:81], v[109:110]
	v_fma_f64 v[46:47], v[46:47], v[82:83], v[42:43]
	global_load_b128 v[42:45], v[30:31], off offset:-32
	v_mul_f64 v[66:67], v[48:49], v[0:1]
	v_add_co_u32 v14, vcc_lo, s16, v22
	v_add_co_ci_u32_e32 v15, vcc_lo, s17, v23, vcc_lo
	global_load_b128 v[36:39], v[34:35], off offset:-16
	v_add_co_u32 v14, vcc_lo, v14, v20
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v21, vcc_lo
	global_load_b64 v[109:110], v[32:33], off offset:2464
	v_add_co_u32 v107, vcc_lo, v14, v24
	v_add_co_ci_u32_e32 v108, vcc_lo, v15, v25, vcc_lo
	s_waitcnt vmcnt(11)
	v_fma_f64 v[18:19], v[56:57], v[84:85], -v[117:118]
	v_fma_f64 v[14:15], v[58:59], v[86:87], -v[52:53]
	global_load_b64 v[52:53], v[26:27], off offset:2464
	global_load_b64 v[74:75], v[34:35], off offset:2464
	global_load_b64 v[72:73], v[107:108], off offset:-2464
	s_waitcnt vmcnt(13)
	v_fma_f64 v[84:85], v[101:102], v[56:57], -v[119:120]
	s_waitcnt vmcnt(12)
	v_fma_f64 v[56:57], v[56:57], v[92:93], v[121:122]
	v_add_f64 v[70:71], v[80:81], v[70:71]
	v_add_f64 v[80:81], v[82:83], v[96:97]
	v_add_co_u32 v82, vcc_lo, 0xfffff000, v26
	s_waitcnt vmcnt(11)
	v_fma_f64 v[46:47], -v[4:5], v[88:89], v[46:47]
	v_fma_f64 v[86:87], v[103:104], v[58:59], -v[66:67]
	v_fma_f64 v[58:59], v[58:59], v[94:95], v[62:63]
	v_fma_f64 v[62:63], -v[6:7], v[90:91], v[68:69]
	global_load_b128 v[66:69], v[34:35], off offset:-32
	global_load_b64 v[117:118], v[107:108], off offset:2464
	v_add_co_ci_u32_e32 v83, vcc_lo, -1, v27, vcc_lo
	global_load_b64 v[90:91], v[30:31], off offset:-2464
	v_add_f64 v[96:97], v[78:79], -v[8:9]
	v_add_f64 v[8:9], v[103:104], -v[48:49]
	global_load_b64 v[125:126], v[82:83], off offset:-832
	v_add_f64 v[84:85], v[92:93], v[84:85]
	v_add_f64 v[121:122], v[94:95], v[86:87]
	v_add_f64 v[94:95], v[76:77], -v[10:11]
	v_add_f64 v[10:11], v[101:102], -v[50:51]
	s_waitcnt vmcnt(9)
	v_fma_f64 v[44:45], -v[2:3], v[44:45], v[56:57]
	v_add_co_u32 v56, vcc_lo, 0xfffff000, v107
	v_add_co_ci_u32_e32 v57, vcc_lo, -1, v108, vcc_lo
	v_add_co_u32 v119, vcc_lo, 0xfffff000, v28
	v_add_co_ci_u32_e32 v120, vcc_lo, -1, v29, vcc_lo
	global_load_b64 v[86:87], v[56:57], off offset:-832
	v_add_co_u32 v127, vcc_lo, 0xfffff000, v32
	v_add_co_ci_u32_e32 v128, vcc_lo, -1, v33, vcc_lo
	v_fma_f64 v[42:43], -v[0:1], v[42:43], v[58:59]
	global_load_b64 v[101:102], v[119:120], off offset:-832
	global_load_b64 v[103:104], v[127:128], off offset:-832
	s_waitcnt vmcnt(11)
	v_fma_f64 v[88:89], -v[4:5], v[36:37], v[46:47]
	v_add_co_u32 v46, vcc_lo, 0x1000, v26
	v_add_co_ci_u32_e32 v47, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v129, vcc_lo, 0x1000, v107
	v_add_co_ci_u32_e32 v130, vcc_lo, 0, v108, vcc_lo
	v_fma_f64 v[76:77], -v[6:7], v[38:39], v[62:63]
	v_add_f64 v[92:93], v[80:81], -v[36:37]
	global_load_b64 v[80:81], v[46:47], off offset:832
	v_add_f64 v[78:79], v[70:71], -v[38:39]
	v_add_co_u32 v70, vcc_lo, 0x1000, v28
	v_add_co_ci_u32_e32 v71, vcc_lo, 0, v29, vcc_lo
	s_waitcnt vmcnt(8)
	v_mul_f64 v[111:112], v[111:112], v[72:73]
	v_mul_f64 v[48:49], v[105:106], v[72:73]
	v_add_co_u32 v58, vcc_lo, 0xffffe000, v107
	v_add_co_ci_u32_e32 v59, vcc_lo, -1, v108, vcc_lo
	v_add_co_u32 v38, vcc_lo, 0x2000, v107
	s_waitcnt vmcnt(7)
	v_fma_f64 v[6:7], -v[2:3], v[68:69], v[44:45]
	v_add_f64 v[2:3], v[121:122], -v[66:67]
	global_load_b64 v[121:122], v[129:130], off offset:832
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v108, vcc_lo
	v_add_co_u32 v107, vcc_lo, 0x1000, v32
	v_add_co_ci_u32_e32 v108, vcc_lo, 0, v33, vcc_lo
	global_load_b64 v[98:99], v[34:35], off offset:-2464
	v_fma_f64 v[0:1], -v[0:1], v[66:67], v[42:43]
	global_load_b64 v[66:67], v[70:71], off offset:832
	v_add_f64 v[36:37], v[84:85], -v[68:69]
	v_add_f64 v[68:69], v[123:124], -v[105:106]
	v_mul_f64 v[44:45], v[72:73], v[113:114]
	v_add_co_u32 v113, vcc_lo, 0x1000, v30
	v_add_co_ci_u32_e32 v114, vcc_lo, 0, v31, vcc_lo
	s_waitcnt vmcnt(9)
	v_fma_f64 v[62:63], v[52:53], v[117:118], -v[111:112]
	v_fma_f64 v[105:106], v[123:124], v[117:118], -v[48:49]
	global_load_b64 v[111:112], v[107:108], off offset:832
	global_load_b64 v[4:5], v[56:57], off offset:-3296
	global_load_b64 v[48:49], v[82:83], off offset:-3296
	v_mul_f64 v[52:53], v[117:118], v[115:116]
	global_load_b64 v[42:43], v[119:120], off offset:-3296
	global_load_b64 v[50:51], v[127:128], off offset:-3296
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[123:124], s[8:9], s[6:7]
	v_fma_f64 v[84:85], v[117:118], v[109:110], -v[44:45]
	v_fma_f64 v[109:110], v[117:118], v[74:75], v[52:53]
	global_load_b64 v[44:45], v[129:130], off offset:3296
	global_load_b64 v[52:53], v[46:47], off offset:3296
	global_load_b64 v[46:47], v[70:71], off offset:3296
	v_add_f64 v[74:75], v[105:106], v[74:75]
	s_waitcnt vmcnt(16)
	v_fma_f64 v[90:91], -v[72:73], v[90:91], v[109:110]
	s_waitcnt vmcnt(14)
	v_mul_f64 v[56:57], v[125:126], v[86:87]
	s_waitcnt vmcnt(13)
	v_mul_f64 v[82:83], v[101:102], v[86:87]
	s_waitcnt vmcnt(12)
	v_mul_f64 v[103:104], v[86:87], v[103:104]
	s_waitcnt vmcnt(10)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[115:116], v[80:81], v[121:122], -v[56:57]
	v_add_co_u32 v80, vcc_lo, 0x1000, v34
	v_add_co_ci_u32_e32 v81, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v119, vcc_lo, 0xfffff000, v30
	v_add_co_ci_u32_e32 v120, vcc_lo, -1, v31, vcc_lo
	s_waitcnt vmcnt(8)
	v_add_f64 v[101:102], v[66:67], -v[101:102]
	v_fma_f64 v[117:118], v[66:67], v[121:122], -v[82:83]
	global_load_b64 v[56:57], v[107:108], off offset:3296
	s_clause 0x2
	global_load_b64 v[70:71], v[113:114], off offset:832
	global_load_b64 v[66:67], v[113:114], off offset:3296
	global_load_b64 v[82:83], v[119:120], off offset:-3296
	v_add_co_u32 v107, vcc_lo, 0xfffff000, v34
	v_add_co_ci_u32_e32 v108, vcc_lo, -1, v35, vcc_lo
	v_add_f64 v[74:75], v[74:75], -v[98:99]
	s_waitcnt vmcnt(11)
	v_fma_f64 v[103:104], v[121:122], v[111:112], -v[103:104]
	s_waitcnt vmcnt(2)
	v_mul_f64 v[111:112], v[121:122], v[70:71]
	s_clause 0x2
	global_load_b64 v[113:114], v[80:81], off offset:832
	global_load_b64 v[80:81], v[80:81], off offset:3296
	global_load_b64 v[70:71], v[107:108], off offset:-3296
	global_load_b64 v[105:106], v[119:120], off offset:-832
	global_load_b64 v[107:108], v[107:108], off offset:-832
	s_waitcnt vmcnt(4)
	v_fma_f64 v[111:112], v[121:122], v[113:114], v[111:112]
	v_mul_f64 v[121:122], s[8:9], s[12:13]
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[105:106], -v[86:87], v[105:106], v[111:112]
	v_mul_f64 v[96:97], v[121:122], v[96:97]
	v_mul_f64 v[54:55], v[121:122], v[54:55]
	v_mul_f64 v[64:65], v[121:122], v[64:65]
	v_mul_f64 v[92:93], v[121:122], v[92:93]
	v_add_nc_u32_e32 v111, -1, v100
	v_mul_f64 v[88:89], v[121:122], v[88:89]
	v_add_nc_u32_e32 v112, 1, v100
	v_fma_f64 v[94:95], v[123:124], v[94:95], -v[96:97]
	v_add_f64 v[96:97], v[117:118], v[113:114]
	v_fma_f64 v[109:110], v[123:124], v[40:41], -v[54:55]
	v_mul_f64 v[40:41], s[10:11], s[12:13]
	v_fma_f64 v[60:61], v[123:124], v[60:61], -v[64:65]
	v_fma_f64 v[54:55], -v[72:73], v[98:99], v[90:91]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[64:65], -v[86:87], v[107:108], v[105:106]
	v_mad_i64_i32 v[86:87], null, 0xb9480, v111, s[18:19]
	v_add_nc_u32_e32 v114, -2, v100
	v_add_nc_u32_e32 v113, 2, v100
	v_mul_f64 v[72:73], s[10:11], s[6:7]
	v_fma_f64 v[78:79], v[123:124], v[78:79], -v[92:93]
	v_fma_f64 v[76:77], v[123:124], v[76:77], -v[88:89]
	v_mad_i64_i32 v[105:106], null, 0xb9480, v114, s[18:19]
	v_add_co_u32 v111, vcc_lo, v86, v20
	v_mad_u64_u32 v[98:99], null, 0xb9480, v113, s[18:19]
	v_add_f64 v[90:91], v[96:97], -v[107:108]
	v_mad_u64_u32 v[96:97], null, 0xb9480, v112, s[18:19]
	v_add_co_ci_u32_e32 v112, vcc_lo, v87, v21, vcc_lo
	v_mul_f64 v[86:87], v[40:41], v[101:102]
	v_mul_f64 v[103:104], v[40:41], v[103:104]
	v_mul_f64 v[64:65], v[40:41], v[64:65]
	v_mul_f64 v[107:108], s[8:9], s[2:3]
	v_add_co_u32 v117, vcc_lo, v96, v20
	v_add_co_ci_u32_e32 v118, vcc_lo, v97, v21, vcc_lo
	v_add_co_u32 v105, vcc_lo, v105, v20
	v_add_co_ci_u32_e32 v106, vcc_lo, v106, v21, vcc_lo
	v_add_co_u32 v113, vcc_lo, v98, v20
	v_add_co_ci_u32_e32 v114, vcc_lo, v99, v21, vcc_lo
	v_add_co_u32 v96, vcc_lo, v111, v24
	v_add_co_ci_u32_e32 v97, vcc_lo, v112, v25, vcc_lo
	v_mul_f64 v[98:99], v[40:41], v[115:116]
	v_add_co_u32 v101, vcc_lo, v105, v24
	v_add_co_ci_u32_e32 v102, vcc_lo, v106, v25, vcc_lo
	v_add_co_u32 v105, vcc_lo, v113, v24
	v_add_co_ci_u32_e32 v106, vcc_lo, v114, v25, vcc_lo
	v_mul_f64 v[90:91], v[40:41], v[90:91]
	v_add_co_u32 v40, vcc_lo, 0xffffe000, v26
	v_add_co_ci_u32_e32 v41, vcc_lo, -1, v27, vcc_lo
	v_add_co_u32 v92, vcc_lo, 0x2000, v26
	v_add_co_ci_u32_e32 v93, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v88, vcc_lo, 0xffe8e000, v32
	v_add_co_ci_u32_e32 v89, vcc_lo, -1, v33, vcc_lo
	global_load_b64 v[101:102], v[101:102], off
	global_load_b64 v[113:114], v[40:41], off offset:-1664
	global_load_b64 v[40:41], v[58:59], off offset:-1664
	global_load_b64 v[88:89], v[88:89], off offset:-2304
	v_add_co_u32 v111, vcc_lo, 0xfff47000, v26
	v_add_co_ci_u32_e32 v112, vcc_lo, -1, v27, vcc_lo
	v_fma_f64 v[68:69], v[72:73], v[68:69], -v[86:87]
	v_add_co_u32 v86, vcc_lo, 0xffe8e000, v26
	v_add_co_ci_u32_e32 v87, vcc_lo, -1, v27, vcc_lo
	v_fma_f64 v[84:85], v[72:73], v[84:85], -v[103:104]
	global_load_b64 v[58:59], v[96:97], off
	global_load_b64 v[96:97], v[111:112], off offset:-1152
	v_fma_f64 v[62:63], v[72:73], v[62:63], -v[98:99]
	v_add_co_u32 v98, vcc_lo, 0xffe8e000, v28
	v_add_co_ci_u32_e32 v99, vcc_lo, -1, v29, vcc_lo
	v_add_co_u32 v103, vcc_lo, 0xfff47000, v32
	v_add_co_ci_u32_e32 v104, vcc_lo, -1, v33, vcc_lo
	global_load_b64 v[86:87], v[86:87], off offset:-2304
	global_load_b64 v[98:99], v[98:99], off offset:-2304
	v_fma_f64 v[54:55], v[72:73], v[54:55], -v[64:65]
	v_fma_f64 v[16:17], v[107:108], v[16:17], v[109:110]
	v_fma_f64 v[6:7], v[107:108], v[6:7], v[76:77]
	v_fma_f64 v[74:75], v[72:73], v[74:75], -v[90:91]
	v_add_co_u32 v90, vcc_lo, 0x172000, v30
	v_add_co_ci_u32_e32 v91, vcc_lo, 0, v31, vcc_lo
	v_add_co_u32 v64, vcc_lo, 0x172000, v32
	global_load_b64 v[72:73], v[105:106], off
	global_load_b64 v[90:91], v[90:91], off offset:2304
	v_add_co_ci_u32_e32 v65, vcc_lo, 0, v33, vcc_lo
	global_load_b64 v[111:112], v[38:39], off offset:1664
	global_load_b64 v[92:93], v[92:93], off offset:1664
	s_clause 0x1
	global_load_b64 v[103:104], v[103:104], off offset:-1152
	global_load_b64 v[64:65], v[64:65], off offset:2304
	v_add_co_u32 v105, vcc_lo, v117, v24
	v_add_co_ci_u32_e32 v106, vcc_lo, v118, v25, vcc_lo
	v_add_co_u32 v115, vcc_lo, 0xb9000, v26
	v_add_co_ci_u32_e32 v116, vcc_lo, 0, v27, vcc_lo
	v_fma_f64 v[38:39], v[107:108], v[10:11], v[94:95]
	v_add_co_u32 v10, vcc_lo, 0x172000, v26
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v109, vcc_lo, 0x172000, v28
	v_add_co_ci_u32_e32 v110, vcc_lo, 0, v29, vcc_lo
	global_load_b64 v[94:95], v[105:106], off
	s_clause 0x1
	global_load_b64 v[105:106], v[115:116], off offset:1152
	global_load_b64 v[115:116], v[10:11], off offset:2304
	global_load_b64 v[109:110], v[109:110], off offset:2304
	v_fma_f64 v[10:11], v[107:108], v[18:19], v[60:61]
	v_add_co_u32 v60, vcc_lo, 0x172000, v34
	v_add_co_ci_u32_e32 v61, vcc_lo, 0, v35, vcc_lo
	v_fma_f64 v[18:19], v[107:108], v[36:37], v[78:79]
	v_add_co_u32 v36, vcc_lo, 0xb9000, v32
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v33, vcc_lo
	global_load_b64 v[60:61], v[60:61], off offset:2304
	global_load_b64 v[78:79], v[36:37], off offset:1152
	v_add_co_u32 v36, vcc_lo, 0xffe8e000, v30
	v_add_co_ci_u32_e32 v37, vcc_lo, -1, v31, vcc_lo
	v_add_nc_u32_e32 v117, -3, v100
	global_load_b64 v[76:77], v[36:37], off offset:-2304
	v_mul_f64 v[36:37], v[48:49], v[4:5]
	v_mul_f64 v[48:49], v[4:5], v[50:51]
	v_mul_f64 v[50:51], v[44:45], v[66:67]
	v_mul_f64 v[66:67], v[42:43], v[4:5]
	v_add_f64 v[42:43], v[46:47], -v[42:43]
	v_fma_f64 v[52:53], v[52:53], v[44:45], -v[36:37]
	v_add_co_u32 v36, vcc_lo, 0xb9000, v30
	v_add_co_ci_u32_e32 v37, vcc_lo, 0, v31, vcc_lo
	v_fma_f64 v[48:49], v[44:45], v[56:57], -v[48:49]
	v_fma_f64 v[50:51], v[44:45], v[80:81], v[50:51]
	v_fma_f64 v[44:45], v[46:47], v[44:45], -v[66:67]
	global_load_b64 v[107:108], v[36:37], off offset:1152
	v_add_co_u32 v66, vcc_lo, 0xb9000, v34
	v_add_co_ci_u32_e32 v67, vcc_lo, 0, v35, vcc_lo
	global_load_b64 v[66:67], v[66:67], off offset:1152
	v_fma_f64 v[50:51], -v[4:5], v[82:83], v[50:51]
	v_add_f64 v[44:45], v[44:45], v[80:81]
	v_mad_i64_i32 v[80:81], null, 0xb9480, v117, s[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], -v[4:5], v[70:71], v[50:51]
	v_add_f64 v[44:45], v[44:45], -v[70:71]
	s_waitcnt vmcnt(20)
	v_mul_f64 v[36:37], v[113:114], v[40:41]
	s_waitcnt vmcnt(19)
	v_mul_f64 v[56:57], v[88:89], v[101:102]
	s_waitcnt vmcnt(17)
	v_mul_f64 v[96:97], v[96:97], v[58:59]
	s_waitcnt vmcnt(16)
	v_mul_f64 v[86:87], v[86:87], v[101:102]
	s_waitcnt vmcnt(15)
	v_mul_f64 v[46:47], v[101:102], v[98:99]
	v_add_co_u32 v98, vcc_lo, 0xfff47000, v30
	v_add_co_ci_u32_e32 v99, vcc_lo, -1, v31, vcc_lo
	global_load_b64 v[98:99], v[98:99], off offset:-1152
	s_waitcnt vmcnt(14)
	v_mul_f64 v[90:91], v[72:73], v[90:91]
	s_waitcnt vmcnt(10)
	v_add_f64 v[88:89], v[64:65], -v[88:89]
	v_fma_f64 v[36:37], v[92:93], v[111:112], -v[36:37]
	v_mul_f64 v[92:93], v[103:104], v[58:59]
	v_fma_f64 v[56:57], v[64:65], v[72:73], -v[56:57]
	v_add_co_u32 v64, vcc_lo, 0xffffe000, v28
	v_add_co_ci_u32_e32 v65, vcc_lo, -1, v29, vcc_lo
	v_add_co_u32 v82, vcc_lo, 0x2000, v30
	v_add_co_ci_u32_e32 v83, vcc_lo, 0, v31, vcc_lo
	global_load_b64 v[64:65], v[64:65], off offset:-1664
	global_load_b64 v[82:83], v[82:83], off offset:1664
	v_add_co_u32 v113, vcc_lo, 0xffe8e000, v34
	v_add_co_ci_u32_e32 v114, vcc_lo, -1, v35, vcc_lo
	s_waitcnt vmcnt(10)
	v_fma_f64 v[96:97], v[105:106], v[94:95], -v[96:97]
	v_mul_f64 v[105:106], s[10:11], s[2:3]
	s_waitcnt vmcnt(9)
	v_fma_f64 v[86:87], v[115:116], v[72:73], -v[86:87]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[46:47], v[72:73], v[109:110], -v[46:47]
	v_add_co_u32 v109, vcc_lo, 0xfff47000, v34
	v_add_co_ci_u32_e32 v110, vcc_lo, -1, v35, vcc_lo
	s_clause 0x1
	global_load_b64 v[113:114], v[113:114], off offset:-2304
	global_load_b64 v[109:110], v[109:110], off offset:-1152
	v_add_nc_u32_e32 v115, 3, v100
	s_waitcnt vmcnt(8)
	v_add_f64 v[103:104], v[78:79], -v[103:104]
	v_fma_f64 v[72:73], v[72:73], v[60:61], v[90:91]
	v_add_co_u32 v90, vcc_lo, 0xffffe000, v32
	v_add_co_ci_u32_e32 v91, vcc_lo, -1, v33, vcc_lo
	v_fma_f64 v[78:79], v[78:79], v[94:95], -v[92:93]
	v_add_co_u32 v92, vcc_lo, 0x2000, v28
	v_add_co_ci_u32_e32 v93, vcc_lo, 0, v29, vcc_lo
	v_add_f64 v[56:57], v[56:57], v[60:61]
	v_add_co_u32 v60, vcc_lo, 0xfff47000, v28
	v_add_co_ci_u32_e32 v61, vcc_lo, -1, v29, vcc_lo
	v_add_co_u32 v50, vcc_lo, 0x2000, v34
	v_add_co_ci_u32_e32 v51, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v80, vcc_lo, v80, v20
	global_load_b64 v[90:91], v[90:91], off offset:-1664
	s_clause 0x1
	global_load_b64 v[92:93], v[92:93], off offset:1664
	global_load_b64 v[60:61], v[60:61], off offset:-1152
	global_load_b64 v[50:51], v[50:51], off offset:1664
	v_add_co_ci_u32_e32 v81, vcc_lo, v81, v21, vcc_lo
	v_add_co_u32 v80, vcc_lo, v80, v24
	v_fma_f64 v[42:43], v[105:106], v[42:43], v[68:69]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v81, vcc_lo, v81, v25, vcc_lo
	v_add_co_u32 v70, vcc_lo, 0xffdd5000, v26
	v_add_co_ci_u32_e32 v71, vcc_lo, -1, v27, vcc_lo
	global_load_b64 v[80:81], v[80:81], off
	global_load_b64 v[70:71], v[70:71], off offset:-3456
	v_fma_f64 v[48:49], v[105:106], v[48:49], v[84:85]
	s_waitcnt vmcnt(13)
	v_fma_f64 v[72:73], -v[101:102], v[76:77], v[72:73]
	v_add_co_u32 v76, vcc_lo, 0x2000, v32
	v_add_co_ci_u32_e32 v77, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v68, vcc_lo, 0xb9000, v28
	v_mad_u64_u32 v[84:85], null, 0xb9480, v115, s[18:19]
	v_add_co_ci_u32_e32 v69, vcc_lo, 0, v29, vcc_lo
	v_fma_f64 v[52:53], v[105:106], v[52:53], v[62:63]
	v_add_co_u32 v62, vcc_lo, 0xffffe000, v30
	v_add_co_ci_u32_e32 v63, vcc_lo, -1, v31, vcc_lo
	v_add_co_u32 v84, vcc_lo, v84, v20
	global_load_b64 v[76:77], v[76:77], off offset:1664
	global_load_b64 v[68:69], v[68:69], off offset:1152
	global_load_b64 v[62:63], v[62:63], off offset:-1664
	v_add_co_ci_u32_e32 v85, vcc_lo, v85, v21, vcc_lo
	v_add_co_u32 v84, vcc_lo, v84, v24
	v_fma_f64 v[44:45], v[105:106], v[44:45], v[74:75]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v85, vcc_lo, v85, v25, vcc_lo
	v_add_co_u32 v74, vcc_lo, 0x22b000, v26
	v_add_co_ci_u32_e32 v75, vcc_lo, 0, v27, vcc_lo
	global_load_b64 v[84:85], v[84:85], off
	global_load_b64 v[74:75], v[74:75], off offset:3456
	s_waitcnt vmcnt(17)
	v_mul_f64 v[107:108], v[94:95], v[107:108]
	v_add_nc_u32_e32 v115, -4, v100
	v_add_nc_u32_e32 v100, 4, v100
	v_fma_f64 v[4:5], v[105:106], v[4:5], v[54:55]
	s_waitcnt vmcnt(16)
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[107:108], v[94:95], v[66:67], v[107:108]
	v_add_f64 v[66:67], v[78:79], v[66:67]
	s_waitcnt vmcnt(15)
	v_fma_f64 v[98:99], -v[58:59], v[98:99], v[107:108]
	v_mul_f64 v[107:108], s[14:15], s[12:13]
	s_waitcnt vmcnt(14)
	v_mul_f64 v[78:79], v[64:65], v[40:41]
	s_waitcnt vmcnt(13)
	v_mul_f64 v[82:83], v[111:112], v[82:83]
	s_waitcnt vmcnt(12)
	v_fma_f64 v[72:73], -v[101:102], v[113:114], v[72:73]
	v_add_f64 v[56:57], v[56:57], -v[113:114]
	v_mul_f64 v[113:114], s[14:15], s[6:7]
	v_mul_f64 v[86:87], v[107:108], v[86:87]
	v_mul_f64 v[88:89], v[107:108], v[88:89]
	v_add_co_u32 v101, vcc_lo, 0xffffe000, v34
	v_add_co_ci_u32_e32 v102, vcc_lo, -1, v35, vcc_lo
	v_mul_f64 v[46:47], v[107:108], v[46:47]
	s_waitcnt vmcnt(11)
	v_add_f64 v[66:67], v[66:67], -v[109:110]
	s_mov_b32 s6, 0x3126e979
	global_load_b64 v[101:102], v[101:102], off offset:-1664
	s_mov_b32 s7, 0x3f6cac08
	s_waitcnt vmcnt(11)
	v_mul_f64 v[90:91], v[40:41], v[90:91]
	s_waitcnt vmcnt(10)
	v_fma_f64 v[78:79], v[92:93], v[111:112], -v[78:79]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[60:61], v[58:59], v[60:61]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[82:83], v[111:112], v[50:51], v[82:83]
	v_fma_f64 v[58:59], -v[58:59], v[109:110], v[98:99]
	v_add_f64 v[64:65], v[92:93], -v[64:65]
	v_mul_f64 v[92:93], s[10:11], s[6:7]
	v_mul_f64 v[56:57], v[107:108], v[56:57]
	s_waitcnt vmcnt(6)
	v_mul_f64 v[70:71], v[70:71], v[80:81]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[76:77], v[111:112], v[76:77], -v[90:91]
	v_add_f64 v[50:51], v[78:79], v[50:51]
	v_fma_f64 v[78:79], v[113:114], v[96:97], -v[86:87]
	s_waitcnt vmcnt(3)
	v_fma_f64 v[62:63], -v[40:41], v[62:63], v[82:83]
	v_add_co_u32 v82, vcc_lo, 0x22b000, v32
	v_add_co_ci_u32_e32 v83, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v86, vcc_lo, 0xffdd5000, v32
	v_add_co_ci_u32_e32 v87, vcc_lo, -1, v33, vcc_lo
	v_fma_f64 v[60:61], v[94:95], v[68:69], -v[60:61]
	v_mul_f64 v[68:69], v[107:108], v[72:73]
	v_fma_f64 v[72:73], v[113:114], v[103:104], -v[88:89]
	v_add_co_u32 v88, vcc_lo, 0x2e5000, v32
	v_add_co_ci_u32_e32 v89, vcc_lo, 0, v33, vcc_lo
	v_add_co_u32 v32, vcc_lo, 0xffd1b000, v32
	v_add_co_ci_u32_e32 v33, vcc_lo, -1, v33, vcc_lo
	s_waitcnt vmcnt(1)
	v_fma_f64 v[70:71], v[74:75], v[84:85], -v[70:71]
	v_add_co_u32 v74, vcc_lo, 0x22b000, v28
	v_add_co_ci_u32_e32 v75, vcc_lo, 0, v29, vcc_lo
	v_add_co_u32 v90, vcc_lo, 0xffdd5000, v28
	v_add_co_ci_u32_e32 v91, vcc_lo, -1, v29, vcc_lo
	v_add_co_u32 v94, vcc_lo, 0x2e5000, v28
	v_add_co_ci_u32_e32 v95, vcc_lo, 0, v29, vcc_lo
	v_add_co_u32 v28, vcc_lo, 0xffd1b000, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, -1, v29, vcc_lo
	v_add_co_u32 v96, vcc_lo, 0x22b000, v34
	v_add_co_ci_u32_e32 v97, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v98, vcc_lo, 0xffdd5000, v34
	v_add_co_ci_u32_e32 v99, vcc_lo, -1, v35, vcc_lo
	v_add_co_u32 v103, vcc_lo, 0x2e5000, v34
	v_add_co_ci_u32_e32 v104, vcc_lo, 0, v35, vcc_lo
	v_add_co_u32 v34, vcc_lo, 0xffd1b000, v34
	v_add_co_ci_u32_e32 v35, vcc_lo, -1, v35, vcc_lo
	v_add_co_u32 v107, vcc_lo, 0x22b000, v30
	v_add_co_ci_u32_e32 v108, vcc_lo, 0, v31, vcc_lo
	v_add_co_u32 v109, vcc_lo, 0xffdd5000, v30
	v_add_co_ci_u32_e32 v110, vcc_lo, -1, v31, vcc_lo
	global_load_b64 v[90:91], v[90:91], off offset:-3456
	global_load_b64 v[107:108], v[107:108], off offset:3456
	s_clause 0x1
	global_load_b64 v[94:95], v[94:95], off offset:512
	global_load_b64 v[74:75], v[74:75], off offset:3456
	global_load_b64 v[86:87], v[86:87], off offset:-3456
	global_load_b64 v[96:97], v[96:97], off offset:3456
	s_clause 0x1
	global_load_b64 v[88:89], v[88:89], off offset:512
	global_load_b64 v[82:83], v[82:83], off offset:3456
	global_load_b64 v[109:110], v[109:110], off offset:-3456
	v_add_co_u32 v111, vcc_lo, 0x2e5000, v30
	v_add_co_ci_u32_e32 v112, vcc_lo, 0, v31, vcc_lo
	v_add_co_u32 v30, vcc_lo, 0xffd1b000, v30
	v_add_co_ci_u32_e32 v31, vcc_lo, -1, v31, vcc_lo
	s_clause 0x1
	global_load_b64 v[111:112], v[111:112], off offset:512
	global_load_b64 v[30:31], v[30:31], off offset:-512
	s_clause 0x2
	global_load_b64 v[98:99], v[98:99], off offset:-3456
	global_load_b64 v[103:104], v[103:104], off offset:512
	global_load_b64 v[34:35], v[34:35], off offset:-512
	v_fma_f64 v[46:47], v[113:114], v[60:61], -v[46:47]
	v_mul_f64 v[60:61], s[8:9], s[6:7]
	v_fma_f64 v[54:55], v[113:114], v[58:59], -v[68:69]
	v_fma_f64 v[56:57], v[113:114], v[66:67], -v[56:57]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[8:9], -v[60:61], v[8:9], v[38:39]
	v_fma_f64 v[2:3], -v[60:61], v[2:3], v[18:19]
	v_fma_f64 v[12:13], -v[60:61], v[12:13], v[16:17]
	v_fma_f64 v[16:17], -v[92:93], v[64:65], v[42:43]
	v_fma_f64 v[18:19], -v[92:93], v[36:37], v[52:53]
	v_mul_f64 v[42:43], s[14:15], s[6:7]
	v_fma_f64 v[0:1], -v[60:61], v[0:1], v[6:7]
	v_fma_f64 v[10:11], -v[60:61], v[14:15], v[10:11]
	v_fma_f64 v[14:15], -v[92:93], v[76:77], v[48:49]
	v_add_f64 v[8:9], v[8:9], -v[16:17]
	v_add_f64 v[2:3], v[2:3], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	s_waitcnt vmcnt(14)
	v_add_f64 v[50:51], v[50:51], -v[101:102]
	v_fma_f64 v[40:41], -v[40:41], v[101:102], v[62:63]
	v_fma_f64 v[36:37], -v[92:93], v[50:51], v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[92:93], v[40:41], v[4:5]
	v_add_f64 v[12:13], v[12:13], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[0:1], v[0:1], -v[4:5]
	s_waitcnt vmcnt(13)
	v_mul_f64 v[90:91], v[80:81], v[90:91]
	s_waitcnt vmcnt(12)
	v_mul_f64 v[107:108], v[84:85], v[107:108]
	s_waitcnt vmcnt(10)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[74:75], v[84:85], v[74:75], -v[90:91]
	s_waitcnt vmcnt(9)
	v_mul_f64 v[90:91], v[86:87], v[80:81]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[107:108], v[84:85], v[96:97], v[107:108]
	s_waitcnt vmcnt(6)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[84:85], v[82:83], v[84:85], -v[90:91]
	s_waitcnt vmcnt(5)
	v_fma_f64 v[90:91], -v[80:81], v[109:110], v[107:108]
	v_mad_i64_i32 v[109:110], null, 0xb9480, v115, s[18:19]
	v_add_co_u32 v107, vcc_lo, 0x2e5000, v26
	v_add_co_ci_u32_e32 v108, vcc_lo, 0, v27, vcc_lo
	v_add_co_u32 v26, vcc_lo, 0xffd1b000, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, -1, v27, vcc_lo
	v_add_co_u32 v115, vcc_lo, v109, v20
	v_add_co_ci_u32_e32 v116, vcc_lo, v110, v21, vcc_lo
	v_mad_u64_u32 v[109:110], null, 0xb9480, v100, s[18:19]
	v_add_f64 v[82:83], v[82:83], -v[86:87]
	v_mul_f64 v[86:87], s[14:15], s[2:3]
	s_load_b256 s[8:15], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v100, vcc_lo, v109, v20
	v_add_co_ci_u32_e32 v117, vcc_lo, v110, v21, vcc_lo
	v_add_co_u32 v109, vcc_lo, v115, v24
	v_add_co_ci_u32_e32 v110, vcc_lo, v116, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v115, vcc_lo, v100, v24
	v_add_co_ci_u32_e32 v116, vcc_lo, v117, v25, vcc_lo
	global_load_b64 v[32:33], v[32:33], off offset:-512
	s_clause 0x1
	global_load_b64 v[109:110], v[109:110], off
	global_load_b64 v[115:116], v[115:116], off
	global_load_b64 v[26:27], v[26:27], off offset:-512
	global_load_b64 v[28:29], v[28:29], off offset:-512
	global_load_b64 v[107:108], v[107:108], off offset:512
	v_add_f64 v[84:85], v[84:85], v[96:97]
	s_waitcnt vmcnt(8)
	v_fma_f64 v[58:59], -v[80:81], v[98:99], v[90:91]
	v_fma_f64 v[38:39], v[86:87], v[82:83], v[72:73]
	v_fma_f64 v[44:45], v[86:87], v[70:71], v[78:79]
	v_fma_f64 v[46:47], v[86:87], v[74:75], v[46:47]
	v_add_f64 v[66:67], v[84:85], -v[98:99]
	v_fma_f64 v[6:7], v[86:87], v[58:59], v[54:55]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[48:49], v[86:87], v[66:67], v[56:57]
	s_waitcnt vmcnt(4)
	v_mul_f64 v[96:97], v[32:33], v[109:110]
	s_waitcnt vmcnt(3)
	v_mul_f64 v[111:112], v[115:116], v[111:112]
	s_waitcnt vmcnt(2)
	v_mul_f64 v[26:27], v[26:27], v[109:110]
	s_waitcnt vmcnt(1)
	v_mul_f64 v[28:29], v[109:110], v[28:29]
	v_add_f64 v[32:33], v[88:89], -v[32:33]
	v_fma_f64 v[96:97], v[88:89], v[115:116], -v[96:97]
	v_fma_f64 v[111:112], v[115:116], v[103:104], v[111:112]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[26:27], v[107:108], v[115:116], -v[26:27]
	v_fma_f64 v[28:29], v[115:116], v[94:95], -v[28:29]
	v_fma_f64 v[16:17], -v[42:43], v[32:33], v[38:39]
	v_add_f64 v[84:85], v[96:97], v[103:104]
	v_fma_f64 v[30:31], -v[109:110], v[30:31], v[111:112]
	v_fma_f64 v[18:19], -v[42:43], v[26:27], v[44:45]
	v_fma_f64 v[26:27], -v[42:43], v[28:29], v[46:47]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[50:51], v[84:85], -v[34:35]
	v_fma_f64 v[30:31], -v[109:110], v[34:35], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[2:3], v[2:3], -v[18:19]
	v_fma_f64 v[14:15], -v[42:43], v[50:51], v[48:49]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[4:5], -v[42:43], v[30:31], v[6:7]
	v_add_f64 v[6:7], v[8:9], -v[16:17]
	v_add_f64 v[8:9], v[12:13], -v[26:27]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v12, vcc_lo, s8, v22
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v12, v20
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v21, vcc_lo
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_add_f64 v[0:1], v[0:1], -v[4:5]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, v12, v24
	v_add_co_ci_u32_e32 v5, vcc_lo, v13, v25, vcc_lo
	v_add_co_u32 v12, vcc_lo, s10, v22
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v23, vcc_lo
	v_add_co_u32 v14, vcc_lo, s12, v22
	v_add_co_ci_u32_e32 v15, vcc_lo, s13, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, v12, v20
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, v14, v20
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, v12, v24
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, v14, v24
	v_add_co_ci_u32_e32 v15, vcc_lo, v15, v25, vcc_lo
	v_add_co_u32 v16, vcc_lo, s14, v22
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v23, vcc_lo
	v_add_co_u32 v18, vcc_lo, s4, v22
	v_add_co_ci_u32_e32 v19, vcc_lo, s5, v23, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, v16, v20
	v_add_co_ci_u32_e32 v17, vcc_lo, v17, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, v18, v20
	v_add_co_ci_u32_e32 v19, vcc_lo, v19, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v16, vcc_lo, v16, v24
	v_add_co_ci_u32_e32 v17, vcc_lo, v17, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v18, vcc_lo, v18, v24
	v_add_co_ci_u32_e32 v19, vcc_lo, v19, v25, vcc_lo
	global_store_b64 v[4:5], v[6:7], off
	global_store_b64 v[12:13], v[2:3], off
	global_store_b64 v[14:15], v[8:9], off
	global_store_b64 v[16:17], v[10:11], off
	global_store_b64 v[18:19], v[0:1], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 400
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 131
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii, .Lfunc_end0-_Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5480
; NumSgprs: 22
; NumVgprs: 131
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 16
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 131
; Occupancy: 10
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .actual_access:  write_only
        .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .offset:         104
        .size:           8
        .value_kind:     by_value
      - .offset:         112
        .size:           8
        .value_kind:     by_value
      - .offset:         120
        .size:           8
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     by_value
      - .offset:         132
        .size:           4
        .value_kind:     by_value
      - .offset:         136
        .size:           4
        .value_kind:     by_value
      - .offset:         144
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         148
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         152
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         156
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         158
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         160
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         162
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         164
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         166
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         200
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         208
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 400
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z7hyptermPdS_S_S_S_S_S_S_S_S_S_S_S_dddiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     131
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
