#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>

#define BLOCK_SIZE 16
#define GRID_SIZE 1

int printMatrix(int *A, int N){
  if(N > 8) return 0;
  int i, j;
  printf("\nA = \n\t");
  for(i = 0; i < N; ++i){
    for(j = 0; j < N; ++j){
      if(j < N-1) printf("%d, ", A[i * N + j]);
      else printf("%d;\n\t", A[i * N + j]);
      //printf("%d, ", A[i * N + j], j < N-1 ? ", " : ";\n\t");
    }
  }
  return 0;
}

__global__ void gpu_matrixNorm(int *A, int *B, int N){
  
  int row, col;
  float mu, sigma;
  mu = 0.0;
  col = blockIdx.x * blockDim.x + threadIdx.x;
  if(col < N){
    for(row = 0; row < N; ++row){
      mu += A[row * N + col];
    }
    mu /= (float) N;
    sigma = 0.0;
    for(row = 0; row < N; ++row){
      sigma += powf(A[row * N + col] - mu, 2.0);
    }
    sigma /= (float) N;
    sigma = sqrt(sigma);
    for(row = 0; row < N; ++row){
      if(sigma == 0.0) B[row * N + col] = 0.0;
      else B[row * N + col] = (A[row * N + col] - mu) / sigma;
    }
  }
}

int matrixNorm(){
  int N = 6000; //Matrix size
  
  srand(300); // Fixed Seed

  // allocate memory in host RAM
  int *A, *B;
  A = (int*)malloc(N*N*sizeof(int));
  B = (int*)malloc(N*N*sizeof(int)); 
  //generate matrix A
  for(int i = 0; i < N; ++i){
    for(int j = 0; j < N; ++j){
      A[i * N + j] = rand() / 32768;
    }
  }
  printMatrix(A, N);
  printMatrix(B, N);
  
  //allocate memory on the device
  int *d_a, *d_b;
  cudaMalloc(&d_a, sizeof(int)*N*N);
  cudaMalloc(&d_b, sizeof(int)*N*N);
  int i, j;
  for(i=0; i<N; i++){
    for(j=0; j<N; j++){
      cudaMemcpy(&d_a[i*N+j], (void*)&A[i*N+j], sizeof(int), cudaMemcpyHostToDevice);
    }
  }
  // Call Matrix Norm function
  int numThreads = 128;
  int numBlocks = ((N*N) + numThreads-1) / numThreads;
  gpu_matrixNorm<<<numBlocks, numThreads>>>(d_a, d_b, N);
  
  for(i=0; i<N; i++){
    for(j=0; j<N; j++){
      cudaMemcpy((void *)&B[i*N+j], &d_b[i*N+j], sizeof(int), cudaMemcpyDeviceToHost);
    }
  }
  printMatrix(B, N);
  
  cudaFree(d_a);
  cudaFree(d_b);
  free(A);
  free(B);
  return 0;
}

int main(int argc, char const *argv[]){
  struct timeval etstart, etstop;  /* Elapsed times using gettimeofday() */
  struct timezone tzdummy;
  unsigned long long time;
  gettimeofday(&etstart, &tzdummy);

  matrixNorm();

  gettimeofday(&etstop, &tzdummy);
  time = (unsigned long long)(etstop.tv_sec - etstart.tv_sec)*1000000+(etstop.tv_usec - etstart.tv_usec);
  printf("Runtime = %g ms.\n", (float)time/(float)1000);
}

	.file	"tmpxft_0033d9e8_00000000-6_matrixNorm.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\nA = \n\t"
.LC1:
	.string	"%d, "
.LC2:
	.string	"%d;\n\t"
	.text
	.globl	_Z11printMatrixPii
	.type	_Z11printMatrixPii, @function
_Z11printMatrixPii:
.LFB2027:
	.cfi_startproc
	endbr64
	cmpl	$8, %esi
	jg	.L13
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%eax, %eax
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	movl	$2, %edi
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	leaq	.LC0(%rip), %rsi
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	__printf_chk@PLT
	movslq	%ebx, %rax
	movq	%rax, 8(%rsp)
.L4:
	cmpl	%ebp, %ebx
	jle	.L18
	movslq	%r12d, %rax
	xorl	%r14d, %r14d
	leaq	0(%r13,%rax,4), %r15
.L7:
	leal	-1(%rbx), %eax
	movl	(%r15,%r14,4), %edx
	leaq	.LC1(%rip), %rsi
	cmpl	%r14d, %eax
	jg	.L16
	leaq	.LC2(%rip), %rsi
.L16:
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%r14
	call	__printf_chk@PLT
	cmpq	%r14, 8(%rsp)
	jne	.L7
	incl	%ebp
	addl	%ebx, %r12d
	jmp	.L4
.L18:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
.L13:
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	.cfi_restore 13
	.cfi_restore 14
	.cfi_restore 15
	xorl	%eax, %eax
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11printMatrixPii, .-_Z11printMatrixPii
	.globl	_Z37__device_stub__Z14gpu_matrixNormPiS_iPiS_i
	.type	_Z37__device_stub__Z14gpu_matrixNormPiS_iPiS_i, @function
_Z37__device_stub__Z14gpu_matrixNormPiS_iPiS_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z14gpu_matrixNormPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L19:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z37__device_stub__Z14gpu_matrixNormPiS_iPiS_i, .-_Z37__device_stub__Z14gpu_matrixNormPiS_iPiS_i
	.globl	_Z14gpu_matrixNormPiS_i
	.type	_Z14gpu_matrixNormPiS_i, @function
_Z14gpu_matrixNormPiS_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z14gpu_matrixNormPiS_iPiS_i
	.cfi_endproc
.LFE2055:
	.size	_Z14gpu_matrixNormPiS_i, .-_Z14gpu_matrixNormPiS_i
	.globl	_Z10matrixNormv
	.type	_Z10matrixNormv, @function
_Z10matrixNormv:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$300, %edi
	movl	$32768, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	srand@PLT
	movl	$144000000, %edi
	call	malloc@PLT
	movl	$144000000, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rax, %rbp
.L25:
	imulq	$24000, %r13, %r14
	xorl	%r12d, %r12d
	addq	%rbx, %r14
.L26:
	call	rand@PLT
	cltd
	idivl	%r15d
	movl	%eax, (%r14,%r12,4)
	incq	%r12
	cmpq	$6000, %r12
	jne	.L26
	incq	%r13
	cmpq	$6000, %r13
	jne	.L25
	movq	%rsp, %rdi
	movl	$144000000, %esi
	xorl	%r13d, %r13d
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$144000000, %esi
	call	cudaMalloc@PLT
.L28:
	imulq	$24000, %r13, %r12
	movl	$6000, %r14d
.L29:
	movq	(%rsp), %rdi
	leaq	(%rbx,%r12), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	addq	%r12, %rdi
	addq	$4, %r12
	call	cudaMemcpy@PLT
	decl	%r14d
	jne	.L29
	incq	%r13
	cmpq	$6000, %r13
	jne	.L28
	movl	$33554433, %edx
	movl	$2147624273, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$7, %rdx
	addq	%rdi, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$6000, %edx
	call	_Z37__device_stub__Z14gpu_matrixNormPiS_iPiS_i
.L31:
	xorl	%r13d, %r13d
.L32:
	imulq	$24000, %r13, %r12
	movl	$6000, %r14d
.L33:
	movq	8(%rsp), %rsi
	leaq	0(%rbp,%r12), %rdi
	movl	$2, %ecx
	movl	$4, %edx
	addq	%r12, %rsi
	addq	$4, %r12
	call	cudaMemcpy@PLT
	decl	%r14d
	jne	.L33
	incq	%r13
	cmpq	$6000, %r13
	jne	.L32
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10matrixNormv, .-_Z10matrixNormv
	.section	.rodata.str1.1
.LC4:
	.string	"Runtime = %g ms.\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	subq	$48, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movq	%rsp, %rbx
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	gettimeofday@PLT
	call	_Z10matrixNormv
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	gettimeofday@PLT
	movq	24(%rsp), %rax
	subq	8(%rsp), %rax
	imulq	$1000000, %rax, %rax
	addq	32(%rsp), %rax
	subq	16(%rsp), %rax
	js	.L41
	cvtsi2ssq	%rax, %xmm0
	jmp	.L42
.L41:
	movq	%rax, %rdx
	andl	$1, %eax
	shrq	%rdx
	orq	%rax, %rdx
	cvtsi2ssq	%rdx, %xmm0
	addss	%xmm0, %xmm0
.L42:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	divss	.LC3(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$48, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z14gpu_matrixNormPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14gpu_matrixNormPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC3:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>

#define BLOCK_SIZE 16
#define GRID_SIZE 1

int printMatrix(int *A, int N){
  if(N > 8) return 0;
  int i, j;
  printf("\nA = \n\t");
  for(i = 0; i < N; ++i){
    for(j = 0; j < N; ++j){
      if(j < N-1) printf("%d, ", A[i * N + j]);
      else printf("%d;\n\t", A[i * N + j]);
      //printf("%d, ", A[i * N + j], j < N-1 ? ", " : ";\n\t");
    }
  }
  return 0;
}

__global__ void gpu_matrixNorm(int *A, int *B, int N){
  
  int row, col;
  float mu, sigma;
  mu = 0.0;
  col = blockIdx.x * blockDim.x + threadIdx.x;
  if(col < N){
    for(row = 0; row < N; ++row){
      mu += A[row * N + col];
    }
    mu /= (float) N;
    sigma = 0.0;
    for(row = 0; row < N; ++row){
      sigma += powf(A[row * N + col] - mu, 2.0);
    }
    sigma /= (float) N;
    sigma = sqrt(sigma);
    for(row = 0; row < N; ++row){
      if(sigma == 0.0) B[row * N + col] = 0.0;
      else B[row * N + col] = (A[row * N + col] - mu) / sigma;
    }
  }
}

int matrixNorm(){
  int N = 6000; //Matrix size
  
  srand(300); // Fixed Seed

  // allocate memory in host RAM
  int *A, *B;
  A = (int*)malloc(N*N*sizeof(int));
  B = (int*)malloc(N*N*sizeof(int)); 
  //generate matrix A
  for(int i = 0; i < N; ++i){
    for(int j = 0; j < N; ++j){
      A[i * N + j] = rand() / 32768;
    }
  }
  printMatrix(A, N);
  printMatrix(B, N);
  
  //allocate memory on the device
  int *d_a, *d_b;
  hipMalloc(&d_a, sizeof(int)*N*N);
  hipMalloc(&d_b, sizeof(int)*N*N);
  int i, j;
  for(i=0; i<N; i++){
    for(j=0; j<N; j++){
      hipMemcpy(&d_a[i*N+j], (void*)&A[i*N+j], sizeof(int), hipMemcpyHostToDevice);
    }
  }
  // Call Matrix Norm function
  int numThreads = 128;
  int numBlocks = ((N*N) + numThreads-1) / numThreads;
  gpu_matrixNorm<<<numBlocks, numThreads>>>(d_a, d_b, N);
  
  for(i=0; i<N; i++){
    for(j=0; j<N; j++){
      hipMemcpy((void *)&B[i*N+j], &d_b[i*N+j], sizeof(int), hipMemcpyDeviceToHost);
    }
  }
  printMatrix(B, N);
  
  hipFree(d_a);
  hipFree(d_b);
  free(A);
  free(B);
  return 0;
}

int main(int argc, char const *argv[]){
  struct timeval etstart, etstop;  /* Elapsed times using gettimeofday() */
  struct timezone tzdummy;
  unsigned long long time;
  gettimeofday(&etstart, &tzdummy);

  matrixNorm();

  gettimeofday(&etstop, &tzdummy);
  time = (unsigned long long)(etstop.tv_sec - etstart.tv_sec)*1000000+(etstop.tv_usec - etstart.tv_usec);
  printf("Runtime = %g ms.\n", (float)time/(float)1000);
}

	.text
	.file	"matrixNorm.hip"
	.globl	_Z11printMatrixPii              # -- Begin function _Z11printMatrixPii
	.type	_Z11printMatrixPii,@function
_Z11printMatrixPii:                     # @_Z11printMatrixPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $esi killed $esi def $rsi
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movq	%rsi, (%rsp)                    # 8-byte Spill
	cmpl	$8, %esi
	jg	.LBB0_6
# %bb.1:
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	cmpl	$0, (%rsp)                      # 4-byte Folded Reload
	jle	.LBB0_6
# %bb.2:                                # %.preheader.lr.ph
	movq	(%rsp), %rax                    # 8-byte Reload
	leal	-1(%rax), %r15d
	movl	%eax, %r12d
	movl	$.L.str.1, %r13d
	xorl	%eax, %eax
	xorl	%r14d, %r14d
.LBB0_3:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_4 Depth 2
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	movl	%eax, %eax
	movq	16(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rbx
	xorl	%ebp, %ebp
.LBB0_4:                                #   Parent Loop BB0_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%r15, %rbp
	movl	$.L.str.2, %edi
	cmovbq	%r13, %rdi
	movl	(%rbx,%rbp,4), %esi
	xorl	%eax, %eax
	callq	printf
	incq	%rbp
	cmpq	%rbp, %r12
	jne	.LBB0_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_3 Depth=1
	incq	%r14
	movl	12(%rsp), %eax                  # 4-byte Reload
	addl	(%rsp), %eax                    # 4-byte Folded Reload
	cmpq	%r12, %r14
	jne	.LBB0_3
.LBB0_6:                                # %.loopexit
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z11printMatrixPii, .Lfunc_end0-_Z11printMatrixPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__gpu_matrixNormPiS_i # -- Begin function _Z29__device_stub__gpu_matrixNormPiS_i
	.type	_Z29__device_stub__gpu_matrixNormPiS_i,@function
_Z29__device_stub__gpu_matrixNormPiS_i: # @_Z29__device_stub__gpu_matrixNormPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14gpu_matrixNormPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__gpu_matrixNormPiS_i, .Lfunc_end1-_Z29__device_stub__gpu_matrixNormPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z10matrixNormv                 # -- Begin function _Z10matrixNormv
	.type	_Z10matrixNormv,@function
_Z10matrixNormv:                        # @_Z10matrixNormv
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$300, %edi                      # imm = 0x12C
	callq	srand
	movl	$144000000, %edi                # imm = 0x8954400
	callq	malloc
	movq	%rax, %rbx
	movl	$144000000, %edi                # imm = 0x8954400
	callq	malloc
	movq	%rax, %r14
	xorl	%r15d, %r15d
	movq	%rbx, %r12
.LBB2_1:                                # %.preheader68
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	xorl	%r13d, %r13d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	32767(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$15, %ecx
	movl	%ecx, (%r12,%r13,4)
	incq	%r13
	cmpq	$6000, %r13                     # imm = 0x1770
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%r15
	addq	$24000, %r12                    # imm = 0x5DC0
	cmpq	$6000, %r15                     # imm = 0x1770
	jne	.LBB2_1
# %bb.4:
	leaq	16(%rsp), %rdi
	movl	$144000000, %esi                # imm = 0x8954400
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$144000000, %esi                # imm = 0x8954400
	callq	hipMalloc
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
.LBB2_5:                                # %.preheader67
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_6 Depth 2
	movl	$6000, %r13d                    # imm = 0x1770
	movq	%r15, %rbp
.LBB2_6:                                #   Parent Loop BB2_5 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	16(%rsp), %rdi
	addq	%rbp, %rdi
	leaq	(%rbx,%rbp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	addq	$4, %rbp
	decq	%r13
	jne	.LBB2_6
# %bb.7:                                #   in Loop: Header=BB2_5 Depth=1
	incq	%r12
	addq	$24000, %r15                    # imm = 0x5DC0
	cmpq	$6000, %r12                     # imm = 0x1770
	jne	.LBB2_5
# %bb.8:
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	281122(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_10
# %bb.9:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$6000, %edx                     # imm = 0x1770
	callq	_Z29__device_stub__gpu_matrixNormPiS_i
.LBB2_10:                               # %.preheader.preheader
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
.LBB2_11:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_12 Depth 2
	movl	$6000, %r13d                    # imm = 0x1770
	movq	%r15, %rbp
.LBB2_12:                               #   Parent Loop BB2_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leaq	(%r14,%rbp), %rdi
	movq	8(%rsp), %rsi
	addq	%rbp, %rsi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	addq	$4, %rbp
	decq	%r13
	jne	.LBB2_12
# %bb.13:                               #   in Loop: Header=BB2_11 Depth=1
	incq	%r12
	addq	$24000, %r15                    # imm = 0x5DC0
	cmpq	$6000, %r12                     # imm = 0x1770
	jne	.LBB2_11
# %bb.14:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z10matrixNormv, .Lfunc_end2-_Z10matrixNormv
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	32(%rsp), %rbx
	leaq	8(%rsp), %r14
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	gettimeofday
	callq	_Z10matrixNormv
	leaq	16(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	gettimeofday
	movq	(%r15), %rcx
	movq	8(%r15), %rax
	subq	(%rbx), %rcx
	imulq	$1000000, %rcx, %rcx            # imm = 0xF4240
	subq	8(%rbx), %rax
	addq	%rcx, %rax
	js	.LBB3_1
# %bb.2:
	cvtsi2ss	%rax, %xmm0
	jmp	.LBB3_3
.LBB3_1:
	movq	%rax, %rcx
	shrq	%rcx
	andl	$1, %eax
	orq	%rcx, %rax
	cvtsi2ss	%rax, %xmm0
	addss	%xmm0, %xmm0
.LBB3_3:
	divss	.LCPI3_0(%rip), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14gpu_matrixNormPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\nA = \n\t"
	.size	.L.str, 8

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d, "
	.size	.L.str.1, 5

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d;\n\t"
	.size	.L.str.2, 6

	.type	_Z14gpu_matrixNormPiS_i,@object # @_Z14gpu_matrixNormPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z14gpu_matrixNormPiS_i
	.p2align	3, 0x0
_Z14gpu_matrixNormPiS_i:
	.quad	_Z29__device_stub__gpu_matrixNormPiS_i
	.size	_Z14gpu_matrixNormPiS_i, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"Runtime = %g ms.\n"
	.size	.L.str.3, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14gpu_matrixNormPiS_i"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__gpu_matrixNormPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14gpu_matrixNormPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14gpu_matrixNormPiS_i ; -- Begin function _Z14gpu_matrixNormPiS_i
	.globl	_Z14gpu_matrixNormPiS_i
	.p2align	8
	.type	_Z14gpu_matrixNormPiS_i,@function
_Z14gpu_matrixNormPiS_i:                ; @_Z14gpu_matrixNormPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s2, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_i32_e64 s2, v1
	s_cbranch_execz .LBB0_12
; %bb.1:                                ; %.preheader
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_cmp_gt_i32 s2, 0
	s_cselect_b32 s0, -1, 0
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v2, v1
	s_mov_b32 s1, s2
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_i32 s1, s1, -1
	s_cmp_lg_u32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_add_nc_u32_e32 v2, s2, v2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v3, v3
	v_add_f32_e32 v0, v0, v3
	s_cbranch_scc1 .LBB0_3
.LBB0_4:                                ; %._crit_edge
	v_cvt_f32_i32_e32 v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v2, null, v4, v4, v0
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v5, v3
	v_div_scale_f32 v5, vcc_lo, v0, v4, v0
	v_mul_f32_e32 v7, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v2, v7, v5
	v_fmac_f32_e32 v7, v6, v3
	v_cndmask_b32_e64 v6, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v2, v7, v5
	v_mov_b32_e32 v5, 0
	v_div_fmas_f32 v2, v2, v3, v7
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v0, v2, v4, v0
	s_cbranch_vccnz .LBB0_7
; %bb.5:                                ; %.lr.ph52.preheader
	v_mov_b32_e32 v2, v1
	s_mov_b32 s3, 0x3e76c4e1
	s_mov_b32 s8, s2
.LBB0_6:                                ; %.lr.ph52
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_i32 s8, s8, -1
	v_lshlrev_b64 v[7:8], 2, v[2:3]
	v_add_nc_u32_e32 v2, s2, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b32 v3, v[7:8], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v3, v0
	v_frexp_mant_f32_e64 v7, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v7
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	v_ldexp_f32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, 1.0, v7
	v_rcp_f32_e32 v9, v8
	v_add_f32_e32 v12, -1.0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_add_f32 v10, -1.0, v7 :: v_dual_sub_f32 v7, v7, v12
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v10, v9
	v_mul_f32_e32 v13, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v11, v8, -v13
	v_fmac_f32_e32 v8, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v13, v8
	v_dual_sub_f32 v12, v10, v7 :: v_dual_sub_f32 v13, v7, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v13, v8
	v_sub_f32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v10, v7
	v_add_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v12, v7
	v_mul_f32_e32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v11, v7
	v_sub_f32_e32 v9, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v10, v8, v8 :: v_dual_sub_f32 v7, v7, v9
	v_fma_f32 v9, v8, v8, -v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v7, v7
	v_fmac_f32_e32 v9, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v10, v9
	v_fmaak_f32 v12, s3, v11, 0x3e91f4c4
	v_sub_f32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v12, v11, v12, 0x3ecccdef :: v_dual_sub_f32 v9, v9, v10
	v_mul_f32_e32 v15, v8, v11
	v_mul_f32_e32 v13, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, v11, v8, -v15
	v_fma_f32 v10, v11, v12, -v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v10, v9, v12
	v_fmac_f32_e32 v16, v11, v7
	v_ldexp_f32 v7, v7, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v13, v10
	v_fmac_f32_e32 v16, v9, v8
	v_ldexp_f32 v8, v8, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v12, v13 :: v_dual_add_f32 v14, 0x3f2aaaaa, v12
	v_dual_sub_f32 v10, v10, v13 :: v_dual_add_f32 v13, 0xbf2aaaaa, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, 0x31739010, v10
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v12
	v_add_f32_e32 v9, v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v15, v16 :: v_dual_sub_f32 v12, v14, v9
	v_mul_f32_e32 v13, v11, v9
	v_sub_f32_e32 v14, v11, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v10, v12
	v_fma_f32 v12, v11, v9, -v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v16, v14
	v_fmac_f32_e32 v12, v11, v10
	v_frexp_exp_i32_f32_e32 v10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v14, v9
	v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v13, v12
	v_cvt_f32_i32_e32 v9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v8, v10
	v_dual_sub_f32 v13, v10, v13 :: v_dual_sub_f32 v8, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v12, v12, v13
	v_mul_f32_e32 v14, 0x3f317218, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v10, v8
	v_add_f32_e32 v7, v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0x3f317218, v9, -v14
	v_add_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, 0xb102e308, v9
	v_dual_add_f32 v9, v11, v7 :: v_dual_add_f32 v8, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v9, v11
	v_dual_sub_f32 v7, v7, v11 :: v_dual_add_f32 v10, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v10, v8
	v_dual_sub_f32 v9, v9, v12 :: v_dual_sub_f32 v14, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v13, v13, v14
	v_add_f32_e32 v11, v13, v7
	v_sub_f32_e32 v15, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v15
	v_dual_add_f32 v8, v9, v8 :: v_dual_sub_f32 v9, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v9
	v_add_f32_e32 v8, v11, v8
	v_sub_f32_e32 v11, v11, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v13, v11 :: v_dual_add_f32 v12, v10, v8
	v_dual_add_f32 v7, v7, v9 :: v_dual_sub_f32 v10, v12, v10
	v_cndmask_b32_e64 v9, 2.0, 1.0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v10
	v_add_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v12, v7
	v_sub_f32_e32 v10, v8, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v10
	v_mul_f32_e32 v11, v9, v8
	v_fma_f32 v8, v9, v8, -v11
	v_cmp_class_f32_e64 vcc_lo, v11, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v9, v7
	v_add_f32_e32 v7, v11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v7, v11, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v10, v12
	v_trunc_f32_e32 v10, v9
	v_mul_f32_e32 v14, 0x3fb8aa3b, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v15, 0x3fb8aa3b, v13, -v14
	v_rndne_f32_e32 v16, v14
	v_dual_fmac_f32 v15, 0x32a5705f, v13 :: v_dual_sub_f32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v14, v14, v15
	v_sub_f32_e32 v7, v7, v11
	v_cvt_i32_f32_e32 v11, v16
	v_exp_f32_e32 v14, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v8, v7
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v8, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v11, 0.5, v9 :: v_dual_cndmask_b32 v8, 0, v8
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
	v_trunc_f32_e32 v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v7, v12, v7 :: v_dual_cndmask_b32 v8, 0x7f800000, v8
	v_cmp_eq_f32_e32 vcc_lo, v10, v9
	v_cmp_neq_f32_e64 s0, v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v7, v8, v7, v8
	v_cmp_eq_f32_e64 s1, 0x7f800000, v8
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 1.0, v3, s0
	v_cndmask_b32_e64 v7, v7, v8, s1
	v_cmp_eq_f32_e64 s1, 0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v7, 0x7fffffff, v7, v9
	v_cndmask_b32_e64 v8, 0x7f800000, 0, s1
	v_cndmask_b32_e64 v9, 0, v3, s0
	v_cmp_class_f32_e64 s0, v3, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v10, 0x7fc00000, v7, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v3
	v_bfi_b32 v8, 0x7fffffff, v8, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v7, v10, vcc_lo
	s_or_b32 vcc_lo, s1, s0
	s_cmp_lg_u32 s8, 0
	v_cndmask_b32_e32 v7, v7, v8, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0x7fc00000, v7, vcc_lo
	v_add_f32_e32 v5, v5, v3
	s_cbranch_scc1 .LBB0_6
.LBB0_7:                                ; %._crit_edge53
	v_cmp_ne_u32_e32 vcc_lo, 1, v6
	s_cbranch_vccnz .LBB0_12
; %bb.8:                                ; %.lr.ph57
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f32 v2, null, v4, v4, v5
	v_div_scale_f32 v7, vcc_lo, v5, v4, v5
	s_mov_b32 s1, s2
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v2, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v6, v3
	v_mul_f32_e32 v6, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v2, v6, v7
	v_fmac_f32_e32 v6, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v2, -v2, v6, v7
	v_div_fmas_f32 v2, v2, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v2, v2, v4, v5
	v_mul_f32_e32 v3, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v3
	v_add_nc_u32_e32 v5, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v4, v3, v2
	v_fma_f32 v7, -v5, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v6
	v_cndmask_b32_e64 v3, v3, v4, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v7
	v_cndmask_b32_e64 v3, v3, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, 0x37800000, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v3, v2, vcc_lo
	v_cmp_neq_f32_e64 s0, 0, v4
.LBB0_9:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v5, v5, v0
	v_div_scale_f32 v6, null, v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	v_fmac_f32_e32 v7, v8, v7
	v_div_scale_f32 v8, vcc_lo, v5, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v8, v7
	v_fma_f32 v10, -v6, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v7
	v_fma_f32 v6, -v6, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v6, v6, v7, v9
	v_div_fixup_f32 v5, v6, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_i32_f32_e32 v5, v5
.LBB0_11:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	s_add_i32 s1, s1, -1
	s_cmp_lg_u32 s1, 0
	global_store_b32 v[2:3], v5, off
	s_cbranch_scc1 .LBB0_9
.LBB0_12:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14gpu_matrixNormPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14gpu_matrixNormPiS_i, .Lfunc_end0-_Z14gpu_matrixNormPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1920
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14gpu_matrixNormPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14gpu_matrixNormPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
