/*
 * Alyxandra Spikerman
 * High Perfomance Computing
 * Homework 6 - Question 1
 */

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>

#define n 64

// taken from transpose.cu from HW5
#define TIMER_CREATE(t)               \
  cudaEvent_t t##_start, t##_end;     \
  cudaEventCreate(&t##_start);        \
  cudaEventCreate(&t##_end);

#define TIMER_START(t)                \
  cudaEventRecord(t##_start);         \
  cudaEventSynchronize(t##_start);    \

#define TIMER_END(t)                             \
  cudaEventRecord(t##_end);                      \
  cudaEventSynchronize(t##_end);                 \
  cudaEventElapsedTime(&t, t##_start, t##_end);  \
  cudaEventDestroy(t##_start);                   \
  cudaEventDestroy(t##_end);

// CUDA kernel
__global__ void get_a(float* a, float* b) {
    int id = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    // taken from https://devtalk.nvidia.com/default/topic/619509/cuda-programming-and-performance/3d-arrays-where-to-start-/post/3968516/#3968516
    // get x,y,z with the index
    int z = id/(n*n);
    id -= z*n*n;
    int y = id/n;
    id -= y*n;
    int x = id;

    for (int i = x; i < n-1; i += stride) {
        for (int j = y; j < n-1; j += stride) {
            for (int k = z; k < n-1; k += stride) {
                if (i > 0 && j > 0 && k > 0) {
                    a[n*n*i + n*j + k] = 0.8 * (b[n*n*(i-1) + n*j + k] +
                                                b[n*n*(i+1) + n*j + k] +
                                                b[n*n*i + n*(j-1) + k] +
                                                b[n*n*i + n*(j+1) + k] +
                                                b[n*n*i + n*j + (k-1)] +
                                                b[n*n*i + n*j + (k+1)]);
                }
            }
        }
    }
}

int main(int argc, char* argv[] ) {
    size_t total_bytes = n * n * n * sizeof(float);
    float* h_a = (float*)malloc(total_bytes);
    float* h_b = (float*)malloc(total_bytes);
    float* d_a;
    cudaMalloc(&d_a, total_bytes);
    float* d_b;
    cudaMalloc(&d_b, total_bytes);

    srand(150);

    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++) {
            for (int k = 0; k < n; k++) {
                h_b[n*n*i + n*j + k] = (rand() % 50) + 1;
            }
        }
    }

    cudaMemcpy(d_a, h_a, total_bytes, cudaMemcpyHostToDevice);
    cudaMemcpy(d_b, h_b, total_bytes, cudaMemcpyHostToDevice);

    printf("\nStart kernel\n\n");

    float Ktime;
    TIMER_CREATE(Ktime);
    TIMER_START(Ktime);

    get_a<<< (n*n*n)/128, 128 >>>(d_a, d_b); // Execute the kernel
    cudaDeviceSynchronize(); // wait for everything to finish before accessing

    TIMER_END(Ktime);
    printf("Kernel Execution Time: %f ms\n", Ktime);

    cudaMemcpy(h_a, d_a, total_bytes, cudaMemcpyDeviceToHost); // Copy histogram to host

    // for (int i = 1; i < n - 1; i++) {
    //     for (int j = 1; j < n - 1; j++) {
    //         for (int k = 1; k < n - 1; k++) {
    //             printf("%f ", h_a[n*n*i + n*j + k]);
    //         }
    //     }
    // }

    // free allocated memory
    cudaFree(d_a);
    cudaFree(d_b);
    free(h_a);
    free(h_b);
    return 0;
}

	.file	"tmpxft_00301ac1_00000000-6_Q1_nontiled.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z26__device_stub__Z5get_aPfS_PfS_
	.type	_Z26__device_stub__Z5get_aPfS_PfS_, @function
_Z26__device_stub__Z5get_aPfS_PfS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5get_aPfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z26__device_stub__Z5get_aPfS_PfS_, .-_Z26__device_stub__Z5get_aPfS_PfS_
	.globl	_Z5get_aPfS_
	.type	_Z5get_aPfS_, @function
_Z5get_aPfS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z5get_aPfS_PfS_
	.cfi_endproc
.LFE2053:
	.size	_Z5get_aPfS_, .-_Z5get_aPfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\nStart kernel\n\n"
.LC1:
	.string	"Kernel Execution Time: %f ms\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1048576, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$1048576, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1048576, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi
	call	cudaMalloc@PLT
	movl	$150, %edi
	call	srand@PLT
.L9:
	movq	%rbp, %r13
	xorl	%r12d, %r12d
	salq	$14, %r13
	addq	%rbx, %r13
.L13:
	movq	%r12, %r14
	xorl	%r15d, %r15d
	salq	$8, %r14
	addq	%r13, %r14
.L10:
	call	rand@PLT
	movl	$50, %ecx
	cltd
	idivl	%ecx
	incl	%edx
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r14,%r15,4)
	incq	%r15
	cmpq	$64, %r15
	jne	.L10
	incq	%r12
	cmpq	$64, %r12
	jne	.L13
	incq	%rbp
	cmpq	$64, %rbp
	jne	.L9
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movl	$33554433, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$2097153, %edi
	salq	$7, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$11, %rdi
	movq	%rdx, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z26__device_stub__Z5get_aPfS_PfS_
.L14:
	call	cudaDeviceSynchronize@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	60(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	60(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$1048576, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z5get_aPfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5get_aPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/*
 * Alyxandra Spikerman
 * High Perfomance Computing
 * Homework 6 - Question 1
 */

#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>

#define n 64

// taken from transpose.cu from HW5
#define TIMER_CREATE(t)               \
  hipEvent_t t##_start, t##_end;     \
  hipEventCreate(&t##_start);        \
  hipEventCreate(&t##_end);

#define TIMER_START(t)                \
  hipEventRecord(t##_start);         \
  hipEventSynchronize(t##_start);    \

#define TIMER_END(t)                             \
  hipEventRecord(t##_end);                      \
  hipEventSynchronize(t##_end);                 \
  hipEventElapsedTime(&t, t##_start, t##_end);  \
  hipEventDestroy(t##_start);                   \
  hipEventDestroy(t##_end);

// CUDA kernel
__global__ void get_a(float* a, float* b) {
    int id = blockIdx.x * blockDim.x + threadIdx.x;
    int stride = blockDim.x * gridDim.x;

    // taken from https://devtalk.nvidia.com/default/topic/619509/cuda-programming-and-performance/3d-arrays-where-to-start-/post/3968516/#3968516
    // get x,y,z with the index
    int z = id/(n*n);
    id -= z*n*n;
    int y = id/n;
    id -= y*n;
    int x = id;

    for (int i = x; i < n-1; i += stride) {
        for (int j = y; j < n-1; j += stride) {
            for (int k = z; k < n-1; k += stride) {
                if (i > 0 && j > 0 && k > 0) {
                    a[n*n*i + n*j + k] = 0.8 * (b[n*n*(i-1) + n*j + k] +
                                                b[n*n*(i+1) + n*j + k] +
                                                b[n*n*i + n*(j-1) + k] +
                                                b[n*n*i + n*(j+1) + k] +
                                                b[n*n*i + n*j + (k-1)] +
                                                b[n*n*i + n*j + (k+1)]);
                }
            }
        }
    }
}

int main(int argc, char* argv[] ) {
    size_t total_bytes = n * n * n * sizeof(float);
    float* h_a = (float*)malloc(total_bytes);
    float* h_b = (float*)malloc(total_bytes);
    float* d_a;
    hipMalloc(&d_a, total_bytes);
    float* d_b;
    hipMalloc(&d_b, total_bytes);

    srand(150);

    for (int i = 0; i < n; i++) {
        for (int j = 0; j < n; j++) {
            for (int k = 0; k < n; k++) {
                h_b[n*n*i + n*j + k] = (rand() % 50) + 1;
            }
        }
    }

    hipMemcpy(d_a, h_a, total_bytes, hipMemcpyHostToDevice);
    hipMemcpy(d_b, h_b, total_bytes, hipMemcpyHostToDevice);

    printf("\nStart kernel\n\n");

    float Ktime;
    TIMER_CREATE(Ktime);
    TIMER_START(Ktime);

    get_a<<< (n*n*n)/128, 128 >>>(d_a, d_b); // Execute the kernel
    hipDeviceSynchronize(); // wait for everything to finish before accessing

    TIMER_END(Ktime);
    printf("Kernel Execution Time: %f ms\n", Ktime);

    hipMemcpy(h_a, d_a, total_bytes, hipMemcpyDeviceToHost); // Copy histogram to host

    // for (int i = 1; i < n - 1; i++) {
    //     for (int j = 1; j < n - 1; j++) {
    //         for (int k = 1; k < n - 1; k++) {
    //             printf("%f ", h_a[n*n*i + n*j + k]);
    //         }
    //     }
    // }

    // free allocated memory
    hipFree(d_a);
    hipFree(d_b);
    free(h_a);
    free(h_b);
    return 0;
}

	.text
	.file	"Q1_nontiled.hip"
	.globl	_Z20__device_stub__get_aPfS_    # -- Begin function _Z20__device_stub__get_aPfS_
	.type	_Z20__device_stub__get_aPfS_,@function
_Z20__device_stub__get_aPfS_:           # @_Z20__device_stub__get_aPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5get_aPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__get_aPfS_, .Lfunc_end0-_Z20__device_stub__get_aPfS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1048576, %edi                  # imm = 0x100000
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movl	$1048576, %edi                  # imm = 0x100000
	callq	malloc
	movq	%rax, %r12
	leaq	16(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	leaq	24(%rsp), %rdi
	movl	$1048576, %esi                  # imm = 0x100000
	callq	hipMalloc
	movl	$150, %edi
	callq	srand
	xorl	%r15d, %r15d
	movq	%r12, %r14
.LBB1_1:                                # %.preheader29
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
                                        #       Child Loop BB1_3 Depth 3
	movq	%r12, %r13
	xorl	%ebp, %ebp
.LBB1_2:                                # %.preheader
                                        #   Parent Loop BB1_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB1_3 Depth 3
	xorl	%ebx, %ebx
.LBB1_3:                                #   Parent Loop BB1_1 Depth=1
                                        #     Parent Loop BB1_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$36, %rcx
	addl	%edx, %ecx
	imull	$50, %ecx, %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%r13,%rbx,4)
	incq	%rbx
	cmpq	$64, %rbx
	jne	.LBB1_3
# %bb.4:                                #   in Loop: Header=BB1_2 Depth=2
	incq	%rbp
	addq	$256, %r13                      # imm = 0x100
	cmpq	$64, %rbp
	jne	.LBB1_2
# %bb.5:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r15
	addq	$16384, %r12                    # imm = 0x4000
	cmpq	$64, %r15
	jne	.LBB1_1
# %bb.6:
	movq	16(%rsp), %rdi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	40(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	leaq	32(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r15), %rdi
	callq	hipEventSynchronize
	movabsq	$4294967424, %rdx               # imm = 0x100000080
	leaq	1920(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	callq	_Z20__device_stub__get_aPfS_
.LBB1_8:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	leaq	52(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	movq	32(%rsp), %rdi
	callq	hipEventDestroy
	movq	8(%rsp), %rdi
	callq	hipEventDestroy
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rsi
	movl	$1048576, %edx                  # imm = 0x100000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5get_aPfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5get_aPfS_,@object            # @_Z5get_aPfS_
	.section	.rodata,"a",@progbits
	.globl	_Z5get_aPfS_
	.p2align	3, 0x0
_Z5get_aPfS_:
	.quad	_Z20__device_stub__get_aPfS_
	.size	_Z5get_aPfS_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Kernel Execution Time: %f ms\n"
	.size	.L.str.1, 30

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5get_aPfS_"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"\nStart kernel\n"
	.size	.Lstr, 15

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__get_aPfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5get_aPfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5get_aPfS_            ; -- Begin function _Z5get_aPfS_
	.globl	_Z5get_aPfS_
	.p2align	8
	.type	_Z5get_aPfS_,@function
_Z5get_aPfS_:                           ; @_Z5get_aPfS_
; %bb.0:
	s_load_b32 s4, s[0:1], 0x1c
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s4, 0xffff
	s_mov_b32 s4, exec_lo
	s_mul_i32 s15, s15, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s15, v0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v2, 20, v2
	v_add_nc_u32_e32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0xfffff000, v4
	v_sub_nc_u32_e32 v5, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v5
	v_lshrrev_b32_e32 v2, 26, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v5, v2
	v_and_b32_e32 v2, 0xffffffc0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v5, v2
	v_cmpx_gt_i32_e32 63, v2
	s_cbranch_execz .LBB0_11
; %bb.1:                                ; %.preheader56.lr.ph
	s_load_b32 s3, s[2:3], 0x0
	v_ashrrev_i32_e32 v3, 6, v3
	s_load_b128 s[4:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 12, v0
	v_ashrrev_i32_e32 v4, 12, v4
	v_cmp_gt_i32_e64 s0, 0x3f000, v1
	v_mov_b32_e32 v1, 0
	v_mul_lo_u32 v6, 0x3ffc0, v3
	v_lshl_add_u32 v0, s15, 12, v0
	v_mul_lo_u32 v7, 0xffffff, v4
	v_cmp_gt_i32_e32 vcc_lo, 0xfc0, v5
	s_mov_b32 s8, 0x9999999a
	s_mov_b32 s9, 0x3fe99999
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v6
	v_sub_nc_u32_e32 v5, v0, v7
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s3, s3, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s10, s3, 12
	s_lshl_b32 s11, s3, 6
.LBB0_2:                                ; %.preheader56
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.3:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_lt_i32_e64 s1, 0, v2
	v_dual_mov_b32 v7, v5 :: v_dual_lshlrev_b32 v6, 12, v2
	v_mov_b32_e32 v8, v3
	s_mov_b32 s14, 0
.LBB0_4:                                ; %.preheader
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_9
; %bb.5:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s2, 0, v8
	v_lshl_add_u32 v9, v8, 6, v6
	s_mov_b32 s16, 0
	s_mov_b32 s18, 0
	s_and_b32 s17, s1, s2
.LBB0_6:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v10, s18, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s2, 0, v10
	s_and_b32 s2, s17, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s19, s2
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=3
	v_add_nc_u32_e32 v11, s18, v7
	v_add_co_u32 v14, s2, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v15, null, 0, 0, s2
	v_add_nc_u32_e32 v0, 0xfffff000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[12:13], 2, v[0:1]
	v_add_nc_u32_e32 v0, 0x1000, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[16:17], 2, v[0:1]
	v_subrev_nc_u32_e32 v0, 64, v11
	v_add_co_u32 v12, s2, s6, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
	v_lshlrev_b64 v[18:19], 2, v[0:1]
	v_add_co_u32 v16, s2, s6, v16
	v_add_nc_u32_e32 v0, -1, v11
	v_add_co_ci_u32_e64 v17, s2, s7, v17, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s2, s6, v18
	v_add_co_ci_u32_e64 v19, s2, s7, v19, s2
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[20:21], 2, v[0:1]
	s_clause 0x2
	global_load_b32 v0, v[12:13], off
	global_load_b32 v10, v[16:17], off
	global_load_b32 v16, v[18:19], off
	v_add_co_u32 v12, s2, s6, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v13, s2, s7, v15, s2
	v_add_co_u32 v14, s2, s6, v20
	v_add_co_ci_u32_e64 v15, s2, s7, v21, s2
	s_clause 0x2
	global_load_b32 v17, v[12:13], off offset:256
	global_load_b32 v14, v[14:15], off
	global_load_b32 v12, v[12:13], off offset:4
	s_waitcnt vmcnt(4)
	v_add_f32_e32 v0, v0, v10
	s_waitcnt vmcnt(3)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v16
	s_waitcnt vmcnt(2)
	v_add_f32_e32 v0, v0, v17
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v0, v14
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[12:13], v0
	v_mul_f64 v[12:13], v[12:13], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v0, v[12:13]
	v_mov_b32_e32 v12, v1
	v_lshlrev_b64 v[10:11], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s2, s4, v10
	v_add_co_ci_u32_e64 v11, s2, s5, v11, s2
	global_store_b32 v[10:11], v0, off
.LBB0_8:                                ;   in Loop: Header=BB0_6 Depth=3
	s_or_b32 exec_lo, exec_lo, s19
	s_add_i32 s18, s18, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s18, v4
	v_cmp_lt_i32_e64 s2, 62, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s16, s2, s16
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_6
.LBB0_9:                                ; %Flow71
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s15
	v_add_nc_u32_e32 v8, s3, v8
	v_add_nc_u32_e32 v7, s11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s2, 62, v8
	s_or_b32 s14, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_4
.LBB0_10:                               ; %Flow73
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v2, s3, v2
	v_add_nc_u32_e32 v5, s10, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_i32_e64 s1, 62, v2
	s_or_b32 s12, s1, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_2
.LBB0_11:                               ; %._crit_edge61
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5get_aPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5get_aPfS_, .Lfunc_end0-_Z5get_aPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 852
; NumSgprs: 22
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5get_aPfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z5get_aPfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
