#include "includes.h"
__global__ void convolution_kernel(unsigned char *input_img, unsigned char *output_img, int height, int width)
{

__shared__ unsigned char input_shared[W][W]; //Shared Memory required for a tile and its halo elements(3 channels)

int chan;
for(chan=0;chan<3;chan++)    //3 Channel Image
{
int tx = threadIdx.x;
int ty = threadIdx.y;

int output_row = blockIdx.x*TILE_WIDTH + tx;
int output_col = blockIdx.y*TILE_WIDTH + ty;

int input_row = output_row - MASK_WIDTH/2;
int input_col = output_col - MASK_WIDTH/2;

if((input_row >= 0) && (input_row < height) && (input_col >= 0) && (input_col < width))
{
input_shared[tx][ty] = input_img[(input_row*width + input_col)*3 + chan];
}
else
{
if(input_row<0 && input_col<0)
{
input_shared[tx][ty] = input_img[chan];
}
else if(input_row<0 && input_col<width)
{
input_shared[tx][ty] = input_img[3*input_col + chan];
}
else if(input_row<0)
{
input_shared[tx][ty] = input_img[3*(width-1) + chan];
}
else if(input_row<height && input_col<0)
{
input_shared[tx][ty] = input_img[input_row*width*3 + chan];
}
else if(input_row<height && input_col>width)
{
input_shared[tx][ty] = input_img[(input_row*width +width-1)*3 + chan];
}
else if(input_row>height && input_col<0)
{
input_shared[tx][ty] = input_img[width*(height-1)*3 + chan];
}
else if(input_row>height && input_col<width)
{
input_shared[tx][ty] = input_img[(width*(height-1)+input_col)*3 + chan];
}
else
{
input_shared[tx][ty] = input_img[(width*(height-1) + (width-1))*3 + chan];
}
}

__syncthreads();

int i;
if(tx<TILE_WIDTH && ty<TILE_WIDTH)
{
int j;
int freq[256];

for(i=0;i<256;i++)freq[i]=0;

for(i=0;i<MASK_WIDTH;i++)
{
for(j=0;j<MASK_WIDTH;j++)
{
freq[input_shared[tx+i][ty+j]]++;
}
}
j=0;
for(i=0;i<256;i++)
{
j=j+freq[i];
if(j>((MASK_WIDTH*MASK_WIDTH)/2))break;
}
}

if(output_row<height && output_col<width)
{
output_img[(output_row*width + output_col)*3 + chan] = i;
}
__syncthreads();
}

}
	.file	"tmpxft_00319de4_00000000-6_convolution_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
	.type	_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii, @function
_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18convolution_kernelPhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii, .-_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
	.globl	_Z18convolution_kernelPhS_ii
	.type	_Z18convolution_kernelPhS_ii, @function
_Z18convolution_kernelPhS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z18convolution_kernelPhS_iiPhS_ii
	.cfi_endproc
.LFE2033:
	.size	_Z18convolution_kernelPhS_ii, .-_Z18convolution_kernelPhS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z18convolution_kernelPhS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convolution_kernelPhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_kernel(unsigned char *input_img, unsigned char *output_img, int height, int width)
{

__shared__ unsigned char input_shared[W][W]; //Shared Memory required for a tile and its halo elements(3 channels)

int chan;
for(chan=0;chan<3;chan++)    //3 Channel Image
{
int tx = threadIdx.x;
int ty = threadIdx.y;

int output_row = blockIdx.x*TILE_WIDTH + tx;
int output_col = blockIdx.y*TILE_WIDTH + ty;

int input_row = output_row - MASK_WIDTH/2;
int input_col = output_col - MASK_WIDTH/2;

if((input_row >= 0) && (input_row < height) && (input_col >= 0) && (input_col < width))
{
input_shared[tx][ty] = input_img[(input_row*width + input_col)*3 + chan];
}
else
{
if(input_row<0 && input_col<0)
{
input_shared[tx][ty] = input_img[chan];
}
else if(input_row<0 && input_col<width)
{
input_shared[tx][ty] = input_img[3*input_col + chan];
}
else if(input_row<0)
{
input_shared[tx][ty] = input_img[3*(width-1) + chan];
}
else if(input_row<height && input_col<0)
{
input_shared[tx][ty] = input_img[input_row*width*3 + chan];
}
else if(input_row<height && input_col>width)
{
input_shared[tx][ty] = input_img[(input_row*width +width-1)*3 + chan];
}
else if(input_row>height && input_col<0)
{
input_shared[tx][ty] = input_img[width*(height-1)*3 + chan];
}
else if(input_row>height && input_col<width)
{
input_shared[tx][ty] = input_img[(width*(height-1)+input_col)*3 + chan];
}
else
{
input_shared[tx][ty] = input_img[(width*(height-1) + (width-1))*3 + chan];
}
}

__syncthreads();

int i;
if(tx<TILE_WIDTH && ty<TILE_WIDTH)
{
int j;
int freq[256];

for(i=0;i<256;i++)freq[i]=0;

for(i=0;i<MASK_WIDTH;i++)
{
for(j=0;j<MASK_WIDTH;j++)
{
freq[input_shared[tx+i][ty+j]]++;
}
}
j=0;
for(i=0;i<256;i++)
{
j=j+freq[i];
if(j>((MASK_WIDTH*MASK_WIDTH)/2))break;
}
}

if(output_row<height && output_col<width)
{
output_img[(output_row*width + output_col)*3 + chan] = i;
}
__syncthreads();
}

}
	.text
	.file	"convolution_kernel.hip"
	.globl	_Z33__device_stub__convolution_kernelPhS_ii # -- Begin function _Z33__device_stub__convolution_kernelPhS_ii
	.type	_Z33__device_stub__convolution_kernelPhS_ii,@function
_Z33__device_stub__convolution_kernelPhS_ii: # @_Z33__device_stub__convolution_kernelPhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convolution_kernelPhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__convolution_kernelPhS_ii, .Lfunc_end0-_Z33__device_stub__convolution_kernelPhS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convolution_kernelPhS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z18convolution_kernelPhS_ii,@object # @_Z18convolution_kernelPhS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z18convolution_kernelPhS_ii
	.p2align	3, 0x0
_Z18convolution_kernelPhS_ii:
	.quad	_Z33__device_stub__convolution_kernelPhS_ii
	.size	_Z18convolution_kernelPhS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18convolution_kernelPhS_ii"
	.size	.L__unnamed_1, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convolution_kernelPhS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convolution_kernelPhS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convolution_kernelPhS_ii ; -- Begin function _Z18convolution_kernelPhS_ii
	.globl	_Z18convolution_kernelPhS_ii
	.p2align	8
	.type	_Z18convolution_kernelPhS_ii,@function
_Z18convolution_kernelPhS_ii:           ; @_Z18convolution_kernelPhS_ii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[16:17], s[0:1], 0x10
	s_load_b128 s[8:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_mov_b32 s13, 0
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v7, s14, 3, v1
	v_lshl_add_u32 v0, s15, 3, v2
	v_or_b32_e32 v6, v1, v2
	v_mad_u32_u24 v3, v1, 10, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_i32_e64 s1, 1, v7
	v_cmp_gt_i32_e64 s2, 1, v0
	v_cmp_lt_i32_e32 vcc_lo, 0, v7
	v_add_nc_u32_e32 v2, -1, v7
	v_add_nc_u32_e32 v1, -1, v0
	v_cmp_lt_i32_e64 s7, 0, v0
	s_and_b32 s12, s1, s2
	v_cmp_gt_u32_e64 s0, 8, v6
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s4, s16, v7
	v_cmp_lt_i32_e64 s5, s17, v0
	v_mad_u64_u32 v[4:5], null, v2, s17, v[1:2]
	v_lshl_add_u32 v5, v1, 1, v1
	v_cmp_gt_i32_e64 s3, s16, v7
	s_delay_alu instid0(VALU_DEP_4)
	s_or_b32 s14, s4, s5
	v_cmp_gt_i32_e64 s6, s17, v0
	s_or_b32 s18, s14, s2
	s_xor_b32 s14, s12, -1
	s_add_i32 s12, s16, -1
	s_or_b32 s2, s5, vcc_lo
	s_mul_i32 s19, s12, s17
	s_xor_b32 s15, s2, -1
	v_cmp_ge_i32_e64 s2, s17, v1
	v_add_nc_u32_e32 v1, s19, v1
	s_and_b32 s6, s3, s6
	v_lshl_add_u32 v4, v4, 1, v4
	s_or_b32 s1, s1, s18
	s_or_b32 s2, s4, s2
	v_mad_u64_u32 v[8:9], null, v7, s17, v[0:1]
	v_mov_b32_e32 v9, 0
	v_cmp_ge_i32_e64 s3, s16, v2
	v_lshl_add_u32 v2, v7, 1, v7
	v_lshl_add_u32 v6, v1, 1, v1
	s_or_b32 s16, s7, s4
	s_xor_b32 s18, s1, -1
	s_or_b32 s4, s5, s3
	v_add_nc_u32_e32 v7, -3, v2
	v_mad_u64_u32 v[0:1], null, v2, s17, -3
	s_add_i32 s5, s17, s19
	v_lshl_add_u32 v8, v8, 1, v8
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v7, v7, s17
	s_mul_i32 s5, s5, 3
	s_mul_i32 s19, s17, 3
	s_or_b32 s3, s7, s3
	s_xor_b32 s4, s4, -1
	s_add_i32 s5, s5, -3
	s_mul_i32 s7, s19, s12
	s_add_i32 s17, s19, -3
	s_mov_b32 s12, s13
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_35 Depth 2
                                        ;     Child Loop BB0_37 Depth 2
                                        ;       Child Loop BB0_38 Depth 3
                                        ;     Child Loop BB0_41 Depth 2
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s1, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s1
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v1, s12, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
; %bb.3:                                ; %Flow211
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s1, s1
	s_cbranch_execz .LBB0_33
; %bb.4:                                ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s19, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s19
	s_cbranch_execz .LBB0_30
; %bb.5:                                ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s20, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s20
; %bb.6:                                ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v1, s12, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
; %bb.7:                                ; %Flow207
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB0_29
; %bb.8:                                ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s21, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s21
	s_cbranch_execz .LBB0_26
; %bb.9:                                ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s22, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB0_23
; %bb.10:                               ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s23, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s23, exec_lo, s23
	s_cbranch_execz .LBB0_20
; %bb.11:                               ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s24, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s24, exec_lo, s24
	s_cbranch_execz .LBB0_17
; %bb.12:                               ;   in Loop: Header=BB0_1 Depth=1
                                        ; implicit-def: $vgpr1_vgpr2
	s_and_saveexec_b32 s25, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, s25
; %bb.13:                               ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v1, s12, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
; %bb.14:                               ; %Flow197
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s25, s25
; %bb.15:                               ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s26, s12, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s27, s26, 31
	v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
; %bb.16:                               ; %Flow198
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
.LBB0_17:                               ; %Flow199
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s24, s24
; %bb.18:                               ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s26, s12, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s27, s26, 31
	v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
; %bb.19:                               ; %Flow200
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
.LBB0_20:                               ; %Flow201
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s23, s23
; %bb.21:                               ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v1, s12, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
; %bb.22:                               ; %Flow202
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_23:                               ; %Flow203
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s22, s22
; %bb.24:                               ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v1, s12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
; %bb.25:                               ; %Flow204
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_26:                               ; %Flow205
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s21, s21
; %bb.27:                               ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s22, s17, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s23, s22, 31
	v_dual_mov_b32 v1, s22 :: v_dual_mov_b32 v2, s23
; %bb.28:                               ; %Flow206
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_29:                               ; %Flow208
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_30:                               ; %Flow209
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_and_not1_saveexec_b32 s19, s19
; %bb.31:                               ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13
; %bb.32:                               ; %Flow210
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
.LBB0_33:                               ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_add_co_u32 v1, s1, s8, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s1, s9, v2, s1
	global_load_u8 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	ds_store_b8 v3, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB0_45
; %bb.34:                               ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s1, 0
.LBB0_35:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s20, s1, 16
	s_add_i32 s1, s1, 4
	scratch_store_b32 off, v9, s20
	s_cmpk_lg_i32 s1, 0x400
	s_cbranch_scc1 .LBB0_35
; %bb.36:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v1, v3
	s_mov_b32 s1, 0
.LBB0_37:                               ; %.preheader
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_38 Depth 3
	s_mov_b32 s20, 0
.LBB0_38:                               ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_37 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s20, v1
	s_add_i32 s20, s20, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s20, 3
	ds_load_u8 v2, v2
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v2, 2, v2
	scratch_load_b32 v10, v2, off offset:16
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, 1, v10
	scratch_store_b32 v2, v10, off offset:16
	s_cbranch_scc1 .LBB0_38
; %bb.39:                               ;   in Loop: Header=BB0_37 Depth=2
	v_add_nc_u32_e32 v1, 10, v1
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s1, 3
	s_cbranch_scc1 .LBB0_37
; %bb.40:                               ; %.preheader155.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v1, 16 :: v_dual_mov_b32 v2, 0
	s_mov_b32 s20, 0
	s_mov_b32 s21, 0
                                        ; implicit-def: $sgpr22
.LBB0_41:                               ; %.preheader155
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b32 v10, v1, off
	s_or_b32 s22, s22, exec_lo
	s_mov_b32 s23, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v10, v2
	v_mov_b32_e32 v10, s21
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_gt_i32_e32 5, v2
; %bb.42:                               ;   in Loop: Header=BB0_41 Depth=2
	s_add_i32 s21, s21, 1
	v_dual_mov_b32 v10, 0x100 :: v_dual_add_nc_u32 v1, 4, v1
	s_cmpk_eq_i32 s21, 0x100
	s_cselect_b32 s1, -1, 0
	s_and_not1_b32 s22, s22, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s22, s22, s1
; %bb.43:                               ; %Flow
                                        ;   in Loop: Header=BB0_41 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s22
	s_or_b32 s20, s1, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s20
	s_cbranch_execnz .LBB0_41
; %bb.44:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_45:                               ; %Flow196
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s19
	s_and_saveexec_b32 s19, s6
	s_cbranch_execz .LBB0_47
; %bb.46:                               ;   in Loop: Header=BB0_1 Depth=1
	v_add_nc_u32_e32 v1, s12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v1, s1, s10, v1
	v_add_co_ci_u32_e64 v2, s1, s11, v2, s1
	global_store_b8 v[1:2], v10, off
.LBB0_47:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_add_i32 s12, s12, 1
	s_waitcnt_vscnt null, 0x0
	s_cmp_lg_u32 s12, 3
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_1
; %bb.48:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convolution_kernelPhS_ii
		.amdhsa_group_segment_fixed_size 100
		.amdhsa_private_segment_fixed_size 1040
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convolution_kernelPhS_ii, .Lfunc_end0-_Z18convolution_kernelPhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1084
; NumSgprs: 30
; NumVgprs: 11
; ScratchSize: 1040
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 100 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 100
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convolution_kernelPhS_ii
    .private_segment_fixed_size: 1040
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z18convolution_kernelPhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
