#include "includes.h"
__global__ void MD_ED_I(float *S, float *T, int trainSize, int window_size, int dimensions, float *data_out, int task, int gm) {

int idx, offset_x;
float sumErr = 0;
long long int i, j;


if(gm == 0){

extern __shared__ float sh_mem[];

float *T2 = (float *)sh_mem;
float *DTW_single_dim =
(float *)&sh_mem[dimensions * window_size]; // offset on the shared memory
// for the segment T2

if (task == 0) {
idx = threadIdx.x * dimensions + threadIdx.y;
offset_x = ((blockDim.x * blockDim.y * window_size) * blockIdx.x) +
idx * window_size;

if (((blockDim.x * blockDim.y * blockIdx.x) + idx) >=
trainSize * dimensions) // 120=train_size
return;

} else { // SUBSEQ_SEARCH

idx = threadIdx.x * dimensions + threadIdx.y;
offset_x =
(blockDim.x * blockIdx.x) +
((threadIdx.y * trainSize) +
threadIdx.x); // use blockIdx and other measure to set well the offset

if ((idx + window_size) > trainSize)
return;
}

if (idx == 0) {
for (i = 0; i < dimensions; i++)
for (j = 0; j < window_size; j++)
*(T2 + (window_size * i + j)) = T[window_size * i + j];
}
__syncthreads();

for (j = 0; j < window_size; j++)
sumErr += (S[offset_x + j] - T2[window_size * threadIdx.y + j]) *
(S[offset_x + j] - T2[window_size * threadIdx.y + j]);

DTW_single_dim[idx] = sqrt(sumErr);

__syncthreads();

if (idx == 0) {
for (i = 0; i < blockDim.x; i++) {
data_out[(blockIdx.x * blockDim.x) + i] = 0.0;
for (j = 0; j < blockDim.y; j++) {
data_out[(blockIdx.x * blockDim.x) + i] +=
DTW_single_dim[i * dimensions + j]; // rivedere formula!
}
}
}

}
else {

extern __shared__ float DTW_single_dim[];

if (task == 0) {
idx = threadIdx.x * dimensions + threadIdx.y;
offset_x = ((blockDim.x * blockDim.y * window_size) * blockIdx.x) +
idx * window_size;

if (((blockDim.x * blockDim.y * blockIdx.x) + idx) >=
trainSize * dimensions) // 120=train_size
return;

} else { // SUBSEQ_SEARCH

idx = threadIdx.x * dimensions + threadIdx.y;
offset_x =
(blockDim.x * blockIdx.x) +
((threadIdx.y * trainSize) +
threadIdx.x); // use blockIdx and other measure to set well the offset

if ((idx + window_size) > trainSize)
return;
}

// if (idx == 0) {
//   for (i = 0; i < dimensions; i++)
//     for (j = 0; j < window_size; j++)
//       *(T2 + (window_size * i + j)) = T[window_size * i + j];
// }
// __syncthreads();

for (j = 0; j < window_size; j++)
sumErr += (S[offset_x + j] - T[window_size * threadIdx.y + j]) *
(S[offset_x + j] - T[window_size * threadIdx.y + j]);

DTW_single_dim[idx] = sqrt(sumErr);

__syncthreads();

if (idx == 0) {
for (i = 0; i < blockDim.x; i++) {
data_out[(blockIdx.x * blockDim.x) + i] = 0.0;
for (j = 0; j < blockDim.y; j++) {
data_out[(blockIdx.x * blockDim.x) + i] +=
DTW_single_dim[i * dimensions + j]; // rivedere formula!
}
}
}

}

}
	.file	"tmpxft_00233ca7_00000000-6_MD_ED_I.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z7MD_ED_IPfS_iiiS_iiPfS_iiiS_ii
	.type	_Z35__device_stub__Z7MD_ED_IPfS_iiiS_iiPfS_iiiS_ii, @function
_Z35__device_stub__Z7MD_ED_IPfS_iiiS_iiPfS_iiiS_ii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z7MD_ED_IPfS_iiiS_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z35__device_stub__Z7MD_ED_IPfS_iiiS_iiPfS_iiiS_ii, .-_Z35__device_stub__Z7MD_ED_IPfS_iiiS_iiPfS_iiiS_ii
	.globl	_Z7MD_ED_IPfS_iiiS_ii
	.type	_Z7MD_ED_IPfS_iiiS_ii, @function
_Z7MD_ED_IPfS_iiiS_ii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z7MD_ED_IPfS_iiiS_iiPfS_iiiS_ii
	.cfi_endproc
.LFE2033:
	.size	_Z7MD_ED_IPfS_iiiS_ii, .-_Z7MD_ED_IPfS_iiiS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7MD_ED_IPfS_iiiS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7MD_ED_IPfS_iiiS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MD_ED_I(float *S, float *T, int trainSize, int window_size, int dimensions, float *data_out, int task, int gm) {

int idx, offset_x;
float sumErr = 0;
long long int i, j;


if(gm == 0){

extern __shared__ float sh_mem[];

float *T2 = (float *)sh_mem;
float *DTW_single_dim =
(float *)&sh_mem[dimensions * window_size]; // offset on the shared memory
// for the segment T2

if (task == 0) {
idx = threadIdx.x * dimensions + threadIdx.y;
offset_x = ((blockDim.x * blockDim.y * window_size) * blockIdx.x) +
idx * window_size;

if (((blockDim.x * blockDim.y * blockIdx.x) + idx) >=
trainSize * dimensions) // 120=train_size
return;

} else { // SUBSEQ_SEARCH

idx = threadIdx.x * dimensions + threadIdx.y;
offset_x =
(blockDim.x * blockIdx.x) +
((threadIdx.y * trainSize) +
threadIdx.x); // use blockIdx and other measure to set well the offset

if ((idx + window_size) > trainSize)
return;
}

if (idx == 0) {
for (i = 0; i < dimensions; i++)
for (j = 0; j < window_size; j++)
*(T2 + (window_size * i + j)) = T[window_size * i + j];
}
__syncthreads();

for (j = 0; j < window_size; j++)
sumErr += (S[offset_x + j] - T2[window_size * threadIdx.y + j]) *
(S[offset_x + j] - T2[window_size * threadIdx.y + j]);

DTW_single_dim[idx] = sqrt(sumErr);

__syncthreads();

if (idx == 0) {
for (i = 0; i < blockDim.x; i++) {
data_out[(blockIdx.x * blockDim.x) + i] = 0.0;
for (j = 0; j < blockDim.y; j++) {
data_out[(blockIdx.x * blockDim.x) + i] +=
DTW_single_dim[i * dimensions + j]; // rivedere formula!
}
}
}

}
else {

extern __shared__ float DTW_single_dim[];

if (task == 0) {
idx = threadIdx.x * dimensions + threadIdx.y;
offset_x = ((blockDim.x * blockDim.y * window_size) * blockIdx.x) +
idx * window_size;

if (((blockDim.x * blockDim.y * blockIdx.x) + idx) >=
trainSize * dimensions) // 120=train_size
return;

} else { // SUBSEQ_SEARCH

idx = threadIdx.x * dimensions + threadIdx.y;
offset_x =
(blockDim.x * blockIdx.x) +
((threadIdx.y * trainSize) +
threadIdx.x); // use blockIdx and other measure to set well the offset

if ((idx + window_size) > trainSize)
return;
}

// if (idx == 0) {
//   for (i = 0; i < dimensions; i++)
//     for (j = 0; j < window_size; j++)
//       *(T2 + (window_size * i + j)) = T[window_size * i + j];
// }
// __syncthreads();

for (j = 0; j < window_size; j++)
sumErr += (S[offset_x + j] - T[window_size * threadIdx.y + j]) *
(S[offset_x + j] - T[window_size * threadIdx.y + j]);

DTW_single_dim[idx] = sqrt(sumErr);

__syncthreads();

if (idx == 0) {
for (i = 0; i < blockDim.x; i++) {
data_out[(blockIdx.x * blockDim.x) + i] = 0.0;
for (j = 0; j < blockDim.y; j++) {
data_out[(blockIdx.x * blockDim.x) + i] +=
DTW_single_dim[i * dimensions + j]; // rivedere formula!
}
}
}

}

}
	.text
	.file	"MD_ED_I.hip"
	.globl	_Z22__device_stub__MD_ED_IPfS_iiiS_ii # -- Begin function _Z22__device_stub__MD_ED_IPfS_iiiS_ii
	.type	_Z22__device_stub__MD_ED_IPfS_iiiS_ii,@function
_Z22__device_stub__MD_ED_IPfS_iiiS_ii:  # @_Z22__device_stub__MD_ED_IPfS_iiiS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7MD_ED_IPfS_iiiS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__MD_ED_IPfS_iiiS_ii, .Lfunc_end0-_Z22__device_stub__MD_ED_IPfS_iiiS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7MD_ED_IPfS_iiiS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7MD_ED_IPfS_iiiS_ii,@object   # @_Z7MD_ED_IPfS_iiiS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z7MD_ED_IPfS_iiiS_ii
	.p2align	3, 0x0
_Z7MD_ED_IPfS_iiiS_ii:
	.quad	_Z22__device_stub__MD_ED_IPfS_iiiS_ii
	.size	_Z7MD_ED_IPfS_iiiS_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7MD_ED_IPfS_iiiS_ii"
	.size	.L__unnamed_1, 22

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__MD_ED_IPfS_iiiS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7MD_ED_IPfS_iiiS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7MD_ED_IPfS_iiiS_ii   ; -- Begin function _Z7MD_ED_IPfS_iiiS_ii
	.globl	_Z7MD_ED_IPfS_iiiS_ii
	.p2align	8
	.type	_Z7MD_ED_IPfS_iiiS_ii,@function
_Z7MD_ED_IPfS_iiiS_ii:                  ; @_Z7MD_ED_IPfS_iiiS_ii
; %bb.0:
	s_clause 0x1
	s_load_b128 s[16:19], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s19, 0
	s_cbranch_scc0 .LBB0_3
; %bb.1:
	s_load_b32 s3, s[0:1], 0x3c
	v_mad_u64_u32 v[2:3], null, v0, s10, v[1:2]
	s_add_u32 s12, s0, 48
	s_addc_u32 s13, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_cmp_lg_u32 s18, 0
	s_cbranch_scc0 .LBB0_4
; %bb.2:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, s9, v2
	v_mul_lo_u32 v3, v1, s8
	s_mul_i32 s2, s15, s3
	s_mov_b32 s11, 0
	v_cmp_ge_i32_e32 vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v3, v0, s2
	s_and_b32 s2, vcc_lo, exec_lo
	s_branch .LBB0_5
.LBB0_3:
	s_mov_b32 s2, -1
	s_branch .LBB0_21
.LBB0_4:
	s_mov_b32 s11, -1
                                        ; implicit-def: $vgpr5
.LBB0_5:                                ; %Flow273
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_7
; %bb.6:
	s_load_b32 s11, s[12:13], 0xc
	s_and_not1_b32 s2, s2, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s11, s11, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s11, s11, s3
	s_mul_i32 s3, s10, s8
	v_mad_u64_u32 v[3:4], null, s11, s15, v[2:3]
	v_cmp_gt_u32_e32 vcc_lo, s3, v3
	v_mul_lo_u32 v5, v3, s9
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
.LBB0_7:                                ; %Flow274
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s11, s2
	s_cbranch_execz .LBB0_20
; %bb.8:
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB0_11
; %bb.9:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_mul_lo_u32 v3, v1, s9
	v_mov_b32_e32 v4, 0
	s_ashr_i32 s3, s9, 31
	s_mov_b32 s2, s9
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 2, v[3:4]
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
.LBB0_10:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v[5:6], off
	global_load_b32 v9, v[7:8], off
	v_add_co_u32 v7, vcc_lo, v7, 4
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_u32 s2, s2, -1
	s_addc_u32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u64 s[2:3], 0
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v3, v3, v9
	v_fmac_f32_e32 v4, v3, v3
	s_cbranch_scc1 .LBB0_10
	s_branch .LBB0_12
.LBB0_11:
	v_mov_b32_e32 v4, 0
.LBB0_12:                               ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	v_mul_f32_e32 v3, 0x4f800000, v4
	v_cndmask_b32_e32 v3, v4, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v6, 1, v4
	v_add_nc_u32_e32 v5, -1, v4
	v_fma_f32 v8, -v6, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v5, v4, v3
	v_cmp_ge_f32_e64 s2, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v5, s2
	v_cmp_lt_f32_e64 s2, 0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v6, s2
	v_mul_f32_e32 v5, 0x37800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v3, 0x260
	v_lshl_add_u32 v5, v2, 2, 0
	v_cndmask_b32_e32 v3, v4, v3, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	ds_store_b32 v5, v3
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_20
; %bb.13:                               ; %.preheader142
	s_load_b32 s2, s[12:13], 0xc
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e64 s3, s2, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_20
; %bb.14:                               ; %.lr.ph153
	s_load_b32 s20, s[12:13], 0xc
	s_and_b32 s2, s2, 0xffff
	s_mov_b32 s3, 0
	s_mul_i32 s12, s15, s2
	s_mov_b32 s13, s3
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[12:13], s[12:13], 2
	s_mov_b32 s28, s3
	s_add_u32 s14, s16, s12
	s_addc_u32 s19, s17, s13
	s_mov_b32 s13, s3
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s20, 16
	s_mov_b64 s[20:21], 0
	s_cmp_lg_u32 s12, 0
	s_cselect_b32 s26, -1, 0
	s_lshl_b32 s27, s10, 2
.LBB0_15:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_17 Depth 2
	s_lshl_b64 s[22:23], s[20:21], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s22, s14, s22
	s_addc_u32 s23, s19, s23
	s_and_not1_b32 vcc_lo, exec_lo, s26
	global_store_b32 v2, v2, s[22:23]
	s_cbranch_vccnz .LBB0_19
; %bb.16:                               ; %.lr.ph150
                                        ;   in Loop: Header=BB0_15 Depth=1
	v_mov_b32_e32 v3, 0
	s_mov_b32 s29, s28
	s_mov_b64 s[24:25], s[12:13]
.LBB0_17:                               ;   Parent Loop BB0_15 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, s29
	s_add_u32 s24, s24, -1
	s_addc_u32 s25, s25, -1
	s_add_i32 s29, s29, 4
	s_cmp_lg_u64 s[24:25], 0
	ds_load_b32 v4, v4
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v4, v3
	s_cbranch_scc1 .LBB0_17
; %bb.18:                               ; %._crit_edge151
                                        ;   in Loop: Header=BB0_15 Depth=1
	global_store_b32 v2, v3, s[22:23]
.LBB0_19:                               ;   in Loop: Header=BB0_15 Depth=1
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_add_i32 s28, s28, s27
	s_cmp_lg_u64 s[20:21], s[2:3]
	s_cbranch_scc1 .LBB0_15
.LBB0_20:                               ; %Flow275
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s2, 0
.LBB0_21:                               ; %Flow290
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_46
; %bb.22:
	s_load_b32 s11, s[0:1], 0x3c
	v_mad_u64_u32 v[2:3], null, v0, s10, v[1:2]
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_mov_b32 s0, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s1, s11, 0xffff
	s_cmp_lg_u32 s18, 0
	s_cbranch_scc0 .LBB0_24
; %bb.23:
	v_add_nc_u32_e32 v4, s9, v2
	v_mul_lo_u32 v3, v1, s8
	s_mul_i32 s0, s15, s1
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_i32_e32 vcc_lo, s8, v4
	v_add3_u32 v3, v3, v0, s0
	s_and_b32 s0, vcc_lo, exec_lo
	s_branch .LBB0_25
.LBB0_24:
	s_mov_b32 s11, -1
                                        ; implicit-def: $vgpr3
.LBB0_25:                               ; %Flow287
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_27
; %bb.26:
	s_load_b32 s11, s[2:3], 0xc
	s_and_not1_b32 s0, s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s11, s11, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s11, s11, s1
	s_mul_i32 s1, s10, s8
	v_mad_u64_u32 v[3:4], null, s11, s15, v[2:3]
	v_cmp_gt_u32_e32 vcc_lo, s1, v3
	v_mul_lo_u32 v3, v3, s9
	s_and_b32 s1, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
.LBB0_27:                               ; %Flow288
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_46
; %bb.28:
	v_cmp_eq_u32_e64 s0, 0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_34
; %bb.29:                               ; %.preheader141
	s_cmp_lt_i32 s10, 1
	s_cbranch_scc1 .LBB0_34
; %bb.30:                               ; %.preheader140.lr.ph
	s_ashr_i32 s11, s10, 31
	s_ashr_i32 s13, s9, 31
	s_mov_b32 s12, s9
	s_cmp_gt_i32 s9, 0
	s_mov_b32 s8, 0
	s_cselect_b32 s14, -1, 0
	s_lshl_b32 s26, s9, 2
	s_lshl_b64 s[18:19], s[12:13], 2
	s_mov_b64 s[20:21], 0
.LBB0_31:                               ; %.preheader140
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_32 Depth 2
	s_mov_b64 s[22:23], s[6:7]
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_mov_b32 s27, s8
	s_mov_b64 s[24:25], s[12:13]
	s_cbranch_vccnz .LBB0_33
.LBB0_32:                               ;   Parent Loop BB0_31 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_load_b32 s28, s[22:23], 0x0
	s_add_u32 s24, s24, -1
	v_mov_b32_e32 v0, s27
	s_addc_u32 s25, s25, -1
	s_add_i32 s27, s27, 4
	s_add_u32 s22, s22, 4
	s_addc_u32 s23, s23, 0
	s_cmp_lg_u64 s[24:25], 0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v4, s28
	ds_store_b32 v0, v4
	s_cbranch_scc1 .LBB0_32
.LBB0_33:                               ; %._crit_edge158
                                        ;   in Loop: Header=BB0_31 Depth=1
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_add_i32 s8, s8, s26
	s_add_u32 s6, s6, s18
	s_addc_u32 s7, s7, s19
	s_cmp_lg_u64 s[20:21], s[10:11]
	s_cbranch_scc1 .LBB0_31
.LBB0_34:                               ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s1
	s_cmp_lt_i32 s9, 1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_37
; %bb.35:                               ; %.lr.ph163
	v_ashrrev_i32_e32 v4, 31, v3
	v_mul_lo_u32 v5, v1, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	v_mov_b32_e32 v3, 0
	v_lshl_add_u32 v4, v5, 2, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_ashr_i32 s5, s9, 31
	s_mov_b32 s4, s9
.LBB0_36:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v5, v[0:1], off
	ds_load_b32 v6, v4
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_add_u32 s4, s4, -1
	s_addc_u32 s5, s5, -1
	v_add_nc_u32_e32 v4, 4, v4
	s_cmp_lg_u64 s[4:5], 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_sub_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v3, v5, v5
	s_cbranch_scc1 .LBB0_36
	s_branch .LBB0_38
.LBB0_37:
	v_mov_b32_e32 v3, 0
.LBB0_38:                               ; %._crit_edge164
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, 0x4f800000, v3
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
	v_cndmask_b32_e32 v0, v3, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v3, -1, v1
	v_add_nc_u32_e32 v4, 1, v1
	v_fma_f32 v5, -v3, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, -v4, v1, v0
	v_cmp_ge_f32_e64 s1, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v3, s1
	v_cmp_lt_f32_e64 s1, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v1, v1, v4, s1
	s_mul_i32 s1, s10, s9
	s_lshl_b32 s1, s1, 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_f32_e32 v3, 0x37800000, v1
	s_add_i32 s11, s1, 0
	v_lshl_add_u32 v2, v2, 2, s11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	ds_store_b32 v2, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_46
; %bb.39:                               ; %.preheader
	s_load_b32 s0, s[2:3], 0xc
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u16_e64 s1, s0, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_46
; %bb.40:                               ; %.lr.ph177
	s_load_b32 s4, s[2:3], 0xc
	s_and_b32 s0, s0, 0xffff
	s_mov_b32 s1, 0
	s_mul_i32 s2, s15, s0
	s_mov_b32 s3, s1
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[2:3], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s12, s16, s2
	s_addc_u32 s13, s17, s3
	s_mov_b32 s3, s1
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s4, 16
	s_mov_b64 s[4:5], 0
	s_cmp_lg_u32 s2, 0
	s_cselect_b32 s14, -1, 0
	s_lshl_b32 s10, s10, 2
.LBB0_41:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_43 Depth 2
	s_lshl_b64 s[6:7], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s6, s12, s6
	s_addc_u32 s7, s13, s7
	s_and_not1_b32 vcc_lo, exec_lo, s14
	global_store_b32 v0, v0, s[6:7]
	s_cbranch_vccnz .LBB0_45
; %bb.42:                               ; %.lr.ph172
                                        ;   in Loop: Header=BB0_41 Depth=1
	v_mov_b32_e32 v1, 0
	s_mov_b32 s15, s11
	s_mov_b64 s[8:9], s[2:3]
.LBB0_43:                               ;   Parent Loop BB0_41 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, s15
	s_add_u32 s8, s8, -1
	s_addc_u32 s9, s9, -1
	s_add_i32 s15, s15, 4
	s_cmp_lg_u64 s[8:9], 0
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v2, v1
	s_cbranch_scc1 .LBB0_43
; %bb.44:                               ; %._crit_edge173
                                        ;   in Loop: Header=BB0_41 Depth=1
	global_store_b32 v0, v1, s[6:7]
.LBB0_45:                               ;   in Loop: Header=BB0_41 Depth=1
	s_add_u32 s4, s4, 1
	s_addc_u32 s5, s5, 0
	s_add_i32 s11, s11, s10
	s_cmp_eq_u64 s[4:5], s[0:1]
	s_cbranch_scc0 .LBB0_41
.LBB0_46:                               ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7MD_ED_IPfS_iiiS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7MD_ED_IPfS_iiiS_ii, .Lfunc_end0-_Z7MD_ED_IPfS_iiiS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1772
; NumSgprs: 32
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7MD_ED_IPfS_iiiS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z7MD_ED_IPfS_iiiS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
