#include <stdio.h>
#include <cuda_runtime.h>

__global__ void VectorAdd(int* A, int* B, int* C, int N)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    if(idx > N )
        return;
    C[idx] = A[idx] + B[idx];
}

void GenerateData(int* data, int N)
{
    for(int i = 0; i< N; ++i)
        (*(data+i)) = i;
}
void VectorAddOnDevice(int N)
{
    int* HA = (int*)malloc(sizeof(int) * N);
    int* HB = (int*)malloc(sizeof(int) * N);
    int* HC = (int*)malloc(sizeof(int) * N);

    GenerateData(HA, N);
    GenerateData(HB, N);

    int nBytes = N * sizeof(int);
    int* DA;
    int* DB;
    int* DC;
    cudaMalloc((int**)&DA, nBytes);
    cudaMalloc((int**)&DB, nBytes);
    cudaMalloc((int**)&DC, nBytes);

    cudaMemcpy(DA, HA,nBytes, cudaMemcpyHostToDevice);
    cudaMemcpy(DB, HB,nBytes, cudaMemcpyHostToDevice);

    dim3 block(32);
    dim3 grid((N + block.x -1) / block.x);

    VectorAdd<<<grid, block>>>(DA, DB,DC,N);
    cudaMemcpy(HC, DC, nBytes, cudaMemcpyDeviceToHost);

    for(int i = 0; i < N;++i)
        printf("%d ", HC[i]);
    printf("\n");

    cudaFree(DA);
    cudaFree(DB);
    cudaFree(DC);

    free(HA);
    free(HB);
    free(HC);
}
	.file	"tmpxft_0032b58a_00000000-6_vectorAdd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12GenerateDataPii
	.type	_Z12GenerateDataPii, @function
_Z12GenerateDataPii:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	cmpl	%eax, %esi
	jle	.L6
	movl	%eax, (%rdi,%rax,4)
	incq	%rax
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z12GenerateDataPii, .-_Z12GenerateDataPii
	.globl	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
	.type	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9VectorAddPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L7:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
	.globl	_Z9VectorAddPiS_S_i
	.type	_Z9VectorAddPiS_S_i, @function
_Z9VectorAddPiS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z9VectorAddPiS_S_i, .-_Z9VectorAddPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d "
.LC1:
	.string	"\n"
	.text
	.globl	_Z17VectorAddOnDevicei
	.type	_Z17VectorAddOnDevicei, @function
_Z17VectorAddOnDevicei:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movslq	%edi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rbp, %rbx
	salq	$2, %rbp
	movq	%rbp, %rdi
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movq	%rbp, %rdi
	movq	%rax, %r14
	call	malloc@PLT
	movq	%rbp, %rdi
	leal	0(,%rbx,4), %ebp
	movq	%rax, %r13
	movslq	%ebp, %rbp
	call	malloc@PLT
	movl	%ebx, %esi
	movq	%r14, %rdi
	movq	%rax, %r12
	call	_Z12GenerateDataPii
	movq	%r13, %rdi
	call	_Z12GenerateDataPii
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movq	%rbp, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	31(%rbx), %eax
	movl	$134217729, %edx
	xorl	%r9d, %r9d
	shrl	$5, %eax
	xorl	%r8d, %r8d
	salq	$5, %rdx
	movl	$1, %ecx
	movl	%eax, 44(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	%ebx, %ecx
	movq	8(%rsp), %rdi
	call	_Z33__device_stub__Z9VectorAddPiS_S_iPiS_S_i
.L13:
	movq	24(%rsp), %rsi
	movq	%rbp, %rdx
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%ebp, %ebp
	leaq	.LC0(%rip), %r15
	call	cudaMemcpy@PLT
.L14:
	cmpl	%ebp, %ebx
	jle	.L19
	movl	(%r12,%rbp,4), %edx
	movq	%r15, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	jmp	.L14
.L19:
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r14, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	movq	%r12, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z17VectorAddOnDevicei, .-_Z17VectorAddOnDevicei
	.section	.rodata.str1.1
.LC2:
	.string	"_Z9VectorAddPiS_S_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9VectorAddPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>



void VectorAddOnDevice(int N = 1024);

void GenerateData(int* data, int N);
	.text
	.file	"vectorAdd.hip"
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_

	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.amdgpu_metadata
---
amdhsa.kernels:  []
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
