#include <iostream>

__global__ void _sobel_process_kernel_(unsigned char* d_src, unsigned char* d_dst, int row, int col)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int src_center = idy * col + idx;
    if(idy >= row || idx >= col)
        return;
    int lidx = (idx <= 0)? 0 : idx - 1;
    int ridx = (idx >= col - 1)? col - 1 : idx + 1;
    int uidy = (idy <= 0)? 0 : idy - 1;
    int didy = (idy >= row - 1)? row - 1 : idy + 1;
    int src_left = idy * col + lidx;
    int src_right = idy * col + ridx;
    int src_up = uidy * col + idx;
    int src_up_left = uidy * col + lidx; 
    int src_up_right = uidy * col + ridx;
    int src_down = didy * col + idx;
    int src_down_left = didy * col + lidx;
    int src_down_right = didy * col + ridx;
    float src_left_r = d_src[src_left];
    float src_right_r = d_src[src_right];
    float src_up_r = d_src[src_up];
    float src_up_left_r = d_src[src_up_left];
    float src_up_right_r = d_src[src_up_right];
    float src_down_r = d_src[src_down];
    float src_down_left_r = d_src[src_down_left];
    float src_down_right_r = d_src[src_down_right];
    float GX = 1 * src_up_right_r + 2 * src_right_r + 1 * src_down_right_r - 1 * src_up_left_r - 2 * src_left_r - 1 * src_down_left_r;
    float GY = 1 * src_up_left_r + 2 * src_up_r + 1 * src_up_right_r - 1 * src_down_left_r - 2 * src_down_r - 1 * src_down_right_r;
    float G = sqrt(pow(GX, 2) + pow(GY, 2));
    unsigned char gray = static_cast<unsigned char>(G);
    d_dst[src_center] = gray;
}

__global__ void _split_channel_kernel_(unsigned char* d_src, unsigned char* d_r, unsigned char* d_g, unsigned char* d_b, int row, int col)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int id = idy * col + idx;
    if(id >= row * col)
        return;
    d_r[id] = d_src[id * 3 + 0];
    d_g[id] = d_src[id * 3 + 1];
    d_b[id] = d_src[id * 3 + 2];
}

extern void _sobel_process_(unsigned char* src, unsigned char* dst, int row, int col)
{
    unsigned char* d_src = nullptr;
    unsigned char* d_dst = nullptr;
    const size_t ARRAY_BYTES = row * col * sizeof(unsigned char);
    cudaMalloc((void**) &d_src, ARRAY_BYTES);
    cudaMalloc((void**) &d_dst, ARRAY_BYTES);
    cudaMemcpy(d_src, src, ARRAY_BYTES, cudaMemcpyHostToDevice);
    dim3 threads(32, 32);
    dim3 blocks(col / threads.x + 1, row / threads.y + 1);
    _sobel_process_kernel_<<<blocks, threads>>>(d_src, d_dst, row, col);
    cudaDeviceSynchronize();
    cudaMemcpy(dst, d_dst, ARRAY_BYTES, cudaMemcpyDeviceToHost);
    cudaFree(d_src);
    cudaFree(d_dst);
}

extern void _split_channel_(unsigned char* src, unsigned char* r, unsigned char* g, unsigned char* b, int row, int col)
{
    unsigned char* d_src = nullptr;
    unsigned char* d_r = nullptr;
    unsigned char* d_g = nullptr;
    unsigned char* d_b = nullptr;
    const size_t ARRAY_BYTES = row * col * sizeof(unsigned char);
    cudaMalloc((void**) &d_src, ARRAY_BYTES * 3);
    cudaMalloc((void**) &d_r, ARRAY_BYTES);
    cudaMalloc((void**) &d_g, ARRAY_BYTES);
    cudaMalloc((void**) &d_b, ARRAY_BYTES);
    cudaMemcpy(d_src, src, ARRAY_BYTES * 3, cudaMemcpyHostToDevice);
    dim3 threads(1, 1);
    dim3 blocks(col / threads.x + 1, row / threads.y + 1);
    _split_channel_kernel_<<<blocks, threads>>>(d_src, d_r, d_g, d_b, row, col);
    cudaDeviceSynchronize();
    cudaMemcpy(r, d_r, ARRAY_BYTES, cudaMemcpyDeviceToHost);
    cudaMemcpy(g, d_g, ARRAY_BYTES, cudaMemcpyDeviceToHost);
    cudaMemcpy(b, d_b, ARRAY_BYTES, cudaMemcpyDeviceToHost);
    cudaFree(d_src);
    cudaFree(d_r);
    cudaFree(d_g);
    cudaFree(d_b);
}
	.file	"tmpxft_0032fc42_00000000-6_sobel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z22_sobel_process_kernel_PhS_iiPhS_ii
	.type	_Z46__device_stub__Z22_sobel_process_kernel_PhS_iiPhS_ii, @function
_Z46__device_stub__Z22_sobel_process_kernel_PhS_iiPhS_ii:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z22_sobel_process_kernel_PhS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z46__device_stub__Z22_sobel_process_kernel_PhS_iiPhS_ii, .-_Z46__device_stub__Z22_sobel_process_kernel_PhS_iiPhS_ii
	.globl	_Z22_sobel_process_kernel_PhS_ii
	.type	_Z22_sobel_process_kernel_PhS_ii, @function
_Z22_sobel_process_kernel_PhS_ii:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z22_sobel_process_kernel_PhS_iiPhS_ii
	.cfi_endproc
.LFE3662:
	.size	_Z22_sobel_process_kernel_PhS_ii, .-_Z22_sobel_process_kernel_PhS_ii
	.globl	_Z15_sobel_process_PhS_ii
	.type	_Z15_sobel_process_PhS_ii, @function
_Z15_sobel_process_PhS_ii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edx, %ebx
	imull	%ecx, %ebx
	subq	$48, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	movslq	%ebx, %rbx
	xorl	%eax, %eax
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	movq	%rax, (%rsp)
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	%r12d, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$5, %eax
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$137438953504, %rdx
	incl	%eax
	movl	%eax, 28(%rsp)
	movl	%ebp, %eax
	shrl	$5, %eax
	incl	%eax
	movl	%eax, 32(%rsp)
	movq	28(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z46__device_stub__Z22_sobel_process_kernel_PhS_iiPhS_ii
.L9:
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$48, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z15_sobel_process_PhS_ii, .-_Z15_sobel_process_PhS_ii
	.globl	_Z50__device_stub__Z22_split_channel_kernel_PhS_S_S_iiPhS_S_S_ii
	.type	_Z50__device_stub__Z22_split_channel_kernel_PhS_S_S_iiPhS_S_S_ii, @function
_Z50__device_stub__Z22_split_channel_kernel_PhS_S_S_iiPhS_S_S_ii:
.LFB3663:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z22_split_channel_kernel_PhS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L12:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3663:
	.size	_Z50__device_stub__Z22_split_channel_kernel_PhS_S_S_iiPhS_S_S_ii, .-_Z50__device_stub__Z22_split_channel_kernel_PhS_S_S_iiPhS_S_S_ii
	.globl	_Z22_split_channel_kernel_PhS_S_S_ii
	.type	_Z22_split_channel_kernel_PhS_S_S_ii, @function
_Z22_split_channel_kernel_PhS_S_S_ii:
.LFB3664:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z22_split_channel_kernel_PhS_S_S_iiPhS_S_S_ii
	.cfi_endproc
.LFE3664:
	.size	_Z22_split_channel_kernel_PhS_S_S_ii, .-_Z22_split_channel_kernel_PhS_S_S_ii
	.globl	_Z15_split_channel_PhS_S_S_ii
	.type	_Z15_split_channel_PhS_S_S_ii, @function
_Z15_split_channel_PhS_S_S_ii:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r9d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r8d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r8d, %ebx
	imull	%r9d, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%rcx, (%rsp)
	movslq	%ebx, %rbx
	leaq	16(%rsp), %rdi
	leaq	(%rbx,%rbx,2), %rdx
	movq	%rdx, %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	xorl	%eax, %eax
	movq	%rdx, 8(%rsp)
	movq	%rax, 16(%rsp)
	movq	%rax, 24(%rsp)
	movq	%rax, 32(%rsp)
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	1(%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 60(%rsp)
	leal	1(%rbp), %eax
	movl	$1, %ecx
	movabsq	$4294967297, %rdx
	movl	%eax, 64(%rsp)
	movq	60(%rsp), %rdi
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	40(%rsp), %rcx
	movq	32(%rsp), %rdx
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z50__device_stub__Z22_split_channel_kernel_PhS_S_S_iiPhS_S_S_ii
.L18:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r14, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L19
	call	__stack_chk_fail@PLT
.L19:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z15_split_channel_PhS_S_S_ii, .-_Z15_split_channel_PhS_S_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z22_split_channel_kernel_PhS_S_S_ii"
.LC1:
	.string	"_Z22_sobel_process_kernel_PhS_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3666:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z22_split_channel_kernel_PhS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z22_sobel_process_kernel_PhS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3666:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>

__global__ void _sobel_process_kernel_(unsigned char* d_src, unsigned char* d_dst, int row, int col)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int src_center = idy * col + idx;
    if(idy >= row || idx >= col)
        return;
    int lidx = (idx <= 0)? 0 : idx - 1;
    int ridx = (idx >= col - 1)? col - 1 : idx + 1;
    int uidy = (idy <= 0)? 0 : idy - 1;
    int didy = (idy >= row - 1)? row - 1 : idy + 1;
    int src_left = idy * col + lidx;
    int src_right = idy * col + ridx;
    int src_up = uidy * col + idx;
    int src_up_left = uidy * col + lidx; 
    int src_up_right = uidy * col + ridx;
    int src_down = didy * col + idx;
    int src_down_left = didy * col + lidx;
    int src_down_right = didy * col + ridx;
    float src_left_r = d_src[src_left];
    float src_right_r = d_src[src_right];
    float src_up_r = d_src[src_up];
    float src_up_left_r = d_src[src_up_left];
    float src_up_right_r = d_src[src_up_right];
    float src_down_r = d_src[src_down];
    float src_down_left_r = d_src[src_down_left];
    float src_down_right_r = d_src[src_down_right];
    float GX = 1 * src_up_right_r + 2 * src_right_r + 1 * src_down_right_r - 1 * src_up_left_r - 2 * src_left_r - 1 * src_down_left_r;
    float GY = 1 * src_up_left_r + 2 * src_up_r + 1 * src_up_right_r - 1 * src_down_left_r - 2 * src_down_r - 1 * src_down_right_r;
    float G = sqrt(pow(GX, 2) + pow(GY, 2));
    unsigned char gray = static_cast<unsigned char>(G);
    d_dst[src_center] = gray;
}

__global__ void _split_channel_kernel_(unsigned char* d_src, unsigned char* d_r, unsigned char* d_g, unsigned char* d_b, int row, int col)
{
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int idy = blockIdx.y * blockDim.y + threadIdx.y;
    int id = idy * col + idx;
    if(id >= row * col)
        return;
    d_r[id] = d_src[id * 3 + 0];
    d_g[id] = d_src[id * 3 + 1];
    d_b[id] = d_src[id * 3 + 2];
}

extern void _sobel_process_(unsigned char* src, unsigned char* dst, int row, int col)
{
    unsigned char* d_src = nullptr;
    unsigned char* d_dst = nullptr;
    const size_t ARRAY_BYTES = row * col * sizeof(unsigned char);
    hipMalloc((void**) &d_src, ARRAY_BYTES);
    hipMalloc((void**) &d_dst, ARRAY_BYTES);
    hipMemcpy(d_src, src, ARRAY_BYTES, hipMemcpyHostToDevice);
    dim3 threads(32, 32);
    dim3 blocks(col / threads.x + 1, row / threads.y + 1);
    _sobel_process_kernel_<<<blocks, threads>>>(d_src, d_dst, row, col);
    hipDeviceSynchronize();
    hipMemcpy(dst, d_dst, ARRAY_BYTES, hipMemcpyDeviceToHost);
    hipFree(d_src);
    hipFree(d_dst);
}

extern void _split_channel_(unsigned char* src, unsigned char* r, unsigned char* g, unsigned char* b, int row, int col)
{
    unsigned char* d_src = nullptr;
    unsigned char* d_r = nullptr;
    unsigned char* d_g = nullptr;
    unsigned char* d_b = nullptr;
    const size_t ARRAY_BYTES = row * col * sizeof(unsigned char);
    hipMalloc((void**) &d_src, ARRAY_BYTES * 3);
    hipMalloc((void**) &d_r, ARRAY_BYTES);
    hipMalloc((void**) &d_g, ARRAY_BYTES);
    hipMalloc((void**) &d_b, ARRAY_BYTES);
    hipMemcpy(d_src, src, ARRAY_BYTES * 3, hipMemcpyHostToDevice);
    dim3 threads(1, 1);
    dim3 blocks(col / threads.x + 1, row / threads.y + 1);
    _split_channel_kernel_<<<blocks, threads>>>(d_src, d_r, d_g, d_b, row, col);
    hipDeviceSynchronize();
    hipMemcpy(r, d_r, ARRAY_BYTES, hipMemcpyDeviceToHost);
    hipMemcpy(g, d_g, ARRAY_BYTES, hipMemcpyDeviceToHost);
    hipMemcpy(b, d_b, ARRAY_BYTES, hipMemcpyDeviceToHost);
    hipFree(d_src);
    hipFree(d_r);
    hipFree(d_g);
    hipFree(d_b);
}
	.text
	.file	"sobel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z37__device_stub___sobel_process_kernel_PhS_ii # -- Begin function _Z37__device_stub___sobel_process_kernel_PhS_ii
	.type	_Z37__device_stub___sobel_process_kernel_PhS_ii,@function
_Z37__device_stub___sobel_process_kernel_PhS_ii: # @_Z37__device_stub___sobel_process_kernel_PhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22_sobel_process_kernel_PhS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub___sobel_process_kernel_PhS_ii, .Lfunc_end0-_Z37__device_stub___sobel_process_kernel_PhS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub___split_channel_kernel_PhS_S_S_ii # -- Begin function _Z37__device_stub___split_channel_kernel_PhS_S_S_ii
	.type	_Z37__device_stub___split_channel_kernel_PhS_S_S_ii,@function
_Z37__device_stub___split_channel_kernel_PhS_S_S_ii: # @_Z37__device_stub___split_channel_kernel_PhS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22_split_channel_kernel_PhS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z37__device_stub___split_channel_kernel_PhS_S_S_ii, .Lfunc_end1-_Z37__device_stub___split_channel_kernel_PhS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15_sobel_process_PhS_ii       # -- Begin function _Z15_sobel_process_PhS_ii
	.type	_Z15_sobel_process_PhS_ii,@function
_Z15_sobel_process_PhS_ii:              # @_Z15_sobel_process_PhS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movq	%rdi, %r12
	xorl	%eax, %eax
	leaq	8(%rsp), %r13
	movq	%rax, (%r13)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	movl	%ecx, %eax
	imull	%edx, %eax
	movslq	%eax, %r14
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	%r12, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebp, %eax
	shrl	$5, %eax
	movl	%r15d, %ecx
	shrl	$5, %ecx
	incl	%ecx
	shlq	$32, %rcx
	leaq	(%rcx,%rax), %rdi
	incq	%rdi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	callq	_Z37__device_stub___sobel_process_kernel_PhS_ii
.LBB2_2:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z15_sobel_process_PhS_ii, .Lfunc_end2-_Z15_sobel_process_PhS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z15_split_channel_PhS_S_S_ii   # -- Begin function _Z15_split_channel_PhS_S_S_ii
	.type	_Z15_split_channel_PhS_S_S_ii,@function
_Z15_split_channel_PhS_S_S_ii:          # @_Z15_split_channel_PhS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movl	%r8d, %r14d
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	movq	%rdx, 56(%rsp)                  # 8-byte Spill
	movq	%rsi, 48(%rsp)                  # 8-byte Spill
	movq	%rdi, 40(%rsp)                  # 8-byte Spill
	xorl	%eax, %eax
	leaq	32(%rsp), %r13
	movq	%rax, (%r13)
	leaq	24(%rsp), %r12
	movq	%rax, (%r12)
	leaq	16(%rsp), %rcx
	movq	%rax, (%rcx)
	leaq	8(%rsp), %rcx
	movq	%rax, (%rcx)
	movl	%r9d, %eax
	imull	%r8d, %eax
	movslq	%eax, %r15
	leaq	(%r15,%r15,2), %rbp
	movq	%r13, %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	1(%rbx), %eax
	leal	1(%r14), %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	%r14d, %r8d
	movl	%ebx, %r9d
	callq	_Z37__device_stub___split_channel_kernel_PhS_S_S_ii
.LBB3_2:
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rsi
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rsi
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z15_split_channel_PhS_S_S_ii, .Lfunc_end3-_Z15_split_channel_PhS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22_sobel_process_kernel_PhS_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22_split_channel_kernel_PhS_S_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22_sobel_process_kernel_PhS_ii,@object # @_Z22_sobel_process_kernel_PhS_ii
	.section	.rodata,"a",@progbits
	.globl	_Z22_sobel_process_kernel_PhS_ii
	.p2align	3, 0x0
_Z22_sobel_process_kernel_PhS_ii:
	.quad	_Z37__device_stub___sobel_process_kernel_PhS_ii
	.size	_Z22_sobel_process_kernel_PhS_ii, 8

	.type	_Z22_split_channel_kernel_PhS_S_S_ii,@object # @_Z22_split_channel_kernel_PhS_S_S_ii
	.globl	_Z22_split_channel_kernel_PhS_S_S_ii
	.p2align	3, 0x0
_Z22_split_channel_kernel_PhS_S_S_ii:
	.quad	_Z37__device_stub___split_channel_kernel_PhS_S_S_ii
	.size	_Z22_split_channel_kernel_PhS_S_S_ii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z22_sobel_process_kernel_PhS_ii"
	.size	.L__unnamed_1, 33

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z22_split_channel_kernel_PhS_S_S_ii"
	.size	.L__unnamed_2, 37

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub___sobel_process_kernel_PhS_ii
	.addrsig_sym _Z37__device_stub___split_channel_kernel_PhS_S_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22_sobel_process_kernel_PhS_ii
	.addrsig_sym _Z22_split_channel_kernel_PhS_S_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22_sobel_process_kernel_PhS_ii ; -- Begin function _Z22_sobel_process_kernel_PhS_ii
	.globl	_Z22_sobel_process_kernel_PhS_ii
	.p2align	8
	.type	_Z22_sobel_process_kernel_PhS_ii,@function
_Z22_sobel_process_kernel_PhS_ii:       ; @_Z22_sobel_process_kernel_PhS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
	v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	v_cmp_gt_i32_e64 s2, s5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, vcc_lo
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	v_add_nc_u32_e32 v5, 1, v2
	s_add_i32 s4, s4, -1
	v_add_nc_u32_e32 v3, -1, v0
	v_add_nc_u32_e32 v4, -1, v2
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mul_lo_u32 v1, v2, s5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v3, 0, v3 :: v_dual_add_nc_u32 v6, 1, v0
	v_cmp_lt_i32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s4, v2
	v_add_nc_u32_e32 v12, v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v4, v4, s5
	v_cndmask_b32_e32 v2, s4, v5, vcc_lo
	s_add_i32 s4, s5, -1
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v2, v2, s5
	v_add_nc_u32_e32 v7, v4, v0
	v_dual_cndmask_b32 v5, s4, v6 :: v_dual_add_nc_u32 v8, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v6, v1, v5
	v_add_nc_u32_e32 v14, v2, v3
	v_add_nc_u32_e32 v9, v4, v5
	v_add_nc_u32_e32 v13, v2, v0
	v_add_nc_u32_e32 v10, v2, v5
	v_ashrrev_i32_e32 v3, 31, v6
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v6
	v_ashrrev_i32_e32 v5, 31, v7
	v_ashrrev_i32_e32 v11, 31, v8
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v7
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v11, vcc_lo
	v_ashrrev_i32_e32 v11, 31, v9
	v_ashrrev_i32_e32 v15, 31, v10
	v_add_co_u32 v8, vcc_lo, s0, v9
	v_add_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v11, vcc_lo
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v15, vcc_lo
	s_clause 0x3
	global_load_u8 v15, v[2:3], off
	global_load_u8 v16, v[4:5], off
	global_load_u8 v6, v[6:7], off
	global_load_u8 v7, v[8:9], off
	v_ashrrev_i32_e32 v3, 31, v12
	v_ashrrev_i32_e32 v5, 31, v14
	global_load_u8 v8, v[10:11], off
	v_add_co_u32 v2, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v14
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	s_clause 0x1
	global_load_u8 v9, v[2:3], off
	global_load_u8 v4, v[4:5], off
	v_ashrrev_i32_e32 v3, 31, v13
	v_add_co_u32 v2, vcc_lo, s0, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_mov_b32 s1, 0x3e76c4e1
	global_load_u8 v2, v[2:3], off
	s_waitcnt vmcnt(7)
	v_cvt_f32_ubyte0_e32 v3, v15
	s_waitcnt vmcnt(5)
	v_cvt_f32_ubyte0_e32 v6, v6
	s_waitcnt vmcnt(4)
	v_cvt_f32_ubyte0_e32 v5, v7
	s_waitcnt vmcnt(3)
	v_cvt_f32_ubyte0_e32 v7, v8
	v_cvt_f32_ubyte0_e32 v8, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, 2.0, v3, v5
	v_add_f32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v3, v3, v6 :: v_dual_fmac_f32 v6, 2.0, v8
	s_waitcnt vmcnt(2)
	v_cvt_f32_ubyte0_e32 v8, v9
	s_waitcnt vmcnt(1)
	v_cvt_f32_ubyte0_e32 v4, v4
	v_fmac_f32_e32 v3, -2.0, v8
	v_add_f32_e32 v5, v6, v5
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v2, v3, v4
	v_sub_f32_e32 v5, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f32_e64 v4, |v2|
	v_fmac_f32_e32 v5, -2.0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	v_sub_f32_e32 v3, v5, v7
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v4, v4, v5
	v_add_f32_e32 v7, 1.0, v4
	v_add_f32_e32 v9, -1.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, -1.0, v7
	v_sub_f32_e32 v4, v4, v13
	v_frexp_mant_f32_e64 v6, |v3|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v6
	v_cndmask_b32_e64 v5, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v5, v6, v5
	v_add_f32_e32 v8, 1.0, v5
	v_add_f32_e32 v12, -1.0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v8
	v_add_f32_e32 v13, -1.0, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v15, v12, v10
	v_mul_f32_e32 v16, v8, v15
	v_rcp_f32_e32 v6, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v11, v9, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, v7, v11
	v_fma_f32 v7, v11, v7, -v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v7, v11, v4 :: v_dual_sub_f32 v4, v5, v13
	v_fma_f32 v5, v15, v8, -v16
	v_fmac_f32_e32 v5, v15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v16, v5
	v_sub_f32_e32 v17, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v12, v17
	v_add_f32_e32 v8, v14, v7
	v_sub_f32_e32 v4, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v8, v14 :: v_dual_sub_f32 v9, v9, v4
	v_dual_sub_f32 v7, v14, v7 :: v_dual_sub_f32 v8, v9, v8
	v_sub_f32_e32 v9, v13, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v7, v7, v8 :: v_dual_sub_f32 v8, v12, v13
	v_add_f32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v6, v4
	v_add_f32_e32 v6, v11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v6, v11
	v_sub_f32_e32 v5, v9, v5
	v_dual_mul_f32 v9, v6, v6 :: v_dual_sub_f32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v8
	v_add_f32_e32 v11, v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v17, v5
	v_mul_f32_e32 v5, v10, v5
	v_fma_f32 v10, v6, v6, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v15, v5
	v_fmac_f32_e32 v10, v6, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v12, v8, v8
	v_sub_f32_e32 v7, v8, v15
	v_add_f32_e32 v13, v9, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v5, v5, v7
	v_fma_f32 v7, v8, v8, -v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v13, v9
	v_add_f32_e32 v11, v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v10, v9
	v_fmac_f32_e32 v7, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v11, s1, v13, 0x3e91f4c4 :: v_dual_add_f32 v14, v12, v7
	v_dual_fmaak_f32 v11, v13, v11, 0x3ecccdef :: v_dual_sub_f32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v16, v13, v11 :: v_dual_mul_f32 v23, v8, v14
	v_sub_f32_e32 v7, v7, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, v13, v11, -v16
	v_dual_fmaak_f32 v15, s1, v14, 0x3e91f4c4 :: v_dual_fmac_f32 v10, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v15, v14, v15, 0x3ecccdef :: v_dual_add_f32 v12, v16, v10
	v_add_f32_e32 v19, 0x3f2aaaaa, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v17, v14, v15 :: v_dual_sub_f32 v16, v12, v16
	v_fma_f32 v11, v14, v15, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v10, v16
	v_add_f32_e32 v16, 0xbf2aaaaa, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v11, v7, v15 :: v_dual_add_f32 v10, 0x31739010, v10
	v_sub_f32_e32 v12, v12, v16
	v_frexp_exp_i32_f32_e32 v15, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, v17, v11
	v_add_f32_e32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
	v_add_f32_e32 v22, 0x3f2aaaaa, v20
	v_mul_f32_e32 v18, v6, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v20, v17 :: v_dual_add_f32 v16, 0xbf2aaaaa, v22
	v_fma_f32 v21, v13, v6, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v17
	v_fma_f32 v17, v14, v8, -v23
	v_sub_f32_e32 v12, v20, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v21, v13, v4
	v_add_f32_e32 v13, v19, v10
	v_fmac_f32_e32 v17, v14, v5
	v_ldexp_f32 v4, v4, 1
	v_ldexp_f32 v5, v5, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v21, v9, v6 :: v_dual_sub_f32 v14, v19, v13
	v_ldexp_f32 v6, v6, 1
	v_frexp_exp_i32_f32_e32 v9, v3
	v_dual_add_f32 v10, v10, v14 :: v_dual_fmac_f32 v17, v7, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v18, v21
	v_ldexp_f32 v8, v8, 1
	v_sub_f32_e32 v18, v7, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v19, v7, v13 :: v_dual_sub_f32 v18, v21, v18
	v_add_f32_e32 v11, 0x31739010, v11
	v_add_f32_e32 v11, v11, v12
	v_cvt_f32_i32_e32 v12, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v22, v11
	v_sub_f32_e32 v14, v22, v15
	v_add_f32_e32 v16, v23, v17
	v_fma_f32 v22, v7, v13, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v11, v11, v14 :: v_dual_mul_f32 v20, v16, v15
	v_dual_sub_f32 v21, v16, v23 :: v_dual_fmac_f32 v22, v7, v10
	v_subrev_co_ci_u32_e64 v7, vcc_lo, 0, v9, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v14, v16, v15, -v20
	v_dual_sub_f32 v9, v17, v21 :: v_dual_mul_f32 v10, 0x3f317218, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v7, v7
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v2|
	v_fmac_f32_e32 v14, v16, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, 0x3f317218, v12, -v10
	v_fmac_f32_e32 v14, v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v22, v18, v13 :: v_dual_fmac_f32 v11, 0xb102e308, v12
	v_add_f32_e32 v13, v20, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v8, v13
	v_dual_sub_f32 v8, v18, v8 :: v_dual_add_f32 v9, v19, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v9, v19
	v_sub_f32_e32 v17, v22, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v17
	v_add_f32_e32 v16, v6, v9
	v_sub_f32_e32 v6, v16, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v9, v6
	v_add_f32_e32 v4, v4, v6
	v_dual_add_f32 v6, v10, v11 :: v_dual_sub_f32 v19, v13, v20
	v_sub_f32_e32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v6, v10
	v_sub_f32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v14
	v_add_f32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v15, 0x3f317218, v7 :: v_dual_add_f32 v12, v18, v5
	v_fma_f32 v9, 0x3f317218, v7, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v18, v12, v18 :: v_dual_fmac_f32 v9, 0xb102e308, v7
	v_dual_sub_f32 v10, v11, v10 :: v_dual_add_f32 v7, v16, v4
	v_dual_add_f32 v8, v15, v9 :: v_dual_add_f32 v13, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v8, v15
	v_dual_add_f32 v14, v8, v12 :: v_dual_sub_f32 v17, v13, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v9, v9, v15
	v_sub_f32_e32 v15, v13, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v6, v6, v15 :: v_dual_sub_f32 v11, v7, v16
	v_sub_f32_e32 v16, v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v4, v4, v11 :: v_dual_sub_f32 v11, v14, v16
	v_sub_f32_e32 v12, v12, v16
	v_dual_sub_f32 v8, v8, v11 :: v_dual_add_f32 v11, v10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v8, v12, v8
	v_sub_f32_e32 v12, v11, v10
	v_sub_f32_e32 v7, v7, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v5, v5, v18 :: v_dual_sub_f32 v4, v4, v12
	v_dual_add_f32 v6, v7, v6 :: v_dual_add_f32 v7, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v11, v6
	v_sub_f32_e32 v11, v11, v12
	v_add_f32_e32 v8, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v15, v7, v9 :: v_dual_add_f32 v16, v13, v6
	v_sub_f32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v12, v14, v8 :: v_dual_sub_f32 v11, v16, v13
	v_add_f32_e32 v4, v4, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v6, v6, v11
	v_dual_add_f32 v4, v4, v6 :: v_dual_sub_f32 v7, v7, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v6, v16, v4 :: v_dual_sub_f32 v5, v5, v15
	v_sub_f32_e32 v7, v9, v7
	v_sub_f32_e32 v9, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v5, v7
	v_sub_f32_e32 v7, v8, v9
	v_add_f32_e32 v9, v6, v6
	v_sub_f32_e32 v8, v6, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_class_f32_e64 vcc_lo, v9, 0x204
	v_dual_add_f32 v5, v5, v7 :: v_dual_sub_f32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, v12, v5
	v_sub_f32_e32 v10, v7, v12
	v_mul_f32_e32 v12, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_add_f32 v8, v7, v7 :: v_dual_sub_f32 v5, v5, v10
	v_mul_f32_e32 v11, 0, v6
	v_fma_f32 v6, v6, 2.0, -v9
	v_dual_fmac_f32 v12, 2.0, v5 :: v_dual_fmac_f32 v11, 2.0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v7, 2.0, -v8
	v_dual_add_f32 v5, v6, v11 :: v_dual_add_f32 v4, v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v6, v9, v5 :: v_dual_add_f32 v7, v8, v4
	v_cndmask_b32_e32 v10, v6, v9, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v6, v6, v9 :: v_dual_cndmask_b32 v11, v7, v8
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v10, v12
	v_cndmask_b32_e64 v13, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	v_dual_mul_f32 v16, 0x3fb8aa3b, v14 :: v_dual_sub_f32 v15, v11, v13
	v_sub_f32_e32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, 0x3fb8aa3b, v14, -v16
	v_mul_f32_e32 v17, 0x3fb8aa3b, v15
	v_rndne_f32_e32 v19, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v5, 0, v5 :: v_dual_fmac_f32 v18, 0x32a5705f, v14
	v_fma_f32 v20, 0x3fb8aa3b, v15, -v17
	v_rndne_f32_e32 v21, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v16, v16, v19 :: v_dual_sub_f32 v7, v7, v8
	v_cvt_i32_f32_e32 v8, v19
	v_dual_fmac_f32 v20, 0x32a5705f, v15 :: v_dual_sub_f32 v17, v17, v21
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v11|
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v4, v7
	v_add_f32_e32 v9, v16, v18
	v_cvt_i32_f32_e32 v10, v21
	v_add_f32_e32 v16, v17, v20
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_exp_f32_e32 v6, v9
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
	v_exp_f32_e32 v9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v13, v4
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v6, v8
	v_ldexp_f32 v7, v9, v10
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, 0, v7, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
	v_dual_add_f32 v5, v12, v5 :: v_dual_cndmask_b32 v6, 0x7f800000, v6
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v6, v5, v6
	v_cndmask_b32_e32 v7, 0x7f800000, v7, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
	v_fma_f32 v4, v7, v4, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v7
	v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v3|
	v_cmp_neq_f32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v4, 0x7f800000, |v4|, s0
	v_cndmask_b32_e32 v2, 0, v5, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0, v4, vcc_lo
	v_add_f32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v3, 0x4f800000, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
	v_cndmask_b32_e32 v2, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v4, -1, v3
	v_add_nc_u32_e32 v5, 1, v3
	v_fma_f32 v6, -v4, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v3, v2
	v_cmp_ge_f32_e64 s0, 0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v4, s0
	v_cmp_lt_f32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v3, v3, v5, s0
	v_mul_f32_e32 v4, 0x37800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v2, 0x260
	v_cndmask_b32_e32 v1, v3, v2, vcc_lo
	v_ashrrev_i32_e32 v2, 31, v0
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v3, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
	global_store_b8 v[0:1], v3, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22_sobel_process_kernel_PhS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22_sobel_process_kernel_PhS_ii, .Lfunc_end0-_Z22_sobel_process_kernel_PhS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2544
; NumSgprs: 18
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22_split_channel_kernel_PhS_S_S_ii ; -- Begin function _Z22_split_channel_kernel_PhS_S_S_ii
	.globl	_Z22_split_channel_kernel_PhS_S_S_ii
	.p2align	8
	.type	_Z22_split_channel_kernel_PhS_S_S_ii,@function
_Z22_split_channel_kernel_PhS_S_S_ii:   ; @_Z22_split_channel_kernel_PhS_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s4, 16
	s_and_b32 s4, s4, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
	s_mul_i32 s14, s14, s4
	s_mul_i32 s2, s3, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v2, s3
	v_add3_u32 v0, s14, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_lshl_add_u32 v1, v0, 1, v0
	v_ashrrev_i32_e32 v6, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
	global_load_u8 v5, v[1:2], off
	s_waitcnt vmcnt(0)
	global_store_b8 v[3:4], v5, off
	global_load_u8 v5, v[1:2], off offset:1
	v_add_co_u32 v3, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_waitcnt vmcnt(0)
	global_store_b8 v[3:4], v5, off
	global_load_u8 v2, v[1:2], off offset:2
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22_split_channel_kernel_PhS_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z22_split_channel_kernel_PhS_S_S_ii, .Lfunc_end1-_Z22_split_channel_kernel_PhS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 256
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22_sobel_process_kernel_PhS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22_sobel_process_kernel_PhS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     24
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22_split_channel_kernel_PhS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z22_split_channel_kernel_PhS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
