/* Block size X: 32 */
__global__ void fct_ale_pre_comm( const int max_levels, const int num_nodes, const int max_num_elems, const int * __restrict__ node_levels, const int * __restrict__ elem_levels, const int * __restrict__ node_elems, const int * __restrict__ node_num_elems, const int * __restrict__ elem_nodes, const double * __restrict__ fct_low_order, const double * __restrict__ ttf, const double * __restrict__ fct_adf_v, const double * __restrict__ fct_adf_h, double * __restrict__ UVrhs, double * __restrict__ fct_ttf_max, double * __restrict__ fct_ttf_min, double * __restrict__ fct_plus, double * __restrict__ fct_minus, const double bignr)
{
    extern __shared__ double sharedBuffer[];
    double * tvert_max = (double *)(sharedBuffer);
    double * tvert_min = (double *)(&sharedBuffer[max_levels]);
    const int node = (blockIdx.x * max_levels);
    const int numelems = node_num_elems[blockIdx.x];

    for ( int level = threadIdx.x; level < node_levels[blockIdx.x]; level += 32 )
    {
        double tvmax = -bignr;
        double tvmin = bignr;
        for ( int elem = 0; elem < numelems ; elem++ )
        {
            int elem_index = node_elems[blockIdx.x * max_num_elems + elem] - 1;
            int node_indices[3] = { (elem_nodes[3 * elem_index] - 1) * max_levels + level,
                                    (elem_nodes[3 * elem_index + 1] - 1) * max_levels + level,
                                    (elem_nodes[3 * elem_index + 2] - 1) * max_levels + level};
            double fctttfmax[3]  = {fmax(fct_low_order[node_indices[0]], ttf[node_indices[0]]), 
                                    fmax(fct_low_order[node_indices[1]], ttf[node_indices[1]]), 
                                    fmax(fct_low_order[node_indices[2]], ttf[node_indices[2]])};
            double fctttfmin[3]  = {fmin(fct_low_order[node_indices[0]], ttf[node_indices[0]]), 
                                    fmin(fct_low_order[node_indices[1]], ttf[node_indices[1]]), 
                                    fmin(fct_low_order[node_indices[2]], ttf[node_indices[2]])};
            double uvrhs1, uvrhs2;
            if(level < elem_levels[elem_index] - 1)
            {
                uvrhs1 = fmax(fctttfmax[0], fmax(fctttfmax[1], fctttfmax[2]));
                uvrhs2 = fmin(fctttfmin[0], fmin(fctttfmin[1], fctttfmin[2]));
            }
            else
            {
                uvrhs1 = bignr;
                uvrhs2 = -bignr;
            }
            tvmax = fmax(uvrhs1, tvmax);
            tvmin = fmin(uvrhs2, tvmin);
            UVrhs[2 * elem_index * max_levels + level] = uvrhs1;
            UVrhs[2 * elem_index * max_levels + level + 1] = uvrhs2;
        }
        tvert_max[level] = tvmax;
        tvert_min[level] = tvmin;
    }
    __syncthreads();
    for ( int level = threadIdx.x; level < node_levels[blockIdx.x]; level += 32 )
    {
        if(level == 0 or level == node_levels[blockIdx.x] - 2)
        {
            fct_ttf_max[node + level] = fmax(fct_low_order[node + level], ttf[node + level]);
            fct_ttf_min[node + level] = fmin(fct_low_order[node + level], ttf[node + level]);
        }
        else
        {
            fct_ttf_max[node + level] = fmax(tvert_max[level], fmax(tvert_max[level - 1], tvert_max[level + 1]));
            fct_ttf_min[node + level] = fmin(tvert_min[level], fmin(tvert_min[level - 1], tvert_min[level + 1]));
        }
        int adf_index = blockIdx.x * (max_levels + 1) + level;
        fct_plus[node + level]  = fmax(0.,fct_adf_v[adf_index]) + fmax(0.,-fct_adf_v[adf_index + 1]);
        fct_minus[node + level] = fmin(0.,fct_adf_v[adf_index]) + fmin(0.,-fct_adf_v[adf_index + 1]);
    }
}

	.file	"tmpxft_002d2972_00000000-6_fct_ale_pre_comm.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z79__device_stub__Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_diiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.type	_Z79__device_stub__Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_diiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, @function
_Z79__device_stub__Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_diiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$376, %rsp
	.cfi_def_cfa_offset 384
	movl	%edi, 28(%rsp)
	leaq	168(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	180(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	152(%rsp), %rdx
	movsd	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%rcx, 40(%rsp)
	leaq	160(%rsp), %rcx
	movq	%rax, 216(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	movq	384(%rsp), %rax
	movq	%r8, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 264(%rsp)
	movq	392(%rsp), %rax
	movq	%r9, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 272(%rsp)
	movq	400(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 280(%rsp)
	movq	408(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 288(%rsp)
	movq	416(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 296(%rsp)
	movq	424(%rsp), %rax
	movl	$1, 176(%rsp)
	movq	%rax, 104(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 304(%rsp)
	movq	432(%rsp), %rax
	movl	$1, 188(%rsp)
	movq	%rax, 112(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 312(%rsp)
	movq	440(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	120(%rsp), %rax
	movq	%rax, 320(%rsp)
	movq	448(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	128(%rsp), %rax
	movq	%rax, 328(%rsp)
	movq	456(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	136(%rsp), %rax
	movq	%rax, 336(%rsp)
	movq	464(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	144(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 352(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 168(%rsp)
	movq	%rax, 180(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	160(%rsp)
	.cfi_def_cfa_offset 392
	leaq	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d(%rip), %rdi
	pushq	160(%rsp)
	.cfi_def_cfa_offset 400
	movq	196(%rsp), %rcx
	movl	204(%rsp), %r8d
	movq	184(%rsp), %rsi
	movl	192(%rsp), %edx
	leaq	232(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 392
	popq	%rdx
	.cfi_def_cfa_offset 384
.L2:
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$376, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z79__device_stub__Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_diiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, .-_Z79__device_stub__Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_diiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.globl	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.type	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, @function
_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z79__device_stub__Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_diiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.cfi_endproc
.LFE2033:
	.size	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, .-_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/* Block size X: 32 */
__global__ void fct_ale_pre_comm( const int max_levels, const int num_nodes, const int max_num_elems, const int * __restrict__ node_levels, const int * __restrict__ elem_levels, const int * __restrict__ node_elems, const int * __restrict__ node_num_elems, const int * __restrict__ elem_nodes, const double * __restrict__ fct_low_order, const double * __restrict__ ttf, const double * __restrict__ fct_adf_v, const double * __restrict__ fct_adf_h, double * __restrict__ UVrhs, double * __restrict__ fct_ttf_max, double * __restrict__ fct_ttf_min, double * __restrict__ fct_plus, double * __restrict__ fct_minus, const double bignr)
{
    extern __shared__ double sharedBuffer[];
    double * tvert_max = (double *)(sharedBuffer);
    double * tvert_min = (double *)(&sharedBuffer[max_levels]);
    const int node = (blockIdx.x * max_levels);
    const int numelems = node_num_elems[blockIdx.x];

    for ( int level = threadIdx.x; level < node_levels[blockIdx.x]; level += 32 )
    {
        double tvmax = -bignr;
        double tvmin = bignr;
        for ( int elem = 0; elem < numelems ; elem++ )
        {
            int elem_index = node_elems[blockIdx.x * max_num_elems + elem] - 1;
            int node_indices[3] = { (elem_nodes[3 * elem_index] - 1) * max_levels + level,
                                    (elem_nodes[3 * elem_index + 1] - 1) * max_levels + level,
                                    (elem_nodes[3 * elem_index + 2] - 1) * max_levels + level};
            double fctttfmax[3]  = {fmax(fct_low_order[node_indices[0]], ttf[node_indices[0]]), 
                                    fmax(fct_low_order[node_indices[1]], ttf[node_indices[1]]), 
                                    fmax(fct_low_order[node_indices[2]], ttf[node_indices[2]])};
            double fctttfmin[3]  = {fmin(fct_low_order[node_indices[0]], ttf[node_indices[0]]), 
                                    fmin(fct_low_order[node_indices[1]], ttf[node_indices[1]]), 
                                    fmin(fct_low_order[node_indices[2]], ttf[node_indices[2]])};
            double uvrhs1, uvrhs2;
            if(level < elem_levels[elem_index] - 1)
            {
                uvrhs1 = fmax(fctttfmax[0], fmax(fctttfmax[1], fctttfmax[2]));
                uvrhs2 = fmin(fctttfmin[0], fmin(fctttfmin[1], fctttfmin[2]));
            }
            else
            {
                uvrhs1 = bignr;
                uvrhs2 = -bignr;
            }
            tvmax = fmax(uvrhs1, tvmax);
            tvmin = fmin(uvrhs2, tvmin);
            UVrhs[2 * elem_index * max_levels + level] = uvrhs1;
            UVrhs[2 * elem_index * max_levels + level + 1] = uvrhs2;
        }
        tvert_max[level] = tvmax;
        tvert_min[level] = tvmin;
    }
    __syncthreads();
    for ( int level = threadIdx.x; level < node_levels[blockIdx.x]; level += 32 )
    {
        if(level == 0 or level == node_levels[blockIdx.x] - 2)
        {
            fct_ttf_max[node + level] = fmax(fct_low_order[node + level], ttf[node + level]);
            fct_ttf_min[node + level] = fmin(fct_low_order[node + level], ttf[node + level]);
        }
        else
        {
            fct_ttf_max[node + level] = fmax(tvert_max[level], fmax(tvert_max[level - 1], tvert_max[level + 1]));
            fct_ttf_min[node + level] = fmin(tvert_min[level], fmin(tvert_min[level - 1], tvert_min[level + 1]));
        }
        int adf_index = blockIdx.x * (max_levels + 1) + level;
        fct_plus[node + level]  = fmax(0.,fct_adf_v[adf_index]) + fmax(0.,-fct_adf_v[adf_index + 1]);
        fct_minus[node + level] = fmin(0.,fct_adf_v[adf_index]) + fmin(0.,-fct_adf_v[adf_index + 1]);
    }
}

	.text
	.file	"fct_ale_pre_comm.hip"
	.globl	_Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d # -- Begin function _Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.type	_Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d,@function
_Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d: # @_Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %r10
	movl	%edi, (%r10)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	32(%rsp), %rax
	movsd	%xmm0, (%rax)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rcx
	movq	%rcx, 48(%rbx)
	leaq	296(%rsp), %rcx
	movq	%rcx, 56(%rbx)
	leaq	304(%rsp), %rcx
	movq	%rcx, 64(%rbx)
	leaq	312(%rsp), %rcx
	movq	%rcx, 72(%rbx)
	leaq	320(%rsp), %rcx
	movq	%rcx, 80(%rbx)
	leaq	328(%rsp), %rcx
	movq	%rcx, 88(%rbx)
	leaq	336(%rsp), %rcx
	movq	%rcx, 96(%rbx)
	leaq	344(%rsp), %rcx
	movq	%rcx, 104(%rbx)
	leaq	352(%rsp), %rcx
	movq	%rcx, 112(%rbx)
	leaq	360(%rsp), %rcx
	movq	%rcx, 120(%rbx)
	leaq	368(%rsp), %rcx
	movq	%rcx, 128(%rbx)
	movq	%rax, 136(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, .Lfunc_end0-_Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d,@object # @_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.section	.rodata,"a",@progbits
	.globl	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.p2align	3, 0x0
_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d:
	.quad	_Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.size	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d"
	.size	.L__unnamed_1, 66

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d ; -- Begin function _Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.globl	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
	.p2align	8
	.type	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d,@function
_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d: ; @_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mov_b32 s29, 0
	s_mov_b32 s26, s15
	s_mov_b32 s27, s29
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[34:35], s[26:27], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s2, s34
	s_addc_u32 s3, s3, s35
	s_load_b32 s3, s[2:3], 0x0
	s_clause 0x3
	s_load_b32 s27, s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x60
	s_load_b64 s[24:25], s[0:1], 0x48
	s_load_b128 s[20:23], s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s33, s2
	s_cbranch_execz .LBB0_8
; %bb.1:                                ; %.lr.ph160
	s_load_b256 s[12:19], s[0:1], 0x18
	s_lshl_b32 s28, s27, 3
	s_load_b64 s[30:31], s[0:1], 0x80
	s_add_i32 s36, s28, 0
	v_mov_b32_e32 v5, v0
	s_mov_b32 s39, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s16, s34
	s_addc_u32 s17, s17, s35
	s_load_b32 s34, s[16:17], 0x0
	s_clause 0x1
	s_load_b32 s28, s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x58
	s_xor_b32 s17, s31, 0x80000000
	s_mov_b32 s16, s30
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s34, 0
	s_mul_i32 s35, s26, s28
	s_cselect_b32 s37, -1, 0
	s_lshl_b32 s38, s27, 1
	s_add_u32 s12, s12, -4
	s_addc_u32 s13, s13, -1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s17
	v_dual_mov_b32 v6, s30 :: v_dual_mov_b32 v7, s31
	s_and_not1_b32 vcc_lo, exec_lo, s37
	s_cbranch_vccnz .LBB0_7
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v8, s16 :: v_dual_mov_b32 v9, s17
	v_dual_mov_b32 v6, s30 :: v_dual_mov_b32 v7, s31
	s_mov_b32 s28, s35
	s_mov_b32 s40, s34
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b64 s[42:43], s[28:29], 2
	v_dual_mov_b32 v1, s30 :: v_dual_mov_b32 v2, s31
	s_add_u32 s42, s14, s42
	s_addc_u32 s43, s15, s43
	v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v4, s17
	s_load_b32 s42, s[42:43], 0x0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s43, s42, 31
	s_add_i32 s41, s42, -1
	s_lshl_b64 s[44:45], s[42:43], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_u32 s42, s12, s44
	s_addc_u32 s43, s13, s45
	s_load_b32 s42, s[42:43], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s42, s42, -1
	v_cmp_gt_i32_e32 vcc_lo, s42, v5
	s_and_saveexec_b32 s42, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	s_mul_i32 s44, s41, 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s45, s44, 31
	s_lshl_b64 s[44:45], s[44:45], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s44, s18, s44
	s_addc_u32 s45, s19, s45
	s_clause 0x1
	s_load_b32 s43, s[44:45], 0x8
	s_load_b64 s[44:45], s[44:45], 0x0
	s_waitcnt lgkmcnt(0)
	s_add_i32 s43, s43, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s43, s27, v[5:6]
	s_add_i32 s43, s45, -1
	v_mad_u64_u32 v[3:4], null, s43, s27, v[5:6]
	s_add_i32 s43, s44, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[14:15], null, s43, s27, v[5:6]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[14:15], 3, v[14:15]
	v_add_co_u32 v10, vcc_lo, s20, v1
	v_add_co_ci_u32_e32 v11, vcc_lo, s21, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s22, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s23, v2, vcc_lo
	v_add_co_u32 v12, vcc_lo, s22, v3
	v_add_co_ci_u32_e32 v13, vcc_lo, s23, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s20, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s21, v4, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[10:11], v[10:11], off
	global_load_b64 v[12:13], v[12:13], off
	global_load_b64 v[3:4], v[3:4], off
	v_add_co_u32 v16, vcc_lo, s22, v14
	v_add_co_ci_u32_e32 v17, vcc_lo, s23, v15, vcc_lo
	v_add_co_u32 v14, vcc_lo, s20, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s21, v15, vcc_lo
	global_load_b64 v[16:17], v[16:17], off
	global_load_b64 v[14:15], v[14:15], off
	s_waitcnt vmcnt(5)
	v_max_f64 v[1:2], v[1:2], v[1:2]
	s_waitcnt vmcnt(4)
	v_max_f64 v[10:11], v[10:11], v[10:11]
	s_waitcnt vmcnt(3)
	v_max_f64 v[12:13], v[12:13], v[12:13]
	s_waitcnt vmcnt(2)
	v_max_f64 v[3:4], v[3:4], v[3:4]
	s_waitcnt vmcnt(1)
	v_max_f64 v[16:17], v[16:17], v[16:17]
	s_waitcnt vmcnt(0)
	v_max_f64 v[14:15], v[14:15], v[14:15]
	v_min_f64 v[18:19], v[10:11], v[1:2]
	v_max_f64 v[1:2], v[10:11], v[1:2]
	v_max_f64 v[10:11], v[3:4], v[12:13]
	v_min_f64 v[3:4], v[3:4], v[12:13]
	v_min_f64 v[12:13], v[14:15], v[16:17]
	v_max_f64 v[14:15], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_max_f64 v[1:2], v[10:11], v[1:2]
	v_min_f64 v[3:4], v[3:4], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_f64 v[1:2], v[14:15], v[1:2]
	v_min_f64 v[3:4], v[12:13], v[3:4]
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s42
	v_max_f64 v[6:7], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_2)
	v_max_f64 v[12:13], v[3:4], v[3:4]
	v_max_f64 v[8:9], v[8:9], v[8:9]
	v_max_f64 v[10:11], v[1:2], v[1:2]
	s_add_i32 s40, s40, -1
	s_add_i32 s28, s28, 1
	s_cmp_eq_u32 s40, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[6:7], v[12:13], v[6:7]
	v_max_f64 v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, s38, s41, v[5:6]
	v_ashrrev_i32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 3, v[10:11]
	v_add_co_u32 v10, vcc_lo, s0, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	global_store_b128 v[10:11], v[1:4], off
	s_cbranch_scc0 .LBB0_4
.LBB0_7:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b32_e32 v1, 3, v5
	v_add_nc_u32_e32 v5, 32, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, 0, v1
	v_cmp_le_i32_e32 vcc_lo, s3, v5
	v_add_nc_u32_e32 v1, s36, v1
	ds_store_b64 v2, v[8:9]
	ds_store_b64 v1, v[6:7]
	s_or_b32 s39, vcc_lo, s39
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s39
	s_cbranch_execnz .LBB0_2
.LBB0_8:                                ; %Flow196
	s_or_b32 exec_lo, exec_lo, s33
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_15
; %bb.9:                                ; %.lr.ph165
	v_lshlrev_b32_e32 v1, 3, v0
	s_add_i32 s12, s27, 1
	s_mul_i32 s1, s26, s27
	s_add_i32 s2, s3, -2
	s_mul_i32 s12, s12, s26
	v_add3_u32 v5, v1, 0, -8
	s_mov_b32 s13, 0
	s_lshl_b32 s14, s27, 3
.LBB0_10:                               ; =>This Inner Loop Header: Depth=1
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cmp_ne_u32_e64 s0, s2, v0
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr1_vgpr2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s15, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s15
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	v_add_nc_u32_e32 v12, s14, v5
	ds_load_2addr_b64 v[1:4], v5 offset1:1
	ds_load_b64 v[10:11], v5 offset:16
	ds_load_2addr_b64 v[6:9], v12 offset1:1
	ds_load_b64 v[12:13], v12 offset:16
	s_waitcnt lgkmcnt(3)
	v_max_f64 v[1:2], v[1:2], v[1:2]
	s_waitcnt lgkmcnt(2)
	v_max_f64 v[10:11], v[10:11], v[10:11]
	s_waitcnt lgkmcnt(1)
	v_max_f64 v[6:7], v[6:7], v[6:7]
	s_waitcnt lgkmcnt(0)
	v_max_f64 v[12:13], v[12:13], v[12:13]
	v_max_f64 v[3:4], v[3:4], v[3:4]
	v_max_f64 v[8:9], v[8:9], v[8:9]
	v_max_f64 v[1:2], v[1:2], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[6:7], v[6:7], v[12:13]
	v_max_f64 v[10:11], v[3:4], v[1:2]
	v_add_nc_u32_e32 v1, s1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_f64 v[3:4], v[8:9], v[6:7]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 3, v[1:2]
	v_add_co_u32 v6, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_store_b64 v[6:7], v[10:11], off
.LBB0_12:                               ; %Flow
                                        ;   in Loop: Header=BB0_10 Depth=1
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_10 Depth=1
	v_add_nc_u32_e32 v1, s1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[6:7], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s22, v6
	v_add_co_ci_u32_e32 v4, vcc_lo, s23, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s20, v6
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v6
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[8:9], v[8:9], off
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	s_waitcnt vmcnt(1)
	v_max_f64 v[3:4], v[3:4], v[3:4]
	s_waitcnt vmcnt(0)
	v_max_f64 v[8:9], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_max_f64 v[10:11], v[8:9], v[3:4]
	v_min_f64 v[3:4], v[8:9], v[3:4]
	global_store_b64 v[6:7], v[10:11], off
.LBB0_14:                               ;   in Loop: Header=BB0_10 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v6, s12, v0
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_add_nc_u32_e32 v0, 32, v0
	v_add_nc_u32_e32 v5, 0x100, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v7, 31, v6
	v_lshlrev_b64 v[6:7], 3, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s24, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s25, v7, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s3, v0
	global_load_b128 v[6:9], v[6:7], off
	s_or_b32 s13, vcc_lo, s13
	s_waitcnt vmcnt(0)
	v_max_f64 v[6:7], v[6:7], v[6:7]
	v_max_f64 v[8:9], -v[8:9], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_max_f64 v[10:11], v[6:7], 0
	v_max_f64 v[12:13], v[8:9], 0
	v_min_f64 v[6:7], v[6:7], 0
	v_min_f64 v[8:9], v[8:9], 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_add_f64 v[6:7], v[6:7], v[8:9]
	v_add_co_u32 v8, s0, s6, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, s7, v2, s0
	v_add_co_u32 v12, s0, s8, v1
	v_add_co_ci_u32_e64 v13, s0, s9, v2, s0
	v_add_co_u32 v1, s0, s10, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v2, s0, s11, v2, s0
	global_store_b64 v[8:9], v[3:4], off
	global_store_b64 v[12:13], v[10:11], off
	global_store_b64 v[1:2], v[6:7], off
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_10
.LBB0_15:                               ; %Flow192
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 136
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 46
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d, .Lfunc_end0-_Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1644
; NumSgprs: 48
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 48
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         96
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  write_only
        .address_space:  global
        .offset:         120
        .size:           8
        .value_kind:     global_buffer
      - .offset:         128
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 136
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d
    .private_segment_fixed_size: 0
    .sgpr_count:     48
    .sgpr_spill_count: 0
    .symbol:         _Z16fct_ale_pre_commiiiPKiS0_S0_S0_S0_PKdS2_S2_S2_PdS3_S3_S3_S3_d.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
