#include <assert.h>
#include "cuda.h"
#include "cuda_runtime.h"
#include <stdio.h>

/*****************************************************/
/* CS149: ALL OF YOUR CODE SHOULD GO IN THIS FILE    */
/*****************************************************/

// You can modify these parameters to match the image input size
#define SIZEX    512
#define SIZEY    512

// no need to modify this:
#define BLOCK_SIZE 256			//The amount of threads in a threadblock for the fft routines
#define PI	3.14159256f

__global__ void gpu_fftx(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {

	//responsible for a single output cell in the FFT'd image.
	//runs in 512-wide threadblocks all working together

	int myRow = blockIdx.y; //processed by the whole threadblock
	int myCol = threadIdx.x + blockIdx.x * blockDim.x; //I calculate this result

	__shared__ float reals[SIZEY];
	__shared__ float imags[SIZEY];

	for (unsigned int i = 0; i < gridDim.x; i++) {
		//each thread loads the pixel value in each grid for which it is responsible.
		int n = (threadIdx.x + i*blockDim.x);
		reals[n] = dReal[myRow * size_x + n];
		imags[n] = dImag[myRow * size_x + n];
	}

	__syncthreads();

	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_y; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = -2 * PI * myCol * n / size_y;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);

	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value;
	dImagOut[myRow * size_x + myCol] = imag_value;

}
__global__ void gpu_ifftx(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {

	//responsible for a single output cell in the FFT'd image.
	//runs in 512-wide threadblocks all working together

	int myRow = blockIdx.y; //processed by the whole threadblock
	int myCol = threadIdx.x + blockIdx.x * blockDim.x; //i calculate this result

	__shared__ float reals[SIZEY];
	__shared__ float imags[SIZEY];

	for (unsigned int i = 0; i < gridDim.x; i++) {
		int n = (threadIdx.x + i*blockDim.x);
		reals[n] = dReal[myRow * size_x + n];
		imags[n] = dImag[myRow * size_x + n];
	}

	__syncthreads();

	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_y; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = 2 * PI * myCol * n / size_y;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);

	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value / size_y;
	dImagOut[myRow * size_x + myCol] = imag_value / size_y;


}
__global__ void gpu_ffty(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {
	int myRow = threadIdx.y + blockIdx.y * blockDim.y; //i calculate this result
	int myCol = blockIdx.x; //calculated by the whole threadblock

	__shared__ float reals[SIZEX];
	__shared__ float imags[SIZEX];

	for (unsigned int i = 0; i < gridDim.y; i++) {
		int n = (threadIdx.y + i*blockDim.y);
		reals[n] = dReal[n * size_x + myCol];
		imags[n] = dImag[n * size_x + myCol];
	}

	__syncthreads();

	//runs over elements in column
	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_x; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = -2 * PI * myRow * n / size_x;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);

	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value;
	dImagOut[myRow * size_x + myCol] = imag_value;

}
__global__ void gpu_iffty(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {
	int myRow = blockIdx.y * blockDim.y + threadIdx.y;
	int myCol = blockIdx.x;

	__shared__ float reals[SIZEX];
	__shared__ float imags[SIZEX];

	for (unsigned int i = 0; i < gridDim.y; i++) {
		int n = (threadIdx.y + i*blockDim.y);
		reals[n] = dReal[n * size_x + myCol];
		imags[n] = dImag[n * size_x + myCol];
	}

	__syncthreads();

	//runs over elements in column
	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_x; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = 2 * PI * myRow * n / size_x;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);
	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value / size_x;
	dImagOut[myRow * size_x + myCol] = imag_value / size_x;
}
__global__ void gpu_filter(float *dReal, float *dImag, int size_x, int size_y) {
	int x = blockIdx.x * blockDim.x + threadIdx.x;
	int y = blockIdx.y * blockDim.y + threadIdx.y;

	int eightX = size_x / 8;
	//int eight7X = size_x - eightX;
	int eightY = size_y / 8;
	int eight7Y = size_y - eightY;

	if (!(x < eightX && y < eightY) && !(x < eightX && y >= eight7Y)
			&& !(x >= eight7Y && y < eightY) && !(x >= eight7Y && y
			>= eight7Y)) {
		dReal[y * size_x + x] = 0;
		dImag[y * size_x + x] = 0;
	}

}

__host__ float filterImage(float *real_image, float *imag_image, int size_x, int size_y)
{
  // check that the sizes match up
  assert(size_x == SIZEX);
  assert(size_y == SIZEY);

  int matSize = size_x * size_y * sizeof(float);

  // These variables are for timing purposes
  float transferDown = 0, transferUp = 0, execution = 0;
  cudaEvent_t start,stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);

  // Create a stream and initialize it
  cudaStream_t filterStream;
  cudaStreamCreate(&filterStream);

  // Alloc space on the device
  float *device_real, *device_imag, *device_real2, *device_imag2;
  cudaMalloc((void**)&device_real, matSize);
  cudaMalloc((void**)&device_imag, matSize);
  cudaMalloc((void**)&device_real2, matSize);
  cudaMalloc((void**)&device_imag2, matSize);

  // Start timing for transfer down
  cudaEventRecord(start,filterStream);
  
  //-----------------------------------------------------------------
  // HERE IS WHERE WE COPY THE MATRICES DOWN TO THE DEVICE
  //-----------------------------------------------------------------
  cudaMemcpy(device_real,real_image,matSize,cudaMemcpyHostToDevice);
  cudaMemcpy(device_imag,imag_image,matSize,cudaMemcpyHostToDevice);
  
  // Stop timing for transfer down
  cudaEventRecord(stop,filterStream);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&transferDown,start,stop);

  // Start timing for the execution
  cudaEventRecord(start,filterStream);



 
  //----------------------------------------------------------------
  // CS149: YOU SHOULD PLACE ALL YOUR KERNEL EXECUTIONS
  //        HERE BETWEEN THE CALLS FOR STARTING AND
  //        FINISHING TIMING FOR THE EXECUTION PHASE
  //----------------------------------------------------------------

  // This is an example kernel call, you should feel free to create
  // as many kernel calls as you feel are needed for your program
  // Each of the parameters are as follows:
  //    1. Number of thread blocks, can be either int or dim3 (see CUDA manual)
  //    2. Number of threads per thread block, can be either int or dim3 (see CUDA manual)
  //    3. Always should be '0' unless you read the CUDA manual
  //    4. Stream to execute kernel on, should always be 'filterStream' for this project
  //
  // Also note that you pass the pointers to the device memory to the kernel call

  // we have to run kernels that does an fft.
  //	ffty:
  //		for each row in the image
  // 			for each cell in the row
  //				access all the other cells in the row


  // FOR ROW-BASED FFT (fftx and ifftx)
  //Here is how we split this up:
  // 	each threadblock is responsible for 512 elements in a row.
  //	threadblocks are arranged in a grid of 512-groups elements by all the rows.
  //	input image is SIZEX by SIZEY
  //	block this into a (SIZEX/512) by SIZEY grid
  //	each threadblock consists of 512 threads for a row in the grid.

  dim3 fftx_dimBlock(BLOCK_SIZE,1);
  dim3 fftx_dimGrid((int)ceil((float)SIZEX/BLOCK_SIZE),SIZEY);

  dim3 ffty_dimBlock(1,BLOCK_SIZE);
  dim3 ffty_dimGrid(SIZEX, (int)ceil((float)SIZEY/BLOCK_SIZE));

  dim3 filter_dimBlock(16,16);
  dim3 filter_dimGrid((int)ceil((float)SIZEX/16), (int)ceil((float)SIZEY/16));


  printf("  Launching fftx kernel with %d threads per block arranged in a grid of %dx%d.\n", fftx_dimBlock.x, fftx_dimGrid.x, fftx_dimGrid.y);
  gpu_fftx<<<fftx_dimGrid, fftx_dimBlock, 0, filterStream>>>(device_real,device_imag,device_real2,device_imag2,size_x,size_y);
  printf("  Launching ffty kernel with %d threads per block arranged in a grid of %dx%d.\n", ffty_dimBlock.y, ffty_dimGrid.x, ffty_dimGrid.y);
  gpu_ffty<<<ffty_dimGrid, ffty_dimBlock, 0, filterStream>>>(device_real2,device_imag2,device_real,device_imag,size_x,size_y);


  printf("  Launching filter kernel with %dx%d threads per block arranged in a grid of %dx%d.\n", filter_dimBlock.x,filter_dimBlock.y, filter_dimGrid.x, filter_dimGrid.y);
  gpu_filter<<<filter_dimGrid, filter_dimBlock, 0, filterStream>>>(device_real,device_imag,size_x,size_y);


  printf("  Launching ifftx kernel with %d threads per block arranged in a grid of %dx%d.\n", fftx_dimBlock.x, fftx_dimGrid.x, fftx_dimGrid.y);
  gpu_ifftx<<<fftx_dimGrid, fftx_dimBlock, 0, filterStream>>>(device_real,device_imag,device_real2,device_imag2,size_x,size_y);
  printf("  Launching iffty kernel with %d threads per block arranged in a grid of %dx%d.\n", ffty_dimBlock.y, ffty_dimGrid.x, ffty_dimGrid.y);
  gpu_iffty<<<ffty_dimGrid, ffty_dimBlock, 0, filterStream>>>(device_real2,device_imag2,device_real,device_imag,size_x,size_y);

  // Finish timimg for the execution 
  cudaEventRecord(stop,filterStream);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&execution,start,stop);

  // Check for any errors in kernel launch
  cudaError_t kernelResult = cudaGetLastError();
  if( kernelResult != cudaSuccess )
  {
    printf("WARNING: CUDA KERNEL CALL FAILED!  %s\n", cudaGetErrorString(kernelResult));
  }

  // Start timing for the transfer up
  cudaEventRecord(start,filterStream);

  //----------------------------------------------------------------
  // HERE IS WHERE WE COPY THE MATRICES BACK FROM THE DEVICE
  //----------------------------------------------------------------
  cudaMemcpy(real_image,device_real,matSize,cudaMemcpyDeviceToHost);
  cudaMemcpy(imag_image,device_imag,matSize,cudaMemcpyDeviceToHost);

  // Finish timing for transfer up
  cudaEventRecord(stop,filterStream);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&transferUp,start,stop);

  // Synchronize the stream
  cudaStreamSynchronize(filterStream);
  // Destroy the stream
  cudaStreamDestroy(filterStream);
  // Destroy the events
  cudaEventDestroy(start);
  cudaEventDestroy(stop);

  // Free the memory
  cudaFree(device_real);
  cudaFree(device_imag);

  // Dump some usage statistics
  printf("CUDA IMPLEMENTATION STATISTICS:\n");
  printf("  Host to Device Transfer Time: %f ms\n", transferDown);
  printf("  Kernel(s) Execution Time: %f ms\n", execution);
  printf("  Device to Host Transfer Time: %f ms\n", transferUp);
  float totalTime = transferDown + execution + transferUp;
  printf("  Total CUDA Execution Time: %f ms\n\n", totalTime);
  // Return the total time to transfer and execute
  return totalTime;
}


	.file	"tmpxft_0023ccfb_00000000-6_ImageCleaner.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z35__device_stub__Z8gpu_fftxPfS_S_S_iiPfS_S_S_ii
	.type	_Z35__device_stub__Z8gpu_fftxPfS_S_S_iiPfS_S_S_ii, @function
_Z35__device_stub__Z8gpu_fftxPfS_S_S_iiPfS_S_S_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8gpu_fftxPfS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z35__device_stub__Z8gpu_fftxPfS_S_S_iiPfS_S_S_ii, .-_Z35__device_stub__Z8gpu_fftxPfS_S_S_iiPfS_S_S_ii
	.globl	_Z8gpu_fftxPfS_S_S_ii
	.type	_Z8gpu_fftxPfS_S_S_ii, @function
_Z8gpu_fftxPfS_S_S_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z8gpu_fftxPfS_S_S_iiPfS_S_S_ii
	.cfi_endproc
.LFE2053:
	.size	_Z8gpu_fftxPfS_S_S_ii, .-_Z8gpu_fftxPfS_S_S_ii
	.globl	_Z36__device_stub__Z9gpu_ifftxPfS_S_S_iiPfS_S_S_ii
	.type	_Z36__device_stub__Z9gpu_ifftxPfS_S_S_iiPfS_S_S_ii, @function
_Z36__device_stub__Z9gpu_ifftxPfS_S_S_iiPfS_S_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9gpu_ifftxPfS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z36__device_stub__Z9gpu_ifftxPfS_S_S_iiPfS_S_S_ii, .-_Z36__device_stub__Z9gpu_ifftxPfS_S_S_iiPfS_S_S_ii
	.globl	_Z9gpu_ifftxPfS_S_S_ii
	.type	_Z9gpu_ifftxPfS_S_S_ii, @function
_Z9gpu_ifftxPfS_S_S_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z9gpu_ifftxPfS_S_S_iiPfS_S_S_ii
	.cfi_endproc
.LFE2055:
	.size	_Z9gpu_ifftxPfS_S_S_ii, .-_Z9gpu_ifftxPfS_S_S_ii
	.globl	_Z35__device_stub__Z8gpu_fftyPfS_S_S_iiPfS_S_S_ii
	.type	_Z35__device_stub__Z8gpu_fftyPfS_S_S_iiPfS_S_S_ii, @function
_Z35__device_stub__Z8gpu_fftyPfS_S_S_iiPfS_S_S_ii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z8gpu_fftyPfS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L13:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z35__device_stub__Z8gpu_fftyPfS_S_S_iiPfS_S_S_ii, .-_Z35__device_stub__Z8gpu_fftyPfS_S_S_iiPfS_S_S_ii
	.globl	_Z8gpu_fftyPfS_S_S_ii
	.type	_Z8gpu_fftyPfS_S_S_ii, @function
_Z8gpu_fftyPfS_S_S_ii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z8gpu_fftyPfS_S_S_iiPfS_S_S_ii
	.cfi_endproc
.LFE2057:
	.size	_Z8gpu_fftyPfS_S_S_ii, .-_Z8gpu_fftyPfS_S_S_ii
	.globl	_Z36__device_stub__Z9gpu_ifftyPfS_S_S_iiPfS_S_S_ii
	.type	_Z36__device_stub__Z9gpu_ifftyPfS_S_S_iiPfS_S_S_ii, @function
_Z36__device_stub__Z9gpu_ifftyPfS_S_S_iiPfS_S_S_ii:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9gpu_ifftyPfS_S_S_ii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L18:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z36__device_stub__Z9gpu_ifftyPfS_S_S_iiPfS_S_S_ii, .-_Z36__device_stub__Z9gpu_ifftyPfS_S_S_iiPfS_S_S_ii
	.globl	_Z9gpu_ifftyPfS_S_S_ii
	.type	_Z9gpu_ifftyPfS_S_S_ii, @function
_Z9gpu_ifftyPfS_S_S_ii:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z9gpu_ifftyPfS_S_S_iiPfS_S_S_ii
	.cfi_endproc
.LFE2059:
	.size	_Z9gpu_ifftyPfS_S_S_ii, .-_Z9gpu_ifftyPfS_S_S_ii
	.globl	_Z34__device_stub__Z10gpu_filterPfS_iiPfS_ii
	.type	_Z34__device_stub__Z10gpu_filterPfS_iiPfS_ii, @function
_Z34__device_stub__Z10gpu_filterPfS_iiPfS_ii:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10gpu_filterPfS_ii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L23:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z34__device_stub__Z10gpu_filterPfS_iiPfS_ii, .-_Z34__device_stub__Z10gpu_filterPfS_iiPfS_ii
	.globl	_Z10gpu_filterPfS_ii
	.type	_Z10gpu_filterPfS_ii, @function
_Z10gpu_filterPfS_ii:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z10gpu_filterPfS_iiPfS_ii
	.cfi_endproc
.LFE2061:
	.size	_Z10gpu_filterPfS_ii, .-_Z10gpu_filterPfS_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"  Launching fftx kernel with %d threads per block arranged in a grid of %dx%d.\n"
.LC2:
	.string	"  Launching ffty kernel with %d threads per block arranged in a grid of %dx%d.\n"
.LC3:
	.string	"  Launching filter kernel with %dx%d threads per block arranged in a grid of %dx%d.\n"
.LC4:
	.string	"  Launching ifftx kernel with %d threads per block arranged in a grid of %dx%d.\n"
.LC5:
	.string	"  Launching iffty kernel with %d threads per block arranged in a grid of %dx%d.\n"
.LC6:
	.string	"WARNING: CUDA KERNEL CALL FAILED!  %s\n"
.LC7:
	.string	"CUDA IMPLEMENTATION STATISTICS:\n"
.LC8:
	.string	"  Host to Device Transfer Time: %f ms\n"
.LC9:
	.string	"  Kernel(s) Execution Time: %f ms\n"
.LC10:
	.string	"  Device to Host Transfer Time: %f ms\n"
.LC11:
	.string	"  Total CUDA Execution Time: %f ms\n\n"
	.text
	.globl	_Z11filterImagePfS_ii
	.type	_Z11filterImagePfS_ii, @function
_Z11filterImagePfS_ii:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%ebp, %ebx
	imull	%r12d, %ebx
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rdi
	sall	$2, %ebx
	movl	$0x00000000, 12(%rsp)
	movl	$0x00000000, 16(%rsp)
	movslq	%ebx, %rbx
	movl	$0x00000000, 20(%rsp)
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	64(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	72(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	12(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	cudaEventRecord@PLT
	movl	$512, %r8d
	xorl	%eax, %eax
	movl	$2, %ecx
	movl	$256, %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	movl	$1, 104(%rsp)
	movl	$1, 112(%rsp)
	movl	$1, 124(%rsp)
	movl	$1, 136(%rsp)
	movl	$1, 148(%rsp)
	call	__printf_chk@PLT
	movl	$16777217, %edx
	movq	40(%rsp), %r9
	movabsq	$2199023255554, %rdi
	salq	$8, %rdx
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdi, 92(%rsp)
	movl	$1, 100(%rsp)
	movq	%rdx, 80(%rsp)
	movl	$1, 88(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z35__device_stub__Z8gpu_fftxPfS_S_S_iiPfS_S_S_ii
.L29:
	movl	$2, %r8d
	movl	$512, %ecx
	xorl	%eax, %eax
	movl	$256, %edx
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	112(%rsp), %ecx
	movl	124(%rsp), %esi
	xorl	%r8d, %r8d
	movl	$256, 108(%rsp)
	movl	$16777217, %edi
	movq	40(%rsp), %r9
	movq	104(%rsp), %rdx
	salq	$9, %rdi
	movq	%rdi, 116(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L30
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z35__device_stub__Z8gpu_fftyPfS_S_S_iiPfS_S_S_ii
.L30:
	movl	$32, %r9d
	movl	$32, %r8d
	xorl	%eax, %eax
	movl	$16, %ecx
	movl	$16, %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	136(%rsp), %ecx
	movq	40(%rsp), %r9
	xorl	%r8d, %r8d
	movl	148(%rsp), %esi
	movabsq	$68719476752, %rdx
	movabsq	$137438953504, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	movl	%r12d, %ecx
	movl	%ebp, %edx
	call	_Z34__device_stub__Z10gpu_filterPfS_iiPfS_ii
.L31:
	movl	$512, %r8d
	movl	$2, %ecx
	xorl	%eax, %eax
	movl	$256, %edx
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	88(%rsp), %ecx
	movl	100(%rsp), %esi
	xorl	%r8d, %r8d
	movq	40(%rsp), %r9
	movq	80(%rsp), %rdx
	movq	92(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z36__device_stub__Z9gpu_ifftxPfS_S_S_iiPfS_S_S_ii
.L32:
	movl	$2, %r8d
	movl	$512, %ecx
	xorl	%eax, %eax
	movl	$256, %edx
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	112(%rsp), %ecx
	movl	124(%rsp), %esi
	xorl	%r8d, %r8d
	movq	40(%rsp), %r9
	movq	104(%rsp), %rdx
	movq	116(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	movq	56(%rsp), %rcx
	movq	48(%rsp), %rdx
	movl	%r12d, %r9d
	movl	%ebp, %r8d
	movq	72(%rsp), %rsi
	movq	64(%rsp), %rdi
	call	_Z36__device_stub__Z9gpu_ifftyPfS_S_S_iiPfS_S_S_ii
.L33:
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L34
	call	cudaGetErrorString@PLT
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movq	%rax, %rdx
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L34:
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	cudaEventRecord@PLT
	movq	48(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r14, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r13, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movq	40(%rsp), %rsi
	movq	32(%rsp), %rdi
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	16(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	40(%rsp), %rdi
	call	cudaStreamSynchronize@PLT
	movq	40(%rsp), %rdi
	call	cudaStreamDestroy@PLT
	movq	24(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	12(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	leaq	.LC9(%rip), %rsi
	cvtss2sd	20(%rsp), %xmm0
	call	__printf_chk@PLT
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	16(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	movb	$1, %al
	movss	12(%rsp), %xmm0
	addss	20(%rsp), %xmm0
	leaq	.LC11(%rip), %rsi
	addss	16(%rsp), %xmm0
	movd	%xmm0, %ebx
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$160, %rsp
	.cfi_def_cfa_offset 48
	movd	%ebx, %xmm0
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11filterImagePfS_ii, .-_Z11filterImagePfS_ii
	.section	.rodata.str1.1
.LC12:
	.string	"_Z10gpu_filterPfS_ii"
.LC13:
	.string	"_Z9gpu_ifftyPfS_S_S_ii"
.LC14:
	.string	"_Z8gpu_fftyPfS_S_S_ii"
.LC15:
	.string	"_Z9gpu_ifftxPfS_S_S_ii"
.LC16:
	.string	"_Z8gpu_fftxPfS_S_S_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2063:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10gpu_filterPfS_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9gpu_ifftyPfS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8gpu_fftyPfS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9gpu_ifftxPfS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8gpu_fftxPfS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2063:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <assert.h>
#include "hip/hip_runtime.h"

#include <stdio.h>

/*****************************************************/
/* CS149: ALL OF YOUR CODE SHOULD GO IN THIS FILE    */
/*****************************************************/

// You can modify these parameters to match the image input size
#define SIZEX    512
#define SIZEY    512

// no need to modify this:
#define BLOCK_SIZE 256			//The amount of threads in a threadblock for the fft routines
#define PI	3.14159256f

__global__ void gpu_fftx(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {

	//responsible for a single output cell in the FFT'd image.
	//runs in 512-wide threadblocks all working together

	int myRow = blockIdx.y; //processed by the whole threadblock
	int myCol = threadIdx.x + blockIdx.x * blockDim.x; //I calculate this result

	__shared__ float reals[SIZEY];
	__shared__ float imags[SIZEY];

	for (unsigned int i = 0; i < gridDim.x; i++) {
		//each thread loads the pixel value in each grid for which it is responsible.
		int n = (threadIdx.x + i*blockDim.x);
		reals[n] = dReal[myRow * size_x + n];
		imags[n] = dImag[myRow * size_x + n];
	}

	__syncthreads();

	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_y; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = -2 * PI * myCol * n / size_y;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);

	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value;
	dImagOut[myRow * size_x + myCol] = imag_value;

}
__global__ void gpu_ifftx(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {

	//responsible for a single output cell in the FFT'd image.
	//runs in 512-wide threadblocks all working together

	int myRow = blockIdx.y; //processed by the whole threadblock
	int myCol = threadIdx.x + blockIdx.x * blockDim.x; //i calculate this result

	__shared__ float reals[SIZEY];
	__shared__ float imags[SIZEY];

	for (unsigned int i = 0; i < gridDim.x; i++) {
		int n = (threadIdx.x + i*blockDim.x);
		reals[n] = dReal[myRow * size_x + n];
		imags[n] = dImag[myRow * size_x + n];
	}

	__syncthreads();

	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_y; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = 2 * PI * myCol * n / size_y;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);

	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value / size_y;
	dImagOut[myRow * size_x + myCol] = imag_value / size_y;


}
__global__ void gpu_ffty(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {
	int myRow = threadIdx.y + blockIdx.y * blockDim.y; //i calculate this result
	int myCol = blockIdx.x; //calculated by the whole threadblock

	__shared__ float reals[SIZEX];
	__shared__ float imags[SIZEX];

	for (unsigned int i = 0; i < gridDim.y; i++) {
		int n = (threadIdx.y + i*blockDim.y);
		reals[n] = dReal[n * size_x + myCol];
		imags[n] = dImag[n * size_x + myCol];
	}

	__syncthreads();

	//runs over elements in column
	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_x; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = -2 * PI * myRow * n / size_x;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);

	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value;
	dImagOut[myRow * size_x + myCol] = imag_value;

}
__global__ void gpu_iffty(float *dReal, float *dImag, float *dRealOut, float *dImagOut, int size_x, int size_y) {
	int myRow = blockIdx.y * blockDim.y + threadIdx.y;
	int myCol = blockIdx.x;

	__shared__ float reals[SIZEX];
	__shared__ float imags[SIZEX];

	for (unsigned int i = 0; i < gridDim.y; i++) {
		int n = (threadIdx.y + i*blockDim.y);
		reals[n] = dReal[n * size_x + myCol];
		imags[n] = dImag[n * size_x + myCol];
	}

	__syncthreads();

	//runs over elements in column
	// Compute the value for this index
	float real_value = 0;
	float imag_value = 0;
	float term, realTerm, imagTerm;
	for (unsigned int n = 0; n < size_x; n++) { 				//(a+bi)(c+di) = (ac-bd) + (bc+ad)i
		term = 2 * PI * myRow * n / size_x;
		realTerm = cos(term);
		imagTerm = sin(term);

		real_value += (reals[n] * realTerm) - (imags[n] * imagTerm);
		imag_value += (imags[n] * realTerm) + (reals[n] * imagTerm);
	}

	// Write the values back into the temporary buffer
	dRealOut[myRow * size_x + myCol] = real_value / size_x;
	dImagOut[myRow * size_x + myCol] = imag_value / size_x;
}
__global__ void gpu_filter(float *dReal, float *dImag, int size_x, int size_y) {
	int x = blockIdx.x * blockDim.x + threadIdx.x;
	int y = blockIdx.y * blockDim.y + threadIdx.y;

	int eightX = size_x / 8;
	//int eight7X = size_x - eightX;
	int eightY = size_y / 8;
	int eight7Y = size_y - eightY;

	if (!(x < eightX && y < eightY) && !(x < eightX && y >= eight7Y)
			&& !(x >= eight7Y && y < eightY) && !(x >= eight7Y && y
			>= eight7Y)) {
		dReal[y * size_x + x] = 0;
		dImag[y * size_x + x] = 0;
	}

}

__host__ float filterImage(float *real_image, float *imag_image, int size_x, int size_y)
{
  // check that the sizes match up
  assert(size_x == SIZEX);
  assert(size_y == SIZEY);

  int matSize = size_x * size_y * sizeof(float);

  // These variables are for timing purposes
  float transferDown = 0, transferUp = 0, execution = 0;
  hipEvent_t start,stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);

  // Create a stream and initialize it
  hipStream_t filterStream;
  hipStreamCreate(&filterStream);

  // Alloc space on the device
  float *device_real, *device_imag, *device_real2, *device_imag2;
  hipMalloc((void**)&device_real, matSize);
  hipMalloc((void**)&device_imag, matSize);
  hipMalloc((void**)&device_real2, matSize);
  hipMalloc((void**)&device_imag2, matSize);

  // Start timing for transfer down
  hipEventRecord(start,filterStream);
  
  //-----------------------------------------------------------------
  // HERE IS WHERE WE COPY THE MATRICES DOWN TO THE DEVICE
  //-----------------------------------------------------------------
  hipMemcpy(device_real,real_image,matSize,hipMemcpyHostToDevice);
  hipMemcpy(device_imag,imag_image,matSize,hipMemcpyHostToDevice);
  
  // Stop timing for transfer down
  hipEventRecord(stop,filterStream);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&transferDown,start,stop);

  // Start timing for the execution
  hipEventRecord(start,filterStream);



 
  //----------------------------------------------------------------
  // CS149: YOU SHOULD PLACE ALL YOUR KERNEL EXECUTIONS
  //        HERE BETWEEN THE CALLS FOR STARTING AND
  //        FINISHING TIMING FOR THE EXECUTION PHASE
  //----------------------------------------------------------------

  // This is an example kernel call, you should feel free to create
  // as many kernel calls as you feel are needed for your program
  // Each of the parameters are as follows:
  //    1. Number of thread blocks, can be either int or dim3 (see CUDA manual)
  //    2. Number of threads per thread block, can be either int or dim3 (see CUDA manual)
  //    3. Always should be '0' unless you read the CUDA manual
  //    4. Stream to execute kernel on, should always be 'filterStream' for this project
  //
  // Also note that you pass the pointers to the device memory to the kernel call

  // we have to run kernels that does an fft.
  //	ffty:
  //		for each row in the image
  // 			for each cell in the row
  //				access all the other cells in the row


  // FOR ROW-BASED FFT (fftx and ifftx)
  //Here is how we split this up:
  // 	each threadblock is responsible for 512 elements in a row.
  //	threadblocks are arranged in a grid of 512-groups elements by all the rows.
  //	input image is SIZEX by SIZEY
  //	block this into a (SIZEX/512) by SIZEY grid
  //	each threadblock consists of 512 threads for a row in the grid.

  dim3 fftx_dimBlock(BLOCK_SIZE,1);
  dim3 fftx_dimGrid((int)ceil((float)SIZEX/BLOCK_SIZE),SIZEY);

  dim3 ffty_dimBlock(1,BLOCK_SIZE);
  dim3 ffty_dimGrid(SIZEX, (int)ceil((float)SIZEY/BLOCK_SIZE));

  dim3 filter_dimBlock(16,16);
  dim3 filter_dimGrid((int)ceil((float)SIZEX/16), (int)ceil((float)SIZEY/16));


  printf("  Launching fftx kernel with %d threads per block arranged in a grid of %dx%d.\n", fftx_dimBlock.x, fftx_dimGrid.x, fftx_dimGrid.y);
  gpu_fftx<<<fftx_dimGrid, fftx_dimBlock, 0, filterStream>>>(device_real,device_imag,device_real2,device_imag2,size_x,size_y);
  printf("  Launching ffty kernel with %d threads per block arranged in a grid of %dx%d.\n", ffty_dimBlock.y, ffty_dimGrid.x, ffty_dimGrid.y);
  gpu_ffty<<<ffty_dimGrid, ffty_dimBlock, 0, filterStream>>>(device_real2,device_imag2,device_real,device_imag,size_x,size_y);


  printf("  Launching filter kernel with %dx%d threads per block arranged in a grid of %dx%d.\n", filter_dimBlock.x,filter_dimBlock.y, filter_dimGrid.x, filter_dimGrid.y);
  gpu_filter<<<filter_dimGrid, filter_dimBlock, 0, filterStream>>>(device_real,device_imag,size_x,size_y);


  printf("  Launching ifftx kernel with %d threads per block arranged in a grid of %dx%d.\n", fftx_dimBlock.x, fftx_dimGrid.x, fftx_dimGrid.y);
  gpu_ifftx<<<fftx_dimGrid, fftx_dimBlock, 0, filterStream>>>(device_real,device_imag,device_real2,device_imag2,size_x,size_y);
  printf("  Launching iffty kernel with %d threads per block arranged in a grid of %dx%d.\n", ffty_dimBlock.y, ffty_dimGrid.x, ffty_dimGrid.y);
  gpu_iffty<<<ffty_dimGrid, ffty_dimBlock, 0, filterStream>>>(device_real2,device_imag2,device_real,device_imag,size_x,size_y);

  // Finish timimg for the execution 
  hipEventRecord(stop,filterStream);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&execution,start,stop);

  // Check for any errors in kernel launch
  hipError_t kernelResult = hipGetLastError();
  if( kernelResult != hipSuccess )
  {
    printf("WARNING: CUDA KERNEL CALL FAILED!  %s\n", hipGetErrorString(kernelResult));
  }

  // Start timing for the transfer up
  hipEventRecord(start,filterStream);

  //----------------------------------------------------------------
  // HERE IS WHERE WE COPY THE MATRICES BACK FROM THE DEVICE
  //----------------------------------------------------------------
  hipMemcpy(real_image,device_real,matSize,hipMemcpyDeviceToHost);
  hipMemcpy(imag_image,device_imag,matSize,hipMemcpyDeviceToHost);

  // Finish timing for transfer up
  hipEventRecord(stop,filterStream);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&transferUp,start,stop);

  // Synchronize the stream
  hipStreamSynchronize(filterStream);
  // Destroy the stream
  hipStreamDestroy(filterStream);
  // Destroy the events
  hipEventDestroy(start);
  hipEventDestroy(stop);

  // Free the memory
  hipFree(device_real);
  hipFree(device_imag);

  // Dump some usage statistics
  printf("CUDA IMPLEMENTATION STATISTICS:\n");
  printf("  Host to Device Transfer Time: %f ms\n", transferDown);
  printf("  Kernel(s) Execution Time: %f ms\n", execution);
  printf("  Device to Host Transfer Time: %f ms\n", transferUp);
  float totalTime = transferDown + execution + transferUp;
  printf("  Total CUDA Execution Time: %f ms\n\n", totalTime);
  // Return the total time to transfer and execute
  return totalTime;
}


	.text
	.file	"ImageCleaner.hip"
	.globl	_Z23__device_stub__gpu_fftxPfS_S_S_ii # -- Begin function _Z23__device_stub__gpu_fftxPfS_S_S_ii
	.type	_Z23__device_stub__gpu_fftxPfS_S_S_ii,@function
_Z23__device_stub__gpu_fftxPfS_S_S_ii:  # @_Z23__device_stub__gpu_fftxPfS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8gpu_fftxPfS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z23__device_stub__gpu_fftxPfS_S_S_ii, .Lfunc_end0-_Z23__device_stub__gpu_fftxPfS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__gpu_ifftxPfS_S_S_ii # -- Begin function _Z24__device_stub__gpu_ifftxPfS_S_S_ii
	.type	_Z24__device_stub__gpu_ifftxPfS_S_S_ii,@function
_Z24__device_stub__gpu_ifftxPfS_S_S_ii: # @_Z24__device_stub__gpu_ifftxPfS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9gpu_ifftxPfS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__gpu_ifftxPfS_S_S_ii, .Lfunc_end1-_Z24__device_stub__gpu_ifftxPfS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__gpu_fftyPfS_S_S_ii # -- Begin function _Z23__device_stub__gpu_fftyPfS_S_S_ii
	.type	_Z23__device_stub__gpu_fftyPfS_S_S_ii,@function
_Z23__device_stub__gpu_fftyPfS_S_S_ii:  # @_Z23__device_stub__gpu_fftyPfS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8gpu_fftyPfS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z23__device_stub__gpu_fftyPfS_S_S_ii, .Lfunc_end2-_Z23__device_stub__gpu_fftyPfS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__gpu_ifftyPfS_S_S_ii # -- Begin function _Z24__device_stub__gpu_ifftyPfS_S_S_ii
	.type	_Z24__device_stub__gpu_ifftyPfS_S_S_ii,@function
_Z24__device_stub__gpu_ifftyPfS_S_S_ii: # @_Z24__device_stub__gpu_ifftyPfS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9gpu_ifftyPfS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z24__device_stub__gpu_ifftyPfS_S_S_ii, .Lfunc_end3-_Z24__device_stub__gpu_ifftyPfS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__gpu_filterPfS_ii # -- Begin function _Z25__device_stub__gpu_filterPfS_ii
	.type	_Z25__device_stub__gpu_filterPfS_ii,@function
_Z25__device_stub__gpu_filterPfS_ii:    # @_Z25__device_stub__gpu_filterPfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_filterPfS_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__gpu_filterPfS_ii, .Lfunc_end4-_Z25__device_stub__gpu_filterPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11filterImagePfS_ii           # -- Begin function _Z11filterImagePfS_ii
	.type	_Z11filterImagePfS_ii,@function
_Z11filterImagePfS_ii:                  # @_Z11filterImagePfS_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, 72(%rsp)                  # 4-byte Spill
	movl	%edx, %r15d
	movq	%rsi, 80(%rsp)                  # 8-byte Spill
	movq	%rdi, %r13
	movl	%edx, %r14d
	imull	%ecx, %r14d
	shll	$2, %r14d
	xorl	%eax, %eax
	leaq	36(%rsp), %rcx
	movl	%eax, (%rcx)
	movl	%eax, 76(%rsp)
	movl	%eax, 32(%rsp)
	leaq	40(%rsp), %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rbp
	movq	%rbp, %rdi
	callq	hipEventCreate
	movq	%rsp, %rbx
	movq	%rbx, %rdi
	callq	hipStreamCreate
	movslq	%r14d, %r12
	leaq	16(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	56(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rax
	movq	(%rax), %rdi
	movq	(%rbx), %rsi
	callq	hipEventRecord
	movq	(%r14), %rdi
	movq	80(%rsp), %r14                  # 8-byte Reload
	movq	%r13, 64(%rsp)                  # 8-byte Spill
	movq	%r13, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rax
	movq	(%rax), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movq	(%rbx), %rsi
	callq	hipEventRecord
	movq	(%rbp), %rdi
	callq	hipEventSynchronize
	leaq	40(%rsp), %r13
	movq	(%r13), %rsi
	movq	(%rbp), %rdx
	movl	72(%rsp), %ebp                  # 4-byte Reload
	leaq	36(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	(%r13), %rdi
	movq	(%rbx), %rsi
	callq	hipEventRecord
	movl	$.L.str, %edi
	movl	$256, %esi                      # imm = 0x100
	movl	$2, %edx
	movl	$512, %ecx                      # imm = 0x200
	xorl	%eax, %eax
	callq	printf
	movq	(%rbx), %r9
	movabsq	$2199023255554, %rdi            # imm = 0x20000000002
	movl	$1, %esi
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movl	%r15d, %r8d
	movl	%ebp, %r9d
	callq	_Z23__device_stub__gpu_fftxPfS_S_S_ii
.LBB5_2:
	movabsq	$1099511627777, %r13            # imm = 0x10000000001
	movabsq	$8589935104, %rbx               # imm = 0x200000200
	movl	$.L.str.1, %edi
	movl	$256, %esi                      # imm = 0x100
	movl	$512, %edx                      # imm = 0x200
	movl	$2, %ecx
	xorl	%eax, %eax
	callq	printf
	movq	(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_4
# %bb.3:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	%r15d, %r8d
	movl	%ebp, %r9d
	callq	_Z23__device_stub__gpu_fftyPfS_S_S_ii
.LBB5_4:
	movl	$.L.str.2, %edi
	movl	$16, %esi
	movl	$16, %edx
	movl	$32, %ecx
	movl	$32, %r8d
	xorl	%eax, %eax
	callq	printf
	movq	(%rsp), %r9
	movabsq	$137438953504, %rdi             # imm = 0x2000000020
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	callq	_Z25__device_stub__gpu_filterPfS_ii
.LBB5_6:
	movl	$.L.str.3, %edi
	movl	$256, %esi                      # imm = 0x100
	movl	$2, %edx
	movl	$512, %ecx                      # imm = 0x200
	xorl	%eax, %eax
	callq	printf
	movq	(%rsp), %r9
	movabsq	$2199023255554, %rdi            # imm = 0x20000000002
	movl	$1, %esi
	movabsq	$4294967552, %rdx               # imm = 0x100000100
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_8
# %bb.7:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rcx
	movl	%r15d, %r8d
	movl	%ebp, %r9d
	callq	_Z24__device_stub__gpu_ifftxPfS_S_S_ii
.LBB5_8:
	movl	$.L.str.4, %edi
	movl	$256, %esi                      # imm = 0x100
	movl	$512, %edx                      # imm = 0x200
	movl	$2, %ecx
	xorl	%eax, %eax
	callq	printf
	movq	(%rsp), %r9
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_10
# %bb.9:
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movl	%r15d, %r8d
	movl	%ebp, %r9d
	callq	_Z24__device_stub__gpu_ifftyPfS_S_S_ii
.LBB5_10:
	movq	24(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	32(%rsp), %rdi
	callq	hipEventElapsedTime
	callq	hipGetLastError
	testl	%eax, %eax
	je	.LBB5_12
# %bb.11:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.5, %edi
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
.LBB5_12:
	movq	40(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	hipEventRecord
	movq	16(%rsp), %rsi
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	%r14, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	76(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	(%rsp), %rdi
	callq	hipStreamSynchronize
	movq	(%rsp), %rdi
	callq	hipStreamDestroy
	movq	40(%rsp), %rdi
	callq	hipEventDestroy
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$.Lstr, %edi
	callq	puts@PLT
	cvtss2sd	36(%rsp), %xmm0
	movl	$.L.str.7, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp), %xmm0
	movl	$.L.str.8, %edi
	movb	$1, %al
	callq	printf
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.9, %edi
	movb	$1, %al
	callq	printf
	movss	36(%rsp), %xmm0                 # xmm0 = mem[0],zero,zero,zero
	addss	32(%rsp), %xmm0
	addss	(%rbx), %xmm0
	movss	%xmm0, 64(%rsp)                 # 4-byte Spill
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.10, %edi
	movb	$1, %al
	callq	printf
	movss	64(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z11filterImagePfS_ii, .Lfunc_end5-_Z11filterImagePfS_ii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8gpu_fftxPfS_S_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9gpu_ifftxPfS_S_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8gpu_fftyPfS_S_S_ii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9gpu_ifftyPfS_S_S_ii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_filterPfS_ii, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z8gpu_fftxPfS_S_S_ii,@object   # @_Z8gpu_fftxPfS_S_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z8gpu_fftxPfS_S_S_ii
	.p2align	3, 0x0
_Z8gpu_fftxPfS_S_S_ii:
	.quad	_Z23__device_stub__gpu_fftxPfS_S_S_ii
	.size	_Z8gpu_fftxPfS_S_S_ii, 8

	.type	_Z9gpu_ifftxPfS_S_S_ii,@object  # @_Z9gpu_ifftxPfS_S_S_ii
	.globl	_Z9gpu_ifftxPfS_S_S_ii
	.p2align	3, 0x0
_Z9gpu_ifftxPfS_S_S_ii:
	.quad	_Z24__device_stub__gpu_ifftxPfS_S_S_ii
	.size	_Z9gpu_ifftxPfS_S_S_ii, 8

	.type	_Z8gpu_fftyPfS_S_S_ii,@object   # @_Z8gpu_fftyPfS_S_S_ii
	.globl	_Z8gpu_fftyPfS_S_S_ii
	.p2align	3, 0x0
_Z8gpu_fftyPfS_S_S_ii:
	.quad	_Z23__device_stub__gpu_fftyPfS_S_S_ii
	.size	_Z8gpu_fftyPfS_S_S_ii, 8

	.type	_Z9gpu_ifftyPfS_S_S_ii,@object  # @_Z9gpu_ifftyPfS_S_S_ii
	.globl	_Z9gpu_ifftyPfS_S_S_ii
	.p2align	3, 0x0
_Z9gpu_ifftyPfS_S_S_ii:
	.quad	_Z24__device_stub__gpu_ifftyPfS_S_S_ii
	.size	_Z9gpu_ifftyPfS_S_S_ii, 8

	.type	_Z10gpu_filterPfS_ii,@object    # @_Z10gpu_filterPfS_ii
	.globl	_Z10gpu_filterPfS_ii
	.p2align	3, 0x0
_Z10gpu_filterPfS_ii:
	.quad	_Z25__device_stub__gpu_filterPfS_ii
	.size	_Z10gpu_filterPfS_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"  Launching fftx kernel with %d threads per block arranged in a grid of %dx%d.\n"
	.size	.L.str, 80

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"  Launching ffty kernel with %d threads per block arranged in a grid of %dx%d.\n"
	.size	.L.str.1, 80

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"  Launching filter kernel with %dx%d threads per block arranged in a grid of %dx%d.\n"
	.size	.L.str.2, 85

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"  Launching ifftx kernel with %d threads per block arranged in a grid of %dx%d.\n"
	.size	.L.str.3, 81

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"  Launching iffty kernel with %d threads per block arranged in a grid of %dx%d.\n"
	.size	.L.str.4, 81

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"WARNING: CUDA KERNEL CALL FAILED!  %s\n"
	.size	.L.str.5, 39

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"  Host to Device Transfer Time: %f ms\n"
	.size	.L.str.7, 39

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"  Kernel(s) Execution Time: %f ms\n"
	.size	.L.str.8, 35

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"  Device to Host Transfer Time: %f ms\n"
	.size	.L.str.9, 39

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"  Total CUDA Execution Time: %f ms\n\n"
	.size	.L.str.10, 37

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8gpu_fftxPfS_S_S_ii"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z9gpu_ifftxPfS_S_S_ii"
	.size	.L__unnamed_2, 23

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z8gpu_fftyPfS_S_S_ii"
	.size	.L__unnamed_3, 22

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z9gpu_ifftyPfS_S_S_ii"
	.size	.L__unnamed_4, 23

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z10gpu_filterPfS_ii"
	.size	.L__unnamed_5, 21

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"CUDA IMPLEMENTATION STATISTICS:"
	.size	.Lstr, 32

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__gpu_fftxPfS_S_S_ii
	.addrsig_sym _Z24__device_stub__gpu_ifftxPfS_S_S_ii
	.addrsig_sym _Z23__device_stub__gpu_fftyPfS_S_S_ii
	.addrsig_sym _Z24__device_stub__gpu_ifftyPfS_S_S_ii
	.addrsig_sym _Z25__device_stub__gpu_filterPfS_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8gpu_fftxPfS_S_S_ii
	.addrsig_sym _Z9gpu_ifftxPfS_S_S_ii
	.addrsig_sym _Z8gpu_fftyPfS_S_S_ii
	.addrsig_sym _Z9gpu_ifftyPfS_S_S_ii
	.addrsig_sym _Z10gpu_filterPfS_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8gpu_fftxPfS_S_S_ii   ; -- Begin function _Z8gpu_fftxPfS_S_S_ii
	.globl	_Z8gpu_fftxPfS_S_S_ii
	.p2align	8
	.type	_Z8gpu_fftxPfS_S_S_ii,@function
_Z8gpu_fftxPfS_S_S_ii:                  ; @_Z8gpu_fftxPfS_S_S_ii
; %bb.0:
	s_clause 0x3
	s_load_b32 s11, s[0:1], 0x34
	s_load_b32 s10, s[0:1], 0x28
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s11, 0xffff
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	v_lshlrev_b32_e32 v3, 2, v0
	s_lshl_b32 s12, s11, 2
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s10, s10, -1
	s_cmp_eq_u32 s10, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_nc_u32_e32 v1, s11, v1
	v_add_co_u32 v6, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v2, v[6:7], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v3, v4, v2 offset1:8
	v_add_nc_u32_e32 v3, s12, v3
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %._crit_edge
	v_mad_u64_u32 v[1:2], null, s14, s11, v[0:1]
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v0, 0
	s_cmp_eq_u32 s9, 0
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB0_14
; %bb.4:                                ; %.lr.ph62
	v_cvt_f32_i32_e32 v2, v1
	v_cvt_f32_i32_e32 v5, s9
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v6, 0xc0c90fda, v2
	s_mov_b32 s3, 0
	s_mov_b32 s10, 0x7fffff
	s_mov_b32 s11, 0xb94c1982
	s_mov_b32 s12, 0x37d75334
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v6, v2
	v_div_scale_f32 v7, null, v5, v5, v2
	v_div_scale_f32 v10, vcc_lo, v2, v5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v8
	v_fma_f32 v7, -v7, v9, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v8, v9
                                        ; implicit-def: $vgpr9
	v_div_fixup_f32 v7, v7, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, 0x7fffffff, v7
	v_cmp_ngt_f32_e64 s13, 0x48000000, |v7|
	s_and_saveexec_b32 s0, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	v_and_or_b32 v17, v8, s10, 0x800000
	v_lshrrev_b32_e32 v14, 23, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xfe5163ab, v17, 0
	v_add_nc_u32_e32 v15, 0xffffff88, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v15
	v_mov_b32_e32 v2, v10
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0x3c439041, v17, v[2:3]
	v_add_nc_u32_e32 v16, v16, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v11
	v_cmp_lt_u32_e64 s0, 31, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, 0xdb629599, v17, v[2:3]
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, v18, v16
	v_dual_mov_b32 v2, v12 :: v_dual_cndmask_b32 v9, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v18
	v_mad_u64_u32 v[12:13], null, 0xf534ddc0, v17, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v13
	v_cndmask_b32_e32 v10, v12, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v17, v[2:3]
	v_cndmask_b32_e64 v9, v10, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v14
	v_mad_u64_u32 v[14:15], null, 0x4e441529, v17, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v15
	v_mad_u64_u32 v[15:16], null, 0xa2f9836e, v17, v[2:3]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v14, v12, vcc_lo
	v_dual_cndmask_b32 v15, v15, v13 :: v_dual_add_nc_u32 v2, v2, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v14, v16, v14 :: v_dual_cndmask_b32 v13, v13, v11
	v_sub_nc_u32_e32 v16, 32, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v15, v17, s0
	v_cndmask_b32_e64 v14, v14, v15, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v17, v13, s0
	v_cndmask_b32_e64 v13, v13, v10, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v14, v14, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v15, s1
	v_cndmask_b32_e64 v15, v15, v13, s1
	v_cndmask_b32_e64 v9, v13, v9, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v14, v12, v16
	v_alignbit_b32 v11, v12, v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v17, v14, vcc_lo
	v_cndmask_b32_e32 v10, v11, v12, vcc_lo
	v_alignbit_b32 v14, v15, v9, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v11, v2, 29, 1
	v_alignbit_b32 v12, v2, v10, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_sub_nc_u32_e32 v13, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v10, v14, 30
	v_alignbit_b32 v9, v14, v9, 30
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v13
	v_xor_b32_e32 v9, v9, v13
	v_lshrrev_b32_e32 v13, 29, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v15, v12
	v_lshrrev_b32_e32 v2, 30, v2
	v_lshlrev_b32_e32 v13, 31, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v15, 32, v15
	v_or_b32_e32 v16, 0.5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v17, 23, v15
	v_sub_nc_u32_e32 v14, 31, v15
	v_sub_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_alignbit_b32 v12, v12, v10, v14
	v_alignbit_b32 v9, v10, v9, v14
	v_alignbit_b32 v10, v12, v9, 9
	v_lshrrev_b32_e32 v12, 9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v10
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, 31, v14
	v_alignbit_b32 v9, v10, v9, v18
	v_or_b32_e32 v10, v12, v16
	v_add_lshl_u32 v12, v14, v15, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v9, 9, v9
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v12
	v_fma_f32 v12, 0x3fc90fda, v10, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 0x33000000, v9
	v_fmac_f32_e32 v12, 0x33a22168, v10
	v_add_nc_u32_e32 v10, v11, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v9, v9, v13
	v_fmac_f32_e32 v12, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v9, v14, v12
.LBB0_7:                                ; %Flow100
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s0, s14
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=1
	v_mul_f32_e64 v2, 0x3f22f983, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v2
	v_fma_f32 v9, 0xbfc90fda, v2, |v7|
	v_cvt_i32_f32_e32 v10, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0xb3a22168, v2
	v_fmac_f32_e32 v9, 0xa7c234c4, v2
; %bb.9:                                ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s0, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=1
	v_and_or_b32 v19, v8, s10, 0x800000
	v_lshrrev_b32_e32 v16, 23, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, 0xfe5163ab, v19, 0
	v_add_nc_u32_e32 v17, 0xffffff88, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v17
	v_mov_b32_e32 v2, v12
	v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0x3c439041, v19, v[2:3]
	v_add_nc_u32_e32 v18, v18, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v13
	v_cmp_lt_u32_e64 s0, 31, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0xdb629599, v19, v[2:3]
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v20, v20, v18
	v_dual_mov_b32 v2, v14 :: v_dual_cndmask_b32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v20
	v_mad_u64_u32 v[14:15], null, 0xf534ddc0, v19, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v2, v15
	v_cndmask_b32_e32 v12, v14, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfc2757d1, v19, v[2:3]
	v_cndmask_b32_e64 v11, v12, v11, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v16
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v19, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v17
	v_mad_u64_u32 v[17:18], null, 0xa2f9836e, v19, v[2:3]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, v16, v14 :: v_dual_add_nc_u32 v2, v2, v20
	v_dual_cndmask_b32 v17, v17, v15 :: v_dual_cndmask_b32 v16, v18, v16
	v_cndmask_b32_e32 v15, v15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v18, 32, v2
	v_cndmask_b32_e64 v14, v17, v19, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v16, v17, s0
	v_cndmask_b32_e64 v17, v19, v15, s0
	v_cndmask_b32_e64 v15, v15, v12, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v16, v14, s1
	v_cndmask_b32_e64 v14, v14, v17, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v15, s1
	v_cndmask_b32_e64 v11, v15, v11, s1
	v_alignbit_b32 v19, v16, v14, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v13, v14, v17, v18
	v_cndmask_b32_e32 v2, v19, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v12, v13, v14, vcc_lo
	v_alignbit_b32 v16, v17, v11, v18
	v_bfe_u32 v13, v2, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v2, v12, 30
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v15, 0, v13
	v_alignbit_b32 v12, v12, v16, 30
	v_alignbit_b32 v11, v16, v11, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v14, v15
	v_xor_b32_e32 v12, v12, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v11, v15
	v_lshrrev_b32_e32 v15, 29, v2
	v_clz_i32_u32_e32 v17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v15, 31, v15
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v18, 0.5, v15
	v_sub_nc_u32_e32 v16, 31, v17
	v_lshlrev_b32_e32 v19, 23, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v14, v12, v16
	v_alignbit_b32 v11, v12, v11, v16
	v_sub_nc_u32_e32 v18, v18, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v14, v11, 9
	v_lshrrev_b32_e32 v14, 9, v14
	v_clz_i32_u32_e32 v16, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v16, 32, v16
	v_sub_nc_u32_e32 v20, 31, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v12, v11, v20
	v_or_b32_e32 v12, v14, v18
	v_add_lshl_u32 v14, v16, v17, 23
	v_lshrrev_b32_e32 v11, 9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, 0x3fc90fda, v12
	v_sub_nc_u32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, 0x3fc90fda, v12, -v16
	v_add_nc_u32_e32 v11, 0x33000000, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, 0x33a22168, v12
	v_or_b32_e32 v11, v11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 0x3fc90fda, v11
	v_lshrrev_b32_e32 v11, 30, v2
	v_dual_add_f32 v2, v16, v14 :: v_dual_add_nc_u32 v11, v13, v11
.LBB0_11:                               ; %Flow
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s0, s13
; %bb.12:                               ;   in Loop: Header=BB0_5 Depth=1
	v_mul_f32_e64 v2, 0x3f22f983, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v11, v2
	v_fma_f32 v2, 0xbfc90fda, v11, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0xb3a22168, v11
	v_fmac_f32_e32 v2, 0xa7c234c4, v11
	v_cvt_i32_f32_e32 v11, v11
; %bb.13:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v12, v9, v9 :: v_dual_and_b32 v13, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v14, v2, v2
	v_xor_b32_e32 v8, v8, v7
	s_add_i32 s3, s3, 1
	v_fmaak_f32 v15, s11, v12, 0x3c0881c4
	v_dual_fmaak_f32 v16, s12, v12, 0xbab64f3b :: v_dual_and_b32 v17, 1, v11
	v_lshlrev_b32_e32 v10, 30, v10
	v_dual_fmaak_f32 v18, s11, v14, 0x3c0881c4 :: v_dual_lshlrev_b32 v11, 30, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v15, v12, v15, 0xbe2aaa9d
	v_fmaak_f32 v16, v12, v16, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v18, v14, v18, 0xbe2aaa9d
	v_and_b32_e32 v11, 0x80000000, v11
	v_mul_f32_e32 v15, v12, v15
	v_fmaak_f32 v16, v12, v16, 0xbf000004
	v_mov_b32_e32 v20, s2
	v_mul_f32_e32 v18, v14, v18
	s_add_i32 s2, s2, 4
	v_fmac_f32_e32 v9, v9, v15
	v_fma_f32 v12, v12, v16, 1.0
	v_and_b32_e32 v15, 0x80000000, v10
	s_cmp_eq_u32 s9, s3
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v12, -v9, v12, vcc_lo
	ds_load_2addr_stride64_b32 v[9:10], v20 offset1:8
	v_fmaak_f32 v19, s12, v14, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v17
	v_xor_b32_e32 v12, v15, v12
	v_fmac_f32_e32 v2, v2, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v19, v14, v19, 0x3d2aabf7
	v_fmaak_f32 v19, v14, v19, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, v14, v19, 1.0
	v_cndmask_b32_e32 v2, v14, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v7, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v2, v8, v11, v2
	v_cndmask_b32_e32 v7, 0x7fc00000, v12, vcc_lo
	v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v8, v9, v2
	v_mul_f32_e32 v2, v10, v2
	v_fma_f32 v8, v7, v10, -v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v2, v7, v9
	v_add_f32_e32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v0, v0, v2
	s_cbranch_scc0 .LBB0_5
.LBB0_14:                               ; %Flow102
	v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[5:6], v4, off
	global_store_b32 v[1:2], v0, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8gpu_fftxPfS_S_S_ii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8gpu_fftxPfS_S_S_ii, .Lfunc_end0-_Z8gpu_fftxPfS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2312
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9gpu_ifftxPfS_S_S_ii  ; -- Begin function _Z9gpu_ifftxPfS_S_S_ii
	.globl	_Z9gpu_ifftxPfS_S_S_ii
	.p2align	8
	.type	_Z9gpu_ifftxPfS_S_S_ii,@function
_Z9gpu_ifftxPfS_S_S_ii:                 ; @_Z9gpu_ifftxPfS_S_S_ii
; %bb.0:
	s_clause 0x3
	s_load_b32 s11, s[0:1], 0x34
	s_load_b32 s10, s[0:1], 0x28
	s_load_b64 s[8:9], s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s11, s11, 0xffff
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB1_3
; %bb.1:                                ; %.lr.ph
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	v_lshlrev_b32_e32 v3, 2, v0
	s_lshl_b32 s12, s11, 2
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s10, s10, -1
	s_cmp_eq_u32 s10, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_nc_u32_e32 v1, s11, v1
	v_add_co_u32 v6, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v2, v[6:7], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v3, v4, v2 offset1:8
	v_add_nc_u32_e32 v3, s12, v3
	s_cbranch_scc0 .LBB1_2
.LBB1_3:                                ; %._crit_edge
	v_mad_u64_u32 v[1:2], null, s14, s11, v[0:1]
	v_cvt_f32_i32_e32 v6, s9
	s_cmp_lg_u32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB1_15
; %bb.4:                                ; %.lr.ph64
	v_cvt_f32_i32_e32 v2, v1
	v_cvt_f32_i32_e32 v0, s9
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v7, 0x40c90fda, v2
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0
	s_mov_b32 s10, 0x7fffff
	s_mov_b32 s11, 0xb94c1982
	s_mov_b32 s12, 0x37d75334
.LBB1_5:                                ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v2, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v7, v2
	v_div_scale_f32 v8, null, v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	v_fmac_f32_e32 v9, v10, v9
	v_div_scale_f32 v11, vcc_lo, v2, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v11, v9
	v_fma_f32 v12, -v8, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v12, v9
	v_fma_f32 v8, -v8, v10, v11
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v9, v10
                                        ; implicit-def: $vgpr10
	v_div_fixup_f32 v8, v8, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v9, 0x7fffffff, v8
	v_cmp_ngt_f32_e64 s13, 0x48000000, |v8|
	v_lshrrev_b32_e32 v13, 23, v9
	v_and_or_b32 v12, v9, s10, 0x800000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s13
	s_xor_b32 s14, exec_lo, s0
	s_cbranch_execz .LBB1_7
; %bb.6:                                ;   in Loop: Header=BB1_5 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v12, 0
	v_dual_mov_b32 v2, v11 :: v_dual_add_nc_u32 v11, 0xffffff88, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0x3c439041, v12, v[2:3]
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, v19, v11
	v_cmp_lt_u32_e64 s0, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	v_dual_mov_b32 v2, v15 :: v_dual_add_nc_u32 v11, v20, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xdb629599, v12, v[2:3]
	v_cmp_lt_u32_e64 s1, 31, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v2, v16
	v_cndmask_b32_e32 v10, v15, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[16:17], null, 0xf534ddc0, v12, v[2:3]
	v_mov_b32_e32 v2, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0xfc2757d1, v12, v[2:3]
	v_mov_b32_e32 v2, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[18:19], null, 0x4e441529, v12, v[2:3]
	v_dual_mov_b32 v2, v19 :: v_dual_cndmask_b32 v21, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v12, v[2:3]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v19, v19, v17 :: v_dual_add_nc_u32 v2, v2, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v18, v20, v18 :: v_dual_cndmask_b32 v17, v17, v15
	v_cndmask_b32_e32 v11, v16, v14, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v19, v21, s0
	v_cndmask_b32_e64 v16, v18, v19, s0
	v_cndmask_b32_e64 v18, v21, v17, s0
	v_sub_nc_u32_e32 v19, 32, v2
	v_cndmask_b32_e64 v17, v17, v11, s0
	v_cndmask_b32_e64 v10, v11, v10, s0
	v_cndmask_b32_e64 v16, v16, v14, s1
	v_cndmask_b32_e64 v14, v14, v18, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v18, v17, s1
	v_cndmask_b32_e64 v10, v17, v10, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v16, v14, v19
	v_alignbit_b32 v15, v14, v18, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v17, v18, v10, v19
	v_dual_cndmask_b32 v2, v20, v16 :: v_dual_cndmask_b32 v11, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v17, v18, vcc_lo
	v_bfe_u32 v14, v2, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v2, v11, 30
	v_alignbit_b32 v11, v11, v17, 30
	v_alignbit_b32 v10, v17, v10, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v16, 0, v14
	v_xor_b32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v11, v16
	v_xor_b32_e32 v10, v10, v16
	v_lshrrev_b32_e32 v16, 29, v2
	v_lshrrev_b32_e32 v2, 30, v2
	v_clz_i32_u32_e32 v18, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v16, 31, v16
	v_min_u32_e32 v18, 32, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v19, 0.5, v16
	v_sub_nc_u32_e32 v17, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v15, v11, v17
	v_alignbit_b32 v10, v11, v10, v17
	v_sub_nc_u32_e32 v19, v19, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v11, v15, v10, 9
	v_lshrrev_b32_e32 v15, 9, v15
	v_clz_i32_u32_e32 v17, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v17, 32, v17
	v_sub_nc_u32_e32 v21, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v10, v21
	v_or_b32_e32 v11, v15, v19
	v_add_lshl_u32 v15, v17, v18, 23
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, 0x3fc90fda, v11
	v_sub_nc_u32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, 0x3fc90fda, v11, -v17
	v_add_nc_u32_e32 v10, 0x33000000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v15, 0x33a22168, v11
	v_add_nc_u32_e32 v11, v14, v2
	v_or_b32_e32 v10, v10, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, 0x3fc90fda, v10
	v_add_f32_e32 v10, v17, v15
.LBB1_7:                                ; %Flow102
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_or_saveexec_b32 s0, s14
	v_mul_f32_e64 v15, 0x3f22f983, |v8|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.8:                                ;   in Loop: Header=BB1_5 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v2, v15
	v_fma_f32 v10, 0xbfc90fda, v2, |v8|
	v_cvt_i32_f32_e32 v11, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0xb3a22168, v2
	v_fmac_f32_e32 v10, 0xa7c234c4, v2
; %bb.9:                                ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s0, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s0
	s_cbranch_execz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_5 Depth=1
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v12, 0
	v_add_nc_u32_e32 v13, 0xffffff88, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v13
	v_mov_b32_e32 v2, v15
	v_cndmask_b32_e64 v20, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0x3c439041, v12, v[2:3]
	v_add_nc_u32_e32 v13, v20, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s0, 31, v13
	v_cndmask_b32_e64 v21, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, v16 :: v_dual_add_nc_u32 v13, v21, v13
	v_mad_u64_u32 v[16:17], null, 0xdb629599, v12, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v13
	v_mov_b32_e32 v2, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v16, v14, vcc_lo
	v_mad_u64_u32 v[17:18], null, 0xf534ddc0, v12, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v18
	v_mad_u64_u32 v[18:19], null, 0xfc2757d1, v12, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v19
	v_mad_u64_u32 v[19:20], null, 0x4e441529, v12, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v2, v20
	v_mad_u64_u32 v[20:21], null, 0xa2f9836e, v12, v[2:3]
	v_cndmask_b32_e64 v2, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v19, v17, vcc_lo
	v_dual_cndmask_b32 v13, v17, v15 :: v_dual_add_nc_u32 v2, v2, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v20, v20, v18 :: v_dual_cndmask_b32 v19, v21, v19
	v_cndmask_b32_e32 v18, v18, v16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v20, v12, s0
	v_cndmask_b32_e64 v17, v19, v20, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v18, s0
	v_sub_nc_u32_e32 v19, 32, v2
	v_cndmask_b32_e64 v18, v18, v13, s0
	v_cndmask_b32_e64 v13, v13, v14, s0
	v_cndmask_b32_e64 v17, v17, v15, s1
	v_cndmask_b32_e64 v15, v15, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v18, s1
	v_cndmask_b32_e64 v13, v18, v13, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v17, v15, v19
	v_alignbit_b32 v16, v15, v12, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v12, v13, v19
	v_cndmask_b32_e32 v2, v20, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, v16, v15, vcc_lo
	v_cndmask_b32_e32 v12, v18, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v15, v2, 29, 1
	v_alignbit_b32 v16, v2, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v14, v14, v12, 30
	v_alignbit_b32 v12, v12, v13, 30
	v_sub_nc_u32_e32 v17, 0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v17
	v_xor_b32_e32 v13, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v17
	v_clz_i32_u32_e32 v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v18, 32, v18
	v_sub_nc_u32_e32 v14, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v16, v13, v14
	v_alignbit_b32 v12, v13, v12, v14
	v_lshrrev_b32_e32 v14, 29, v2
	v_alignbit_b32 v13, v16, v12, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v14, 31, v14
	v_lshrrev_b32_e32 v16, 9, v16
	v_clz_i32_u32_e32 v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v19, 0.5, v14
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v20
	v_sub_nc_u32_e32 v21, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v13, v12, v21
	v_or_b32_e32 v13, v16, v19
	v_add_lshl_u32 v16, v17, v18, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v12, 9, v12
	v_mul_f32_e32 v17, 0x3fc90fda, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v12, v16
	v_fma_f32 v16, 0x3fc90fda, v13, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, 0x33000000, v12
	v_fmac_f32_e32 v16, 0x33a22168, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v12, v12, v14
	v_fmac_f32_e32 v16, 0x3fc90fda, v12
	v_lshrrev_b32_e32 v12, 30, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, v17, v16
	v_add_nc_u32_e32 v14, v15, v12
                                        ; implicit-def: $vgpr15
.LBB1_11:                               ; %Flow
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_and_not1_saveexec_b32 s0, s13
; %bb.12:                               ;   in Loop: Header=BB1_5 Depth=1
	v_rndne_f32_e32 v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, 0xbfc90fda, v12, |v8|
	v_cvt_i32_f32_e32 v14, v12
	v_fmac_f32_e32 v2, 0xb3a22168, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0xa7c234c4, v12
; %bb.13:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB1_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v12, v10, v10 :: v_dual_and_b32 v13, 1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v2, v2
	v_xor_b32_e32 v9, v9, v8
	s_add_i32 s3, s3, 1
	v_fmaak_f32 v16, s11, v12, 0x3c0881c4
	v_dual_fmaak_f32 v17, s12, v12, 0xbab64f3b :: v_dual_and_b32 v18, 1, v14
	v_lshlrev_b32_e32 v11, 30, v11
	v_dual_fmaak_f32 v19, s11, v15, 0x3c0881c4 :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v16, v12, v16, 0xbe2aaa9d
	v_fmaak_f32 v17, v12, v17, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v19, v15, v19, 0xbe2aaa9d
	v_dual_mul_f32 v16, v12, v16 :: v_dual_and_b32 v13, 0x80000000, v14
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v17, v12, v17, 0xbf000004
	v_mov_b32_e32 v21, s2
	s_add_i32 s2, s2, 4
	s_cmp_eq_u32 s9, s3
	v_fmac_f32_e32 v10, v10, v16
	v_fma_f32 v12, v12, v17, 1.0
	v_and_b32_e32 v16, 0x80000000, v11
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v12, -v10, v12, vcc_lo
	ds_load_2addr_stride64_b32 v[10:11], v21 offset1:8
	v_fmaak_f32 v20, s12, v15, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_xor_b32_e32 v12, v16, v12
	v_mul_f32_e32 v19, v15, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v20, v15, v20, 0x3d2aabf7
	v_fmac_f32_e32 v2, v2, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v20, v15, v20, 0xbf000004
	v_fma_f32 v15, v15, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v15, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x1f8
	v_xor3_b32 v2, v9, v13, v2
	v_cndmask_b32_e32 v8, 0x7fc00000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v9, v10, v2
	v_mul_f32_e32 v2, v11, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, v8, v11, -v9
	v_dual_fmac_f32 v2, v8, v10 :: v_dual_add_f32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v4, v2
	s_cbranch_scc0 .LBB1_5
; %bb.14:                               ; %Flow103
	s_mov_b32 s0, 0
	s_branch .LBB1_16
.LBB1_15:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr0
.LBB1_16:                               ; %Flow104
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_18
; %bb.17:                               ; %._crit_edge.._crit_edge65_crit_edge
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	v_mov_b32_e32 v0, v6
.LBB1_18:                               ; %._crit_edge65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v6, null, v0, v0, v5
	v_div_scale_f32 v7, null, v0, v0, v4
	v_div_scale_f32 v10, vcc_lo, v5, v0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v8, v6
	v_rcp_f32_e32 v9, v7
	v_div_scale_f32 v11, s0, v4, v0, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v2, -v6, v8, 1.0
	v_fma_f32 v3, -v7, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v8, v2, v8 :: v_dual_fmac_f32 v9, v3, v9
	v_mad_u64_u32 v[2:3], null, s15, s8, v[1:2]
	v_dual_mul_f32 v12, v10, v8 :: v_dual_mul_f32 v13, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_fma_f32 v1, -v6, v12, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v7, v13, v11
	v_dual_fmac_f32 v12, v1, v8 :: v_dual_fmac_f32 v13, v14, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	v_fma_f32 v6, -v6, v12, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v3, -v7, v13, v11
	v_div_fmas_f32 v8, v6, v8, v12
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v3, v3, v9, v13
	v_add_co_u32 v6, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v2, vcc_lo
	v_div_fixup_f32 v5, v8, v0, v5
	v_div_fixup_f32 v3, v3, v0, v4
	v_add_co_u32 v0, vcc_lo, s6, v1
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
	global_store_b32 v[6:7], v5, off
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9gpu_ifftxPfS_S_S_ii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z9gpu_ifftxPfS_S_S_ii, .Lfunc_end1-_Z9gpu_ifftxPfS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2484
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8gpu_fftyPfS_S_S_ii   ; -- Begin function _Z8gpu_fftyPfS_S_S_ii
	.globl	_Z8gpu_fftyPfS_S_S_ii
	.p2align	8
	.type	_Z8gpu_fftyPfS_S_S_ii,@function
_Z8gpu_fftyPfS_S_S_ii:                  ; @_Z8gpu_fftyPfS_S_S_ii
; %bb.0:
	s_clause 0x3
	s_load_b32 s10, s[0:1], 0x34
	s_load_b32 s9, s[0:1], 0x2c
	s_load_b32 s8, s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s10, s10, 16
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	v_mad_u64_u32 v[0:1], null, v2, s8, s[14:15]
	v_lshlrev_b32_e32 v3, 2, v2
	s_lshl_b32 s11, s10, 2
	s_mul_i32 s12, s8, s10
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s9, s9, -1
	s_cmp_eq_u32 s9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_nc_u32_e32 v0, s12, v0
	v_add_co_u32 v6, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v1, v[6:7], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v3, v4, v1 offset1:8
	v_add_nc_u32_e32 v3, s11, v3
	s_cbranch_scc0 .LBB2_2
.LBB2_3:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s10, v[2:3]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
	s_cmp_eq_u32 s8, 0
	s_mov_b32 s2, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB2_14
; %bb.4:                                ; %.lr.ph62
	v_cvt_f32_i32_e32 v1, v0
	v_cvt_f32_i32_e32 v5, s8
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v6, 0xc0c90fda, v1
	s_mov_b32 s3, 0
	s_mov_b32 s9, 0x7fffff
	s_mov_b32 s10, 0xb94c1982
	s_mov_b32 s11, 0x37d75334
.LBB2_5:                                ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v6, v1
	v_div_scale_f32 v7, null, v5, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v8, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v7, v8, 1.0
	v_fmac_f32_e32 v8, v9, v8
	v_div_scale_f32 v10, vcc_lo, v1, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v10, v8
	v_fma_f32 v11, -v7, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, v11, v8
	v_fma_f32 v7, -v7, v9, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v7, v7, v8, v9
                                        ; implicit-def: $vgpr9
	v_div_fixup_f32 v7, v7, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, 0x7fffffff, v7
	v_cmp_ngt_f32_e64 s12, 0x48000000, |v7|
	s_and_saveexec_b32 s0, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s13, exec_lo, s0
	s_cbranch_execz .LBB2_7
; %bb.6:                                ;   in Loop: Header=BB2_5 Depth=1
	v_lshrrev_b32_e32 v14, 23, v8
	v_and_or_b32 v17, v8, s9, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v15, 0xffffff88, v14
	v_mad_u64_u32 v[9:10], null, 0xfe5163ab, v17, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v15
	v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v1, v10 :: v_dual_add_nc_u32 v16, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0x3c439041, v17, v[1:2]
	v_cmp_lt_u32_e64 s0, 31, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v18, 0, 0xffffffe0, s0
	v_dual_mov_b32 v1, v11 :: v_dual_add_nc_u32 v18, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, 0xdb629599, v17, v[1:2]
	v_cmp_lt_u32_e64 s1, 31, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v1, v12
	v_cndmask_b32_e32 v9, v11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0xf534ddc0, v17, v[1:2]
	v_dual_mov_b32 v1, v13 :: v_dual_cndmask_b32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0xfc2757d1, v17, v[1:2]
	v_cndmask_b32_e64 v9, v10, v9, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v14
	v_mad_u64_u32 v[14:15], null, 0x4e441529, v17, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v15
	v_mad_u64_u32 v[15:16], null, 0xa2f9836e, v17, v[1:2]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v14, v12, vcc_lo
	v_add_nc_u32_e32 v1, v1, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
	v_cndmask_b32_e32 v13, v13, v11, vcc_lo
	v_sub_nc_u32_e32 v16, 32, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v15, v17, s0
	v_cndmask_b32_e64 v14, v14, v15, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v17, v13, s0
	v_cndmask_b32_e64 v13, v13, v10, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e64 v14, v14, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v15, s1
	v_cndmask_b32_e64 v15, v15, v13, s1
	v_cndmask_b32_e64 v9, v13, v9, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v14, v12, v16
	v_alignbit_b32 v11, v12, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v1, v17, v14 :: v_dual_cndmask_b32 v10, v11, v12
	v_alignbit_b32 v14, v15, v9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v11, v1, 29, 1
	v_alignbit_b32 v12, v1, v10, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_sub_nc_u32_e32 v13, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v10, v14, 30
	v_alignbit_b32 v9, v14, v9, 30
	v_xor_b32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v13
	v_xor_b32_e32 v9, v9, v13
	v_lshrrev_b32_e32 v13, 29, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v15, v12
	v_lshrrev_b32_e32 v1, 30, v1
	v_lshlrev_b32_e32 v13, 31, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v15, 32, v15
	v_or_b32_e32 v16, 0.5, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v14, 31, v15
	v_lshlrev_b32_e32 v17, 23, v15
	v_alignbit_b32 v12, v12, v10, v14
	v_alignbit_b32 v9, v10, v9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, v16, v17
	v_alignbit_b32 v10, v12, v9, 9
	v_lshrrev_b32_e32 v12, 9, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v14, v10
	v_min_u32_e32 v14, 32, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, 31, v14
	v_alignbit_b32 v9, v10, v9, v18
	v_or_b32_e32 v10, v12, v16
	v_add_lshl_u32 v12, v14, v15, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v9, 9, v9
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v12
	v_fma_f32 v12, 0x3fc90fda, v10, -v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, 0x33000000, v9
	v_fmac_f32_e32 v12, 0x33a22168, v10
	v_add_nc_u32_e32 v10, v11, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v9, v9, v13
	v_fmac_f32_e32 v12, 0x3fc90fda, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v9, v14, v12
.LBB2_7:                                ; %Flow96
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_and_not1_saveexec_b32 s0, s13
; %bb.8:                                ;   in Loop: Header=BB2_5 Depth=1
	v_mul_f32_e64 v1, 0x3f22f983, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v1, v1
	v_fma_f32 v9, 0xbfc90fda, v1, |v7|
	v_cvt_i32_f32_e32 v10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v9, 0xb3a22168, v1
	v_fmac_f32_e32 v9, 0xa7c234c4, v1
; %bb.9:                                ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s0, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s0
	s_cbranch_execz .LBB2_11
; %bb.10:                               ;   in Loop: Header=BB2_5 Depth=1
	v_lshrrev_b32_e32 v16, 23, v8
	v_and_or_b32 v19, v8, s9, 0x800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v17, 0xffffff88, v16
	v_mad_u64_u32 v[11:12], null, 0xfe5163ab, v19, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e32 vcc_lo, 63, v17
	v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
	v_dual_mov_b32 v1, v12 :: v_dual_add_nc_u32 v18, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0x3c439041, v19, v[1:2]
	v_cmp_lt_u32_e64 s0, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	v_dual_mov_b32 v1, v13 :: v_dual_add_nc_u32 v20, v20, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[13:14], null, 0xdb629599, v19, v[1:2]
	v_cmp_lt_u32_e64 s1, 31, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v1, v14
	v_cndmask_b32_e32 v11, v13, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, 0xf534ddc0, v19, v[1:2]
	v_dual_mov_b32 v1, v15 :: v_dual_cndmask_b32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xfc2757d1, v19, v[1:2]
	v_cndmask_b32_e64 v11, v12, v11, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v16
	v_mad_u64_u32 v[16:17], null, 0x4e441529, v19, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v17
	v_mad_u64_u32 v[17:18], null, 0xa2f9836e, v19, v[1:2]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v19, v16, v14, vcc_lo
	v_add_nc_u32_e32 v1, v1, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v17, v17, v15 :: v_dual_cndmask_b32 v16, v18, v16
	v_cndmask_b32_e32 v15, v15, v13, vcc_lo
	v_sub_nc_u32_e32 v18, 32, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v17, v19, s0
	v_cndmask_b32_e64 v16, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v19, v15, s0
	v_cndmask_b32_e64 v15, v15, v12, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e64 v16, v16, v14, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v14, v17, s1
	v_cndmask_b32_e64 v17, v17, v15, s1
	v_cndmask_b32_e64 v11, v15, v11, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v16, v14, v18
	v_alignbit_b32 v13, v14, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v1, v19, v16 :: v_dual_cndmask_b32 v12, v13, v14
	v_alignbit_b32 v16, v17, v11, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v13, v1, 29, 1
	v_alignbit_b32 v14, v1, v12, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	v_sub_nc_u32_e32 v15, 0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v12, v16, 30
	v_alignbit_b32 v11, v16, v11, 30
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v15
	v_xor_b32_e32 v11, v11, v15
	v_lshrrev_b32_e32 v15, 29, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v17, v14
	v_lshlrev_b32_e32 v15, 31, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v17, 32, v17
	v_or_b32_e32 v18, 0.5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v16, 31, v17
	v_lshlrev_b32_e32 v19, 23, v17
	v_alignbit_b32 v14, v14, v12, v16
	v_alignbit_b32 v11, v12, v11, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v18, v18, v19
	v_alignbit_b32 v12, v14, v11, 9
	v_lshrrev_b32_e32 v14, 9, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v16, v12
	v_min_u32_e32 v16, 32, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v20, 31, v16
	v_alignbit_b32 v11, v12, v11, v20
	v_or_b32_e32 v12, v14, v18
	v_add_lshl_u32 v14, v16, v17, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v11, 9, v11
	v_mul_f32_e32 v16, 0x3fc90fda, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v11, v14
	v_fma_f32 v14, 0x3fc90fda, v12, -v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v11, 0x33000000, v11
	v_fmac_f32_e32 v14, 0x33a22168, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v11, v11, v15
	v_fmac_f32_e32 v14, 0x3fc90fda, v11
	v_lshrrev_b32_e32 v11, 30, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v16, v14
	v_add_nc_u32_e32 v11, v13, v11
.LBB2_11:                               ; %Flow
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_and_not1_saveexec_b32 s0, s12
; %bb.12:                               ;   in Loop: Header=BB2_5 Depth=1
	v_mul_f32_e64 v1, 0x3f22f983, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v11, v1
	v_fma_f32 v1, 0xbfc90fda, v11, |v7|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0xb3a22168, v11
	v_fmac_f32_e32 v1, 0xa7c234c4, v11
	v_cvt_i32_f32_e32 v11, v11
; %bb.13:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB2_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v12, v9, v9 :: v_dual_and_b32 v13, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v14, v1, v1
	v_xor_b32_e32 v8, v8, v7
	s_add_i32 s3, s3, 1
	v_fmaak_f32 v15, s10, v12, 0x3c0881c4
	v_dual_fmaak_f32 v16, s11, v12, 0xbab64f3b :: v_dual_and_b32 v17, 1, v11
	v_lshlrev_b32_e32 v10, 30, v10
	v_dual_fmaak_f32 v18, s10, v14, 0x3c0881c4 :: v_dual_lshlrev_b32 v11, 30, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v15, v12, v15, 0xbe2aaa9d
	v_fmaak_f32 v16, v12, v16, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v18, v14, v18, 0xbe2aaa9d
	v_and_b32_e32 v11, 0x80000000, v11
	v_mul_f32_e32 v15, v12, v15
	v_fmaak_f32 v16, v12, v16, 0xbf000004
	v_mov_b32_e32 v20, s2
	v_mul_f32_e32 v18, v14, v18
	s_add_i32 s2, s2, 4
	v_fmac_f32_e32 v9, v9, v15
	v_fma_f32 v12, v12, v16, 1.0
	v_and_b32_e32 v15, 0x80000000, v10
	v_fmac_f32_e32 v1, v1, v18
	s_cmp_eq_u32 s8, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, -v9, v12, vcc_lo
	ds_load_2addr_stride64_b32 v[9:10], v20 offset1:8
	v_fmaak_f32 v19, s11, v14, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v17
	v_xor_b32_e32 v12, v15, v12
	v_fmaak_f32 v19, v14, v19, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v19, v14, v19, 0xbf000004
	v_fma_f32 v14, v14, v19, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v14, v1, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v7, 0x1f8
	v_xor3_b32 v1, v8, v11, v1
	v_cndmask_b32_e32 v7, 0x7fc00000, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v8, v9, v1
	v_mul_f32_e32 v1, v10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v7, v10, -v8
	v_dual_fmac_f32 v1, v7, v9 :: v_dual_add_f32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v3, v3, v1
	s_cbranch_scc0 .LBB2_5
.LBB2_14:                               ; %Flow98
	v_mad_u64_u32 v[1:2], null, v0, s8, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[5:6], v4, off
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8gpu_fftyPfS_S_S_ii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z8gpu_fftyPfS_S_S_ii, .Lfunc_end2-_Z8gpu_fftyPfS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2316
; NumSgprs: 18
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9gpu_ifftyPfS_S_S_ii  ; -- Begin function _Z9gpu_ifftyPfS_S_S_ii
	.globl	_Z9gpu_ifftyPfS_S_S_ii
	.p2align	8
	.type	_Z9gpu_ifftyPfS_S_S_ii,@function
_Z9gpu_ifftyPfS_S_S_ii:                 ; @_Z9gpu_ifftyPfS_S_S_ii
; %bb.0:
	s_clause 0x3
	s_load_b32 s10, s[0:1], 0x34
	s_load_b32 s9, s[0:1], 0x2c
	s_load_b32 s8, s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s10, s10, 16
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB3_3
; %bb.1:                                ; %.lr.ph.preheader
	v_mad_u64_u32 v[0:1], null, v2, s8, s[14:15]
	v_lshlrev_b32_e32 v3, 2, v2
	s_lshl_b32 s11, s10, 2
	s_mul_i32 s12, s8, s10
.LBB3_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v1, 31, v0
	s_add_i32 s9, s9, -1
	s_cmp_eq_u32 s9, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	v_add_nc_u32_e32 v0, s12, v0
	v_add_co_u32 v6, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s2, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
	global_load_b32 v1, v[6:7], off
	global_load_b32 v4, v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v3, v4, v1 offset1:8
	v_add_nc_u32_e32 v3, s11, v3
	s_cbranch_scc0 .LBB3_2
.LBB3_3:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s10, v[2:3]
	v_cvt_f32_i32_e32 v6, s8
	s_cmp_lg_u32 s8, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB3_15
; %bb.4:                                ; %.lr.ph64
	v_cvt_f32_i32_e32 v1, v0
	v_cvt_f32_i32_e32 v3, s8
	v_mov_b32_e32 v2, 0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v7, 0x40c90fda, v1
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0
	s_mov_b32 s9, 0x7fffff
	s_mov_b32 s10, 0xb94c1982
	s_mov_b32 s11, 0x37d75334
.LBB3_5:                                ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_u32_e32 v1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v7, v1
	v_div_scale_f32 v8, null, v3, v3, v1
	v_div_scale_f32 v11, vcc_lo, v1, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	v_fmac_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v11, v9
	v_fma_f32 v12, -v8, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v12, v9
	v_fma_f32 v8, -v8, v10, v11
                                        ; implicit-def: $vgpr11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v9, v10
                                        ; implicit-def: $vgpr10
	v_div_fixup_f32 v8, v8, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_b32_e32 v9, 0x7fffffff, v8
	v_cmp_ngt_f32_e64 s12, 0x48000000, |v8|
	v_lshrrev_b32_e32 v13, 23, v9
	v_and_or_b32 v12, v9, s9, 0x800000
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s12
	s_xor_b32 s13, exec_lo, s0
	s_cbranch_execz .LBB3_7
; %bb.6:                                ;   in Loop: Header=BB3_5 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v12, 0
	v_mov_b32_e32 v1, v11
	v_add_nc_u32_e32 v11, 0xffffff88, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0x3c439041, v12, v[1:2]
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v15
	v_add_nc_u32_e32 v11, v19, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0xdb629599, v12, v[1:2]
	v_cmp_lt_u32_e64 s0, 31, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v1, v16 :: v_dual_cndmask_b32 v10, v15, v10
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0xf534ddc0, v12, v[1:2]
	v_add_nc_u32_e32 v11, v20, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s1, 31, v11
	v_mov_b32_e32 v1, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, 0xfc2757d1, v12, v[1:2]
	v_mov_b32_e32 v1, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[18:19], null, 0x4e441529, v12, v[1:2]
	v_mov_b32_e32 v1, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v21, v18, v16, vcc_lo
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v12, v[1:2]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v1, v11
	v_dual_cndmask_b32 v19, v19, v17 :: v_dual_cndmask_b32 v18, v20, v18
	v_cndmask_b32_e32 v17, v17, v15, vcc_lo
	v_cndmask_b32_e32 v11, v16, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_cndmask_b32_e64 v14, v19, v21, s0
	v_cndmask_b32_e64 v16, v18, v19, s0
	v_cndmask_b32_e64 v18, v21, v17, s0
	v_sub_nc_u32_e32 v19, 32, v1
	v_cndmask_b32_e64 v17, v17, v11, s0
	v_cndmask_b32_e64 v10, v11, v10, s0
	v_cndmask_b32_e64 v16, v16, v14, s1
	v_cndmask_b32_e64 v14, v14, v18, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v18, v18, v17, s1
	v_cndmask_b32_e64 v10, v17, v10, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v16, v14, v19
	v_alignbit_b32 v15, v14, v18, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v17, v18, v10, v19
	v_cndmask_b32_e32 v1, v20, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v11, v15, v14, vcc_lo
	v_cndmask_b32_e32 v17, v17, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v14, v1, 29, 1
	v_alignbit_b32 v15, v1, v11, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v11, v11, v17, 30
	v_alignbit_b32 v10, v17, v10, 30
	v_sub_nc_u32_e32 v16, 0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v15, v15, v16
	v_xor_b32_e32 v11, v11, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v16
	v_lshrrev_b32_e32 v16, 29, v1
	v_lshrrev_b32_e32 v1, 30, v1
	v_clz_i32_u32_e32 v18, v15
	v_lshlrev_b32_e32 v16, 31, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v18, 32, v18
	v_or_b32_e32 v19, 0.5, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v17, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	v_alignbit_b32 v15, v15, v11, v17
	v_alignbit_b32 v10, v11, v10, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v20
	v_alignbit_b32 v11, v15, v10, 9
	v_lshrrev_b32_e32 v15, 9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v17, v11
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v21, 31, v17
	v_alignbit_b32 v10, v11, v10, v21
	v_or_b32_e32 v11, v15, v19
	v_add_lshl_u32 v15, v17, v18, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v10, 9, v10
	v_mul_f32_e32 v17, 0x3fc90fda, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v15
	v_fma_f32 v15, 0x3fc90fda, v11, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 0x33000000, v10
	v_fmac_f32_e32 v15, 0x33a22168, v11
	v_add_nc_u32_e32 v11, v14, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v10, v10, v16
	v_fmac_f32_e32 v15, 0x3fc90fda, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v10, v17, v15
.LBB3_7:                                ; %Flow98
                                        ;   in Loop: Header=BB3_5 Depth=1
	s_or_saveexec_b32 s0, s13
	v_mul_f32_e64 v15, 0x3f22f983, |v8|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.8:                                ;   in Loop: Header=BB3_5 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v1, v15
	v_fma_f32 v10, 0xbfc90fda, v1, |v8|
	v_cvt_i32_f32_e32 v11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0xb3a22168, v1
	v_fmac_f32_e32 v10, 0xa7c234c4, v1
; %bb.9:                                ; %_ZL3cosf.exit
                                        ;   in Loop: Header=BB3_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $vgpr1
	s_and_saveexec_b32 s0, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s0
	s_cbranch_execz .LBB3_11
; %bb.10:                               ;   in Loop: Header=BB3_5 Depth=1
	v_mad_u64_u32 v[14:15], null, 0xfe5163ab, v12, 0
	v_add_nc_u32_e32 v13, 0xffffff88, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v13
	v_mov_b32_e32 v1, v15
	v_cndmask_b32_e64 v20, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[15:16], null, 0x3c439041, v12, v[1:2]
	v_add_nc_u32_e32 v13, v20, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v16
	v_cmp_lt_u32_e64 s0, 31, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0xdb629599, v12, v[1:2]
	v_cndmask_b32_e64 v21, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v13, v21, v13
	v_dual_mov_b32 v1, v17 :: v_dual_cndmask_b32 v14, v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v13
	v_mad_u64_u32 v[17:18], null, 0xf534ddc0, v12, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v18
	v_mad_u64_u32 v[18:19], null, 0xfc2757d1, v12, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v19
	v_mad_u64_u32 v[19:20], null, 0x4e441529, v12, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v1, v20
	v_mad_u64_u32 v[20:21], null, 0xa2f9836e, v12, v[1:2]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v12, v19, v17, vcc_lo
	v_dual_cndmask_b32 v20, v20, v18 :: v_dual_add_nc_u32 v1, v1, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, v21, v19 :: v_dual_cndmask_b32 v18, v18, v16
	v_cndmask_b32_e32 v13, v17, v15, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v20, v12, s0
	v_cndmask_b32_e64 v17, v19, v20, s0
	v_cndmask_b32_e64 v12, v12, v18, s0
	v_sub_nc_u32_e32 v19, 32, v1
	v_cndmask_b32_e64 v18, v18, v13, s0
	v_cndmask_b32_e64 v13, v13, v14, s0
	v_cndmask_b32_e64 v17, v17, v15, s1
	v_cndmask_b32_e64 v15, v15, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v18, s1
	v_cndmask_b32_e64 v13, v18, v13, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v20, v17, v15, v19
	v_alignbit_b32 v16, v15, v12, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v12, v13, v19
	v_cndmask_b32_e32 v1, v20, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v14, v16, v15, vcc_lo
	v_cndmask_b32_e32 v12, v18, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v15, v1, 29, 1
	v_alignbit_b32 v16, v1, v14, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v14, v14, v12, 30
	v_alignbit_b32 v12, v12, v13, 30
	v_sub_nc_u32_e32 v17, 0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v16, v16, v17
	v_xor_b32_e32 v13, v14, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v12, v12, v17
	v_clz_i32_u32_e32 v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v18, 32, v18
	v_sub_nc_u32_e32 v14, 31, v18
	v_lshlrev_b32_e32 v20, 23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_alignbit_b32 v16, v16, v13, v14
	v_alignbit_b32 v12, v13, v12, v14
	v_lshrrev_b32_e32 v14, 29, v1
	v_alignbit_b32 v13, v16, v12, 9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v14, 31, v14
	v_lshrrev_b32_e32 v16, 9, v16
	v_clz_i32_u32_e32 v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v19, 0.5, v14
	v_min_u32_e32 v17, 32, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v19, v19, v20
	v_sub_nc_u32_e32 v21, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v12, v13, v12, v21
	v_or_b32_e32 v13, v16, v19
	v_add_lshl_u32 v16, v17, v18, 23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshrrev_b32_e32 v12, 9, v12
	v_mul_f32_e32 v17, 0x3fc90fda, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v12, v16
	v_fma_f32 v16, 0x3fc90fda, v13, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v12, 0x33000000, v12
	v_fmac_f32_e32 v16, 0x33a22168, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v12, v12, v14
	v_fmac_f32_e32 v16, 0x3fc90fda, v12
	v_lshrrev_b32_e32 v12, 30, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v17, v16
	v_add_nc_u32_e32 v14, v15, v12
                                        ; implicit-def: $vgpr15
.LBB3_11:                               ; %Flow
                                        ;   in Loop: Header=BB3_5 Depth=1
	s_and_not1_saveexec_b32 s0, s12
; %bb.12:                               ;   in Loop: Header=BB3_5 Depth=1
	v_rndne_f32_e32 v12, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v1, 0xbfc90fda, v12, |v8|
	v_cvt_i32_f32_e32 v14, v12
	v_fmac_f32_e32 v1, 0xb3a22168, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0xa7c234c4, v12
; %bb.13:                               ; %_ZL3sinf.exit
                                        ;   in Loop: Header=BB3_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mul_f32 v12, v10, v10 :: v_dual_and_b32 v13, 1, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v15, v1, v1
	v_xor_b32_e32 v9, v9, v8
	s_add_i32 s3, s3, 1
	v_fmaak_f32 v16, s10, v12, 0x3c0881c4
	v_dual_fmaak_f32 v17, s11, v12, 0xbab64f3b :: v_dual_and_b32 v18, 1, v14
	v_lshlrev_b32_e32 v11, 30, v11
	v_dual_fmaak_f32 v19, s10, v15, 0x3c0881c4 :: v_dual_lshlrev_b32 v14, 30, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v16, v12, v16, 0xbe2aaa9d
	v_fmaak_f32 v17, v12, v17, 0x3d2aabf7
	v_cmp_eq_u32_e32 vcc_lo, 0, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v19, v15, v19, 0xbe2aaa9d
	v_dual_mul_f32 v16, v12, v16 :: v_dual_and_b32 v13, 0x80000000, v14
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v17, v12, v17, 0xbf000004
	v_mov_b32_e32 v21, s2
	s_add_i32 s2, s2, 4
	s_cmp_eq_u32 s8, s3
	v_fmac_f32_e32 v10, v10, v16
	v_fma_f32 v12, v12, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v12, -v10, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v18
	v_and_b32_e32 v16, 0x80000000, v11
	ds_load_2addr_stride64_b32 v[10:11], v21 offset1:8
	v_fmaak_f32 v20, s11, v15, 0xbab64f3b
	v_xor_b32_e32 v12, v16, v12
	v_mul_f32_e32 v19, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v20, v15, v20, 0x3d2aabf7 :: v_dual_fmac_f32 v1, v1, v19
	v_fmaak_f32 v20, v15, v20, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v15, v15, v20, 1.0
	v_cndmask_b32_e32 v1, v15, v1, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v8, 0x1f8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v1, v9, v13, v1
	v_cndmask_b32_e32 v8, 0x7fc00000, v12, vcc_lo
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, v10, v1
	v_mul_f32_e32 v1, v11, v1
	v_fma_f32 v9, v8, v11, -v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, v8, v10
	v_add_f32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v1
	s_cbranch_scc0 .LBB3_5
; %bb.14:                               ; %Flow99
	s_mov_b32 s0, 0
	s_branch .LBB3_16
.LBB3_15:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
.LBB3_16:                               ; %Flow100
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB3_18
; %bb.17:                               ; %._crit_edge.._crit_edge65_crit_edge
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v6
	v_mov_b32_e32 v5, 0
.LBB3_18:                               ; %._crit_edge65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v6, null, v3, v3, v5
	v_div_scale_f32 v7, null, v3, v3, v4
	v_div_scale_f32 v10, vcc_lo, v5, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v8, v6
	v_rcp_f32_e32 v9, v7
	v_div_scale_f32 v11, s0, v4, v3, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v1, -v6, v8, 1.0
	v_fma_f32 v2, -v7, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v8, v1, v8 :: v_dual_fmac_f32 v9, v2, v9
	v_mad_u64_u32 v[1:2], null, v0, s8, s[14:15]
	v_dual_mul_f32 v12, v10, v8 :: v_dual_mul_f32 v13, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_fma_f32 v0, -v6, v12, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v14, -v7, v13, v11
	v_dual_fmac_f32 v12, v0, v8 :: v_dual_fmac_f32 v13, v14, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_fma_f32 v6, -v6, v12, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v2, -v7, v13, v11
	v_div_fmas_f32 v8, v6, v8, v12
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v2, v2, v9, v13
	v_add_co_u32 v6, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_div_fixup_f32 v5, v8, v3, v5
	v_div_fixup_f32 v2, v2, v3, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[6:7], v5, off
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9gpu_ifftyPfS_S_S_ii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z9gpu_ifftyPfS_S_S_ii, .Lfunc_end3-_Z9gpu_ifftyPfS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2496
; NumSgprs: 18
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10gpu_filterPfS_ii    ; -- Begin function _Z10gpu_filterPfS_ii
	.globl	_Z10gpu_filterPfS_ii
	.p2align	8
	.type	_Z10gpu_filterPfS_ii,@function
_Z10gpu_filterPfS_ii:                   ; @_Z10gpu_filterPfS_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_ashr_i32 s6, s4, 31
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	s_ashr_i32 s7, s5, 31
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_lshr_b32 s2, s6, 29
	s_lshr_b32 s3, s7, 29
	s_add_i32 s2, s4, s2
	s_add_i32 s3, s5, s3
	s_ashr_i32 s2, s2, 3
	s_ashr_i32 s3, s3, 3
	v_cmp_gt_i32_e64 s2, s2, v0
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s6, s2, vcc_lo
	s_xor_b32 s6, s6, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s7, s6
	s_cbranch_execz .LBB4_4
; %bb.1:
	s_sub_i32 s5, s5, s3
	s_xor_b32 s2, s2, -1
	v_cmp_gt_i32_e64 s3, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB4_4
; %bb.2:
	v_cmp_gt_i32_e64 s2, s5, v0
	s_xor_b32 s5, vcc_lo, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB4_4
; %bb.3:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v4, off
.LBB4_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_filterPfS_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z10gpu_filterPfS_ii, .Lfunc_end4-_Z10gpu_filterPfS_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 304
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8gpu_fftxPfS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8gpu_fftxPfS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9gpu_ifftxPfS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9gpu_ifftxPfS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8gpu_fftyPfS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8gpu_fftyPfS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9gpu_ifftyPfS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9gpu_ifftyPfS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10gpu_filterPfS_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10gpu_filterPfS_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
