// cuda code for MPPI
// IMPORTANT make sure the macro declarations are accurate

#define SAMPLE_COUNT 2048
#define HORIZON 20

#define CONTROL_DIM 2
#define STATE_DIM 4
#define TEMPERATURE 1
#define DT 0.1

// evaluate step cost based on target state x_goal,current state x and control u
__device__
float evaluate_cost(float* x_goal, float* x, float* u);

// forward dynamics by one step
__device__
void forward_dynamics( float* x, float* u);

__global__
void evaluate_control_sequence(float *out_cost, float* x_goal, float *x0, float *in_control, float *in_epsilon){
  // get global thread id
  int id = blockIdx.x * blockDim.x + threadIdx.x;
  if (id>=SAMPLE_COUNT){
    return;
  }
  //printf("id = %d\n",id);
  float x[STATE_DIM];
  // copy to local state
  // NOTE possible time saving by copy to local memory
  for (int i=0; i<STATE_DIM; i++){
    x[i] = *(x0 + i);
  }

  // DEBUG
  /*
  if (id==0){
    printf("x0, %.2f, %.2f, %.2f, %.2f \n",x0[0],x0[1],x0[2],x0[3]);

  }
  */

  
  float* u = in_control + id*HORIZON*CONTROL_DIM; 

  // initialize cost
  float cost = 0;
  // run simulation
  for (int i=0; i<HORIZON; i++){
    // step forward dynamics, update state x in place
    forward_dynamics(x,u);

    // evaluate step cost
    cost += evaluate_cost(x_goal,x,u);
    // FIXME ignoring additional cost
    /*
    for (int j=0; j<CONTROL_DIM; j++){
      cost += u[i]*in_epsilon[id*HORIZON*CONTROL_DIM + i*CONTROL_DIM + j];
    }
    */
    // DEBUG
    /*
    if (id==0){
      printf("step=%d, S= %.3f, u: %.2f, %.2f ",i,cost,u[0],u[1]);
      printf("x: %.2f, %.2f, %.2f, %.2f \n",id,x[0],x[1],x[2],x[3]);
    }
    */

    u += CONTROL_DIM;

  }
  out_cost[id] = cost;

}

// for dual mass system
/*
__device__
float evaluate_cost(float* x, float* u){
    return (x[0]-1)*(x[0]-1)*1.0 + x[1]*x[1]*0.01 + (x[2]-3)*(x[2]-3)*1.0 + x[3]*x[3]*0.01;

}

__device__
void forward_dynamics(float* x,float* u){
    // prepare constants
    const float m1 = 1;
    const float m2 = 1;
    const float k1 = 1;
    const float k2 = 1;
    const float c1 = 1.4;
    const float c2 = 1.4;

    const float dt = DT;

    float x1 = x[0];
    float dx1 = x[1];
    float x2 = x[2];
    float dx2 = x[3];

    float ddx1 = -(k1*x1 + c1*dx1 + k2*(x1-x2) + c2*(dx1-dx2)-u[0])/m1;
    float ddx2 = -(k2*(x2-x1) + c2*(dx2-dx1)-u[1])/m2;

    //printf("id = %d, ddx1=%.2f, ddx2=%.2f \n",id,ddx1,ddx2);
    //float temp=-(k1*x1 + c1*dx1 + k2*(x1-x2) + c2*(dx1-dx2)-u0)/m1;
    x1 += dx1*dt;
    dx1 += ddx1*dt;
    x2 += dx2*dt;
    dx2 += ddx2*dt;
    //printf("id = %d, step = %d cost = %.2f, x= %.2f, %.2f, %.2f, %.2f \n",id,i,cost,x1,dx1,x2,dx2);

    x[0] = x1;
    x[1] = dx1;
    x[2] = x2;
    x[3] = dx2;
    return;
}
*/

// for Ji's decoupled system
__device__
float evaluate_cost(float* x_goal, float* x, float* u){
  // find state error
  float x0,x1,x2,x3;
  x0 = x_goal[0] - x[0];
  x1 = x_goal[1] - x[1];
  x2 = x_goal[2] - x[2];
  x3 = x_goal[3] - x[3];
  return x0*x0 + x1*x1 + x2*x2 + x3*x3 + u[0]*u[0] + u[1]*u[1];
}

__device__
void forward_dynamics(float* x,float* u){
  x[0] += x[2] + 0.5*u[0];
  x[1] += x[3] + 0.5*u[1];
  x[2] += u[0];
  x[3] += u[1];
  return;
}

// dummy placeholder for compiler testing
/*
int main(void){
  int blockSize = 1;
  int numBlocks = 256;
  int  N = 100;
  float *out_cost,*x_goal,*x0,*in_control,*in_epsilon;
   
  cudaMallocManaged(&out_cost, N*sizeof(float));
  cudaMallocManaged(&x_goal, N*sizeof(float));
  cudaMallocManaged(&x0, N*sizeof(float));
  cudaMallocManaged(&in_control, N*sizeof(float));
  cudaMallocManaged(&in_epsilon, N*sizeof(float));

  evaluate_control_sequence<<<numBlocks, blockSize>>>(out_cost,x_goal,x0,in_control,in_epsilon);
  return 0;

}
*/

	.file	"tmpxft_0031159b_00000000-6_mppi.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13evaluate_costPfS_S_
	.type	_Z13evaluate_costPfS_S_, @function
_Z13evaluate_costPfS_S_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z13evaluate_costPfS_S_, .-_Z13evaluate_costPfS_S_
	.globl	_Z16forward_dynamicsPfS_
	.type	_Z16forward_dynamicsPfS_, @function
_Z16forward_dynamicsPfS_:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2009:
	.size	_Z16forward_dynamicsPfS_, .-_Z16forward_dynamicsPfS_
	.globl	_Z53__device_stub__Z25evaluate_control_sequencePfS_S_S_S_PfS_S_S_S_
	.type	_Z53__device_stub__Z25evaluate_control_sequencePfS_S_S_S_PfS_S_S_S_, @function
_Z53__device_stub__Z25evaluate_control_sequencePfS_S_S_S_PfS_S_S_S_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L6
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z25evaluate_control_sequencePfS_S_S_S_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L6:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L8
	call	__stack_chk_fail@PLT
.L8:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z53__device_stub__Z25evaluate_control_sequencePfS_S_S_S_PfS_S_S_S_, .-_Z53__device_stub__Z25evaluate_control_sequencePfS_S_S_S_PfS_S_S_S_
	.globl	_Z25evaluate_control_sequencePfS_S_S_S_
	.type	_Z25evaluate_control_sequencePfS_S_S_S_, @function
_Z25evaluate_control_sequencePfS_S_S_S_:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z25evaluate_control_sequencePfS_S_S_S_PfS_S_S_S_
	.cfi_endproc
.LFE2035:
	.size	_Z25evaluate_control_sequencePfS_S_S_S_, .-_Z25evaluate_control_sequencePfS_S_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z25evaluate_control_sequencePfS_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z25evaluate_control_sequencePfS_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
// cuda code for MPPI
// IMPORTANT make sure the macro declarations are accurate

#define SAMPLE_COUNT 2048
#define HORIZON 20

#define CONTROL_DIM 2
#define STATE_DIM 4
#define TEMPERATURE 1
#define DT 0.1

// evaluate step cost based on target state x_goal,current state x and control u
__device__
float evaluate_cost(float* x_goal, float* x, float* u);

// forward dynamics by one step
__device__
void forward_dynamics( float* x, float* u);

__global__
void evaluate_control_sequence(float *out_cost, float* x_goal, float *x0, float *in_control, float *in_epsilon){
  // get global thread id
  int id = blockIdx.x * blockDim.x + threadIdx.x;
  if (id>=SAMPLE_COUNT){
    return;
  }
  //printf("id = %d\n",id);
  float x[STATE_DIM];
  // copy to local state
  // NOTE possible time saving by copy to local memory
  for (int i=0; i<STATE_DIM; i++){
    x[i] = *(x0 + i);
  }

  // DEBUG
  /*
  if (id==0){
    printf("x0, %.2f, %.2f, %.2f, %.2f \n",x0[0],x0[1],x0[2],x0[3]);

  }
  */

  
  float* u = in_control + id*HORIZON*CONTROL_DIM; 

  // initialize cost
  float cost = 0;
  // run simulation
  for (int i=0; i<HORIZON; i++){
    // step forward dynamics, update state x in place
    forward_dynamics(x,u);

    // evaluate step cost
    cost += evaluate_cost(x_goal,x,u);
    // FIXME ignoring additional cost
    /*
    for (int j=0; j<CONTROL_DIM; j++){
      cost += u[i]*in_epsilon[id*HORIZON*CONTROL_DIM + i*CONTROL_DIM + j];
    }
    */
    // DEBUG
    /*
    if (id==0){
      printf("step=%d, S= %.3f, u: %.2f, %.2f ",i,cost,u[0],u[1]);
      printf("x: %.2f, %.2f, %.2f, %.2f \n",id,x[0],x[1],x[2],x[3]);
    }
    */

    u += CONTROL_DIM;

  }
  out_cost[id] = cost;

}

// for dual mass system
/*
__device__
float evaluate_cost(float* x, float* u){
    return (x[0]-1)*(x[0]-1)*1.0 + x[1]*x[1]*0.01 + (x[2]-3)*(x[2]-3)*1.0 + x[3]*x[3]*0.01;

}

__device__
void forward_dynamics(float* x,float* u){
    // prepare constants
    const float m1 = 1;
    const float m2 = 1;
    const float k1 = 1;
    const float k2 = 1;
    const float c1 = 1.4;
    const float c2 = 1.4;

    const float dt = DT;

    float x1 = x[0];
    float dx1 = x[1];
    float x2 = x[2];
    float dx2 = x[3];

    float ddx1 = -(k1*x1 + c1*dx1 + k2*(x1-x2) + c2*(dx1-dx2)-u[0])/m1;
    float ddx2 = -(k2*(x2-x1) + c2*(dx2-dx1)-u[1])/m2;

    //printf("id = %d, ddx1=%.2f, ddx2=%.2f \n",id,ddx1,ddx2);
    //float temp=-(k1*x1 + c1*dx1 + k2*(x1-x2) + c2*(dx1-dx2)-u0)/m1;
    x1 += dx1*dt;
    dx1 += ddx1*dt;
    x2 += dx2*dt;
    dx2 += ddx2*dt;
    //printf("id = %d, step = %d cost = %.2f, x= %.2f, %.2f, %.2f, %.2f \n",id,i,cost,x1,dx1,x2,dx2);

    x[0] = x1;
    x[1] = dx1;
    x[2] = x2;
    x[3] = dx2;
    return;
}
*/

// for Ji's decoupled system
__device__
float evaluate_cost(float* x_goal, float* x, float* u){
  // find state error
  float x0,x1,x2,x3;
  x0 = x_goal[0] - x[0];
  x1 = x_goal[1] - x[1];
  x2 = x_goal[2] - x[2];
  x3 = x_goal[3] - x[3];
  return x0*x0 + x1*x1 + x2*x2 + x3*x3 + u[0]*u[0] + u[1]*u[1];
}

__device__
void forward_dynamics(float* x,float* u){
  x[0] += x[2] + 0.5*u[0];
  x[1] += x[3] + 0.5*u[1];
  x[2] += u[0];
  x[3] += u[1];
  return;
}

// dummy placeholder for compiler testing
/*
int main(void){
  int blockSize = 1;
  int numBlocks = 256;
  int  N = 100;
  float *out_cost,*x_goal,*x0,*in_control,*in_epsilon;
   
  cudaMallocManaged(&out_cost, N*sizeof(float));
  cudaMallocManaged(&x_goal, N*sizeof(float));
  cudaMallocManaged(&x0, N*sizeof(float));
  cudaMallocManaged(&in_control, N*sizeof(float));
  cudaMallocManaged(&in_epsilon, N*sizeof(float));

  evaluate_control_sequence<<<numBlocks, blockSize>>>(out_cost,x_goal,x0,in_control,in_epsilon);
  return 0;

}
*/

	.text
	.file	"mppi.hip"
	.globl	_Z40__device_stub__evaluate_control_sequencePfS_S_S_S_ # -- Begin function _Z40__device_stub__evaluate_control_sequencePfS_S_S_S_
	.type	_Z40__device_stub__evaluate_control_sequencePfS_S_S_S_,@function
_Z40__device_stub__evaluate_control_sequencePfS_S_S_S_: # @_Z40__device_stub__evaluate_control_sequencePfS_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25evaluate_control_sequencePfS_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__evaluate_control_sequencePfS_S_S_S_, .Lfunc_end0-_Z40__device_stub__evaluate_control_sequencePfS_S_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25evaluate_control_sequencePfS_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25evaluate_control_sequencePfS_S_S_S_,@object # @_Z25evaluate_control_sequencePfS_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z25evaluate_control_sequencePfS_S_S_S_
	.p2align	3, 0x0
_Z25evaluate_control_sequencePfS_S_S_S_:
	.quad	_Z40__device_stub__evaluate_control_sequencePfS_S_S_S_
	.size	_Z25evaluate_control_sequencePfS_S_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z25evaluate_control_sequencePfS_S_S_S_"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__evaluate_control_sequencePfS_S_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25evaluate_control_sequencePfS_S_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25evaluate_control_sequencePfS_S_S_S_ ; -- Begin function _Z25evaluate_control_sequencePfS_S_S_S_
	.globl	_Z25evaluate_control_sequencePfS_S_S_S_
	.p2align	8
	.type	_Z25evaluate_control_sequencePfS_S_S_S_,@function
_Z25evaluate_control_sequencePfS_S_S_S_: ; @_Z25evaluate_control_sequencePfS_S_S_S_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x800, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader.preheader
	s_load_b256 s[0:7], s[0:1], 0x0
	s_mov_b64 s[8:9], 0
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr2
.LBB0_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_load_b32 s10, s[4:5], 0x0
	s_cmp_eq_u32 s8, 0
	s_cselect_b32 s11, -1, 0
	s_cmp_eq_u32 s8, 1
	s_cselect_b32 s12, -1, 0
	s_cmp_eq_u32 s8, 2
	s_cselect_b32 s13, -1, 0
	s_cmp_eq_u32 s8, 3
	s_cselect_b32 s14, -1, 0
	s_add_u32 s8, s8, 1
	s_addc_u32 s9, s9, 0
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s8, 4
	s_waitcnt lgkmcnt(0)
	v_cndmask_b32_e64 v3, v3, s10, s11
	v_cndmask_b32_e64 v4, v4, s10, s12
	v_cndmask_b32_e64 v0, v0, s10, s13
	v_cndmask_b32_e64 v2, v2, s10, s14
	s_cbranch_scc0 .LBB0_2
; %bb.3:
	v_mul_lo_u32 v5, v1, 40
	s_load_b128 s[8:11], s[2:3], 0x0
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[6:7], 2, v[5:6]
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v6, s2
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
	v_cvt_f64_f32_e32 v[10:11], v2
	v_cvt_f64_f32_e32 v[14:15], v0
	v_cvt_f64_f32_e32 v[18:19], v4
	global_load_b64 v[8:9], v[8:9], off
	v_cvt_f64_f32_e32 v[3:4], v3
	s_add_u32 s2, s2, 8
	s_addc_u32 s3, s3, 0
	s_cmpk_eq_i32 s2, 0xa0
	s_waitcnt vmcnt(0)
	v_cvt_f64_f32_e32 v[12:13], v9
	v_cvt_f64_f32_e32 v[16:17], v8
	v_add_f32_e32 v2, v2, v9
	v_add_f32_e32 v0, v0, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[10:11], v[12:13], 0.5, v[10:11]
	v_fma_f64 v[12:13], v[16:17], 0.5, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[18:19]
	v_add_f64 v[12:13], v[12:13], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_f64_e32 v4, v[10:11]
	v_cvt_f32_f64_e32 v3, v[12:13]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, s9, v4 :: v_dual_sub_f32 v11, s8, v3
	v_mul_f32_e32 v10, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v10, v11, v11 :: v_dual_sub_f32 v11, s11, v2
	v_sub_f32_e32 v12, s10, v0
	v_fmac_f32_e32 v10, v12, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v11
	v_fmac_f32_e32 v10, v8, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v9, v9
	v_add_f32_e32 v5, v5, v10
	s_cbranch_scc0 .LBB0_4
; %bb.5:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25evaluate_control_sequencePfS_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25evaluate_control_sequencePfS_S_S_S_, .Lfunc_end0-_Z25evaluate_control_sequencePfS_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 464
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25evaluate_control_sequencePfS_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z25evaluate_control_sequencePfS_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
