#include <stdio.h>
#include <stdlib.h>

#define PI 3.14159265
#define PADDING_SIZE 1
#define FILTER_SIZE 3

// declaring constant memory for kernel
__device__ __constant__ float d_filterKernel[FILTER_SIZE] = { -1, 0, 1};


__global__ void convolution( float *image, int paddedX, int paddedY,
							 int blockX, int blockY, 
							 float *outputMag, float *outputAng,
							  int imgRows, int imgCols)
{

	/*
		this blockOrigin(X,Y) are w.r.t to the padded image 
		these are the coordinates where blocks (0,0) are placed in padded image
	*/
	
	int blockOriginX = blockIdx.x * blockX  + PADDING_SIZE;
	int blockOriginY = blockIdx.y * blockY  + PADDING_SIZE;
	// printf("blockOriginX:%d blockOriginY:%d\n",blockOriginX,blockOriginY);
	
	/*
		this tileOrigin(X,Y) are w.r.t to the padded image 
		these are the coordinates where tiles (0,0) are placed in padded image	
	*/	

	int tileOriginX = blockOriginX - PADDING_SIZE;
	int tileOriginY = blockOriginY - PADDING_SIZE;
	// printf("tileOriginX:%d tileOriginY:%d\n",tileOriginX,tileOriginY);

	/*	
		these coordinates specify the ends of this tile
		if( tileX is not divisible by 4 ) the last iteration when threads will be reused will exceed tile size
		so less than this tilesize or if ending of image is hit
		
	*/

	int tileEndX = min(tileOriginX + blockX + 2*PADDING_SIZE, paddedX);
	int tileEndY = min(tileOriginY + blockY + 2*PADDING_SIZE, paddedY);
	// printf("tileEndX:%d \n",tileEndX );
	
	// Allocating shared memory for this kernel
	extern __shared__ float imageTile[];

	/*
		the same thread is used to bring as many as 4 global memory to shared memory depending on whether it hits any boundary
	*/	

	for (int m = 0; m < 4; ++m)
	{
		/*		
			((m*blockDim.x)+threadIdx.x)) will give the threadIdx of tile along x direction in mth iteration 
			(tileOriginX +((m*blockDim.x)+threadIdx.x)) will give the global threadIdx along x direction in mth direction
		*/

		if( (tileOriginX +((m*blockDim.x)+threadIdx.x))<tileEndX &&  tileOriginY +threadIdx.y<tileEndY )
		{
				imageTile[((m*blockDim.x)+threadIdx.x)*blockDim.y+threadIdx.y] 
					= image[(tileOriginX +((m*blockDim.x)+threadIdx.x))*paddedY + tileOriginY  +threadIdx.y];		
		}
		// printf("threadIdx.x:%d threadIdx.y:%d \n",(m*blockDim.x)+threadIdx.x, threadIdx.y );

	}

	__syncthreads();

	for (int m = 0; m < 4; ++m)
	{
		if( ((m*blockDim.x)+threadIdx.x)<blockX && threadIdx.y<blockY 
			&& (tileOriginX + ((m*blockDim.x)+threadIdx.x))<imgRows && tileOriginY + threadIdx.y<imgCols)
		{
			double gX = 0, gY = 0, gMag = 0, gAng = 0;				
			for (int k = -PADDING_SIZE; k <= PADDING_SIZE ; ++k)
			{
				// along x direction 
				gX += d_filterKernel[k+PADDING_SIZE] * imageTile[((m*blockDim.x)+threadIdx.x +k +PADDING_SIZE )*blockDim.y + threadIdx.y +PADDING_SIZE];
				gY += d_filterKernel[k+PADDING_SIZE] * imageTile[((m*blockDim.x)+threadIdx.x +PADDING_SIZE )*blockDim.y + k +threadIdx.y +PADDING_SIZE];

			}
			// this 90.1 is to make gAng + else it becomes -0.0000
			gMag = sqrt(gX*gX + gY*gY);
			if( gX==0 )
				gAng = 90;
			else 
				gAng = atan(gY/gX)*180.0/PI + 90.1;
			outputMag[(tileOriginX + ((m*blockDim.x)+threadIdx.x))*(imgCols)+ tileOriginY + threadIdx.y] = gMag;
			outputAng[(tileOriginX + ((m*blockDim.x)+threadIdx.x))*(imgCols)+ tileOriginY + threadIdx.y] = gAng;
			
			// printf("threadIdx.x:%d threadIdx.y:%d \n", (m*blockDim.x)+threadIdx.x, threadIdx.y );

		}
	}

}
// i= 303756 -nan 0

__global__ void max(float *d_outputBMag,float *d_outputBAng,
					float *d_outputGMag,float *d_outputGAng,
					float *d_outputRMag,float *d_outputRAng,
					float *d_outputMag,float  *d_outputAng,
					int imgRows, int  imgCols)
{

	int tidx = blockIdx.x*blockDim.x + threadIdx.x;
	int tidy = blockIdx.y*blockDim.y + threadIdx.y;

	if( tidx<imgRows && tidy<imgCols)
	{
		float maxMag = d_outputBMag[tidx*imgCols + tidy], maxAng = d_outputBAng[tidx*imgCols + tidy];
		
		if( maxMag < d_outputGMag[tidx*imgCols + tidy] )
			maxMag = d_outputGMag[tidx*imgCols + tidy], maxAng = d_outputGAng[tidx*imgCols + tidy];

		if( maxMag < d_outputRMag[tidx*imgCols + tidy] )
			maxMag = d_outputRMag[tidx*imgCols + tidy], maxAng = d_outputRAng[tidx*imgCols + tidy];

		d_outputMag[tidx*imgCols + tidy] = maxMag,d_outputAng[tidx*imgCols + tidy] = maxAng; 
	}


}


__global__ void histogram(float *grad,float *dir, int height, int width,float *output)
{
    // 
    int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
    
    float magnitude=grad[i*width+j];
    float direction=dir[i*width+j];

    int blockNum=blockIdx.y*gridDim.x+blockIdx.x;

    //initializing the 9-element array for each block.
    if(threadIdx.x==0&&threadIdx.y==0)
    {
	    for(int k=0;k<9;++k)
	    {
	    	output[k+blockNum*9]=0;
	    }
	}
    __syncthreads();
    //waiting for initialization.

    //calculating the histogram values
    int low=(direction/20);
    atomicAdd(&output[blockNum*9+low],magnitude*((low+1)*20 -direction)/20.0);
    atomicAdd(&output[blockNum*9+(low+1)%9],magnitude*((direction-low*20)/20.0));	
}

	.file	"tmpxft_0021c1d6_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z41__device_stub__Z11convolutionPfiiiiS_S_iiPfiiiiS_S_ii
	.type	_Z41__device_stub__Z11convolutionPfiiiiS_S_iiPfiiiiS_S_ii, @function
_Z41__device_stub__Z11convolutionPfiiiiS_S_iiPfiiiiS_S_ii:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 32(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 28(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z11convolutionPfiiiiS_S_ii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z41__device_stub__Z11convolutionPfiiiiS_S_iiPfiiiiS_S_ii, .-_Z41__device_stub__Z11convolutionPfiiiiS_S_iiPfiiiiS_S_ii
	.globl	_Z11convolutionPfiiiiS_S_ii
	.type	_Z11convolutionPfiiiiS_S_ii, @function
_Z11convolutionPfiiiiS_S_ii:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z11convolutionPfiiiiS_S_iiPfiiiiS_S_ii
	.cfi_endproc
.LFE2052:
	.size	_Z11convolutionPfiiiiS_S_ii, .-_Z11convolutionPfiiiiS_S_ii
	.globl	_Z38__device_stub__Z3maxPfS_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_ii
	.type	_Z38__device_stub__Z3maxPfS_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_ii, @function
_Z38__device_stub__Z3maxPfS_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_ii:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rax, 8(%rsp)
	movq	248(%rsp), %rax
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 184(%rsp)
	movq	%rsp, %rax
	movq	%rax, 192(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z3maxPfS_S_S_S_S_S_S_ii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L8:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z38__device_stub__Z3maxPfS_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_ii, .-_Z38__device_stub__Z3maxPfS_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_ii
	.globl	_Z3maxPfS_S_S_S_S_S_S_ii
	.type	_Z3maxPfS_S_S_S_S_S_S_ii, @function
_Z3maxPfS_S_S_S_S_S_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z3maxPfS_S_S_S_S_S_S_iiPfS_S_S_S_S_S_S_ii
	.cfi_endproc
.LFE2054:
	.size	_Z3maxPfS_S_S_S_S_S_S_ii, .-_Z3maxPfS_S_S_S_S_S_S_ii
	.globl	_Z34__device_stub__Z9histogramPfS_iiS_PfS_iiS_
	.type	_Z34__device_stub__Z9histogramPfS_iiS_PfS_iiS_, @function
_Z34__device_stub__Z9histogramPfS_iiS_PfS_iiS_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9histogramPfS_iiS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z34__device_stub__Z9histogramPfS_iiS_PfS_iiS_, .-_Z34__device_stub__Z9histogramPfS_iiS_PfS_iiS_
	.globl	_Z9histogramPfS_iiS_
	.type	_Z9histogramPfS_iiS_, @function
_Z9histogramPfS_iiS_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z34__device_stub__Z9histogramPfS_iiS_PfS_iiS_
	.cfi_endproc
.LFE2056:
	.size	_Z9histogramPfS_iiS_, .-_Z9histogramPfS_iiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z9histogramPfS_iiS_"
.LC1:
	.string	"_Z3maxPfS_S_S_S_S_S_S_ii"
.LC2:
	.string	"_Z11convolutionPfiiiiS_S_ii"
.LC3:
	.string	"d_filterKernel"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z9histogramPfS_iiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3maxPfS_S_S_S_S_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11convolutionPfiiiiS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$12, %r9d
	leaq	_ZL14d_filterKernel(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2058:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL14d_filterKernel
	.comm	_ZL14d_filterKernel,12,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

#define PI 3.14159265
#define PADDING_SIZE 1
#define FILTER_SIZE 3

// declaring constant memory for kernel
__device__ __constant__ float d_filterKernel[FILTER_SIZE] = { -1, 0, 1};


__global__ void convolution( float *image, int paddedX, int paddedY,
							 int blockX, int blockY, 
							 float *outputMag, float *outputAng,
							  int imgRows, int imgCols)
{

	/*
		this blockOrigin(X,Y) are w.r.t to the padded image 
		these are the coordinates where blocks (0,0) are placed in padded image
	*/
	
	int blockOriginX = blockIdx.x * blockX  + PADDING_SIZE;
	int blockOriginY = blockIdx.y * blockY  + PADDING_SIZE;
	// printf("blockOriginX:%d blockOriginY:%d\n",blockOriginX,blockOriginY);
	
	/*
		this tileOrigin(X,Y) are w.r.t to the padded image 
		these are the coordinates where tiles (0,0) are placed in padded image	
	*/	

	int tileOriginX = blockOriginX - PADDING_SIZE;
	int tileOriginY = blockOriginY - PADDING_SIZE;
	// printf("tileOriginX:%d tileOriginY:%d\n",tileOriginX,tileOriginY);

	/*	
		these coordinates specify the ends of this tile
		if( tileX is not divisible by 4 ) the last iteration when threads will be reused will exceed tile size
		so less than this tilesize or if ending of image is hit
		
	*/

	int tileEndX = min(tileOriginX + blockX + 2*PADDING_SIZE, paddedX);
	int tileEndY = min(tileOriginY + blockY + 2*PADDING_SIZE, paddedY);
	// printf("tileEndX:%d \n",tileEndX );
	
	// Allocating shared memory for this kernel
	extern __shared__ float imageTile[];

	/*
		the same thread is used to bring as many as 4 global memory to shared memory depending on whether it hits any boundary
	*/	

	for (int m = 0; m < 4; ++m)
	{
		/*		
			((m*blockDim.x)+threadIdx.x)) will give the threadIdx of tile along x direction in mth iteration 
			(tileOriginX +((m*blockDim.x)+threadIdx.x)) will give the global threadIdx along x direction in mth direction
		*/

		if( (tileOriginX +((m*blockDim.x)+threadIdx.x))<tileEndX &&  tileOriginY +threadIdx.y<tileEndY )
		{
				imageTile[((m*blockDim.x)+threadIdx.x)*blockDim.y+threadIdx.y] 
					= image[(tileOriginX +((m*blockDim.x)+threadIdx.x))*paddedY + tileOriginY  +threadIdx.y];		
		}
		// printf("threadIdx.x:%d threadIdx.y:%d \n",(m*blockDim.x)+threadIdx.x, threadIdx.y );

	}

	__syncthreads();

	for (int m = 0; m < 4; ++m)
	{
		if( ((m*blockDim.x)+threadIdx.x)<blockX && threadIdx.y<blockY 
			&& (tileOriginX + ((m*blockDim.x)+threadIdx.x))<imgRows && tileOriginY + threadIdx.y<imgCols)
		{
			double gX = 0, gY = 0, gMag = 0, gAng = 0;				
			for (int k = -PADDING_SIZE; k <= PADDING_SIZE ; ++k)
			{
				// along x direction 
				gX += d_filterKernel[k+PADDING_SIZE] * imageTile[((m*blockDim.x)+threadIdx.x +k +PADDING_SIZE )*blockDim.y + threadIdx.y +PADDING_SIZE];
				gY += d_filterKernel[k+PADDING_SIZE] * imageTile[((m*blockDim.x)+threadIdx.x +PADDING_SIZE )*blockDim.y + k +threadIdx.y +PADDING_SIZE];

			}
			// this 90.1 is to make gAng + else it becomes -0.0000
			gMag = sqrt(gX*gX + gY*gY);
			if( gX==0 )
				gAng = 90;
			else 
				gAng = atan(gY/gX)*180.0/PI + 90.1;
			outputMag[(tileOriginX + ((m*blockDim.x)+threadIdx.x))*(imgCols)+ tileOriginY + threadIdx.y] = gMag;
			outputAng[(tileOriginX + ((m*blockDim.x)+threadIdx.x))*(imgCols)+ tileOriginY + threadIdx.y] = gAng;
			
			// printf("threadIdx.x:%d threadIdx.y:%d \n", (m*blockDim.x)+threadIdx.x, threadIdx.y );

		}
	}

}
// i= 303756 -nan 0

__global__ void max(float *d_outputBMag,float *d_outputBAng,
					float *d_outputGMag,float *d_outputGAng,
					float *d_outputRMag,float *d_outputRAng,
					float *d_outputMag,float  *d_outputAng,
					int imgRows, int  imgCols)
{

	int tidx = blockIdx.x*blockDim.x + threadIdx.x;
	int tidy = blockIdx.y*blockDim.y + threadIdx.y;

	if( tidx<imgRows && tidy<imgCols)
	{
		float maxMag = d_outputBMag[tidx*imgCols + tidy], maxAng = d_outputBAng[tidx*imgCols + tidy];
		
		if( maxMag < d_outputGMag[tidx*imgCols + tidy] )
			maxMag = d_outputGMag[tidx*imgCols + tidy], maxAng = d_outputGAng[tidx*imgCols + tidy];

		if( maxMag < d_outputRMag[tidx*imgCols + tidy] )
			maxMag = d_outputRMag[tidx*imgCols + tidy], maxAng = d_outputRAng[tidx*imgCols + tidy];

		d_outputMag[tidx*imgCols + tidy] = maxMag,d_outputAng[tidx*imgCols + tidy] = maxAng; 
	}


}


__global__ void histogram(float *grad,float *dir, int height, int width,float *output)
{
    // 
    int j = blockIdx.x * blockDim.x + threadIdx.x;
	int i = blockIdx.y * blockDim.y + threadIdx.y;
    
    float magnitude=grad[i*width+j];
    float direction=dir[i*width+j];

    int blockNum=blockIdx.y*gridDim.x+blockIdx.x;

    //initializing the 9-element array for each block.
    if(threadIdx.x==0&&threadIdx.y==0)
    {
	    for(int k=0;k<9;++k)
	    {
	    	output[k+blockNum*9]=0;
	    }
	}
    __syncthreads();
    //waiting for initialization.

    //calculating the histogram values
    int low=(direction/20);
    atomicAdd(&output[blockNum*9+low],magnitude*((low+1)*20 -direction)/20.0);
    atomicAdd(&output[blockNum*9+(low+1)%9],magnitude*((direction-low*20)/20.0));	
}

	.text
	.file	"kernel.hip"
	.globl	_Z26__device_stub__convolutionPfiiiiS_S_ii # -- Begin function _Z26__device_stub__convolutionPfiiiiS_S_ii
	.type	_Z26__device_stub__convolutionPfiiiiS_S_ii,@function
_Z26__device_stub__convolutionPfiiiiS_S_ii: # @_Z26__device_stub__convolutionPfiiiiS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	8(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convolutionPfiiiiS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__convolutionPfiiiiS_S_ii, .Lfunc_end0-_Z26__device_stub__convolutionPfiiiiS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__maxPfS_S_S_S_S_S_S_ii # -- Begin function _Z18__device_stub__maxPfS_S_S_S_S_S_S_ii
	.type	_Z18__device_stub__maxPfS_S_S_S_S_S_S_ii,@function
_Z18__device_stub__maxPfS_S_S_S_S_S_S_ii: # @_Z18__device_stub__maxPfS_S_S_S_S_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3maxPfS_S_S_S_S_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__maxPfS_S_S_S_S_S_S_ii, .Lfunc_end1-_Z18__device_stub__maxPfS_S_S_S_S_S_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__histogramPfS_iiS_ # -- Begin function _Z24__device_stub__histogramPfS_iiS_
	.type	_Z24__device_stub__histogramPfS_iiS_,@function
_Z24__device_stub__histogramPfS_iiS_:   # @_Z24__device_stub__histogramPfS_iiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	movq	%rsp, %rdx
	movl	%ecx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9histogramPfS_iiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z24__device_stub__histogramPfS_iiS_, .Lfunc_end2-_Z24__device_stub__histogramPfS_iiS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convolutionPfiiiiS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3maxPfS_S_S_S_S_S_S_ii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9histogramPfS_iiS_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$d_filterKernel, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$12, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	d_filterKernel,@object          # @d_filterKernel
	.local	d_filterKernel
	.comm	d_filterKernel,12,4
	.type	_Z11convolutionPfiiiiS_S_ii,@object # @_Z11convolutionPfiiiiS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z11convolutionPfiiiiS_S_ii
	.p2align	3, 0x0
_Z11convolutionPfiiiiS_S_ii:
	.quad	_Z26__device_stub__convolutionPfiiiiS_S_ii
	.size	_Z11convolutionPfiiiiS_S_ii, 8

	.type	_Z3maxPfS_S_S_S_S_S_S_ii,@object # @_Z3maxPfS_S_S_S_S_S_S_ii
	.globl	_Z3maxPfS_S_S_S_S_S_S_ii
	.p2align	3, 0x0
_Z3maxPfS_S_S_S_S_S_S_ii:
	.quad	_Z18__device_stub__maxPfS_S_S_S_S_S_S_ii
	.size	_Z3maxPfS_S_S_S_S_S_S_ii, 8

	.type	_Z9histogramPfS_iiS_,@object    # @_Z9histogramPfS_iiS_
	.globl	_Z9histogramPfS_iiS_
	.p2align	3, 0x0
_Z9histogramPfS_iiS_:
	.quad	_Z24__device_stub__histogramPfS_iiS_
	.size	_Z9histogramPfS_iiS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z11convolutionPfiiiiS_S_ii"
	.size	.L__unnamed_1, 28

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z3maxPfS_S_S_S_S_S_S_ii"
	.size	.L__unnamed_2, 25

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9histogramPfS_iiS_"
	.size	.L__unnamed_3, 21

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"d_filterKernel"
	.size	.L__unnamed_4, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__convolutionPfiiiiS_S_ii
	.addrsig_sym _Z18__device_stub__maxPfS_S_S_S_S_S_S_ii
	.addrsig_sym _Z24__device_stub__histogramPfS_iiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym d_filterKernel
	.addrsig_sym _Z11convolutionPfiiiiS_S_ii
	.addrsig_sym _Z3maxPfS_S_S_S_S_S_S_ii
	.addrsig_sym _Z9histogramPfS_iiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11convolutionPfiiiiS_S_ii ; -- Begin function _Z11convolutionPfiiiiS_S_ii
	.globl	_Z11convolutionPfiiiiS_S_ii
	.p2align	8
	.type	_Z11convolutionPfiiiiS_S_ii,@function
_Z11convolutionPfiiiiS_S_ii:            ; @_Z11convolutionPfiiiiS_S_ii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b32 s10, s[0:1], 0x3c
	s_load_b64 s[8:9], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s33, s14, s6
	s_mul_i32 s15, s15, s7
	v_add_nc_u32_e32 v5, s33, v1
	s_add_i32 s3, s7, s15
	v_add_nc_u32_e32 v2, s15, v0
	s_add_i32 s3, s3, 2
	s_add_i32 s2, s6, s33
	s_min_i32 s11, s3, s5
	s_add_i32 s2, s2, 2
	v_mad_u64_u32 v[3:4], null, s5, v5, v[2:3]
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, v1
	v_cmp_le_u32_e32 vcc_lo, s11, v2
	s_min_i32 s4, s2, s4
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_and_b32 s64, s10, 0xffff
	s_mov_b32 s10, 4
	s_mul_i32 s5, s5, s64
	s_xor_b32 s11, vcc_lo, -1
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v6, s33, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v6
	s_and_b32 s13, vcc_lo, s11
	s_and_saveexec_b32 s12, s13
	s_cbranch_execz .LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_lshlrev_b64 v[6:7], 2, v[3:4]
	s_load_b32 s13, s[2:3], 0xc
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s8, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	global_load_b32 v8, v[6:7], off
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s13, s13, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, v5, s13, v[0:1]
	v_lshl_add_u32 v6, v6, 2, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v6, v8
.LBB0_3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v5, s64, v5
	v_add_nc_u32_e32 v3, s5, v3
	s_add_i32 s10, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x28
	s_load_b128 s[8:11], s[0:1], 0x18
	v_cmp_le_u32_e32 vcc_lo, s7, v0
	v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, 1, v1
	v_mov_b32_e32 v11, v1
	s_mov_b32 s12, 0xbd3237f4
	s_mov_b32 s14, 0xb5e68a13
	s_mov_b32 s16, 0x69efb384
	s_mov_b32 s18, 0xaf56de9b
	s_mov_b32 s20, 0xa595c56f
	s_mov_b32 s22, 0xa57d9582
	s_mov_b32 s24, 0x5f08b19f
	s_mov_b32 s26, 0xfc27006a
	s_mov_b32 s28, 0x5711927a
	s_mov_b32 s30, 0xe82d3ff0
	s_mov_b32 s34, 0x6ef28734
	s_mov_b32 s36, 0x6a214619
	s_mov_b32 s38, 0x8427b883
	s_mov_b32 s40, 0x8b207f05
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_u32_e64 s0, s5, v2
	s_mov_b32 s42, 0x57b87036
	s_mov_b32 s44, 0x19378e4f
	s_mov_b32 s46, 0x17e1913c
	s_mov_b32 s48, 0x92376b7d
	s_mov_b32 s50, 0x999952cc
	s_mov_b32 s52, 0x55555523
	s_mov_b32 s54, 0xeeb562d6
	s_mov_b32 s56, 0x336a0500
	s_mov_b32 s58, 0x53c8d4f1
	s_mov_b32 s60, 0x66666666
	s_mov_b32 s13, 0xbf23e260
	s_mov_b32 s15, 0x3eeba404
	s_mov_b32 s17, 0x3f4b2bb0
	s_mov_b32 s19, 0xbf67952d
	s_mov_b32 s21, 0x3f7d6d43
	s_mov_b32 s23, 0xbf8c6ea4
	s_mov_b32 s25, 0x3f967e29
	s_mov_b32 s27, 0xbf9e9ae6
	s_mov_b32 s29, 0x3fa2c15b
	s_mov_b32 s31, 0xbfa59976
	s_mov_b32 s35, 0x3fa82d5d
	s_mov_b32 s37, 0xbfaae5ce
	s_mov_b32 s39, 0x3fae1bb4
	s_mov_b32 s41, 0xbfb110e4
	s_mov_b32 s43, 0x3fb3b136
	s_mov_b32 s45, 0xbfb745d1
	s_mov_b32 s47, 0x3fbc71c7
	s_mov_b32 s49, 0xbfc24924
	s_mov_b32 s51, 0x3fc99999
	s_mov_b32 s53, 0xbfd55555
	s_mov_b32 s55, 0x3ffaf154
	s_mov_b32 s57, 0x3fedd9ad
	s_mov_b32 s59, 0x400921fb
	s_mov_b32 s61, 0x40568666
	s_mov_b32 s1, 0
	s_xor_b32 s7, vcc_lo, -1
	s_barrier
	buffer_gl0_inv
.LBB0_5:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
	v_mad_u64_u32 v[3:4], null, s1, s64, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s6, v3
	s_and_b32 s62, vcc_lo, s7
	s_and_saveexec_b32 s65, s62
	s_cbranch_execz .LBB0_12
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	v_add_nc_u32_e32 v12, s33, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v12
	s_and_b32 s62, s0, vcc_lo
	s_and_b32 exec_lo, exec_lo, s62
	s_cbranch_execz .LBB0_12
; %bb.7:                                ; %.preheader
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_load_b32 s62, s[2:3], 0xc
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s62, s62, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v11, s62
	v_mad_u64_u32 v[5:6], null, v9, s62, v[0:1]
	s_lshl_b32 s66, s62, 2
	s_mov_b64 s[62:63], 0
	v_add_lshl_u32 v6, v0, v7, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v7, v5, 2, 0
	v_add3_u32 v8, 0, 4, v6
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
.LBB0_8:                                ;   Parent Loop BB0_5 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_getpc_b64 s[68:69]
	s_add_u32 s68, s68, d_filterKernel@rel32@lo+4
	s_addc_u32 s69, s69, d_filterKernel@rel32@hi+12
	s_add_u32 s68, s62, s68
	s_addc_u32 s69, s63, s69
	ds_load_b32 v13, v8
	ds_load_b32 v14, v7
	s_load_b32 s67, s[68:69], 0x0
	v_add_nc_u32_e32 v7, 4, v7
	s_add_u32 s62, s62, 4
	s_addc_u32 s63, s63, 0
	s_cmp_eq_u32 s62, 12
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v13, s67, v13 :: v_dual_add_nc_u32 v8, s66, v8
	v_mul_f32_e32 v15, s67, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[13:14], v13
	v_cvt_f64_f32_e32 v[15:16], v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[13:14]
	v_add_f64 v[3:4], v[3:4], v[15:16]
	s_cbranch_scc0 .LBB0_8
; %bb.9:                                ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0x40568000
	s_mov_b32 s62, exec_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_cmpx_neq_f64_e32 0, v[5:6]
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[3:4]
	v_div_scale_f64 v[17:18], vcc_lo, v[3:4], v[5:6], v[3:4]
	v_rcp_f64_e32 v[13:14], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[7:8], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[7:8], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[7:8], v[15:16], v[17:18]
	v_div_fmas_f64 v[7:8], v[7:8], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[7:8], v[7:8], v[5:6], v[3:4]
	v_dual_mov_b32 v13, v7 :: v_dual_and_b32 v14, 0x7fffffff, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[15:16], null, v[13:14], v[13:14], 1.0
	v_div_scale_f64 v[21:22], vcc_lo, 1.0, v[13:14], 1.0
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_mul_f64 v[19:20], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[15:16], v[19:20], v[21:22]
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[19:20]
	v_cmp_gt_f64_e64 vcc_lo, |v[7:8]|, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[15:16], v[15:16], |v[7:8]|, 1.0
	v_dual_cndmask_b32 v14, v14, v16 :: v_dual_cndmask_b32 v13, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[13:14], v[13:14]
	v_fma_f64 v[17:18], v[15:16], s[14:15], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[16:17]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[20:21]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[24:25]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[28:29]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[34:35]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[38:39]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[42:43]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[46:47]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[50:51]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[15:16], v[15:16], v[17:18]
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], s[56:57], s[54:55], -v[13:14]
	v_dual_cndmask_b32 v14, v14, v16 :: v_dual_cndmask_b32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v8, 0x7fffffff, v14, v8
	v_mul_f64 v[7:8], 0x40668000, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[13:14], null, s[58:59], s[58:59], v[7:8]
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[7:8], s[58:59], v[7:8]
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[7:8], v[13:14], s[58:59], v[7:8]
	v_add_f64 v[7:8], v[7:8], s[60:61]
.LBB0_11:                               ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s62
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[3:4], v[3:4], v[3:4]
	v_cvt_f32_f64_e32 v7, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], v[5:6], v[5:6], v[3:4]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[3:4]
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v5, 8, v5
	v_ldexp_f64 v[3:4], v[3:4], v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[5:6], v[3:4]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[13:14], v[3:4], v[5:6]
	v_mul_f64 v[5:6], v[5:6], 0.5
	v_fma_f64 v[15:16], -v[5:6], v[13:14], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[5:6], v[5:6], v[15:16], v[5:6]
	v_fma_f64 v[15:16], -v[13:14], v[13:14], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[15:16], v[5:6], v[13:14]
	v_fma_f64 v[15:16], -v[13:14], v[13:14], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[15:16], v[5:6], v[13:14]
	v_cndmask_b32_e64 v13, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x260
	v_ldexp_f64 v[5:6], v[5:6], v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v3, v5, v3
	v_cvt_f32_f64_e32 v13, v[3:4]
	v_mad_u64_u32 v[3:4], null, v12, s5, v[2:3]
	v_mov_b32_e32 v4, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v5, vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_store_b32 v[5:6], v13, off
	global_store_b32 v[3:4], v7, off
.LBB0_12:                               ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s65
	v_add_nc_u32_e32 v9, s64, v9
	v_add_nc_u32_e32 v11, s64, v11
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 4
	s_cbranch_scc0 .LBB0_5
; %bb.13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convolutionPfiiiiS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 23
		.amdhsa_next_free_sgpr 70
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11convolutionPfiiiiS_S_ii, .Lfunc_end0-_Z11convolutionPfiiiiS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1952
; NumSgprs: 72
; NumVgprs: 23
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 72
; NumVGPRsForWavesPerEU: 23
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z3maxPfS_S_S_S_S_S_S_ii ; -- Begin function _Z3maxPfS_S_S_S_S_S_S_ii
	.globl	_Z3maxPfS_S_S_S_S_S_S_ii
	.p2align	8
	.type	_Z3maxPfS_S_S_S_S_S_S_ii,@function
_Z3maxPfS_S_S_S_S_S_S_ii:               ; @_Z3maxPfS_S_S_S_S_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b64 s[16:17], s[0:1], 0x40
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s16, v0
	v_cmp_gt_i32_e64 s2, s17, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b512 s[0:15], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v0, s17, v[1:2]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	global_load_b32 v4, v[4:5], off
	v_add_co_u32 v2, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
	v_mov_b32_e32 v5, s7
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(1)
	v_cmp_lt_f32_e32 vcc_lo, v6, v4
	v_dual_mov_b32 v3, s6 :: v_dual_cndmask_b32 v4, v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, s2, v3, vcc_lo
	v_cndmask_b32_e32 v5, s3, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e64 s0, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v4, v4, v2, s0
	v_cndmask_b32_e64 v2, v3, s10, s0
	v_cndmask_b32_e64 v3, v5, s11, s0
	v_add_co_u32 v2, vcc_lo, v2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v3, v1, vcc_lo
	global_load_b32 v5, v[2:3], off
	v_add_co_u32 v2, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s14, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v1, vcc_lo
	global_store_b32 v[2:3], v4, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v5, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3maxPfS_S_S_S_S_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z3maxPfS_S_S_S_S_S_S_ii, .Lfunc_end1-_Z3maxPfS_S_S_S_S_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 20
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z9histogramPfS_iiS_    ; -- Begin function _Z9histogramPfS_iiS_
	.globl	_Z9histogramPfS_iiS_
	.p2align	8
	.type	_Z9histogramPfS_iiS_,@function
_Z9histogramPfS_iiS_:                   ; @_Z9histogramPfS_iiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x14
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
	s_load_b128 s[4:7], s[0:1], 0x0
	s_mul_i32 s2, s14, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s3
	v_add3_u32 v2, s2, v0, v2
	v_or_b32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_mov_b32 s6, exec_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[2:3], off
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x20
	s_load_b64 s[0:1], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s2, s14
	s_mul_i32 s2, s2, 9
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.preheader.preheader
	s_ashr_i32 s3, s2, 31
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[4:5], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s3, s0, s4
	s_addc_u32 s7, s1, s5
	s_mov_b64 s[4:5], 0
.LBB2_2:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s3, s4
	s_addc_u32 s9, s7, s5
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_lg_u32 s4, 36
	global_store_b32 v0, v0, s[8:9]
	s_cbranch_scc1 .LBB2_2
.LBB2_3:                                ; %Flow48
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v0, null, 0x41a00000, 0x41a00000, v5
	v_div_scale_f32 v3, vcc_lo, v5, 0x41a00000, v5
	s_waitcnt_vscnt null, 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v1, v0
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s3, 0
	v_fma_f32 v2, -v0, v1, 1.0
	v_fmac_f32_e32 v1, v2, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v3, v1
	v_fma_f32 v6, -v0, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v6, v1
	v_fma_f32 v0, -v0, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v0, v0, v1, v2
	v_div_fixup_f32 v0, v0, 0x41a00000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v6, v0
	v_add_nc_u32_e32 v7, 1, v6
	v_add_nc_u32_e32 v0, s2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v7, 20
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_cvt_f32_i32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v5
	global_load_b32 v3, v[0:1], off
	v_mul_f32_e32 v2, v4, v2
	v_div_scale_f32 v8, null, 0x41a00000, 0x41a00000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v9, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v8, v9, 1.0
	v_fmac_f32_e32 v9, v10, v9
	v_div_scale_f32 v10, vcc_lo, v2, 0x41a00000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v10, v9
	v_fma_f32 v12, -v8, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v11, v12, v9
	v_fma_f32 v8, -v8, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v9, v11
	v_div_fixup_f32 v8, v8, 0x41a00000, v2
.LBB2_4:                                ; %atomicrmw.start
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v8
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_4
; %bb.5:                                ; %atomicrmw.end
	s_or_b32 exec_lo, exec_lo, s3
	v_mul_lo_u32 v0, v6, 20
	v_mul_hi_i32 v10, 0x38e38e39, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v0, v0
	v_lshrrev_b32_e32 v11, 31, v10
	v_ashrrev_i32_e32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v0, v5, v0
	v_add_nc_u32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[5:6], v0
	v_lshl_add_u32 v10, v10, 3, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v7, v7, v10
	v_div_scale_f64 v[8:9], null, 0x40340000, 0x40340000, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[0:1], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[2:3], -v[8:9], v[0:1], 1.0
	v_fma_f64 v[10:11], v[0:1], v[2:3], v[0:1]
	v_add_nc_u32_e32 v0, s2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, 0
	global_load_b32 v3, v[0:1], off
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_div_scale_f64 v[12:13], vcc_lo, v[5:6], 0x40340000, v[5:6]
	v_mul_f64 v[14:15], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[8:9], v[14:15], v[12:13]
	v_div_fmas_f64 v[7:8], v[7:8], v[10:11], v[14:15]
	v_cvt_f64_f32_e32 v[9:10], v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[7:8], 0x40340000, v[5:6]
	v_mul_f64 v[4:5], v[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_f32_f64_e32 v4, v[4:5]
.LBB2_6:                                ; %atomicrmw.start31
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v2, v3, v4
	global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v2, v3
	v_mov_b32_e32 v3, v2
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB2_6
; %bb.7:                                ; %atomicrmw.end30
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9histogramPfS_iiS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9histogramPfS_iiS_, .Lfunc_end2-_Z9histogramPfS_iiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 952
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	d_filterKernel          ; @d_filterKernel
	.type	d_filterKernel,@object
	.data
	.globl	d_filterKernel
	.p2align	2, 0x0
d_filterKernel:
	.long	0xbf800000                      ; float -1
	.long	0x00000000                      ; float 0
	.long	0x3f800000                      ; float 1
	.size	d_filterKernel, 12

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym d_filterKernel
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         168
        .size:           4
        .value_kind:     hidden_dynamic_lds_size
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11convolutionPfiiiiS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     72
    .sgpr_spill_count: 0
    .symbol:         _Z11convolutionPfiiiiS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     23
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3maxPfS_S_S_S_S_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         _Z3maxPfS_S_S_S_S_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9histogramPfS_iiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9histogramPfS_iiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
