// Uses multiple kernel calls keeping each node as source so that label of v won't get updated before it's block starts executing. 
// As might lead to the another iteration in the search and later v's potential might again get changed 
// by some other u giving inconsistent potential values(paths).

#include <math.h>
#include <limits.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stdbool.h>
#define ll long long int

// hashing used to update all of the attributes of a node at the same time
// This is to avoid race conditions as multiple u's could try to label a particular neighbour
// Using a mutex lock instead would severely affect performance as threads would be in busy wait
__host__ __device__ ll hash(int potential, int parent, int labelled, int scanned, int direction)
{
    // potential can take any integer values
    ll hash_value = potential;
    // parent can only be in [0, 1024)
    hash_value <<= 10; 
    hash_value += parent;
    // Rest are boolean values
    // false is 0 and true is 1
    hash_value <<= 1;
    hash_value += labelled; 
    hash_value <<= 1; 
    hash_value += scanned;
    hash_value <<= 1;
    // '-' is 0 and '+' is 1
    hash_value += direction;

    return hash_value;
}


// The following functions return the corresponding field 
// in the hashed value using bitwise operations.
__host__ __device__ int potential(ll hash_value)
{
    return hash_value>>13;
}

__host__ __device__ int parent(ll hash_value)
{
    return (hash_value>>3)&(((1<<10)-1));
}

__host__ __device__ int labelled(ll hash_value)
{
    return (hash_value>>2)&1;
}

__host__ __device__ int scanned(ll hash_value)
{
    return (hash_value>>1)&1;
}

__host__ __device__ int direction(ll hash_value)
{
    return (hash_value)&1;
}

// Note: Using the same u potential multiple nodes can be assigned potentials, but eventually no more than one of them will be in the path.
// There is frequent context switch between cpu and gpu, try improving that by moving the loop inside kernel -- dynamic parallelism performed.

// Kernel tries to expand the frontier by one step ... frontier is the collection of nodes who had just been labelled in the previous iteration.
__global__ void parallel_traverse(int u, int *d_flow, int *d_capacity, ll *d_label, int *d_flag, int n)
{
    int v = threadIdx.x;
    // printf("u: %d, v: %d, d_label[u]: %lld\n", u, v, d_label[u]);
    if(labelled(d_label[u]) == 1 && scanned(d_label[u]) == 0)
    {
        if(labelled(d_label[v]) == 0)
        {
            // v can be reached via forward edge
            if(d_flow[u*n+v] < d_capacity[u*n+v])
            {
                int v_potential = min(potential(d_label[u]), d_capacity[u*n+v]-d_flow[u*n+v]);
                // labels[v] = {true, false, u, '+', v_potential};
                d_label[v] = hash(v_potential, u, 1, 0, 1);
                *d_flag += 1;
            }

            // v can be reached by reducing the flow (backward edge)
            if(d_flow[v*n+u] > 0)
            {
                int v_potential = min(potential(d_label[u]), d_flow[v*n+u]);
                // labels[v] = {true, false, u, '-', v_potential};
                d_label[v] = hash(v_potential, u, 1, 0, 0); 
                *d_flag += 1;                   
            }
        }
        
        // Note __syncthreads() can be used only with the current kernel configuration as can only be performed on a single block
        __syncthreads();
        // scanned[u] = true;
        d_label[u] |= 1<<1;
        // printf("%d\n", scanned(d_label[u]));
    }
}

int fordFulkerson(int *capacity, int n, int s, int t)
{
    // flag variable is to show if any update is happening in an iteration
    int *flag = (int *)malloc(sizeof(int));
    int *flow = (int *)malloc(n*n*sizeof(int));
    memset(flow, 0, n*n*sizeof(int)); 
    // Memory allocated only once
    ll *label = (ll *)malloc(n*sizeof(ll));
    memset(label, 0, n*sizeof(ll)); 

    int *d_capacity;
    cudaMalloc(&d_capacity, n*n*sizeof(int));
    int *d_flag;
    cudaMalloc(&d_flag, sizeof(int));
    int *d_flow;
    cudaMalloc(&d_flow, n*n*sizeof(int));
    ll *d_label;
    cudaMalloc(&d_label, n*sizeof(ll));

    cudaMemcpy(d_capacity, capacity, n*n*sizeof(int), cudaMemcpyHostToDevice);

    while(true)
    {
        memset(label, 0, n*sizeof(ll)); 

        // labelled[s] = true;
        // direction[s] = '+';
        // potential[s] = INT_MAX;
        label[s] = hash(INT_MAX, s, 1, 0, 0);
        // printf("label[s]: %lld\n", label[s]);
        cudaMemcpy(d_flow, flow, n*n*sizeof(int), cudaMemcpyHostToDevice);
        cudaMemcpy(d_label, label, n*sizeof(ll), cudaMemcpyHostToDevice);

        // while sink is not yet labelled
        while(labelled(label[t]) == 0)
        {
            *flag = 0;
            cudaMemcpy(d_flag, flag, sizeof(int), cudaMemcpyHostToDevice);
            for(int i=0;i<n;++i)
            {
                parallel_traverse<<<1, n>>>(i, d_flow, d_capacity, d_label, d_flag, n);
            }
            cudaMemcpy(label, d_label, n*sizeof(ll), cudaMemcpyDeviceToHost);
            cudaMemcpy(flag, d_flag, sizeof(int), cudaMemcpyDeviceToHost);

            // printf("flag: %d\n", *flag);
            if(*flag == 0)
            {
                break;
            }
        }

        // Below line is not needed as it doesn't change in device
        // cudaMemcpy(flow, d_flow, sizeof(flow), cudaMemcpyDeviceToHost);

        if(*flag == 0)
        {
            // No more augmenting paths can be found
            int net_flow = 0;
            for(int i=0;i<n;++i)
            {
                net_flow += flow[s*n+i];
            }
            // Returning sum of flows originating from source
            return net_flow;
        }

        // Potential of sink is the bottleneck flow through the augmenting path
        int x = t, y, t_potential = potential(label[t]);
        // printf("%d\n", t_potential);
        while(x != s)
        {
            // printf("%d ", x);
            // Getting bits from 3 to 13 - y = parent[x]
            y = parent(label[x]); 

            // Updating all flow values on the path depending on the direction of the link
            // if(labels[x].direction == '+')
            if(direction(label[x]) == 1)
            {
                flow[y*n+x] += t_potential;
            }
            else
            {
                flow[x*n+y] -= t_potential;
            }

            x = y;
        }
        // printf("%d\n", t_potential);
    }
}

int main()
{
    int n, m;
    scanf("%d %d", &n, &m);

    // 1-D arrays to pass the same to the kernel
    int *capacity = (int *)malloc(n*n*sizeof(int));
    memset(capacity, 0, n*n*sizeof(int)); 

    int u, v, w;
    for(int i=0;i<m;++i)
    {
        scanf("%d %d %d", &u, &v, &w);
        capacity[u*n+v] = w; 
    }

    printf("%d\n", fordFulkerson(capacity, n, 0, n-1));
}

	.file	"tmpxft_00255340_00000000-6_parallel_code_v1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2037:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4hashiiiii
	.type	_Z4hashiiiii, @function
_Z4hashiiiii:
.LFB2027:
	.cfi_startproc
	endbr64
	movslq	%edi, %rdi
	movslq	%esi, %rsi
	movslq	%edx, %rdx
	movslq	%ecx, %rcx
	salq	$10, %rdi
	movslq	%r8d, %rax
	addq	%rdi, %rsi
	addq	%rsi, %rsi
	addq	%rsi, %rdx
	addq	%rdx, %rdx
	addq	%rdx, %rcx
	addq	%rcx, %rcx
	addq	%rcx, %rax
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z4hashiiiii, .-_Z4hashiiiii
	.globl	_Z9potentialx
	.type	_Z9potentialx, @function
_Z9potentialx:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	sarq	$13, %rax
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z9potentialx, .-_Z9potentialx
	.globl	_Z6parentx
	.type	_Z6parentx, @function
_Z6parentx:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	sarq	$3, %rax
	andl	$1023, %eax
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z6parentx, .-_Z6parentx
	.globl	_Z8labelledx
	.type	_Z8labelledx, @function
_Z8labelledx:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	sarq	$2, %rax
	andl	$1, %eax
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z8labelledx, .-_Z8labelledx
	.globl	_Z7scannedx
	.type	_Z7scannedx, @function
_Z7scannedx:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	sarq	%rax
	andl	$1, %eax
	ret
	.cfi_endproc
.LFE2031:
	.size	_Z7scannedx, .-_Z7scannedx
	.globl	_Z9directionx
	.type	_Z9directionx, @function
_Z9directionx:
.LFB2032:
	.cfi_startproc
	endbr64
	movl	%edi, %eax
	andl	$1, %eax
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z9directionx, .-_Z9directionx
	.globl	_Z45__device_stub__Z17parallel_traverseiPiS_PxS_iiPiS_PxS_i
	.type	_Z45__device_stub__Z17parallel_traverseiPiS_PxS_iiPiS_PxS_i, @function
_Z45__device_stub__Z17parallel_traverseiPiS_PxS_iiPiS_PxS_i:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z17parallel_traverseiPiS_PxS_i(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z45__device_stub__Z17parallel_traverseiPiS_PxS_iiPiS_PxS_i, .-_Z45__device_stub__Z17parallel_traverseiPiS_PxS_iiPiS_PxS_i
	.globl	_Z17parallel_traverseiPiS_PxS_i
	.type	_Z17parallel_traverseiPiS_PxS_i, @function
_Z17parallel_traverseiPiS_PxS_i:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z17parallel_traverseiPiS_PxS_iiPiS_PxS_i
	.cfi_endproc
.LFE2060:
	.size	_Z17parallel_traverseiPiS_PxS_i, .-_Z17parallel_traverseiPiS_PxS_i
	.globl	_Z13fordFulkersonPiiii
	.type	_Z13fordFulkersonPiiii, @function
_Z13fordFulkersonPiiii:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdi, %r15
	movl	$4, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%edx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movl	%ecx, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movq	%rax, %r14
	movl	%ebx, %eax
	imull	%ebx, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	movq	8(%rsp), %rcx
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, %rbp
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	movslq	%ebx, %rax
	salq	$3, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	movq	(%rsp), %rcx
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, %r12
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	movq	8(%rsp), %rsi
	leaq	48(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	64(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdx
	movq	48(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movslq	%r13d, %rax
	leaq	(%r12,%rax,8), %rdx
	movq	%rdx, 24(%rsp)
	movl	$2147483647, %edx
	salq	$10, %rdx
	addq	%rdx, %rax
	leaq	4(,%rax,8), %rax
	movq	%rax, 40(%rsp)
	movslq	20(%rsp), %rax
	leaq	(%r12,%rax,8), %rax
	movq	%rax, 32(%rsp)
.L29:
	movq	(%rsp), %rcx
	xorl	%esi, %esi
	movq	%r12, %rdi
	movq	%rcx, %rdx
	call	__memset_chk@PLT
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rax
	movl	$1, %ecx
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rdi
	movq	%rsi, (%rax)
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movq	72(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
.L15:
	movq	32(%rsp), %rax
	movq	(%rax), %rdx
	testb	$4, %dl
	jne	.L35
	xorl	%eax, %eax
	movq	56(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rsi
	movl	%eax, (%r14)
	movl	$4, %edx
	xorl	%r15d, %r15d
	call	cudaMemcpy@PLT
.L16:
	cmpl	%ebx, %r15d
	jge	.L36
	movl	%ebx, 92(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movl	100(%rsp), %ecx
	movq	%rax, %rdi
	movq	92(%rsp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L17
	movq	56(%rsp), %r8
	movq	72(%rsp), %rcx
	movl	%ebx, %r9d
	movl	%r15d, %edi
	movq	48(%rsp), %rdx
	movq	64(%rsp), %rsi
	call	_Z45__device_stub__Z17parallel_traverseiPiS_PxS_iiPiS_PxS_i
.L17:
	incl	%r15d
	jmp	.L16
.L36:
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rsi
	movl	$2, %ecx
	movq	%r14, %rdi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	cmpl	$0, (%r14)
	jne	.L15
	jmp	.L19
.L35:
	cmpl	$0, (%r14)
	jne	.L31
.L19:
	imull	%ebx, %r13d
	xorl	%eax, %eax
	xorl	%edx, %edx
	movslq	%r13d, %r13
	leaq	0(%rbp,%r13,4), %rcx
.L23:
	cmpl	%eax, %ebx
	jle	.L37
	addl	(%rcx,%rax,4), %edx
	incq	%rax
	jmp	.L23
.L31:
	movl	20(%rsp), %eax
	sarq	$13, %rdx
.L25:
	cmpl	%r13d, %eax
	je	.L29
	movslq	%eax, %rcx
	movq	(%r12,%rcx,8), %rcx
	movq	%rcx, %rsi
	sarq	$3, %rsi
	andl	$1023, %esi
	andb	$1, %cl
	je	.L26
	movl	%ebx, %ecx
	imull	%esi, %ecx
	addl	%ecx, %eax
	cltq
	addl	%edx, 0(%rbp,%rax,4)
	jmp	.L27
.L26:
	imull	%ebx, %eax
	addl	%esi, %eax
	cltq
	subl	%edx, 0(%rbp,%rax,4)
.L27:
	movl	%esi, %eax
	jmp	.L25
.L37:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	movl	%edx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z13fordFulkersonPiiii, .-_Z13fordFulkersonPiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d %d"
.LC1:
	.string	"%d %d %d"
.LC2:
	.string	"%d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC0(%rip), %rdi
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdx
	leaq	4(%rsp), %rsi
	call	__isoc23_scanf@PLT
	movl	4(%rsp), %ebx
	imull	%ebx, %ebx
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movq	%rbx, %rcx
	movq	%rbx, %rdx
	xorl	%esi, %esi
	movq	%rax, %rdi
	movq	%rax, %rbp
	leaq	.LC1(%rip), %rbx
	call	__memset_chk@PLT
.L39:
	cmpl	%r12d, 8(%rsp)
	jle	.L43
	leaq	16(%rsp), %rdx
	leaq	20(%rsp), %rcx
	movq	%rbx, %rdi
	xorl	%eax, %eax
	leaq	12(%rsp), %rsi
	incl	%r12d
	call	__isoc23_scanf@PLT
	movl	12(%rsp), %eax
	movl	20(%rsp), %edx
	imull	4(%rsp), %eax
	addl	16(%rsp), %eax
	cltq
	movl	%edx, 0(%rbp,%rax,4)
	jmp	.L39
.L43:
	movl	4(%rsp), %esi
	xorl	%edx, %edx
	movq	%rbp, %rdi
	leal	-1(%rsi), %ecx
	call	_Z13fordFulkersonPiiii
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	movl	%eax, %edx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z17parallel_traverseiPiS_PxS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17parallel_traverseiPiS_PxS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Uses multiple kernel calls keeping each node as source so that label of v won't get updated before it's block starts executing. 
// As might lead to the another iteration in the search and later v's potential might again get changed 
// by some other u giving inconsistent potential values(paths).


#include <hip/hip_runtime.h>
#include <math.h>
#include <limits.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stdbool.h>
#define ll long long int

// hashing used to update all of the attributes of a node at the same time
// This is to avoid race conditions as multiple u's could try to label a particular neighbour
// Using a mutex lock instead would severely affect performance as threads would be in busy wait
__host__ __device__ ll hash(int potential, int parent, int labelled, int scanned, int direction)
{
    // potential can take any integer values
    ll hash_value = potential;
    // parent can only be in [0, 1024)
    hash_value <<= 10; 
    hash_value += parent;
    // Rest are boolean values
    // false is 0 and true is 1
    hash_value <<= 1;
    hash_value += labelled; 
    hash_value <<= 1; 
    hash_value += scanned;
    hash_value <<= 1;
    // '-' is 0 and '+' is 1
    hash_value += direction;

    return hash_value;
}


// The following functions return the corresponding field 
// in the hashed value using bitwise operations.
__host__ __device__ int potential(ll hash_value)
{
    return hash_value>>13;
}

__host__ __device__ int parent(ll hash_value)
{
    return (hash_value>>3)&(((1<<10)-1));
}

__host__ __device__ int labelled(ll hash_value)
{
    return (hash_value>>2)&1;
}

__host__ __device__ int scanned(ll hash_value)
{
    return (hash_value>>1)&1;
}

__host__ __device__ int direction(ll hash_value)
{
    return (hash_value)&1;
}

// Note: Using the same u potential multiple nodes can be assigned potentials, but eventually no more than one of them will be in the path.
// There is frequent context switch between cpu and gpu, try improving that by moving the loop inside kernel -- dynamic parallelism performed.

// Kernel tries to expand the frontier by one step ... frontier is the collection of nodes who had just been labelled in the previous iteration.
__global__ void parallel_traverse(int u, int *d_flow, int *d_capacity, ll *d_label, int *d_flag, int n)
{
    int v = threadIdx.x;
    // printf("u: %d, v: %d, d_label[u]: %lld\n", u, v, d_label[u]);
    if(labelled(d_label[u]) == 1 && scanned(d_label[u]) == 0)
    {
        if(labelled(d_label[v]) == 0)
        {
            // v can be reached via forward edge
            if(d_flow[u*n+v] < d_capacity[u*n+v])
            {
                int v_potential = min(potential(d_label[u]), d_capacity[u*n+v]-d_flow[u*n+v]);
                // labels[v] = {true, false, u, '+', v_potential};
                d_label[v] = hash(v_potential, u, 1, 0, 1);
                *d_flag += 1;
            }

            // v can be reached by reducing the flow (backward edge)
            if(d_flow[v*n+u] > 0)
            {
                int v_potential = min(potential(d_label[u]), d_flow[v*n+u]);
                // labels[v] = {true, false, u, '-', v_potential};
                d_label[v] = hash(v_potential, u, 1, 0, 0); 
                *d_flag += 1;                   
            }
        }
        
        // Note __syncthreads() can be used only with the current kernel configuration as can only be performed on a single block
        __syncthreads();
        // scanned[u] = true;
        d_label[u] |= 1<<1;
        // printf("%d\n", scanned(d_label[u]));
    }
}

int fordFulkerson(int *capacity, int n, int s, int t)
{
    // flag variable is to show if any update is happening in an iteration
    int *flag = (int *)malloc(sizeof(int));
    int *flow = (int *)malloc(n*n*sizeof(int));
    memset(flow, 0, n*n*sizeof(int)); 
    // Memory allocated only once
    ll *label = (ll *)malloc(n*sizeof(ll));
    memset(label, 0, n*sizeof(ll)); 

    int *d_capacity;
    hipMalloc(&d_capacity, n*n*sizeof(int));
    int *d_flag;
    hipMalloc(&d_flag, sizeof(int));
    int *d_flow;
    hipMalloc(&d_flow, n*n*sizeof(int));
    ll *d_label;
    hipMalloc(&d_label, n*sizeof(ll));

    hipMemcpy(d_capacity, capacity, n*n*sizeof(int), hipMemcpyHostToDevice);

    while(true)
    {
        memset(label, 0, n*sizeof(ll)); 

        // labelled[s] = true;
        // direction[s] = '+';
        // potential[s] = INT_MAX;
        label[s] = hash(INT_MAX, s, 1, 0, 0);
        // printf("label[s]: %lld\n", label[s]);
        hipMemcpy(d_flow, flow, n*n*sizeof(int), hipMemcpyHostToDevice);
        hipMemcpy(d_label, label, n*sizeof(ll), hipMemcpyHostToDevice);

        // while sink is not yet labelled
        while(labelled(label[t]) == 0)
        {
            *flag = 0;
            hipMemcpy(d_flag, flag, sizeof(int), hipMemcpyHostToDevice);
            for(int i=0;i<n;++i)
            {
                parallel_traverse<<<1, n>>>(i, d_flow, d_capacity, d_label, d_flag, n);
            }
            hipMemcpy(label, d_label, n*sizeof(ll), hipMemcpyDeviceToHost);
            hipMemcpy(flag, d_flag, sizeof(int), hipMemcpyDeviceToHost);

            // printf("flag: %d\n", *flag);
            if(*flag == 0)
            {
                break;
            }
        }

        // Below line is not needed as it doesn't change in device
        // cudaMemcpy(flow, d_flow, sizeof(flow), cudaMemcpyDeviceToHost);

        if(*flag == 0)
        {
            // No more augmenting paths can be found
            int net_flow = 0;
            for(int i=0;i<n;++i)
            {
                net_flow += flow[s*n+i];
            }
            // Returning sum of flows originating from source
            return net_flow;
        }

        // Potential of sink is the bottleneck flow through the augmenting path
        int x = t, y, t_potential = potential(label[t]);
        // printf("%d\n", t_potential);
        while(x != s)
        {
            // printf("%d ", x);
            // Getting bits from 3 to 13 - y = parent[x]
            y = parent(label[x]); 

            // Updating all flow values on the path depending on the direction of the link
            // if(labels[x].direction == '+')
            if(direction(label[x]) == 1)
            {
                flow[y*n+x] += t_potential;
            }
            else
            {
                flow[x*n+y] -= t_potential;
            }

            x = y;
        }
        // printf("%d\n", t_potential);
    }
}

int main()
{
    int n, m;
    scanf("%d %d", &n, &m);

    // 1-D arrays to pass the same to the kernel
    int *capacity = (int *)malloc(n*n*sizeof(int));
    memset(capacity, 0, n*n*sizeof(int)); 

    int u, v, w;
    for(int i=0;i<m;++i)
    {
        scanf("%d %d %d", &u, &v, &w);
        capacity[u*n+v] = w; 
    }

    printf("%d\n", fordFulkerson(capacity, n, 0, n-1));
}

	.text
	.file	"parallel_code_v1.hip"
	.globl	_Z4hashiiiii                    # -- Begin function _Z4hashiiiii
	.type	_Z4hashiiiii,@function
_Z4hashiiiii:                           # @_Z4hashiiiii
	.cfi_startproc
# %bb.0:
	movslq	%edi, %rax
	movslq	%esi, %rsi
	shlq	$11, %rax
	leaq	(%rax,%rsi,2), %rax
	movslq	%edx, %rdx
	addq	%rax, %rdx
	movslq	%ecx, %rax
	movslq	%r8d, %rcx
	leaq	(%rcx,%rax,2), %rax
	leaq	(%rax,%rdx,4), %rax
	retq
.Lfunc_end0:
	.size	_Z4hashiiiii, .Lfunc_end0-_Z4hashiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z9potentialx                   # -- Begin function _Z9potentialx
	.type	_Z9potentialx,@function
_Z9potentialx:                          # @_Z9potentialx
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	shrq	$13, %rax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end1:
	.size	_Z9potentialx, .Lfunc_end1-_Z9potentialx
	.cfi_endproc
                                        # -- End function
	.globl	_Z6parentx                      # -- Begin function _Z6parentx
	.type	_Z6parentx,@function
_Z6parentx:                             # @_Z6parentx
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	shrl	$3, %eax
	andl	$1023, %eax                     # imm = 0x3FF
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end2:
	.size	_Z6parentx, .Lfunc_end2-_Z6parentx
	.cfi_endproc
                                        # -- End function
	.globl	_Z8labelledx                    # -- Begin function _Z8labelledx
	.type	_Z8labelledx,@function
_Z8labelledx:                           # @_Z8labelledx
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	shrl	$2, %eax
	andl	$1, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end3:
	.size	_Z8labelledx, .Lfunc_end3-_Z8labelledx
	.cfi_endproc
                                        # -- End function
	.globl	_Z7scannedx                     # -- Begin function _Z7scannedx
	.type	_Z7scannedx,@function
_Z7scannedx:                            # @_Z7scannedx
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	shrl	%eax
	andl	$1, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end4:
	.size	_Z7scannedx, .Lfunc_end4-_Z7scannedx
	.cfi_endproc
                                        # -- End function
	.globl	_Z9directionx                   # -- Begin function _Z9directionx
	.type	_Z9directionx,@function
_Z9directionx:                          # @_Z9directionx
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	andl	$1, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end5:
	.size	_Z9directionx, .Lfunc_end5-_Z9directionx
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__parallel_traverseiPiS_PxS_i # -- Begin function _Z32__device_stub__parallel_traverseiPiS_PxS_i
	.type	_Z32__device_stub__parallel_traverseiPiS_PxS_i,@function
_Z32__device_stub__parallel_traverseiPiS_PxS_i: # @_Z32__device_stub__parallel_traverseiPiS_PxS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17parallel_traverseiPiS_PxS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z32__device_stub__parallel_traverseiPiS_PxS_i, .Lfunc_end6-_Z32__device_stub__parallel_traverseiPiS_PxS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z13fordFulkersonPiiii          # -- Begin function _Z13fordFulkersonPiiii
	.type	_Z13fordFulkersonPiiii,@function
_Z13fordFulkersonPiiii:                 # @_Z13fordFulkersonPiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	movl	%edx, 8(%rsp)                   # 4-byte Spill
	movl	%esi, %ebp
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	$4, %edi
	callq	malloc
	movq	%rax, %r12
	movl	%ebp, %r13d
	imull	%r13d, %r13d
	shlq	$2, %r13
	movl	$1, %edi
	movq	%r13, %rsi
	callq	calloc@PLT
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movslq	%ebp, %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leaq	(,%rax,8), %r14
	movl	$1, %edi
	movq	%r14, %rsi
	callq	calloc@PLT
	movq	%rax, %rbx
	leaq	72(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	48(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	leaq	64(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%r14, 56(%rsp)                  # 8-byte Spill
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	72(%rsp), %rax
	movq	(%rax), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, 96(%rsp)                  # 8-byte Spill
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movslq	8(%rsp), %rcx                   # 4-byte Folded Reload
	movabsq	$17592186036228, %rax           # imm = 0xFFFFFFFE004
	movq	%rcx, 88(%rsp)                  # 8-byte Spill
	leaq	(%rax,%rcx,8), %rax
	movq	%rax, 80(%rsp)                  # 8-byte Spill
	movslq	12(%rsp), %rax                  # 4-byte Folded Reload
	movq	%rax, 24(%rsp)                  # 8-byte Spill
	movl	32(%rsp), %r14d                 # 4-byte Reload
	movq	%r14, 32(%rsp)                  # 8-byte Spill
	btsq	$32, %r14
	incq	%r15
.LBB7_1:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB7_2 Depth 2
                                        #       Child Loop BB7_5 Depth 3
                                        #     Child Loop BB7_17 Depth 2
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movq	56(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rdx
	callq	memset@PLT
	movq	88(%rsp), %rax                  # 8-byte Reload
	movq	80(%rsp), %rcx                  # 8-byte Reload
	movq	%rcx, (%rbx,%rax,8)
	movq	64(%rsp), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	96(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
.LBB7_2:                                #   Parent Loop BB7_1 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB7_5 Depth 3
	movq	24(%rsp), %rax                  # 8-byte Reload
	testb	$4, (%rbx,%rax,8)
	jne	.LBB7_9
# %bb.3:                                #   in Loop: Header=BB7_2 Depth=2
	movl	$0, (%r12)
	movq	48(%rsp), %rdi
	movl	$4, %edx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%ebp, %ebp
	jle	.LBB7_8
# %bb.4:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB7_2 Depth=2
	xorl	%r13d, %r13d
.LBB7_5:                                # %.lr.ph
                                        #   Parent Loop BB7_1 Depth=1
                                        #     Parent Loop BB7_2 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_7
# %bb.6:                                #   in Loop: Header=BB7_5 Depth=3
	movq	64(%rsp), %rsi
	movq	72(%rsp), %rdx
	movq	40(%rsp), %rcx
	movq	48(%rsp), %r8
	movl	%r13d, %edi
	movl	%ebp, %r9d
	callq	_Z32__device_stub__parallel_traverseiPiS_PxS_i
.LBB7_7:                                #   in Loop: Header=BB7_5 Depth=3
	incl	%r13d
	cmpl	%r13d, %ebp
	jne	.LBB7_5
.LBB7_8:                                # %._crit_edge
                                        #   in Loop: Header=BB7_2 Depth=2
	movq	40(%rsp), %rsi
	movq	%rbx, %rdi
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	48(%rsp), %rsi
	movl	$4, %edx
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, (%r12)
	jne	.LBB7_2
	jmp	.LBB7_10
.LBB7_9:                                # %.loopexit80
                                        #   in Loop: Header=BB7_1 Depth=1
	cmpl	$0, (%r12)
	je	.LBB7_10
# %bb.15:                               #   in Loop: Header=BB7_1 Depth=1
	movl	12(%rsp), %eax                  # 4-byte Reload
	cmpl	8(%rsp), %eax                   # 4-byte Folded Reload
	je	.LBB7_1
# %bb.16:                               # %.lr.ph88.preheader
                                        #   in Loop: Header=BB7_1 Depth=1
	movq	24(%rsp), %rax                  # 8-byte Reload
	movq	(%rbx,%rax,8), %rax
	shrq	$13, %rax
	movl	12(%rsp), %edx                  # 4-byte Reload
.LBB7_17:                               # %.lr.ph88
                                        #   Parent Loop BB7_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movslq	%edx, %rcx
	movl	(%rbx,%rcx,8), %esi
	movl	%esi, %ecx
	shrl	$3, %ecx
	andl	$1023, %ecx                     # imm = 0x3FF
	testb	$1, %sil
	jne	.LBB7_18
# %bb.19:                               #   in Loop: Header=BB7_17 Depth=2
	imull	%ebp, %edx
	addl	%ecx, %edx
	movslq	%edx, %rdx
	movq	16(%rsp), %rsi                  # 8-byte Reload
	subl	%eax, (%rsi,%rdx,4)
	jmp	.LBB7_20
.LBB7_18:                               #   in Loop: Header=BB7_17 Depth=2
	movl	%ecx, %esi
	imull	%ebp, %esi
	addl	%edx, %esi
	movslq	%esi, %rdx
	movq	16(%rsp), %rsi                  # 8-byte Reload
	addl	%eax, (%rsi,%rdx,4)
.LBB7_20:                               #   in Loop: Header=BB7_17 Depth=2
	movl	%ecx, %edx
	cmpl	8(%rsp), %ecx                   # 4-byte Folded Reload
	jne	.LBB7_17
	jmp	.LBB7_1
.LBB7_10:                               # %.preheader
	testl	%ebp, %ebp
	jle	.LBB7_11
# %bb.13:                               # %.lr.ph91
	movl	8(%rsp), %eax                   # 4-byte Reload
	imull	%ebp, %eax
	cltq
	movq	16(%rsp), %rcx                  # 8-byte Reload
	leaq	(%rcx,%rax,4), %rcx
	xorl	%edx, %edx
	xorl	%eax, %eax
	movq	32(%rsp), %rsi                  # 8-byte Reload
.LBB7_14:                               # =>This Inner Loop Header: Depth=1
	addl	(%rcx,%rdx,4), %eax
	incq	%rdx
	cmpq	%rdx, %rsi
	jne	.LBB7_14
	jmp	.LBB7_12
.LBB7_11:
	xorl	%eax, %eax
.LBB7_12:                               # %._crit_edge92
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z13fordFulkersonPiiii, .Lfunc_end7-_Z13fordFulkersonPiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	20(%rsp), %rbx
	leaq	16(%rsp), %r15
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%r15, %rdx
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%rbx), %r14d
	movl	%r14d, %esi
	imull	%esi, %esi
	shlq	$2, %rsi
	movl	$1, %edi
	callq	calloc@PLT
	movq	%rax, %rbx
	cmpl	$0, (%r15)
	jle	.LBB8_3
# %bb.1:                                # %.lr.ph.preheader
	leaq	12(%rsp), %r15
	leaq	8(%rsp), %r12
	leaq	4(%rsp), %r13
	xorl	%ebp, %ebp
.LBB8_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.1, %edi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	4(%rsp), %eax
	movslq	12(%rsp), %rcx
	movslq	20(%rsp), %r14
	imulq	%r14, %rcx
	movslq	8(%rsp), %rdx
	addq	%rcx, %rdx
	movl	%eax, (%rbx,%rdx,4)
	incl	%ebp
	cmpl	16(%rsp), %ebp
	jl	.LBB8_2
.LBB8_3:                                # %._crit_edge
	leal	-1(%r14), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	xorl	%edx, %edx
	callq	_Z13fordFulkersonPiiii
	movl	$.L.str.2, %edi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	printf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	main, .Lfunc_end8-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB9_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB9_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17parallel_traverseiPiS_PxS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end9:
	.size	__hip_module_ctor, .Lfunc_end9-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB10_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB10_2:
	retq
.Lfunc_end10:
	.size	__hip_module_dtor, .Lfunc_end10-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17parallel_traverseiPiS_PxS_i,@object # @_Z17parallel_traverseiPiS_PxS_i
	.section	.rodata,"a",@progbits
	.globl	_Z17parallel_traverseiPiS_PxS_i
	.p2align	3, 0x0
_Z17parallel_traverseiPiS_PxS_i:
	.quad	_Z32__device_stub__parallel_traverseiPiS_PxS_i
	.size	_Z17parallel_traverseiPiS_PxS_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d %d"
	.size	.L.str, 6

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d %d %d"
	.size	.L.str.1, 9

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d\n"
	.size	.L.str.2, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z17parallel_traverseiPiS_PxS_i"
	.size	.L__unnamed_1, 32

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__parallel_traverseiPiS_PxS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17parallel_traverseiPiS_PxS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17parallel_traverseiPiS_PxS_i ; -- Begin function _Z17parallel_traverseiPiS_PxS_i
	.globl	_Z17parallel_traverseiPiS_PxS_i
	.p2align	8
	.type	_Z17parallel_traverseiPiS_PxS_i,@function
_Z17parallel_traverseiPiS_PxS_i:        ; @_Z17parallel_traverseiPiS_PxS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s14, s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x8
	s_mov_b32 s19, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[14:15], 3
	s_add_u32 s2, s8, s12
	s_addc_u32 s3, s9, s13
	s_load_b64 s[16:17], s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s18, s16, 6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[18:19], 4
	s_cbranch_scc1 .LBB0_7
; %bb.1:
	v_lshlrev_b32_e32 v1, 3, v0
	s_mov_b32 s15, exec_lo
	global_load_b32 v2, v1, s[8:9]
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v2, 4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u64_e32 0, v[2:3]
	s_cbranch_execz .LBB0_6
; %bb.2:
	s_load_b32 s0, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, s0, s14, v[0:1]
	v_add_co_u32 v1, s1, s8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_ci_u32_e64 v2, null, s9, 0, s1
	global_load_b32 v3, v[4:5], off
	global_load_b32 v4, v[6:7], off
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v4, v3
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_alignbit_b32 v5, s17, s16, 13
	v_sub_nc_u32_e32 v3, v4, v3
	s_load_b32 s6, s[10:11], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_i32_e32 v3, v5, v3
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 13, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_add_i32 s6, s6, 1
	v_add_co_u32 v3, vcc_lo, v3, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, s6
	v_or_b32_e32 v3, 5, v3
	global_store_b64 v[1:2], v[3:4], off
	global_store_b32 v5, v6, s[10:11]
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s1
	v_mad_u64_u32 v[3:4], null, v0, s0, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	global_load_b32 v0, v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, 0, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_mov_b32_e32 v5, 0
	s_clause 0x1
	global_load_b64 v[3:4], v5, s[2:3]
	global_load_b32 v6, v5, s[10:11]
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v3, v4, v3, 13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_i32_e32 v3, v3, v0
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 13, v[3:4]
	v_add_co_u32 v0, vcc_lo, v3, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
	v_or_b32_e32 v3, 4, v0
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, 1, v6
	global_store_b64 v[1:2], v[3:4], off
	global_store_b32 v5, v0, s[10:11]
.LBB0_6:                                ; %Flow65
	s_or_b32 exec_lo, exec_lo, s15
	v_mov_b32_e32 v0, 0
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v1, v0, s[2:3]
	s_waitcnt vmcnt(0)
	v_or_b32_e32 v1, 2, v1
	global_store_b32 v0, v1, s[2:3]
.LBB0_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17parallel_traverseiPiS_PxS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17parallel_traverseiPiS_PxS_i, .Lfunc_end0-_Z17parallel_traverseiPiS_PxS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 22
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17parallel_traverseiPiS_PxS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z17parallel_traverseiPiS_PxS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
