#include <cuda.h>
#include <iostream>
#include <sys/time.h>
#include <stdio.h>

using namespace std;

/* Overlapping data transfers and kernel execution
 * - pinned memory
 * - streams
 * - different strategies depending on concurrent data transfers enabled or not
 */

#define TILE_DIM    16
#define BLOCK_ROWS  16

__global__ void transposeNaive(double *odata, double* idata, int width, int height, int nreps)
{
  int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
  int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;

  int index_in  = xIndex + width * yIndex;
  int index_out = yIndex + height * xIndex;
  for (int r=0; r < nreps; r++) {
    for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS) {
      odata[index_out+i] = idata[index_in+i*width];
    }
  }
}

int main() {


	// check if device can overlap data transfers with computation
	int deviceCount; 
	cudaGetDeviceCount(&deviceCount); 
	int device; 
	for (device = 0; device < deviceCount; ++device) { 
		cudaDeviceProp deviceProp; 
		cudaGetDeviceProperties(&deviceProp, device); 
		printf("Device %d has compute capability %d.%d.\n", device, 
			deviceProp.major, deviceProp.minor);
		cout << " asyncEngineCount = " << deviceProp.deviceOverlap << endl;
	}
	/************************/

	// side length of square matrix
	int side = 2048;

	// number of elements in a single matrx
	int n = side*side;

	// number of matrices to transpose
	int nTranspose = 96;

	// number of transpose operations on a single matrix
	int nreps = 20;


        // (*) Try with different nStream (nTranspose = integerConstant * nStream)
	int nStream = 4;

	// (*) define streams here	
      	cudaStream_t stream[nStream];
        for (int i=0; i<nStream; i++)
                cudaStreamCreate(&stream[i]);

	// create events
	cudaEvent_t start, stop; 
	cudaEventCreate(&start); 
	cudaEventCreate(&stop);

	// (*) modify here to allocate pinned host memory with cudaMallocHost 
	double *data;
	cudaMallocHost((void**) &data, nTranspose * n * sizeof(double));
     
	// data initialization
	for (int j=0; j<nTranspose; j++)	   
	for (int i=0; i<n; i++) {
                data[i+j*n] = double(i+j*n);
        }

	double *data_dev;
	// (*) modify device memory allocation size according to nStream
        cudaMalloc((void**) &data_dev, nStream * 2 * n * sizeof(double));

	dim3 grid(side/16,side/16,1);
        dim3 threads(16,16,1);

	// record start event
	cudaEventRecord(start, 0);

	int inzeep = 0;
	for (int i=0; i<nTranspose; i++) {

		// (*) modify following lines for overlaping computation and data transfers

		int offset = inzeep * n;

		cudaMemcpyAsync(data_dev + offset*2, data + i*n, n * sizeof(double), 
				cudaMemcpyHostToDevice, stream[inzeep]);

		transposeNaive <<< grid, threads, 0, stream[inzeep]  >>>(data_dev + offset*2 +n, 
				data_dev + offset*2, side, side, nreps);

		cudaMemcpyAsync(data + i*n, data_dev + offset*2 + n, n * sizeof(double), 
				cudaMemcpyDeviceToHost, stream[inzeep]);

		inzeep++;
		inzeep = inzeep%nStream;
	}

	// record stop event
	cudaEventRecord(stop, 0);

	// elapsed time
        cudaEventSynchronize(stop);
        float elapsedTime; 
	cudaEventElapsedTime(&elapsedTime, start, stop);
	cout << "Comp time = " << elapsedTime/1000.0 << endl;

	// destroy events
	cudaEventDestroy(start); 
	cudaEventDestroy(stop);

	// (*) Destroy streams here
	for (int i=0; i<nStream; i++)
                cudaStreamDestroy(stream[i]);


	cudaFree(data_dev);

	cout << "value check = " << data[n+5467] << endl;
	
	// (*) modify here to free pinned host memory
	cudaFreeHost(data);
}


	.file	"tmpxft_003a4781_00000000-6_sol1.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z14transposeNaivePdS_iiiPdS_iii
	.type	_Z39__device_stub__Z14transposeNaivePdS_iiiPdS_iii, @function
_Z39__device_stub__Z14transposeNaivePdS_iiiPdS_iii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14transposeNaivePdS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z39__device_stub__Z14transposeNaivePdS_iiiPdS_iii, .-_Z39__device_stub__Z14transposeNaivePdS_iiiPdS_iii
	.globl	_Z14transposeNaivePdS_iii
	.type	_Z14transposeNaivePdS_iii, @function
_Z14transposeNaivePdS_iii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z14transposeNaivePdS_iiiPdS_iii
	.cfi_endproc
.LFE3661:
	.size	_Z14transposeNaivePdS_iii, .-_Z14transposeNaivePdS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Device %d has compute capability %d.%d.\n"
.LC1:
	.string	" asyncEngineCount = "
.LC2:
	.string	"Comp time = "
.LC4:
	.string	"value check = "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC0(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	xorl	%ebx, %ebx
	subq	$1128, %rsp
	.cfi_def_cfa_offset 1184
	movq	%fs:40, %rax
	movq	%rax, 1112(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rdi
	call	cudaGetDeviceCount@PLT
.L9:
	cmpl	%ebx, 16(%rsp)
	leaq	80(%rsp), %r12
	jle	.L22
	movl	%ebx, %esi
	movq	%r12, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	440(%rsp), %ecx
	movl	%ebx, %edx
	xorl	%eax, %eax
	movl	444(%rsp), %r8d
	movq	%rbp, %rsi
	movl	$2, %edi
	incl	%ebx
	call	__printf_chk@PLT
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	464(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	jmp	.L9
.L22:
	movq	%r12, %rdi
	call	cudaStreamCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	96(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	104(%rsp), %rdi
	call	cudaStreamCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	32(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	movl	$3221225472, %esi
	call	cudaMallocHost@PLT
	movq	40(%rsp), %rcx
	xorl	%edx, %edx
.L11:
	xorl	%eax, %eax
.L12:
	leal	(%rdx,%rax), %esi
	cvtsi2sdl	%esi, %xmm0
	movsd	%xmm0, (%rcx,%rax,8)
	incq	%rax
	cmpq	$4194304, %rax
	jne	.L12
	addl	$4194304, %edx
	addq	$33554432, %rcx
	cmpl	$402653184, %edx
	jne	.L11
	leaq	48(%rsp), %rdi
	movl	$268435456, %esi
	xorl	%ebp, %ebp
	xorl	%ebx, %ebx
	call	cudaMalloc@PLT
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	movabsq	$549755814016, %rax
	movq	%rax, 56(%rsp)
	movl	$3221225472, %r15d
	movabsq	$68719476752, %rax
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	cudaEventRecord@PLT
.L15:
	movl	%ebx, %r13d
	movq	40(%rsp), %rsi
	movslq	%ebx, %r14
	movl	$1, %ecx
	sall	$23, %r13d
	movq	80(%rsp,%r14,8), %r8
	movl	$33554432, %edx
	movslq	%r13d, %r13
	addq	%rbp, %rsi
	leaq	0(,%r13,8), %r10
	leaq	33554432(,%r13,8), %r13
	movq	%r10, %rdi
	addq	48(%rsp), %rdi
	movq	%r10, 8(%rsp)
	call	cudaMemcpyAsync@PLT
	movl	76(%rsp), %ecx
	movl	64(%rsp), %esi
	xorl	%r8d, %r8d
	movq	80(%rsp,%r14,8), %r9
	movq	68(%rsp), %rdx
	movq	56(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movq	8(%rsp), %r10
	testl	%eax, %eax
	jne	.L14
	movq	48(%rsp), %rdi
	movl	$20, %r8d
	movl	$2048, %ecx
	movl	$2048, %edx
	leaq	(%rdi,%r10), %rsi
	addq	%r13, %rdi
	call	_Z39__device_stub__Z14transposeNaivePdS_iiiPdS_iii
.L14:
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdi
	movl	$2, %ecx
	incl	%ebx
	movq	80(%rsp,%r14,8), %r8
	movl	$33554432, %edx
	andl	$3, %ebx
	addq	%rbp, %rdi
	addq	%r13, %rsi
	addq	$33554432, %rbp
	call	cudaMemcpyAsync@PLT
	cmpq	%r15, %rbp
	jne	.L15
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	leaq	_ZSt4cout(%rip), %rbp
	xorl	%ebx, %ebx
	call	cudaEventRecord@PLT
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	20(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rbp, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	20(%rsp), %xmm0
	divsd	.LC3(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	24(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
.L16:
	movq	(%r12,%rbx,8), %rdi
	incq	%rbx
	call	cudaStreamDestroy@PLT
	cmpq	$4, %rbx
	jne	.L16
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rbp, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	movq	40(%rsp), %rax
	movsd	33598168(%rax), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	40(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	1112(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$1128, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z14transposeNaivePdS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14transposeNaivePdS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#include <stdio.h>

using namespace std;

/* Overlapping data transfers and kernel execution
 * - pinned memory
 * - streams
 * - different strategies depending on concurrent data transfers enabled or not
 */

#define TILE_DIM    16
#define BLOCK_ROWS  16

__global__ void transposeNaive(double *odata, double* idata, int width, int height, int nreps)
{
  int xIndex = blockIdx.x * TILE_DIM + threadIdx.x;
  int yIndex = blockIdx.y * TILE_DIM + threadIdx.y;

  int index_in  = xIndex + width * yIndex;
  int index_out = yIndex + height * xIndex;
  for (int r=0; r < nreps; r++) {
    for (int i=0; i<TILE_DIM; i+=BLOCK_ROWS) {
      odata[index_out+i] = idata[index_in+i*width];
    }
  }
}

int main() {


	// check if device can overlap data transfers with computation
	int deviceCount; 
	hipGetDeviceCount(&deviceCount); 
	int device; 
	for (device = 0; device < deviceCount; ++device) { 
		hipDeviceProp_t deviceProp; 
		hipGetDeviceProperties(&deviceProp, device); 
		printf("Device %d has compute capability %d.%d.\n", device, 
			deviceProp.major, deviceProp.minor);
		cout << " asyncEngineCount = " << deviceProp.deviceOverlap << endl;
	}
	/************************/

	// side length of square matrix
	int side = 2048;

	// number of elements in a single matrx
	int n = side*side;

	// number of matrices to transpose
	int nTranspose = 96;

	// number of transpose operations on a single matrix
	int nreps = 20;


        // (*) Try with different nStream (nTranspose = integerConstant * nStream)
	int nStream = 4;

	// (*) define streams here	
      	hipStream_t stream[nStream];
        for (int i=0; i<nStream; i++)
                hipStreamCreate(&stream[i]);

	// create events
	hipEvent_t start, stop; 
	hipEventCreate(&start); 
	hipEventCreate(&stop);

	// (*) modify here to allocate pinned host memory with cudaMallocHost 
	double *data;
	hipHostMalloc((void**) &data, nTranspose * n * sizeof(double), hipHostMallocDefault);
     
	// data initialization
	for (int j=0; j<nTranspose; j++)	   
	for (int i=0; i<n; i++) {
                data[i+j*n] = double(i+j*n);
        }

	double *data_dev;
	// (*) modify device memory allocation size according to nStream
        hipMalloc((void**) &data_dev, nStream * 2 * n * sizeof(double));

	dim3 grid(side/16,side/16,1);
        dim3 threads(16,16,1);

	// record start event
	hipEventRecord(start, 0);

	int inzeep = 0;
	for (int i=0; i<nTranspose; i++) {

		// (*) modify following lines for overlaping computation and data transfers

		int offset = inzeep * n;

		hipMemcpyAsync(data_dev + offset*2, data + i*n, n * sizeof(double), 
				hipMemcpyHostToDevice, stream[inzeep]);

		transposeNaive <<< grid, threads, 0, stream[inzeep]  >>>(data_dev + offset*2 +n, 
				data_dev + offset*2, side, side, nreps);

		hipMemcpyAsync(data + i*n, data_dev + offset*2 + n, n * sizeof(double), 
				hipMemcpyDeviceToHost, stream[inzeep]);

		inzeep++;
		inzeep = inzeep%nStream;
	}

	// record stop event
	hipEventRecord(stop, 0);

	// elapsed time
        hipEventSynchronize(stop);
        float elapsedTime; 
	hipEventElapsedTime(&elapsedTime, start, stop);
	cout << "Comp time = " << elapsedTime/1000.0 << endl;

	// destroy events
	hipEventDestroy(start); 
	hipEventDestroy(stop);

	// (*) Destroy streams here
	for (int i=0; i<nStream; i++)
                hipStreamDestroy(stream[i]);


	hipFree(data_dev);

	cout << "value check = " << data[n+5467] << endl;
	
	// (*) modify here to free pinned host memory
	hipHostFree(data);
}


	.text
	.file	"sol1.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z29__device_stub__transposeNaivePdS_iii # -- Begin function _Z29__device_stub__transposeNaivePdS_iii
	.type	_Z29__device_stub__transposeNaivePdS_iii,@function
_Z29__device_stub__transposeNaivePdS_iii: # @_Z29__device_stub__transposeNaivePdS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14transposeNaivePdS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__transposeNaivePdS_iii, .Lfunc_end0-_Z29__device_stub__transposeNaivePdS_iii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$1528, %rsp                     # imm = 0x5F8
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	leaq	-68(%rbp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDeviceCount
	cmpl	$0, (%rbx)
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph
	leaq	-1568(%rbp), %rbx
	xorl	%r14d, %r14d
.LBB1_2:                                # =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	hipGetDevicePropertiesR0600
	movl	-1208(%rbp), %edx
	movl	-1204(%rbp), %ecx
	movl	$.L.str, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$20, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	-1184(%rbp), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	incl	%r14d
	cmpl	-68(%rbp), %r14d
	jl	.LBB1_2
.LBB1_3:                                # %._crit_edge
	movq	%rsp, -80(%rbp)                 # 8-byte Spill
	movq	%rsp, %r13
	addq	$-32, %r13
	movq	%r13, %rsp
	xorl	%ebx, %ebx
.LBB1_4:                                # =>This Inner Loop Header: Depth=1
	leaq	(%rbx,%r13), %rdi
	callq	hipStreamCreate
	addq	$8, %rbx
	cmpq	$32, %rbx
	jne	.LBB1_4
# %bb.5:
	leaq	-1568(%rbp), %rdi
	callq	hipEventCreate
	leaq	-64(%rbp), %rdi
	callq	hipEventCreate
	leaq	-56(%rbp), %rbx
	xorl	%r14d, %r14d
	movl	$3221225472, %esi               # imm = 0xC0000000
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movq	(%rbx), %rax
	xorl	%ecx, %ecx
.LBB1_6:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_7 Depth 2
	xorl	%edx, %edx
.LBB1_7:                                #   Parent Loop BB1_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%r14,%rdx), %esi
	xorps	%xmm0, %xmm0
	cvtsi2sd	%esi, %xmm0
	movsd	%xmm0, (%rax,%rdx,8)
	incq	%rdx
	cmpq	$4194304, %rdx                  # imm = 0x400000
	jne	.LBB1_7
# %bb.8:                                #   in Loop: Header=BB1_6 Depth=1
	incq	%rcx
	addq	$4194304, %r14                  # imm = 0x400000
	addq	$33554432, %rax                 # imm = 0x2000000
	cmpq	$96, %rcx
	jne	.LBB1_6
# %bb.9:
	leaq	-48(%rbp), %rdi
	movl	$268435456, %esi                # imm = 0x10000000
	callq	hipMalloc
	movq	-1568(%rbp), %rdi
	xorl	%r12d, %r12d
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$96, %ebx
	xorl	%eax, %eax
.LBB1_10:                               # =>This Inner Loop Header: Depth=1
	movslq	%eax, %r14
	shll	$23, %eax
	cltq
	movq	%rax, -88(%rbp)                 # 8-byte Spill
	leaq	(,%rax,8), %r15
	movq	-48(%rbp), %rdi
	addq	%r15, %rdi
	movq	-56(%rbp), %rsi
	addq	%r12, %rsi
	movq	(%r13,%r14,8), %r8
	movl	$33554432, %edx                 # imm = 0x2000000
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%r13,%r14,8), %r9
	movabsq	$549755814016, %rdi             # imm = 0x8000000080
	movl	$1, %esi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_12
# %bb.11:                               #   in Loop: Header=BB1_10 Depth=1
	movq	-48(%rbp), %rax
	movq	-88(%rbp), %rcx                 # 8-byte Reload
	leaq	(%rax,%rcx,8), %rsi
	leaq	(%rax,%rcx,8), %rdi
	addq	$33554432, %rdi                 # imm = 0x2000000
	movl	$2048, %edx                     # imm = 0x800
	movl	$2048, %ecx                     # imm = 0x800
	movl	$20, %r8d
	callq	_Z29__device_stub__transposeNaivePdS_iii
.LBB1_12:                               #   in Loop: Header=BB1_10 Depth=1
	movq	-56(%rbp), %rdi
	addq	%r12, %rdi
	addq	-48(%rbp), %r15
	movl	$33554432, %eax                 # imm = 0x2000000
	addq	%rax, %r15
	movq	(%r13,%r14,8), %r8
	movl	$33554432, %edx                 # imm = 0x2000000
	movq	%r15, %rsi
	movl	$2, %ecx
	callq	hipMemcpyAsync
	leal	1(%r14), %eax
	leal	4(%r14), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-4, %ecx
	negl	%ecx
	leal	(%r14,%rcx), %eax
	incl	%eax
	movl	$33554432, %ecx                 # imm = 0x2000000
	addq	%rcx, %r12
	decq	%rbx
	jne	.LBB1_10
# %bb.13:
	movq	-64(%rbp), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-64(%rbp), %rdi
	callq	hipEventSynchronize
	movq	-1568(%rbp), %rsi
	movq	-64(%rbp), %rdx
	leaq	-92(%rbp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtss2sd	(%rbx), %xmm0
	divsd	.LCPI1_0(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	-1568(%rbp), %rdi
	callq	hipEventDestroy
	movq	-64(%rbp), %rdi
	callq	hipEventDestroy
.LBB1_14:                               # =>This Inner Loop Header: Depth=1
	movq	(%r13,%r14,8), %rdi
	callq	hipStreamDestroy
	incq	%r14
	cmpq	$4, %r14
	jne	.LBB1_14
# %bb.15:
	movq	-48(%rbp), %rdi
	callq	hipFree
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	-56(%rbp), %rax
	movsd	33598168(%rax), %xmm0           # xmm0 = mem[0],zero
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	-56(%rbp), %rdi
	callq	hipHostFree
	movq	-80(%rbp), %rsp                 # 8-byte Reload
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14transposeNaivePdS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14transposeNaivePdS_iii,@object # @_Z14transposeNaivePdS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z14transposeNaivePdS_iii
	.p2align	3, 0x0
_Z14transposeNaivePdS_iii:
	.quad	_Z29__device_stub__transposeNaivePdS_iii
	.size	_Z14transposeNaivePdS_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Device %d has compute capability %d.%d.\n"
	.size	.L.str, 41

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" asyncEngineCount = "
	.size	.L.str.1, 21

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Comp time = "
	.size	.L.str.2, 13

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"value check = "
	.size	.L.str.3, 15

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14transposeNaivePdS_iii"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__transposeNaivePdS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14transposeNaivePdS_iii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14transposeNaivePdS_iii ; -- Begin function _Z14transposeNaivePdS_iii
	.globl	_Z14transposeNaivePdS_iii
	.p2align	8
	.type	_Z14transposeNaivePdS_iii,@function
_Z14transposeNaivePdS_iii:              ; @_Z14transposeNaivePdS_iii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s6, 1
	s_cbranch_scc1 .LBB0_2
; %bb.1:                                ; %.critedge.lr.ph
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s14, 4, v1
	v_lshl_add_u32 v1, s15, 4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:                                ; %._crit_edge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14transposeNaivePdS_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14transposeNaivePdS_iii, .Lfunc_end0-_Z14transposeNaivePdS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 184
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14transposeNaivePdS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14transposeNaivePdS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
