#include "sum.hh"
#include "../runtime/node.hh"



namespace gpu
{

    namespace
    {

        constexpr std::size_t BLOCK_SIZE = 512;

        __global__
        void mse(const dbl_t* a, const dbl_t* b, dbl_t* out,
                 std::size_t len)
        {
            __shared__ float partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto i = threadIdx.x;
            std::size_t step = BLOCK_SIZE;

            float init = 0;
            for (std::size_t j = i; j < len; j += step)
                init += (a[j] - b[j]) * (a[j] - b[j]);
        
            partial[i] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (i < s)
                    partial[i] += partial[i + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile float* vpartial = partial;
            if (i < 32)
            {
                vpartial[i] += vpartial[i + 32];
                vpartial[i] += vpartial[i + 16];
                vpartial[i] += vpartial[i + 8];
                vpartial[i] += vpartial[i + 4];
                vpartial[i] += vpartial[i + 2];
                vpartial[i] += vpartial[i + 1];
            }


            if (i == 0)
                *out = partial[0] / len;
        }

        __global__
        void mse_grad(const dbl_t* a, const dbl_t* b, dbl_t* out, std::size_t len)
        {
            std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t stride = blockDim.x * gridDim.x;
            dbl_t coeff = dbl_t(2) / len;

            for (std::size_t i = index; i < len; i += stride)
                out[i] = coeff * (a[i] - b[i]);
        }


        __global__
        void mat_sum_rows(const dbl_t* x, dbl_t* y,
                          std::size_t rows, std::size_t cols)
        {
            __shared__ dbl_t partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto row = blockIdx.x;
            auto col = threadIdx.x;
            std::size_t step = BLOCK_SIZE;

            dbl_t init = 0;
            for (std::size_t i = col; i < cols; i += step)
                init += x[row * cols + i];
        
            partial[col] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (col < s)
                    partial[col] += partial[col + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile dbl_t* vpartial = partial;
            if (col < 32)
            {
                vpartial[col] += vpartial[col + 32];
                vpartial[col] += vpartial[col + 16];
                vpartial[col] += vpartial[col + 8];
                vpartial[col] += vpartial[col + 4];
                vpartial[col] += vpartial[col + 2];
                vpartial[col] += vpartial[col + 1];
            }
            
            if (col == 0)
                y[row] = partial[0];
        }


        __global__
        void mat_sum_cols(const dbl_t* x, dbl_t* y,
                          std::size_t rows, std::size_t cols)
        {
            __shared__ dbl_t partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto col = blockIdx.x;
            auto row = threadIdx.x;
            std::size_t step = BLOCK_SIZE;
            
            dbl_t init = 0;
            for (std::size_t i = row; i < rows; i += step)
                init += x[i * cols + col];
        
            partial[row] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (row < s)
                    partial[row] += partial[row + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile dbl_t* vpartial = partial;
            if (row < 32)
            {
                vpartial[row] += vpartial[row + 32];
                vpartial[row] += vpartial[row + 16];
                vpartial[row] += vpartial[row + 8];
                vpartial[row] += vpartial[row + 4];
                vpartial[row] += vpartial[row + 2];
                vpartial[row] += vpartial[row + 1];
            }
            
            if (row == 0)
                y[col] = partial[0];
        }

        __device__
        std::size_t argmax(const dbl_t* begin, const dbl_t* end)
        {
            const dbl_t* res = begin;
            for (const dbl_t* it = begin; it != end; ++it)
                if (*it > *res)
                    res = it;
            return res - begin;
        }

        __global__
        void argmax_acc(const dbl_t* a, const dbl_t* b, dbl_t* out,
                        std::size_t rows, std::size_t cols)
        {
            __shared__ dbl_t partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto i = threadIdx.x;
            std::size_t step = BLOCK_SIZE;

            dbl_t init = 0;
            for (std::size_t j = i; j < rows; j += step)
                init += argmax(a + j * cols, a + (j + 1) * cols)  
                    == argmax(b + j * cols, b + (j + 1) * cols);
                    
            partial[i] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (i < s)
                    partial[i] += partial[i + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile dbl_t* vpartial = partial;
            if (i < 32)
            {
                vpartial[i] += vpartial[i + 32];
                vpartial[i] += vpartial[i + 16];
                vpartial[i] += vpartial[i + 8];
                vpartial[i] += vpartial[i + 4];
                vpartial[i] += vpartial[i + 2];
                vpartial[i] += vpartial[i + 1];
            }


            if (i == 0)
                *out = partial[0];
        }

        __global__
        void vect_add(const dbl_t* a, const dbl_t* b, dbl_t* y, std::size_t len)
        {
            std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t stride = blockDim.x * gridDim.x;

            for (std::size_t i = index; i < len; i += stride)
                y[i] = a[i] + b[i];
        }

    }

    void kernel_mse(rt::Node* node)
    {
        std::size_t len = node->len1 * node->len2;
        mse<<<1, BLOCK_SIZE>>>(node->in1, node->in2, node->out1, len);
    }

    void kernel_mse_grad(rt::Node* node)
    {
        std::size_t len = node->len1;
        std::size_t nb_blocks = (len + BLOCK_SIZE - 1)/ BLOCK_SIZE;
        mse_grad<<<nb_blocks, BLOCK_SIZE>>>(node->in2, node->in1, node->out1, node->len1);
    }

    void kernel_mat_sum_rows(rt::Node* node)
    {
        std::size_t rows = node->len1;
        std::size_t cols = node->len2;
        mat_sum_rows<<<rows, BLOCK_SIZE>>>(node->in1, node->out1, rows, cols);
    }

    void kernel_mat_sum_cols(rt::Node* node)
    {
        std::size_t rows = node->len1;
        std::size_t cols = node->len2;
        mat_sum_cols<<<cols, BLOCK_SIZE>>>(node->in1, node->out1, rows, cols);
    }

    void kernel_argmax_acc(rt::Node* node)
    {
        argmax_acc<<<1, BLOCK_SIZE>>>(node->in1, node->in2, node->out1,
                                      node->len1, node->len2);
    }

    void kernel_add(rt::Node* node)
    {
        std::size_t len = node->len1;
        std::size_t block_size = 256;
        std::size_t nb_blocks = (len + block_size - 1)/ block_size;
        vect_add<<<nb_blocks, block_size>>>(node->in1, node->in2, node->out1, len);
    }

}

	.file	"tmpxft_002952d0_00000000-6_sum.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2886:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2886:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a86argmaxEPKfS2_
	.hidden	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a86argmaxEPKfS2_
	.type	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a86argmaxEPKfS2_, @function
_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a86argmaxEPKfS2_:
.LFB2877:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2877:
	.size	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a86argmaxEPKfS2_, .-_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a86argmaxEPKfS2_
	.globl	_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm
	.hidden	_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm
	.type	_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm, @function
_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm:
.LFB2908:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2908:
	.size	_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm, .-_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm
	.globl	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm
	.hidden	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm
	.type	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm, @function
_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm:
.LFB2909:
	.cfi_startproc
	endbr64
	jmp	_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm
	.cfi_endproc
.LFE2909:
	.size	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm, .-_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm
	.globl	_ZN3gpu10kernel_mseEPN2rt4NodeE
	.type	_ZN3gpu10kernel_mseEPN2rt4NodeE, @function
_ZN3gpu10kernel_mseEPN2rt4NodeE:
.LFB2878:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	salq	$9, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	120(%rdi), %rbp
	movq	128(%rdi), %r12
	movabsq	$4294967297, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	%rbp, %rcx
	movq	88(%rbx), %rdx
	movq	72(%rbx), %rsi
	imulq	%r12, %rcx
	movq	64(%rbx), %rdi
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z75__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_PfmPKfS0_Pfm
.L10:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2878:
	.size	_ZN3gpu10kernel_mseEPN2rt4NodeE, .-_ZN3gpu10kernel_mseEPN2rt4NodeE
	.globl	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm
	.hidden	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm
	.type	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm, @function
_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm:
.LFB2910:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2910:
	.size	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm, .-_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm
	.globl	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm
	.hidden	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm
	.type	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm, @function
_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm:
.LFB2911:
	.cfi_startproc
	endbr64
	jmp	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm
	.cfi_endproc
.LFE2911:
	.size	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm, .-_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm
	.globl	_ZN3gpu15kernel_mse_gradEPN2rt4NodeE
	.type	_ZN3gpu15kernel_mse_gradEPN2rt4NodeE, @function
_ZN3gpu15kernel_mse_gradEPN2rt4NodeE:
.LFB2879:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$8388609, %edx
	movq	%rdi, %rbx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	movq	120(%rdi), %rax
	addq	$511, %rax
	shrq	$9, %rax
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	movq	120(%rbx), %rcx
	movq	88(%rbx), %rdx
	movq	64(%rbx), %rsi
	movq	72(%rbx), %rdi
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_PfmPKfS0_Pfm
.L18:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2879:
	.size	_ZN3gpu15kernel_mse_gradEPN2rt4NodeE, .-_ZN3gpu15kernel_mse_gradEPN2rt4NodeE
	.globl	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm
	.hidden	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm
	.type	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm, @function
_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm:
.LFB2912:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L21:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2912:
	.size	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm, .-_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm
	.globl	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm
	.hidden	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm
	.type	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm, @function
_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm:
.LFB2913:
	.cfi_startproc
	endbr64
	jmp	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm
	.cfi_endproc
.LFE2913:
	.size	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm, .-_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm
	.globl	_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE
	.type	_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE, @function
_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE:
.LFB2880:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	120(%rdi), %rbp
	movq	128(%rdi), %r12
	movq	%rax, 12(%rsp)
	movl	16(%rsp), %esi
	movl	%ebp, 8(%rsp)
	movq	8(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	movq	88(%rbx), %rsi
	movq	64(%rbx), %rdi
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%r12, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 24
	movq	%rbp, %rdx
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmmPKfPfmm
.L26:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2880:
	.size	_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE, .-_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE
	.globl	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm
	.hidden	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm
	.type	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm, @function
_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm:
.LFB2914:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L29:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2914:
	.size	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm, .-_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm
	.globl	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm
	.hidden	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm
	.type	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm, @function
_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm:
.LFB2915:
	.cfi_startproc
	endbr64
	jmp	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm
	.cfi_endproc
.LFE2915:
	.size	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm, .-_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm
	.globl	_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE
	.type	_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE, @function
_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE:
.LFB2881:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$8388609, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	128(%rdi), %rbp
	movq	120(%rdi), %r12
	movq	%rax, 12(%rsp)
	movl	16(%rsp), %esi
	movl	%ebp, 8(%rsp)
	movq	8(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	movq	88(%rbx), %rsi
	movq	64(%rbx), %rdi
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 32
	movq	%rbp, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 24
	movq	%r12, %rdx
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	_Z83__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmmPKfPfmm
.L34:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2881:
	.size	_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE, .-_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE
	.globl	_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm
	.hidden	_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm
	.type	_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm, @function
_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm:
.LFB2916:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L37
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L37:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L39
	call	__stack_chk_fail@PLT
.L39:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2916:
	.size	_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm, .-_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm
	.globl	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm
	.hidden	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm
	.type	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm, @function
_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm:
.LFB2917:
	.cfi_startproc
	endbr64
	jmp	_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm
	.cfi_endproc
.LFE2917:
	.size	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm, .-_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm
	.globl	_ZN3gpu17kernel_argmax_accEPN2rt4NodeE
	.type	_ZN3gpu17kernel_argmax_accEPN2rt4NodeE, @function
_ZN3gpu17kernel_argmax_accEPN2rt4NodeE:
.LFB2882:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	$8388609, %edx
	movq	%rdi, %rbx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L42
	movq	120(%rbx), %rcx
	movq	88(%rbx), %rdx
	movq	72(%rbx), %rsi
	movq	64(%rbx), %rdi
	movq	128(%rbx), %r8
	addq	$32, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_Z84__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_PfmmPKfS0_Pfmm
.L42:
	.cfi_restore_state
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2882:
	.size	_ZN3gpu17kernel_argmax_accEPN2rt4NodeE, .-_ZN3gpu17kernel_argmax_accEPN2rt4NodeE
	.globl	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm
	.hidden	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm
	.type	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm, @function
_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm:
.LFB2918:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L45:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2918:
	.size	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm, .-_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm
	.globl	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm
	.hidden	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm
	.type	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm, @function
_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm:
.LFB2919:
	.cfi_startproc
	endbr64
	jmp	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm
	.cfi_endproc
.LFE2919:
	.size	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm, .-_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm
	.globl	_ZN3gpu10kernel_addEPN2rt4NodeE
	.type	_ZN3gpu10kernel_addEPN2rt4NodeE, @function
_ZN3gpu10kernel_addEPN2rt4NodeE:
.LFB2883:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	salq	$8, %rdx
	movl	$1, %ecx
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	movq	120(%rdi), %rbp
	leaq	255(%rbp), %rax
	shrq	$8, %rax
	movl	%eax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L50
	movq	88(%rbx), %rdx
	movq	72(%rbx), %rsi
	movq	%rbp, %rcx
	movq	64(%rbx), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z80__device_stub__ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_PfmPKfS0_Pfm
.L50:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2883:
	.size	_ZN3gpu10kernel_addEPN2rt4NodeE, .-_ZN3gpu10kernel_addEPN2rt4NodeE
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm"
.LC1:
	.string	"_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm"
.LC2:
	.string	"_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm"
.LC3:
	.string	"_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm"
.LC4:
	.string	"_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm"
.LC5:
	.string	"_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2921:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88vect_addEPKfS2_Pfm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a810argmax_accEPKfS2_Pfmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_colsEPKfPfmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a812mat_sum_rowsEPKfPfmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a88mse_gradEPKfS2_Pfm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN3gpu38_GLOBAL__N__079d64bb_6_sum_cu_1837d0a83mseEPKfS2_Pfm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2921:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "sum.hh"
#include "../runtime/node.hh"



namespace gpu
{

    namespace
    {

        constexpr std::size_t BLOCK_SIZE = 512;

        __global__
        void mse(const dbl_t* a, const dbl_t* b, dbl_t* out,
                 std::size_t len)
        {
            __shared__ float partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto i = threadIdx.x;
            std::size_t step = BLOCK_SIZE;

            float init = 0;
            for (std::size_t j = i; j < len; j += step)
                init += (a[j] - b[j]) * (a[j] - b[j]);
        
            partial[i] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (i < s)
                    partial[i] += partial[i + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile float* vpartial = partial;
            if (i < 32)
            {
                vpartial[i] += vpartial[i + 32];
                vpartial[i] += vpartial[i + 16];
                vpartial[i] += vpartial[i + 8];
                vpartial[i] += vpartial[i + 4];
                vpartial[i] += vpartial[i + 2];
                vpartial[i] += vpartial[i + 1];
            }


            if (i == 0)
                *out = partial[0] / len;
        }

        __global__
        void mse_grad(const dbl_t* a, const dbl_t* b, dbl_t* out, std::size_t len)
        {
            std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t stride = blockDim.x * gridDim.x;
            dbl_t coeff = dbl_t(2) / len;

            for (std::size_t i = index; i < len; i += stride)
                out[i] = coeff * (a[i] - b[i]);
        }


        __global__
        void mat_sum_rows(const dbl_t* x, dbl_t* y,
                          std::size_t rows, std::size_t cols)
        {
            __shared__ dbl_t partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto row = blockIdx.x;
            auto col = threadIdx.x;
            std::size_t step = BLOCK_SIZE;

            dbl_t init = 0;
            for (std::size_t i = col; i < cols; i += step)
                init += x[row * cols + i];
        
            partial[col] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (col < s)
                    partial[col] += partial[col + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile dbl_t* vpartial = partial;
            if (col < 32)
            {
                vpartial[col] += vpartial[col + 32];
                vpartial[col] += vpartial[col + 16];
                vpartial[col] += vpartial[col + 8];
                vpartial[col] += vpartial[col + 4];
                vpartial[col] += vpartial[col + 2];
                vpartial[col] += vpartial[col + 1];
            }
            
            if (col == 0)
                y[row] = partial[0];
        }


        __global__
        void mat_sum_cols(const dbl_t* x, dbl_t* y,
                          std::size_t rows, std::size_t cols)
        {
            __shared__ dbl_t partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto col = blockIdx.x;
            auto row = threadIdx.x;
            std::size_t step = BLOCK_SIZE;
            
            dbl_t init = 0;
            for (std::size_t i = row; i < rows; i += step)
                init += x[i * cols + col];
        
            partial[row] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (row < s)
                    partial[row] += partial[row + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile dbl_t* vpartial = partial;
            if (row < 32)
            {
                vpartial[row] += vpartial[row + 32];
                vpartial[row] += vpartial[row + 16];
                vpartial[row] += vpartial[row + 8];
                vpartial[row] += vpartial[row + 4];
                vpartial[row] += vpartial[row + 2];
                vpartial[row] += vpartial[row + 1];
            }
            
            if (row == 0)
                y[col] = partial[0];
        }

        __device__
        std::size_t argmax(const dbl_t* begin, const dbl_t* end)
        {
            const dbl_t* res = begin;
            for (const dbl_t* it = begin; it != end; ++it)
                if (*it > *res)
                    res = it;
            return res - begin;
        }

        __global__
        void argmax_acc(const dbl_t* a, const dbl_t* b, dbl_t* out,
                        std::size_t rows, std::size_t cols)
        {
            __shared__ dbl_t partial[2 * BLOCK_SIZE];

            //load all elements of the array in shared memory
            auto i = threadIdx.x;
            std::size_t step = BLOCK_SIZE;

            dbl_t init = 0;
            for (std::size_t j = i; j < rows; j += step)
                init += argmax(a + j * cols, a + (j + 1) * cols)  
                    == argmax(b + j * cols, b + (j + 1) * cols);
                    
            partial[i] = init;
            __syncthreads();

            for (std::size_t s = BLOCK_SIZE / 2; s > 32; s >>= 1)
            {
                if (i < s)
                    partial[i] += partial[i + s];

                __syncthreads();
            }

            //if not volatile, must use __synctthreads again, why ?
            volatile dbl_t* vpartial = partial;
            if (i < 32)
            {
                vpartial[i] += vpartial[i + 32];
                vpartial[i] += vpartial[i + 16];
                vpartial[i] += vpartial[i + 8];
                vpartial[i] += vpartial[i + 4];
                vpartial[i] += vpartial[i + 2];
                vpartial[i] += vpartial[i + 1];
            }


            if (i == 0)
                *out = partial[0];
        }

        __global__
        void vect_add(const dbl_t* a, const dbl_t* b, dbl_t* y, std::size_t len)
        {
            std::size_t index = blockIdx.x * blockDim.x + threadIdx.x;
            std::size_t stride = blockDim.x * gridDim.x;

            for (std::size_t i = index; i < len; i += stride)
                y[i] = a[i] + b[i];
        }

    }

    void kernel_mse(rt::Node* node)
    {
        std::size_t len = node->len1 * node->len2;
        mse<<<1, BLOCK_SIZE>>>(node->in1, node->in2, node->out1, len);
    }

    void kernel_mse_grad(rt::Node* node)
    {
        std::size_t len = node->len1;
        std::size_t nb_blocks = (len + BLOCK_SIZE - 1)/ BLOCK_SIZE;
        mse_grad<<<nb_blocks, BLOCK_SIZE>>>(node->in2, node->in1, node->out1, node->len1);
    }

    void kernel_mat_sum_rows(rt::Node* node)
    {
        std::size_t rows = node->len1;
        std::size_t cols = node->len2;
        mat_sum_rows<<<rows, BLOCK_SIZE>>>(node->in1, node->out1, rows, cols);
    }

    void kernel_mat_sum_cols(rt::Node* node)
    {
        std::size_t rows = node->len1;
        std::size_t cols = node->len2;
        mat_sum_cols<<<cols, BLOCK_SIZE>>>(node->in1, node->out1, rows, cols);
    }

    void kernel_argmax_acc(rt::Node* node)
    {
        argmax_acc<<<1, BLOCK_SIZE>>>(node->in1, node->in2, node->out1,
                                      node->len1, node->len2);
    }

    void kernel_add(rt::Node* node)
    {
        std::size_t len = node->len1;
        std::size_t block_size = 256;
        std::size_t nb_blocks = (len + block_size - 1)/ block_size;
        vect_add<<<nb_blocks, block_size>>>(node->in1, node->in2, node->out1, len);
    }

}

	.text
	.file	"sum.hip"
	.globl	_ZN3gpu10kernel_mseEPN2rt4NodeE # -- Begin function _ZN3gpu10kernel_mseEPN2rt4NodeE
	.type	_ZN3gpu10kernel_mseEPN2rt4NodeE,@function
_ZN3gpu10kernel_mseEPN2rt4NodeE:        # @_ZN3gpu10kernel_mseEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r14
	movq	120(%rdi), %r15
	movq	128(%rdi), %rbx
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	511(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 32
	imulq	%r15, %rbx
	movq	64(%r14), %rdi
	movq	72(%r14), %rsi
	movq	88(%r14), %rdx
	movq	%rbx, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm # TAILCALL
.Lfunc_end0:
	.size	_ZN3gpu10kernel_mseEPN2rt4NodeE, .Lfunc_end0-_ZN3gpu10kernel_mseEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm
_ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm: # @_ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm, .Lfunc_end1-_ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu15kernel_mse_gradEPN2rt4NodeE # -- Begin function _ZN3gpu15kernel_mse_gradEPN2rt4NodeE
	.type	_ZN3gpu15kernel_mse_gradEPN2rt4NodeE,@function
_ZN3gpu15kernel_mse_gradEPN2rt4NodeE:   # @_ZN3gpu15kernel_mse_gradEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	movl	$511, %eax                      # imm = 0x1FF
	addq	120(%rdi), %rax
	shrq	$9, %rax
	movl	%eax, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB2_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB2_2:
	.cfi_def_cfa_offset 16
	movq	64(%rbx), %rsi
	movq	72(%rbx), %rdi
	movq	88(%rbx), %rdx
	movq	120(%rbx), %rcx
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm # TAILCALL
.Lfunc_end2:
	.size	_ZN3gpu15kernel_mse_gradEPN2rt4NodeE, .Lfunc_end2-_ZN3gpu15kernel_mse_gradEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm
_ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm: # @_ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm, .Lfunc_end3-_ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE # -- Begin function _ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE
	.type	_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE,@function
_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE: # @_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r15
	movq	120(%rdi), %rbx
	movq	128(%rdi), %r14
	movl	%ebx, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB4_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB4_2:
	.cfi_def_cfa_offset 32
	movq	64(%r15), %rdi
	movq	88(%r15), %rsi
	movq	%rbx, %rdx
	movq	%r14, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm # TAILCALL
.Lfunc_end4:
	.size	_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE, .Lfunc_end4-_ZN3gpu19kernel_mat_sum_rowsEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm
_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm: # @_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm, .Lfunc_end5-_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE # -- Begin function _ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE
	.type	_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE,@function
_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE: # @_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rdi, %r15
	movq	120(%rdi), %rbx
	movq	128(%rdi), %r14
	movl	%r14d, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB6_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB6_2:
	.cfi_def_cfa_offset 32
	movq	64(%r15), %rdi
	movq	88(%r15), %rsi
	movq	%rbx, %rdx
	movq	%r14, %rcx
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm # TAILCALL
.Lfunc_end6:
	.size	_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE, .Lfunc_end6-_ZN3gpu19kernel_mat_sum_colsEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm
_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm: # @_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm, .Lfunc_end7-_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu17kernel_argmax_accEPN2rt4NodeE # -- Begin function _ZN3gpu17kernel_argmax_accEPN2rt4NodeE
	.type	_ZN3gpu17kernel_argmax_accEPN2rt4NodeE,@function
_ZN3gpu17kernel_argmax_accEPN2rt4NodeE: # @_ZN3gpu17kernel_argmax_accEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	leaq	511(%rdi), %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB8_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB8_2:
	.cfi_def_cfa_offset 16
	movq	64(%rbx), %rdi
	movq	72(%rbx), %rsi
	movq	88(%rbx), %rdx
	movq	120(%rbx), %rcx
	movq	128(%rbx), %r8
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm # TAILCALL
.Lfunc_end8:
	.size	_ZN3gpu17kernel_argmax_accEPN2rt4NodeE, .Lfunc_end8-_ZN3gpu17kernel_argmax_accEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm
_ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm: # @_ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm, .Lfunc_end9-_ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm
	.cfi_endproc
                                        # -- End function
	.globl	_ZN3gpu10kernel_addEPN2rt4NodeE # -- Begin function _ZN3gpu10kernel_addEPN2rt4NodeE
	.type	_ZN3gpu10kernel_addEPN2rt4NodeE,@function
_ZN3gpu10kernel_addEPN2rt4NodeE:        # @_ZN3gpu10kernel_addEPN2rt4NodeE
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movq	%rdi, %r14
	movq	120(%rdi), %rbx
	leaq	255(%rbx), %rax
	shrq	$8, %rax
	movl	%eax, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB10_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB10_2:
	.cfi_def_cfa_offset 32
	movq	64(%r14), %rdi
	movq	72(%r14), %rsi
	movq	88(%r14), %rdx
	movq	%rbx, %rcx
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm # TAILCALL
.Lfunc_end10:
	.size	_ZN3gpu10kernel_addEPN2rt4NodeE, .Lfunc_end10-_ZN3gpu10kernel_addEPN2rt4NodeE
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm,@function # -- Begin function _ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm
_ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm: # @_ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm, .Lfunc_end11-_ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB12_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB12_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end12:
	.size	__hip_module_ctor, .Lfunc_end12-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB13_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB13_2:
	retq
.Lfunc_end13:
	.size	__hip_module_dtor, .Lfunc_end13-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm,@object # @_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm:
	.quad	_ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm
	.size	_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm, 8

	.type	_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm,@object # @_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm:
	.quad	_ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm
	.size	_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm, 8

	.type	_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm,@object # @_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm:
	.quad	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm
	.size	_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm, 8

	.type	_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm,@object # @_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm:
	.quad	_ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm
	.size	_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm, 8

	.type	_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm,@object # @_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm:
	.quad	_ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm
	.size	_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm, 8

	.type	_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm,@object # @_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm
	.p2align	3, 0x0
_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm:
	.quad	_ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm
	.size	_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm"
	.size	.L__unnamed_2, 41

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm"
	.size	.L__unnamed_3, 44

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm"
	.size	.L__unnamed_4, 44

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm"
	.size	.L__unnamed_5, 45

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm"
	.size	.L__unnamed_6, 41

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN3gpu12_GLOBAL__N_118__device_stub__mseEPKfS2_Pfm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_123__device_stub__mse_gradEPKfS2_Pfm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_rowsEPKfPfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_127__device_stub__mat_sum_colsEPKfPfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_125__device_stub__argmax_accEPKfS2_Pfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_123__device_stub__vect_addEPKfS2_Pfm
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm
	.addrsig_sym _ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm ; -- Begin function _ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm,@function
_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm:    ; @_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v8, 2, v0
	s_mov_b32 s8, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v9, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u64_e64 s[6:7], v[0:1]
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.lr.ph.preheader
	v_add_co_u32 v2, s2, s2, v8
	v_add_co_u32 v4, s0, s0, v8
	v_mov_b32_e32 v7, v1
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v6, v0
	v_add_co_ci_u32_e64 v3, null, s3, 0, s2
	v_add_co_ci_u32_e64 v5, null, s1, 0, s0
	s_mov_b32 s1, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	global_load_b32 v10, v[4:5], off
	global_load_b32 v11, v[2:3], off
	v_add_co_u32 v6, vcc_lo, 0x200, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, 0x800, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e32 vcc_lo, s[6:7], v[6:7]
	v_add_co_u32 v4, s0, 0x800, v4
	v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v10, v10
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_4:                                ; %Flow76
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s8
	s_mov_b64 s[0:1], 0x100
	ds_store_b32 v8, v9
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u64_e64 s[0:1], v[0:1]
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	v_lshl_add_u32 v2, s0, 2, v8
	ds_load_b32 v2, v2
	ds_load_b32 v3, v8
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v8, v2
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, 0x42, s[0:1]
	s_lshr_b64 s[0:1], s[0:1], 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB0_5
; %bb.8:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_lshl_add_u32 v1, v0, 2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v8
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v2, 0, s3, s0
	v_cndmask_b32_e32 v3, 0, v1, vcc_lo
	v_cndmask_b32_e64 v4, 0, s3, vcc_lo
	v_cndmask_b32_e64 v1, 0, v8, s0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 64, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s3, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 32, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s3, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 16, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s3, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 8, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s3, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 4, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s3, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mov_b32_e32 v0, 0
	s_clz_i32_u32 s0, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_min_u32 s2, s0, 32
	s_lshl_b64 s[0:1], s[6:7], s2
	ds_load_b32 v1, v0
	s_min_u32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s1, s0
	v_cvt_f32_u32_e32 v2, s0
	s_sub_i32 s0, 32, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_ldexp_f32 v2, v2, s0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v3, null, v2, v2, v1
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, v1, v2, v1
	v_mul_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v3, v6, v5
	v_fmac_f32_e32 v6, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v6, v5
	v_div_fmas_f32 v3, v3, v4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f32 v1, v3, v2, v1
	global_store_b32 v0, v1, s[4:5]
.LBB0_12:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 9
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm,comdat
.Lfunc_end0:
	.size	_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm, .Lfunc_end0-_ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 984
; NumSgprs: 11
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 11
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm ; -- Begin function _ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm,@function
_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm: ; @_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmpx_gt_u64_e64 s[10:11], v[1:2]
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clz_i32_u32 s3, s11
	s_load_b32 s0, s[0:1], 0x0
	s_min_u32 s3, s3, 32
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[10:11], s3
	s_sub_i32 s3, 32, s3
	s_min_u32 s12, s12, 1
	s_or_b32 s12, s13, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s12
	v_ldexp_f32 v0, v0, s3
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_div_scale_f32 v3, null, v0, v0, 2.0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s0, s2
	s_lshl_b64 s[12:13], s[2:3], 2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	v_div_scale_f32 v5, vcc_lo, 2.0, v0, 2.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v4
	v_fma_f32 v7, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v4
	v_fma_f32 v3, -v3, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v3, v4, v6
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_div_fixup_f32 v0, v5, v0, 2.0
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, s2
	global_load_b32 v9, v[5:6], off
	global_load_b32 v7, v[7:8], off
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[1:2]
	v_add_co_u32 v3, s0, v3, s12
	v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v7, v9, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v7, v0, v7
	global_store_b32 v[5:6], v7, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_2
.LBB1_3:                                ; %Flow29
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm,comdat
.Lfunc_end1:
	.size	_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm, .Lfunc_end1-_ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 384
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm ; -- Begin function _ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm,@function
_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm: ; @_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm
; %bb.0:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x18
	s_load_b128 s[0:3], s[0:1], 0x0
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v6, 2, v0
	s_mov_b32 s4, s15
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v7, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u64_e64 s[6:7], v[0:1]
	s_cbranch_execz .LBB2_4
; %bb.1:                                ; %.lr.ph
	s_mul_i32 s9, s7, s4
	s_mul_hi_u32 s10, s6, s4
	s_mul_i32 s8, s6, s4
	s_add_i32 s9, s10, s9
	v_mov_b32_e32 v5, v1
	s_lshl_b64 s[8:9], s[8:9], 2
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v0
	s_add_u32 s0, s0, s8
	s_addc_u32 s1, s1, s9
	v_add_co_u32 v2, s0, s0, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, null, s1, 0, s0
	s_mov_b32 s1, 0
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[2:3], off
	v_add_co_u32 v4, vcc_lo, 0x200, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v2, s0, 0x800, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	v_cmp_le_u64_e32 vcc_lo, s[6:7], v[4:5]
	s_or_b32 s1, vcc_lo, s1
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v7, v7, v8
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB2_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB2_4:                                ; %Flow64
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
	s_mov_b64 s[0:1], 0x100
	ds_store_b32 v6, v7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_5:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u64_e64 s[0:1], v[0:1]
	s_cbranch_execz .LBB2_7
; %bb.6:                                ;   in Loop: Header=BB2_5 Depth=1
	v_lshl_add_u32 v2, s0, 2, v6
	ds_load_b32 v2, v2
	ds_load_b32 v3, v6
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v2, v2, v3
	ds_store_b32 v6, v2
.LBB2_7:                                ;   in Loop: Header=BB2_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	v_cmp_gt_u64_e64 s5, 0x42, s[0:1]
	s_lshr_b64 s[0:1], s[0:1], 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccz .LBB2_5
; %bb.8:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB2_10
; %bb.9:
	v_lshl_add_u32 v1, v0, 2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v6
	s_mov_b64 s[6:7], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v2, 0, s7, s0
	v_cndmask_b32_e32 v3, 0, v1, vcc_lo
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	v_cndmask_b32_e64 v1, 0, v6, s0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 64, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 32, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 16, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 8, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v4, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v5, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v3, 4, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v3
	v_cndmask_b32_e32 v3, 0, v3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v4, v5
	v_cndmask_b32_e64 v4, 0, s7, vcc_lo
	flat_store_b32 v[1:2], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v3, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v4, v[1:2] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	flat_store_b32 v[1:2], v3 dlc
	s_waitcnt_vscnt null, 0x0
.LBB2_10:
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s5, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB2_12
; %bb.11:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB2_12:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm,comdat
.Lfunc_end2:
	.size	_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm, .Lfunc_end2-_ZN3gpu12_GLOBAL__N_112mat_sum_rowsEPKfPfmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 856
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm ; -- Begin function _ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm,@function
_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm: ; @_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s8, s15
	s_mov_b32 s10, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v6, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u64_e64 s[4:5], v[0:1]
	s_cbranch_execz .LBB3_4
; %bb.1:                                ; %.lr.ph
	v_mad_u64_u32 v[2:3], null, s6, v0, 0
	s_mov_b32 s9, 0
	v_mov_b32_e32 v6, 0
	s_lshl_b64 s[12:13], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	s_add_u32 s0, s0, s12
	s_addc_u32 s1, s1, s13
	v_mad_u64_u32 v[4:5], null, s7, v0, v[3:4]
	s_lshl_b64 s[6:7], s[6:7], 11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v3, v4
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.LBB3_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v7, v[2:3], off
	v_add_co_u32 v4, vcc_lo, 0x200, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v2, s0, v2, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
	v_cmp_le_u64_e32 vcc_lo, s[4:5], v[4:5]
	s_or_b32 s9, vcc_lo, s9
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v7
	s_and_not1_b32 exec_lo, exec_lo, s9
	s_cbranch_execnz .LBB3_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s9
.LBB3_4:                                ; %Flow67
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s10
	v_lshlrev_b32_e32 v2, 2, v0
	s_mov_b64 s[0:1], 0x100
	ds_store_b32 v2, v6
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB3_5:                                ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u64_e64 s[0:1], v[0:1]
	s_cbranch_execz .LBB3_7
; %bb.6:                                ;   in Loop: Header=BB3_5 Depth=1
	v_lshl_add_u32 v3, s0, 2, v2
	ds_load_b32 v3, v3
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	ds_store_b32 v2, v3
.LBB3_7:                                ;   in Loop: Header=BB3_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	v_cmp_gt_u64_e64 s4, 0x42, s[0:1]
	s_lshr_b64 s[0:1], s[0:1], 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB3_5
; %bb.8:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB3_10
; %bb.9:
	v_lshl_add_u32 v1, v0, 2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v2
	s_mov_b64 s[4:5], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v4, 0, s5, s0
	v_cndmask_b32_e64 v3, 0, v2, s0
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s5, vcc_lo
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 64, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s5, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 32, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s5, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 16, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s5, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s5, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, 4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cndmask_b32_e64 v2, 0, s5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v6
	flat_store_b32 v[3:4], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB3_10:
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s9, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB3_12
; %bb.11:
	v_mov_b32_e32 v0, 0
	s_lshl_b64 s[0:1], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[0:1]
.LBB3_12:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm,comdat
.Lfunc_end3:
	.size	_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm, .Lfunc_end3-_ZN3gpu12_GLOBAL__N_112mat_sum_colsEPKfPfmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 860
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm ; -- Begin function _ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm,@function
_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm: ; @_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x20
	v_mov_b32_e32 v1, 0
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v14, v1
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u64_e64 s[10:11], v[0:1]
	s_cbranch_execz .LBB4_10
; %bb.1:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v14, 0 :: v_dual_mov_b32 v3, v1
	v_mov_b32_e32 v2, v0
	s_lshl_b64 s[2:3], s[0:1], 2
	s_mov_b32 s15, 0
.LBB4_2:                                ; %.lr.ph
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_4 Depth 2
                                        ;     Child Loop BB4_7 Depth 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v3, s0
	v_mul_lo_u32 v7, v2, s1
	v_mad_u64_u32 v[4:5], null, v2, s0, 0
	s_cmp_lg_u64 s[0:1], 0
	s_cselect_b32 s16, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v5, v7, v6
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_and_saveexec_b32 s17, s16
	s_cbranch_execz .LBB4_5
; %bb.3:                                ; %.lr.ph.preheader.i
                                        ;   in Loop: Header=BB4_2 Depth=1
	global_load_b32 v12, v[4:5], off
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_mov_b64 s[12:13], s[2:3]
.LBB4_4:                                ; %.lr.ph.i
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v13, v[10:11], off
	s_add_u32 s12, s12, -4
	s_addc_u32 s13, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[12:13], 0
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v13, v12
	v_dual_cndmask_b32 v12, v12, v13 :: v_dual_cndmask_b32 v7, v7, v11
	v_cndmask_b32_e32 v6, v6, v10, vcc_lo
	v_add_co_u32 v10, vcc_lo, v10, 4
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
	s_cbranch_scc1 .LBB4_4
.LBB4_5:                                ; %Flow93
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_and_saveexec_b32 s17, s16
	s_cbranch_execz .LBB4_8
; %bb.6:                                ; %.lr.ph.preheader.i61
                                        ;   in Loop: Header=BB4_2 Depth=1
	global_load_b32 v15, v[8:9], off
	v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v12, v8
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_mov_b64 s[12:13], s[2:3]
.LBB4_7:                                ; %.lr.ph.i63
                                        ;   Parent Loop BB4_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v16, v[12:13], off
	s_add_u32 s12, s12, -4
	s_addc_u32 s13, s13, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[12:13], 0
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v16, v15
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_dual_cndmask_b32 v11, v11, v13 :: v_dual_cndmask_b32 v10, v10, v12
	v_add_co_u32 v12, vcc_lo, v12, 4
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	s_cbranch_scc1 .LBB4_7
.LBB4_8:                                ; %Flow91
                                        ;   in Loop: Header=BB4_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	v_sub_co_u32 v4, vcc_lo, v6, v4
	v_sub_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
	v_sub_co_u32 v6, vcc_lo, v10, v8
	v_sub_co_ci_u32_e32 v7, vcc_lo, v11, v9, vcc_lo
	v_add_co_u32 v2, vcc_lo, 0x200, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	v_cndmask_b32_e64 v4, 0, 1.0, vcc_lo
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_f32_e32 v14, v14, v4
	s_or_b32 s15, vcc_lo, s15
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB4_2
; %bb.9:                                ; %Flow94
	s_or_b32 exec_lo, exec_lo, s15
.LBB4_10:                               ; %Flow95
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s14
	v_lshlrev_b32_e32 v2, 2, v0
	s_mov_b64 s[0:1], 0x100
	ds_store_b32 v2, v14
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB4_11:                               ; =>This Inner Loop Header: Depth=1
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u64_e64 s[0:1], v[0:1]
	s_cbranch_execz .LBB4_13
; %bb.12:                               ;   in Loop: Header=BB4_11 Depth=1
	v_lshl_add_u32 v3, s0, 2, v2
	ds_load_b32 v3, v3
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v3, v3, v4
	ds_store_b32 v2, v3
.LBB4_13:                               ;   in Loop: Header=BB4_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_u64_e64 s2, 0x42, s[0:1]
	s_lshr_b64 s[0:1], s[0:1], 1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB4_11
; %bb.14:
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e32 32, v0
	s_cbranch_execz .LBB4_16
; %bb.15:
	v_lshl_add_u32 v1, v0, 2, 0x80
	v_cmp_ne_u32_e64 s0, -1, v2
	s_mov_b64 s[2:3], src_shared_base
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e64 v4, 0, s3, s0
	v_cndmask_b32_e64 v3, 0, v2, s0
	v_cndmask_b32_e32 v5, 0, v1, vcc_lo
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 64, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 32, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 16, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 8, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v5
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v1, v1, v6
	v_cndmask_b32_e64 v6, 0, s3, vcc_lo
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v5, v[5:6] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v6, v[3:4] glc dlc
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, 4, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, -1, v1
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cndmask_b32_e64 v2, 0, s3, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v5, v5, v6
	flat_store_b32 v[3:4], v5 dlc
	s_waitcnt_vscnt null, 0x0
	flat_load_b32 v1, v[1:2] glc dlc
	s_waitcnt vmcnt(0)
	flat_load_b32 v2, v[3:4] glc dlc
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_f32_e32 v1, v1, v2
	flat_store_b32 v[3:4], v1 dlc
	s_waitcnt_vscnt null, 0x0
.LBB4_16:
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB4_18
; %bb.17:
	v_mov_b32_e32 v0, 0
	ds_load_b32 v1, v0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v0, v1, s[8:9]
.LBB4_18:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 40
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm,comdat
.Lfunc_end4:
	.size	_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm, .Lfunc_end4-_ZN3gpu12_GLOBAL__N_110argmax_accEPKfS2_Pfmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1108
; NumSgprs: 20
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.section	.text._ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm,comdat
	.globl	_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm ; -- Begin function _ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm
	.p2align	8
	.type	_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm,@function
_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm: ; @_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_u32 s0, s0, 32
	s_addc_u32 s1, s1, 0
	s_mov_b32 s3, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v2, 0
	v_cmpx_gt_u64_e64 s[10:11], v[1:2]
	s_cbranch_execz .LBB5_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b32 s0, s[0:1], 0x0
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[2:3], 2
.LBB5_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_u32 v5, vcc_lo, s4, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v7, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v1, vcc_lo, v1, s2
	global_load_b32 v0, v[5:6], off
	global_load_b32 v7, v[7:8], off
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
	v_add_co_u32 v5, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_u64_e32 vcc_lo, s[10:11], v[1:2]
	v_add_co_u32 v3, s0, v3, s12
	v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
	s_or_b32 s3, vcc_lo, s3
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v7
	global_store_b32 v[5:6], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB5_2
.LBB5_3:                                ; %Flow27
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm,"axG",@progbits,_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm,comdat
.Lfunc_end5:
	.size	_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm, .Lfunc_end5-_ZN3gpu12_GLOBAL__N_18vect_addEPKfS2_Pfm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 240
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm
    .private_segment_fixed_size: 0
    .sgpr_count:     11
    .sgpr_spill_count: 0
    .symbol:         _ZN3gpu12_GLOBAL__N_13mseEPKfS2_Pfm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZN3gpu12_GLOBAL__N_18mse_gradEPKfS2_Pfm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
