typedef int int32_t;
#define CUCL_GLOBAL_KERNEL extern "C" __global__
#define GASQ
#define GLOB_ID_1D (blockDim.x * blockIdx.x + threadIdx.x)
#define LOC_ID_1D (threadIdx.x)
#define GRP_ID_1D (blockIdx.x)
#define LOC_SZ_1D (blockDim.x)
#define LOCSHAR_MEM __shared__
#define LSMASQ
#define BARRIER_SYNC __syncthreads()
CUCL_GLOBAL_KERNEL void bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000( GASQ float const * const filts, // CUCL IN out_chan:in_chan:y:x
					  GASQ float const * const out_grad_loss, // CUCL IN img:chan:y:x
					 
					  GASQ float * const in_grad_loss ) // CUCL OUT img:chan:y:x
/* work */  // CUCL REF pels_blk:out_ix_blk:pels_tile:out_ix_tile:pels:out_ix
/* oix */  // CUCL REF in_chan:sy:sx
/* fioc */  // CUCL REF out_chan:ky:kx
{
  // CUCL IX pel_ix out_grad_loss use_dims=img:y:x
  // CUCL IX filt_elem_ix fioc
  // CUCL IX out_ix oix
  // CUCL IX GRP_ID_1D work use_dims=pels_blk:out_ix_blk
  // CUCL IX LOC_ID_1D work use_dims=pels_tile:out_ix_tile
  // note: <each thread handles> work use_dims=pels:out_out_ix; with pels_sz==out_chan_sz==t_tile_sz (currently); loops over in.chan==filts.in_chan

  LOCSHAR_MEM float in_smem[40];
  LOCSHAR_MEM float filts_smem[120];
  float out_tile[8*8] = {0}; // tile of output for this thread to compute, stored in registers
  // reg. buffers for one strip each from in and filts, for the same filts element
  float filts_strip[8]; // across output chans
  float in_strip[8]; // across pels (approx square block in x/y space, favoring x if sqrt() not integer)

  int32_t const blk_out_ix = (GRP_ID_1D%9)*15*8;
  int32_t const blk_pel_ix = (GRP_ID_1D/9)*5*8;

  for( int32_t filt_elem_ix = 0; filt_elem_ix != 1024; ++filt_elem_ix ) {
    BARRIER_SYNC;
    for( int32_t i = 0; i != 1; ++i ) {
      if( (LOC_ID_1D+LOC_SZ_1D*i) < 40 ) { 
	int32_t const pel_ix = (blk_pel_ix+LOC_ID_1D+LOC_SZ_1D*i);
	float v = 0;
	int const smem_in_ix_y = ((pel_ix/6)%6)+(filt_elem_ix%1) - 0;
	int const smem_in_ix_x = (pel_ix%6)+(filt_elem_ix%1) - 0;
	if(smem_in_ix_y >= 0 && smem_in_ix_x >= 0 && (pel_ix/36) < 1 &&
	   smem_in_ix_x < 6 && smem_in_ix_y < 6 ) {
	  v = out_grad_loss[(pel_ix/36)*36000 +
			    filt_elem_ix*36 +
			    smem_in_ix_y*6 +
			    smem_in_ix_x*1];
	}
	in_smem[LOC_ID_1D+LOC_SZ_1D*i] = v;
      }
    }
    for( int32_t i = 0; i != 2; ++i ) {
      if( (LOC_ID_1D+LOC_SZ_1D*i) < 120 ) { 
	int32_t const out_ix = (blk_out_ix+LOC_ID_1D+LOC_SZ_1D*i);
	float v = 0;
	int const smem_filt_ix_y = (out_ix%1)+(filt_elem_ix%1)*1;
	int const smem_filt_ix_x = (out_ix%1)+(filt_elem_ix%1)*1;
	if( out_ix < 1024 && filt_elem_ix < 1000
	    && smem_filt_ix_x < 1 && smem_filt_ix_y < 1 ) {
	  v = filts[filt_elem_ix*1024 +
		    out_ix*1 + 
		    smem_filt_ix_y*1 +
		    smem_filt_ix_x*1];
	}
	filts_smem[LOC_ID_1D+LOC_SZ_1D*i] = v;
      }
    }

    BARRIER_SYNC;
    // begin loads
   filts_strip[0] = filts_smem[(LOC_ID_1D%15)*8+0];
   filts_strip[1] = filts_smem[(LOC_ID_1D%15)*8+1];
   filts_strip[2] = filts_smem[(LOC_ID_1D%15)*8+2];
   filts_strip[3] = filts_smem[(LOC_ID_1D%15)*8+3];
   filts_strip[4] = filts_smem[(LOC_ID_1D%15)*8+4];
   filts_strip[5] = filts_smem[(LOC_ID_1D%15)*8+5];
   filts_strip[6] = filts_smem[(LOC_ID_1D%15)*8+6];
   filts_strip[7] = filts_smem[(LOC_ID_1D%15)*8+7];
   in_strip[0] = in_smem[(LOC_ID_1D/15)*8+0];
   in_strip[1] = in_smem[(LOC_ID_1D/15)*8+1];
   in_strip[2] = in_smem[(LOC_ID_1D/15)*8+2];
   in_strip[3] = in_smem[(LOC_ID_1D/15)*8+3];
   in_strip[4] = in_smem[(LOC_ID_1D/15)*8+4];
   in_strip[5] = in_smem[(LOC_ID_1D/15)*8+5];
   in_strip[6] = in_smem[(LOC_ID_1D/15)*8+6];
   in_strip[7] = in_smem[(LOC_ID_1D/15)*8+7];
    // end loads;
    // begin fmas
   out_tile[0] += filts_strip[0]*in_strip[0];
   out_tile[1] += filts_strip[1]*in_strip[0];
   out_tile[2] += filts_strip[2]*in_strip[0];
   out_tile[3] += filts_strip[3]*in_strip[0];
   out_tile[4] += filts_strip[4]*in_strip[0];
   out_tile[5] += filts_strip[5]*in_strip[0];
   out_tile[6] += filts_strip[6]*in_strip[0];
   out_tile[7] += filts_strip[7]*in_strip[0];
   out_tile[8] += filts_strip[0]*in_strip[1];
   out_tile[9] += filts_strip[1]*in_strip[1];
   out_tile[10] += filts_strip[2]*in_strip[1];
   out_tile[11] += filts_strip[3]*in_strip[1];
   out_tile[12] += filts_strip[4]*in_strip[1];
   out_tile[13] += filts_strip[5]*in_strip[1];
   out_tile[14] += filts_strip[6]*in_strip[1];
   out_tile[15] += filts_strip[7]*in_strip[1];
   out_tile[16] += filts_strip[0]*in_strip[2];
   out_tile[17] += filts_strip[1]*in_strip[2];
   out_tile[18] += filts_strip[2]*in_strip[2];
   out_tile[19] += filts_strip[3]*in_strip[2];
   out_tile[20] += filts_strip[4]*in_strip[2];
   out_tile[21] += filts_strip[5]*in_strip[2];
   out_tile[22] += filts_strip[6]*in_strip[2];
   out_tile[23] += filts_strip[7]*in_strip[2];
   out_tile[24] += filts_strip[0]*in_strip[3];
   out_tile[25] += filts_strip[1]*in_strip[3];
   out_tile[26] += filts_strip[2]*in_strip[3];
   out_tile[27] += filts_strip[3]*in_strip[3];
   out_tile[28] += filts_strip[4]*in_strip[3];
   out_tile[29] += filts_strip[5]*in_strip[3];
   out_tile[30] += filts_strip[6]*in_strip[3];
   out_tile[31] += filts_strip[7]*in_strip[3];
   out_tile[32] += filts_strip[0]*in_strip[4];
   out_tile[33] += filts_strip[1]*in_strip[4];
   out_tile[34] += filts_strip[2]*in_strip[4];
   out_tile[35] += filts_strip[3]*in_strip[4];
   out_tile[36] += filts_strip[4]*in_strip[4];
   out_tile[37] += filts_strip[5]*in_strip[4];
   out_tile[38] += filts_strip[6]*in_strip[4];
   out_tile[39] += filts_strip[7]*in_strip[4];
   out_tile[40] += filts_strip[0]*in_strip[5];
   out_tile[41] += filts_strip[1]*in_strip[5];
   out_tile[42] += filts_strip[2]*in_strip[5];
   out_tile[43] += filts_strip[3]*in_strip[5];
   out_tile[44] += filts_strip[4]*in_strip[5];
   out_tile[45] += filts_strip[5]*in_strip[5];
   out_tile[46] += filts_strip[6]*in_strip[5];
   out_tile[47] += filts_strip[7]*in_strip[5];
   out_tile[48] += filts_strip[0]*in_strip[6];
   out_tile[49] += filts_strip[1]*in_strip[6];
   out_tile[50] += filts_strip[2]*in_strip[6];
   out_tile[51] += filts_strip[3]*in_strip[6];
   out_tile[52] += filts_strip[4]*in_strip[6];
   out_tile[53] += filts_strip[5]*in_strip[6];
   out_tile[54] += filts_strip[6]*in_strip[6];
   out_tile[55] += filts_strip[7]*in_strip[6];
   out_tile[56] += filts_strip[0]*in_strip[7];
   out_tile[57] += filts_strip[1]*in_strip[7];
   out_tile[58] += filts_strip[2]*in_strip[7];
   out_tile[59] += filts_strip[3]*in_strip[7];
   out_tile[60] += filts_strip[4]*in_strip[7];
   out_tile[61] += filts_strip[5]*in_strip[7];
   out_tile[62] += filts_strip[6]*in_strip[7];
   out_tile[63] += filts_strip[7]*in_strip[7];
    // end fmas;
  }

  int32_t pel_ix = blk_pel_ix + (LOC_ID_1D/15)*8; // first pel_ix for this thread
  int32_t igl_y, igl_x;
  for( int32_t work_pel = 0; work_pel < 8; ++work_pel, ++pel_ix) {
    int32_t out_ix = blk_out_ix + (LOC_ID_1D%15)*8; // first out_ix for this thread
    // begin outs_to_filts_strip
   switch(work_pel) { 
   filts_strip[0] = out_tile[0];
   filts_strip[1] = out_tile[1];
   filts_strip[2] = out_tile[2];
   filts_strip[3] = out_tile[3];
   filts_strip[4] = out_tile[4];
   filts_strip[5] = out_tile[5];
   filts_strip[6] = out_tile[6];
   filts_strip[7] = out_tile[7];
   break;
   filts_strip[0] = out_tile[8];
   filts_strip[1] = out_tile[9];
   filts_strip[2] = out_tile[10];
   filts_strip[3] = out_tile[11];
   filts_strip[4] = out_tile[12];
   filts_strip[5] = out_tile[13];
   filts_strip[6] = out_tile[14];
   filts_strip[7] = out_tile[15];
   break;
   filts_strip[0] = out_tile[16];
   filts_strip[1] = out_tile[17];
   filts_strip[2] = out_tile[18];
   filts_strip[3] = out_tile[19];
   filts_strip[4] = out_tile[20];
   filts_strip[5] = out_tile[21];
   filts_strip[6] = out_tile[22];
   filts_strip[7] = out_tile[23];
   break;
   filts_strip[0] = out_tile[24];
   filts_strip[1] = out_tile[25];
   filts_strip[2] = out_tile[26];
   filts_strip[3] = out_tile[27];
   filts_strip[4] = out_tile[28];
   filts_strip[5] = out_tile[29];
   filts_strip[6] = out_tile[30];
   filts_strip[7] = out_tile[31];
   break;
   filts_strip[0] = out_tile[32];
   filts_strip[1] = out_tile[33];
   filts_strip[2] = out_tile[34];
   filts_strip[3] = out_tile[35];
   filts_strip[4] = out_tile[36];
   filts_strip[5] = out_tile[37];
   filts_strip[6] = out_tile[38];
   filts_strip[7] = out_tile[39];
   break;
   filts_strip[0] = out_tile[40];
   filts_strip[1] = out_tile[41];
   filts_strip[2] = out_tile[42];
   filts_strip[3] = out_tile[43];
   filts_strip[4] = out_tile[44];
   filts_strip[5] = out_tile[45];
   filts_strip[6] = out_tile[46];
   filts_strip[7] = out_tile[47];
   break;
   filts_strip[0] = out_tile[48];
   filts_strip[1] = out_tile[49];
   filts_strip[2] = out_tile[50];
   filts_strip[3] = out_tile[51];
   filts_strip[4] = out_tile[52];
   filts_strip[5] = out_tile[53];
   filts_strip[6] = out_tile[54];
   filts_strip[7] = out_tile[55];
   break;
   filts_strip[0] = out_tile[56];
   filts_strip[1] = out_tile[57];
   filts_strip[2] = out_tile[58];
   filts_strip[3] = out_tile[59];
   filts_strip[4] = out_tile[60];
   filts_strip[5] = out_tile[61];
   filts_strip[6] = out_tile[62];
   filts_strip[7] = out_tile[63];
   break;
   } 
    // end outs_to_filts_strip;
    // begin stores
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[0];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[1];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[2];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[3];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[4];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[5];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[6];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[7];
};
   ++out_ix;
    // end stores;
  }
}

	.file	"tmpxft_0036a790_00000000-6_nvrtc_ICE_on_bad_swtich.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z88__device_stub__Z62bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000PKfS0_PfPKfS0_Pf
	.type	_Z88__device_stub__Z62bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000PKfS0_PfPKfS0_Pf, @function
_Z88__device_stub__Z62bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000PKfS0_PfPKfS0_Pf:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z88__device_stub__Z62bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000PKfS0_PfPKfS0_Pf, .-_Z88__device_stub__Z62bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000PKfS0_PfPKfS0_Pf
	.globl	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.type	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000, @function
bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z88__device_stub__Z62bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000PKfS0_PfPKfS0_Pf
	.cfi_endproc
.LFE2033:
	.size	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000, .-bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
typedef int int32_t;
#define CUCL_GLOBAL_KERNEL extern "C" __global__
#define GASQ
#define GLOB_ID_1D (blockDim.x * blockIdx.x + threadIdx.x)
#define LOC_ID_1D (threadIdx.x)
#define GRP_ID_1D (blockIdx.x)
#define LOC_SZ_1D (blockDim.x)
#define LOCSHAR_MEM __shared__
#define LSMASQ
#define BARRIER_SYNC __syncthreads()
CUCL_GLOBAL_KERNEL void bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000( GASQ float const * const filts, // CUCL IN out_chan:in_chan:y:x
					  GASQ float const * const out_grad_loss, // CUCL IN img:chan:y:x
					 
					  GASQ float * const in_grad_loss ) // CUCL OUT img:chan:y:x
/* work */  // CUCL REF pels_blk:out_ix_blk:pels_tile:out_ix_tile:pels:out_ix
/* oix */  // CUCL REF in_chan:sy:sx
/* fioc */  // CUCL REF out_chan:ky:kx
{
  // CUCL IX pel_ix out_grad_loss use_dims=img:y:x
  // CUCL IX filt_elem_ix fioc
  // CUCL IX out_ix oix
  // CUCL IX GRP_ID_1D work use_dims=pels_blk:out_ix_blk
  // CUCL IX LOC_ID_1D work use_dims=pels_tile:out_ix_tile
  // note: <each thread handles> work use_dims=pels:out_out_ix; with pels_sz==out_chan_sz==t_tile_sz (currently); loops over in.chan==filts.in_chan

  LOCSHAR_MEM float in_smem[40];
  LOCSHAR_MEM float filts_smem[120];
  float out_tile[8*8] = {0}; // tile of output for this thread to compute, stored in registers
  // reg. buffers for one strip each from in and filts, for the same filts element
  float filts_strip[8]; // across output chans
  float in_strip[8]; // across pels (approx square block in x/y space, favoring x if sqrt() not integer)

  int32_t const blk_out_ix = (GRP_ID_1D%9)*15*8;
  int32_t const blk_pel_ix = (GRP_ID_1D/9)*5*8;

  for( int32_t filt_elem_ix = 0; filt_elem_ix != 1024; ++filt_elem_ix ) {
    BARRIER_SYNC;
    for( int32_t i = 0; i != 1; ++i ) {
      if( (LOC_ID_1D+LOC_SZ_1D*i) < 40 ) { 
	int32_t const pel_ix = (blk_pel_ix+LOC_ID_1D+LOC_SZ_1D*i);
	float v = 0;
	int const smem_in_ix_y = ((pel_ix/6)%6)+(filt_elem_ix%1) - 0;
	int const smem_in_ix_x = (pel_ix%6)+(filt_elem_ix%1) - 0;
	if(smem_in_ix_y >= 0 && smem_in_ix_x >= 0 && (pel_ix/36) < 1 &&
	   smem_in_ix_x < 6 && smem_in_ix_y < 6 ) {
	  v = out_grad_loss[(pel_ix/36)*36000 +
			    filt_elem_ix*36 +
			    smem_in_ix_y*6 +
			    smem_in_ix_x*1];
	}
	in_smem[LOC_ID_1D+LOC_SZ_1D*i] = v;
      }
    }
    for( int32_t i = 0; i != 2; ++i ) {
      if( (LOC_ID_1D+LOC_SZ_1D*i) < 120 ) { 
	int32_t const out_ix = (blk_out_ix+LOC_ID_1D+LOC_SZ_1D*i);
	float v = 0;
	int const smem_filt_ix_y = (out_ix%1)+(filt_elem_ix%1)*1;
	int const smem_filt_ix_x = (out_ix%1)+(filt_elem_ix%1)*1;
	if( out_ix < 1024 && filt_elem_ix < 1000
	    && smem_filt_ix_x < 1 && smem_filt_ix_y < 1 ) {
	  v = filts[filt_elem_ix*1024 +
		    out_ix*1 + 
		    smem_filt_ix_y*1 +
		    smem_filt_ix_x*1];
	}
	filts_smem[LOC_ID_1D+LOC_SZ_1D*i] = v;
      }
    }

    BARRIER_SYNC;
    // begin loads
   filts_strip[0] = filts_smem[(LOC_ID_1D%15)*8+0];
   filts_strip[1] = filts_smem[(LOC_ID_1D%15)*8+1];
   filts_strip[2] = filts_smem[(LOC_ID_1D%15)*8+2];
   filts_strip[3] = filts_smem[(LOC_ID_1D%15)*8+3];
   filts_strip[4] = filts_smem[(LOC_ID_1D%15)*8+4];
   filts_strip[5] = filts_smem[(LOC_ID_1D%15)*8+5];
   filts_strip[6] = filts_smem[(LOC_ID_1D%15)*8+6];
   filts_strip[7] = filts_smem[(LOC_ID_1D%15)*8+7];
   in_strip[0] = in_smem[(LOC_ID_1D/15)*8+0];
   in_strip[1] = in_smem[(LOC_ID_1D/15)*8+1];
   in_strip[2] = in_smem[(LOC_ID_1D/15)*8+2];
   in_strip[3] = in_smem[(LOC_ID_1D/15)*8+3];
   in_strip[4] = in_smem[(LOC_ID_1D/15)*8+4];
   in_strip[5] = in_smem[(LOC_ID_1D/15)*8+5];
   in_strip[6] = in_smem[(LOC_ID_1D/15)*8+6];
   in_strip[7] = in_smem[(LOC_ID_1D/15)*8+7];
    // end loads;
    // begin fmas
   out_tile[0] += filts_strip[0]*in_strip[0];
   out_tile[1] += filts_strip[1]*in_strip[0];
   out_tile[2] += filts_strip[2]*in_strip[0];
   out_tile[3] += filts_strip[3]*in_strip[0];
   out_tile[4] += filts_strip[4]*in_strip[0];
   out_tile[5] += filts_strip[5]*in_strip[0];
   out_tile[6] += filts_strip[6]*in_strip[0];
   out_tile[7] += filts_strip[7]*in_strip[0];
   out_tile[8] += filts_strip[0]*in_strip[1];
   out_tile[9] += filts_strip[1]*in_strip[1];
   out_tile[10] += filts_strip[2]*in_strip[1];
   out_tile[11] += filts_strip[3]*in_strip[1];
   out_tile[12] += filts_strip[4]*in_strip[1];
   out_tile[13] += filts_strip[5]*in_strip[1];
   out_tile[14] += filts_strip[6]*in_strip[1];
   out_tile[15] += filts_strip[7]*in_strip[1];
   out_tile[16] += filts_strip[0]*in_strip[2];
   out_tile[17] += filts_strip[1]*in_strip[2];
   out_tile[18] += filts_strip[2]*in_strip[2];
   out_tile[19] += filts_strip[3]*in_strip[2];
   out_tile[20] += filts_strip[4]*in_strip[2];
   out_tile[21] += filts_strip[5]*in_strip[2];
   out_tile[22] += filts_strip[6]*in_strip[2];
   out_tile[23] += filts_strip[7]*in_strip[2];
   out_tile[24] += filts_strip[0]*in_strip[3];
   out_tile[25] += filts_strip[1]*in_strip[3];
   out_tile[26] += filts_strip[2]*in_strip[3];
   out_tile[27] += filts_strip[3]*in_strip[3];
   out_tile[28] += filts_strip[4]*in_strip[3];
   out_tile[29] += filts_strip[5]*in_strip[3];
   out_tile[30] += filts_strip[6]*in_strip[3];
   out_tile[31] += filts_strip[7]*in_strip[3];
   out_tile[32] += filts_strip[0]*in_strip[4];
   out_tile[33] += filts_strip[1]*in_strip[4];
   out_tile[34] += filts_strip[2]*in_strip[4];
   out_tile[35] += filts_strip[3]*in_strip[4];
   out_tile[36] += filts_strip[4]*in_strip[4];
   out_tile[37] += filts_strip[5]*in_strip[4];
   out_tile[38] += filts_strip[6]*in_strip[4];
   out_tile[39] += filts_strip[7]*in_strip[4];
   out_tile[40] += filts_strip[0]*in_strip[5];
   out_tile[41] += filts_strip[1]*in_strip[5];
   out_tile[42] += filts_strip[2]*in_strip[5];
   out_tile[43] += filts_strip[3]*in_strip[5];
   out_tile[44] += filts_strip[4]*in_strip[5];
   out_tile[45] += filts_strip[5]*in_strip[5];
   out_tile[46] += filts_strip[6]*in_strip[5];
   out_tile[47] += filts_strip[7]*in_strip[5];
   out_tile[48] += filts_strip[0]*in_strip[6];
   out_tile[49] += filts_strip[1]*in_strip[6];
   out_tile[50] += filts_strip[2]*in_strip[6];
   out_tile[51] += filts_strip[3]*in_strip[6];
   out_tile[52] += filts_strip[4]*in_strip[6];
   out_tile[53] += filts_strip[5]*in_strip[6];
   out_tile[54] += filts_strip[6]*in_strip[6];
   out_tile[55] += filts_strip[7]*in_strip[6];
   out_tile[56] += filts_strip[0]*in_strip[7];
   out_tile[57] += filts_strip[1]*in_strip[7];
   out_tile[58] += filts_strip[2]*in_strip[7];
   out_tile[59] += filts_strip[3]*in_strip[7];
   out_tile[60] += filts_strip[4]*in_strip[7];
   out_tile[61] += filts_strip[5]*in_strip[7];
   out_tile[62] += filts_strip[6]*in_strip[7];
   out_tile[63] += filts_strip[7]*in_strip[7];
    // end fmas;
  }

  int32_t pel_ix = blk_pel_ix + (LOC_ID_1D/15)*8; // first pel_ix for this thread
  int32_t igl_y, igl_x;
  for( int32_t work_pel = 0; work_pel < 8; ++work_pel, ++pel_ix) {
    int32_t out_ix = blk_out_ix + (LOC_ID_1D%15)*8; // first out_ix for this thread
    // begin outs_to_filts_strip
   switch(work_pel) { 
   filts_strip[0] = out_tile[0];
   filts_strip[1] = out_tile[1];
   filts_strip[2] = out_tile[2];
   filts_strip[3] = out_tile[3];
   filts_strip[4] = out_tile[4];
   filts_strip[5] = out_tile[5];
   filts_strip[6] = out_tile[6];
   filts_strip[7] = out_tile[7];
   break;
   filts_strip[0] = out_tile[8];
   filts_strip[1] = out_tile[9];
   filts_strip[2] = out_tile[10];
   filts_strip[3] = out_tile[11];
   filts_strip[4] = out_tile[12];
   filts_strip[5] = out_tile[13];
   filts_strip[6] = out_tile[14];
   filts_strip[7] = out_tile[15];
   break;
   filts_strip[0] = out_tile[16];
   filts_strip[1] = out_tile[17];
   filts_strip[2] = out_tile[18];
   filts_strip[3] = out_tile[19];
   filts_strip[4] = out_tile[20];
   filts_strip[5] = out_tile[21];
   filts_strip[6] = out_tile[22];
   filts_strip[7] = out_tile[23];
   break;
   filts_strip[0] = out_tile[24];
   filts_strip[1] = out_tile[25];
   filts_strip[2] = out_tile[26];
   filts_strip[3] = out_tile[27];
   filts_strip[4] = out_tile[28];
   filts_strip[5] = out_tile[29];
   filts_strip[6] = out_tile[30];
   filts_strip[7] = out_tile[31];
   break;
   filts_strip[0] = out_tile[32];
   filts_strip[1] = out_tile[33];
   filts_strip[2] = out_tile[34];
   filts_strip[3] = out_tile[35];
   filts_strip[4] = out_tile[36];
   filts_strip[5] = out_tile[37];
   filts_strip[6] = out_tile[38];
   filts_strip[7] = out_tile[39];
   break;
   filts_strip[0] = out_tile[40];
   filts_strip[1] = out_tile[41];
   filts_strip[2] = out_tile[42];
   filts_strip[3] = out_tile[43];
   filts_strip[4] = out_tile[44];
   filts_strip[5] = out_tile[45];
   filts_strip[6] = out_tile[46];
   filts_strip[7] = out_tile[47];
   break;
   filts_strip[0] = out_tile[48];
   filts_strip[1] = out_tile[49];
   filts_strip[2] = out_tile[50];
   filts_strip[3] = out_tile[51];
   filts_strip[4] = out_tile[52];
   filts_strip[5] = out_tile[53];
   filts_strip[6] = out_tile[54];
   filts_strip[7] = out_tile[55];
   break;
   filts_strip[0] = out_tile[56];
   filts_strip[1] = out_tile[57];
   filts_strip[2] = out_tile[58];
   filts_strip[3] = out_tile[59];
   filts_strip[4] = out_tile[60];
   filts_strip[5] = out_tile[61];
   filts_strip[6] = out_tile[62];
   filts_strip[7] = out_tile[63];
   break;
   } 
    // end outs_to_filts_strip;
    // begin stores
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[0];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[1];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[2];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[3];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[4];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[5];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[6];
};
   ++out_ix;
   
  igl_y = (((pel_ix/6)%6)-0)*1+(out_ix%1);
  igl_x = ((pel_ix%6)-0)*1+(out_ix%1);
  if( igl_x >= 0 && igl_y >= 0 && igl_y < 6 && igl_x < 6 &&
      out_ix < 1024 && (pel_ix/36) < 1 ) {
    in_grad_loss[ (pel_ix/36)*36864 + out_ix*36 + 
		  igl_y*6 + igl_x*1] = filts_strip[7];
};
   ++out_ix;
    // end stores;
  }
}

	.text
	.file	"nvrtc_ICE_on_bad_swtich.hip"
	.globl	__device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000 # -- Begin function __device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.type	__device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000,@function
__device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000: # @__device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000, .Lfunc_end0-__device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000,@object # @bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.section	.rodata,"a",@progbits
	.globl	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.p2align	3, 0x0
bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000:
	.quad	__device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.size	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000"
	.size	.L__unnamed_1, 63

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000 ; -- Begin function bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.globl	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
	.p2align	8
	.type	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000,@function
bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000: ; @bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x0
	s_mul_hi_u32 s4, s15, 0x38e38e39
	v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
	s_lshr_b32 s4, s4, 1
	s_mov_b32 s6, 0
	s_mul_i32 s7, s4, 9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s8, s15, s7
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s5, 0xffff
	s_mul_i32 s5, s8, 0x78
	s_lshl_b32 s8, s7, 2
	s_mov_b32 s9, s5
.LBB0_1:                                ; %.critedge
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v5, v0
	s_cmpk_lt_u32 s6, 0x3e8
	s_mov_b32 s11, 2
	s_cselect_b32 s10, -1, 0
	s_barrier
	buffer_gl0_inv
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s12, exec_lo
	v_cmpx_gt_u32_e32 0x78, v5
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=2
	v_add_nc_u32_e32 v1, s5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, 0x400, v1
	v_mov_b32_e32 v1, 0
	s_and_b32 s14, s10, vcc_lo
	s_and_saveexec_b32 s13, s14
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=2
	v_add_nc_u32_e32 v1, s9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_add_co_u32 v6, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	global_load_b32 v1, v[6:7], off
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=2
	s_or_b32 exec_lo, exec_lo, s12
	v_add_nc_u32_e32 v5, s7, v5
	v_add_nc_u32_e32 v4, s8, v4
	s_add_i32 s11, s11, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, 0
	s_cbranch_scc0 .LBB0_2
; %bb.7:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s6, s6, 1
	s_addk_i32 s9, 0x400
	s_cmpk_eq_i32 s6, 0x400
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_1
; %bb.8:
	v_mul_u32_u24_e32 v1, 0x1112, v0
	s_load_b64 s[10:11], s[0:1], 0x10
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 16, v1
	v_mul_lo_u16 v2, v1, 15
	v_lshlrev_b16 v1, 3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u16 v0, v0, v2
	v_lshlrev_b16 v0, 3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v2, 0xffff, v0
	v_and_b32_e32 v0, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v4, 2, v2
	v_add_nc_u32_e32 v11, s5, v2
	v_mad_u64_u32 v[8:9], null, s4, 40, v[0:1]
	ds_load_b128 v[0:3], v4
	ds_load_b128 v[4:7], v4 offset:16
	v_or_b32_e32 v12, 3, v11
	v_or_b32_e32 v13, 4, v11
	v_or_b32_e32 v9, 1, v11
	v_or_b32_e32 v10, 2, v11
	v_or_b32_e32 v14, 7, v11
	v_cmp_gt_u32_e64 s2, 0x400, v12
	v_cmp_gt_u32_e64 s3, 0x400, v13
	v_or_b32_e32 v12, 5, v11
	v_or_b32_e32 v13, 6, v11
	v_cmp_gt_u32_e64 s0, 0x400, v9
	v_cmp_gt_u32_e64 s1, 0x400, v10
	v_mad_u64_u32 v[9:10], null, v11, 36, v[8:9]
	v_cmp_gt_u32_e32 vcc_lo, 0x400, v11
	v_cmp_gt_u32_e64 s4, 0x400, v12
	v_cmp_gt_u32_e64 s5, 0x400, v13
	v_cmp_gt_u32_e64 s6, 0x400, v14
.LBB0_9:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v12, s12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_i32 v10, 0x2aaaaaab, v12
	v_cmp_gt_i32_e64 s8, 36, v12
	v_lshrrev_b32_e32 v11, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v11, v10, v11
	v_mul_hi_i32 v10, 0x2aaaaaab, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v13, 31, v10
	v_add_nc_u32_e32 v10, v10, v13
	v_mad_u64_u32 v[13:14], null, v11, -6, v[12:13]
	v_mul_hi_i32 v14, 0x38e38e39, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v10, 6
	v_lshrrev_b32_e32 v12, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v11, v10
	v_mul_lo_u32 v11, v11, 6
	v_or_b32_e32 v13, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_i32_e64 s7, -1, v13
	v_ashrrev_i32_e32 v13, 3, v14
	s_and_b32 s9, s7, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s8
	s_and_saveexec_b32 s13, s9
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v14, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v14, 0x9000, v14
	v_mad_i32_i24 v14, v10, 6, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, v14, v11
	v_add3_u32 v14, v9, s12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v14, s9, s10, v14
	v_add_co_ci_u32_e64 v15, s9, s11, v15, s9
	global_store_b32 v[14:15], v0, off
.LBB0_11:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_add_nc_u32_e32 v14, s12, v9
	s_and_b32 s9, s7, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s8
	s_and_saveexec_b32 s13, s9
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v15, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, 0x9000, v15
	v_mad_i32_i24 v15, v10, 6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v11
	v_add3_u32 v15, v14, v15, 36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s9, s10, v15
	v_add_co_ci_u32_e64 v16, s9, s11, v16, s9
	global_store_b32 v[15:16], v1, off
.LBB0_13:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_b32 s9, s7, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s8
	s_and_saveexec_b32 s13, s9
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v15, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, 0x9000, v15
	v_mad_i32_i24 v15, v10, 6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v11
	v_add3_u32 v15, v14, v15, 0x48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s9, s10, v15
	v_add_co_ci_u32_e64 v16, s9, s11, v16, s9
	global_store_b32 v[15:16], v2, off
.LBB0_15:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_b32 s9, s7, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s8
	s_and_saveexec_b32 s13, s9
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v15, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, 0x9000, v15
	v_mad_i32_i24 v15, v10, 6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v11
	v_add3_u32 v15, v14, v15, 0x6c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s9, s10, v15
	v_add_co_ci_u32_e64 v16, s9, s11, v16, s9
	global_store_b32 v[15:16], v3, off
.LBB0_17:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_b32 s9, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s8
	s_and_saveexec_b32 s13, s9
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v15, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, 0x9000, v15
	v_mad_i32_i24 v15, v10, 6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v11
	v_add3_u32 v15, v14, v15, 0x90
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s9, s10, v15
	v_add_co_ci_u32_e64 v16, s9, s11, v16, s9
	global_store_b32 v[15:16], v4, off
.LBB0_19:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_b32 s9, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s8
	s_and_saveexec_b32 s13, s9
	s_cbranch_execz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v15, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, 0x9000, v15
	v_mad_i32_i24 v15, v10, 6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v11
	v_add3_u32 v15, v14, v15, 0xb4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s9, s10, v15
	v_add_co_ci_u32_e64 v16, s9, s11, v16, s9
	global_store_b32 v[15:16], v5, off
.LBB0_21:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_b32 s9, s7, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, s9, s8
	s_and_saveexec_b32 s13, s9
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v15, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v15, 0x9000, v15
	v_mad_i32_i24 v15, v10, 6, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v11
	v_add3_u32 v15, v14, v15, 0xd8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v15, s9, s10, v15
	v_add_co_ci_u32_e64 v16, s9, s11, v16, s9
	global_store_b32 v[15:16], v6, off
.LBB0_23:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_b32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, s7, s8
	s_and_saveexec_b32 s8, s7
	s_cbranch_execz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_9 Depth=1
	v_add_nc_u32_e32 v12, v13, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v12, 0x9000, v12
	v_mad_i32_i24 v10, v10, 6, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v10, v11
	v_add3_u32 v10, v14, v10, 0xfc
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s7, s10, v10
	v_add_co_ci_u32_e64 v11, s7, s11, v11, s7
	global_store_b32 v[10:11], v7, off
.LBB0_25:                               ;   in Loop: Header=BB0_9 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 8
	s_cbranch_scc0 .LBB0_9
; %bb.26:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
		.amdhsa_group_segment_fixed_size 480
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000, .Lfunc_end0-bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1648
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 480 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 480
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         bconv__out_chan_1000__in_chan_1024__y_1__x_1__img_1__chan_1000.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     17
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
