// CUDA-C includes
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>

__device__ int find_minLri(int *Lrpr, uint16_t m_u16TotalDisp) {
    int minLri = INT_MAX;
    for (int i=0; i<m_u16TotalDisp; i++) {
        if (minLri > Lrpr[i]) {
            minLri = Lrpr[i];
        }
    }
    return minLri;
} // end find_minLri()

__device__ int find_min(int a, int b, int c, int d) {
    int minimum = a;
    if (minimum > b)
        minimum = b;
    if (minimum > c)
        minimum = c;
    if (minimum > d)
        minimum = d;
    return minimum;
} // end find_min()

__global__ void cost_computation(int *Lr, int *initCost, uint8_t m_u8Directions, uint8_t m_u8DEBUGLeftNeighbor,
                                 uint16_t m_u16height_after_census, uint16_t m_u16width_after_census,
                                 uint16_t m_u16TotalDisp, uint8_t m_u16P1, uint8_t m_u16P2) {
    //#######################################################################################
    //          SGBM Cost Computation
    //#######################################################################################

    int r = blockIdx.x * blockDim.x + threadIdx.x;

    // Computing cost along 5 directions only. (i,j-1) (i-1,j-1) (i-1,j) (i-1,j+1) (i,j+1)
    __shared__ int iDisp, jDisp;

    if (r < m_u8Directions) {
    //for (int r=0; r<m_u8Directions; r++) {
        if (r==0) {
            iDisp = 0; jDisp = 0-m_u8DEBUGLeftNeighbor;
        }
        else if (r==1) {
            iDisp = -1; jDisp = -1;
        }
        else if (r==2) {
            iDisp = -1; jDisp = 0;
        }
        else if (r==3) {
            iDisp = -1; jDisp = 1;
        }
        else if (r==4) {
            iDisp = 0; jDisp = 1;
        }
        //if (i < m_u16height_after_census) {
        for (int i=0; i<m_u16height_after_census; i++) {
            //if (i < m_u16width_after_census) {
            for (int j=0; j<m_u16width_after_census; j++) {
                // Compute p-r
                int iNorm = i + iDisp; //height
                int jNorm = j + jDisp; //width
                int *Lrpr = Lr+((r*m_u16height_after_census+iNorm)*m_u16width_after_census+jNorm)*m_u16TotalDisp;

                //#######################################################################################
                //         Find min_k{Lr(p-r,k)}
                //#######################################################################################
                //if (d < m_u16TotalDisp) {
                for (int d=0; d<m_u16TotalDisp; d++) {
                    int Cpd = initCost[(i*m_u16width_after_census+j)*m_u16TotalDisp+d];

                    int tmp;
                    if ( (((r==0)||(r==1))&&(jNorm<0)) || (((r==1)||(r==2)||(r==3))&&(i==0)) || ((r==3)&&(j==m_u16width_after_census-1)))
                    {
                        tmp = Cpd;
                    } else {
                        int minLri = find_minLri(Lrpr, m_u16TotalDisp);
                        int Lrpdm1, Lrpdp1;
                        if (d==0)
                            Lrpdm1 = INT_MAX-m_u16P1;
                        else
                            Lrpdm1 = Lrpr[d-1];
                        if (d==m_u16TotalDisp-1)
                            Lrpdp1 = INT_MAX-m_u16P1;
                        else
                            Lrpdp1 = Lrpr[d+1];

                        int v1 = find_min(Lrpr[d], Lrpdm1+m_u16P1, Lrpdp1+m_u16P1, minLri+m_u16P2);

                        tmp = Cpd + v1 - minLri;
                    }
                    Lr[((r*m_u16height_after_census+i)*m_u16width_after_census+j)*m_u16TotalDisp+d] = tmp;
                }
            }
        }
    }
} // end cost_computation()

__device__ int compute_hamming_distance (uint64_t a, uint64_t b)
{
    //#######################################################################################
    //Hamming Distance as cost initialization
    //#######################################################################################
    uint64_t tmp;
    int sum = 0;

    tmp = a^b;
    for(int i=0;i<64;i++){
        if(tmp&0x1<<i){
            sum ++;
        }
    }
    return sum;
} // end compute_hamming_distance()



__global__ void compute_hamming(uint64_t *ct1, uint64_t *ct2, int *accumulatedCost,
                                uint64_t m_u16yMin, uint64_t m_u16yMax, uint64_t m_u16xMin, uint64_t m_u16xMax,
                                uint64_t m_u16TotalDisp, uint64_t m_u16width_after_census, uint64_t m_s16MinDisp)
{
    //#######################################################################################
    //Hamming Distance as cost initialization
    //#######################################################################################

    int d = blockIdx.x * blockDim.x + threadIdx.x;

    for (int i=m_u16yMin; i<m_u16yMax; i++) {
        for (int j=m_u16xMin; j<m_u16xMax; j++) {
            //for (int d=0; d<m_u16TotalDisp; d++) {
            if (d < m_u16TotalDisp) {
                int dist = compute_hamming_distance(ct1[i*m_u16width_after_census+j], ct2[i*m_u16width_after_census+j-(d+m_s16MinDisp)]);
                int Loop = (i*m_u16width_after_census+j)*m_u16TotalDisp + d;
                accumulatedCost[Loop] = dist;
            }
        }
    }
} // end compute_cost()


__global__ void cost_aggregation(int *aggregatedCost, int *Lr, uint16_t m_u16height_after_census,
                                 uint16_t m_u16width_after_census, uint16_t m_u16TotalDisp, uint16_t m_u8Directions)
{
    //#######################################################################################
    //          SGBM Cost Aggregation
    //#######################################################################################
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    if (i < m_u16height_after_census) {
    //for (int i=0; i<m_u16height_after_census; i++) {
        for (int j=0; j<m_u16width_after_census; j++)
        {
            for (int d=0; d<m_u16TotalDisp; d++)
            {
                int *ptr = aggregatedCost + (i*m_u16width_after_census+j)*m_u16TotalDisp+d;
                ptr[0] = 0;

                for (int r=0; r<m_u8Directions; r++)
                {
                    ptr[0] += Lr[((r*m_u16height_after_census+i)*m_u16width_after_census+j)*m_u16TotalDisp+d];
                }
            }
        }
    }
}// end cost_aggregation()

	.file	"tmpxft_00394d09_00000000-6_cuda_interface.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11find_minLriPit
	.type	_Z11find_minLriPit, @function
_Z11find_minLriPit:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z11find_minLriPit, .-_Z11find_minLriPit
	.globl	_Z8find_miniiii
	.type	_Z8find_miniiii, @function
_Z8find_miniiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z8find_miniiii, .-_Z8find_miniiii
	.globl	_Z24compute_hamming_distancemm
	.type	_Z24compute_hamming_distancemm, @function
_Z24compute_hamming_distancemm:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z24compute_hamming_distancemm, .-_Z24compute_hamming_distancemm
	.globl	_Z45__device_stub__Z16cost_computationPiS_hhttthhPiS_hhttthh
	.type	_Z45__device_stub__Z16cost_computationPiS_hhttthhPiS_hhttthh, @function
_Z45__device_stub__Z16cost_computationPiS_hhttthhPiS_hhttthh:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	208(%rsp), %eax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movw	%ax, 12(%rsp)
	movl	216(%rsp), %eax
	movb	%dl, 28(%rsp)
	leaq	48(%rsp), %rdx
	movb	%al, 8(%rsp)
	movl	224(%rsp), %eax
	movb	%cl, 24(%rsp)
	leaq	56(%rsp), %rcx
	movw	%r8w, 20(%rsp)
	movw	%r9w, 16(%rsp)
	movb	%al, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z16cost_computationPiS_hhttthh(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L8:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z45__device_stub__Z16cost_computationPiS_hhttthhPiS_hhttthh, .-_Z45__device_stub__Z16cost_computationPiS_hhttthhPiS_hhttthh
	.globl	_Z16cost_computationPiS_hhttthh
	.type	_Z16cost_computationPiS_hhttthh, @function
_Z16cost_computationPiS_hhttthh:
.LFB2055:
	.cfi_startproc
	endbr64
	movzbl	24(%rsp), %eax
	movzbl	%cl, %ecx
	movzbl	%dl, %edx
	movzwl	%r9w, %r9d
	movzwl	%r8w, %r8d
	movl	%eax, 24(%rsp)
	movzbl	16(%rsp), %eax
	movl	%eax, 16(%rsp)
	movzwl	8(%rsp), %eax
	movl	%eax, 8(%rsp)
	jmp	_Z45__device_stub__Z16cost_computationPiS_hhttthhPiS_hhttthh
	.cfi_endproc
.LFE2055:
	.size	_Z16cost_computationPiS_hhttthh, .-_Z16cost_computationPiS_hhttthh
	.globl	_Z46__device_stub__Z15compute_hammingPmS_PimmmmmmmPmS_Pimmmmmmm
	.type	_Z46__device_stub__Z15compute_hammingPmS_PimmmmmmmPmS_Pimmmmmmm, @function
_Z46__device_stub__Z15compute_hammingPmS_PimmmmmmmPmS_Pimmmmmmm:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z15compute_hammingPmS_Pimmmmmmm(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L14:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z46__device_stub__Z15compute_hammingPmS_PimmmmmmmPmS_Pimmmmmmm, .-_Z46__device_stub__Z15compute_hammingPmS_PimmmmmmmPmS_Pimmmmmmm
	.globl	_Z15compute_hammingPmS_Pimmmmmmm
	.type	_Z15compute_hammingPmS_Pimmmmmmm, @function
_Z15compute_hammingPmS_Pimmmmmmm:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z15compute_hammingPmS_PimmmmmmmPmS_Pimmmmmmm
	.cfi_endproc
.LFE2057:
	.size	_Z15compute_hammingPmS_Pimmmmmmm, .-_Z15compute_hammingPmS_Pimmmmmmm
	.globl	_Z42__device_stub__Z16cost_aggregationPiS_ttttPiS_tttt
	.type	_Z42__device_stub__Z16cost_aggregationPiS_ttttPiS_tttt, @function
_Z42__device_stub__Z16cost_aggregationPiS_ttttPiS_tttt:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movw	%dx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movw	%cx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movw	%r8w, 4(%rsp)
	movw	%r9w, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 136(%rsp)
	movq	%rsp, %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z16cost_aggregationPiS_tttt(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L19:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z42__device_stub__Z16cost_aggregationPiS_ttttPiS_tttt, .-_Z42__device_stub__Z16cost_aggregationPiS_ttttPiS_tttt
	.globl	_Z16cost_aggregationPiS_tttt
	.type	_Z16cost_aggregationPiS_tttt, @function
_Z16cost_aggregationPiS_tttt:
.LFB2059:
	.cfi_startproc
	endbr64
	movzwl	%cx, %ecx
	movzwl	%dx, %edx
	movzwl	%r9w, %r9d
	movzwl	%r8w, %r8d
	jmp	_Z42__device_stub__Z16cost_aggregationPiS_ttttPiS_tttt
	.cfi_endproc
.LFE2059:
	.size	_Z16cost_aggregationPiS_tttt, .-_Z16cost_aggregationPiS_tttt
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z16cost_aggregationPiS_tttt"
.LC1:
	.string	"_Z15compute_hammingPmS_Pimmmmmmm"
.LC2:
	.string	"_Z16cost_computationPiS_hhttthh"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z16cost_aggregationPiS_tttt(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15compute_hammingPmS_Pimmmmmmm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16cost_computationPiS_hhttthh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// CUDA-C includes
#include <hip/hip_runtime.h>

#include <stdio.h>

__device__ int find_minLri(int *Lrpr, uint16_t m_u16TotalDisp) {
    int minLri = INT_MAX;
    for (int i=0; i<m_u16TotalDisp; i++) {
        if (minLri > Lrpr[i]) {
            minLri = Lrpr[i];
        }
    }
    return minLri;
} // end find_minLri()

__device__ int find_min(int a, int b, int c, int d) {
    int minimum = a;
    if (minimum > b)
        minimum = b;
    if (minimum > c)
        minimum = c;
    if (minimum > d)
        minimum = d;
    return minimum;
} // end find_min()

__global__ void cost_computation(int *Lr, int *initCost, uint8_t m_u8Directions, uint8_t m_u8DEBUGLeftNeighbor,
                                 uint16_t m_u16height_after_census, uint16_t m_u16width_after_census,
                                 uint16_t m_u16TotalDisp, uint8_t m_u16P1, uint8_t m_u16P2) {
    //#######################################################################################
    //          SGBM Cost Computation
    //#######################################################################################

    int r = blockIdx.x * blockDim.x + threadIdx.x;

    // Computing cost along 5 directions only. (i,j-1) (i-1,j-1) (i-1,j) (i-1,j+1) (i,j+1)
    __shared__ int iDisp, jDisp;

    if (r < m_u8Directions) {
    //for (int r=0; r<m_u8Directions; r++) {
        if (r==0) {
            iDisp = 0; jDisp = 0-m_u8DEBUGLeftNeighbor;
        }
        else if (r==1) {
            iDisp = -1; jDisp = -1;
        }
        else if (r==2) {
            iDisp = -1; jDisp = 0;
        }
        else if (r==3) {
            iDisp = -1; jDisp = 1;
        }
        else if (r==4) {
            iDisp = 0; jDisp = 1;
        }
        //if (i < m_u16height_after_census) {
        for (int i=0; i<m_u16height_after_census; i++) {
            //if (i < m_u16width_after_census) {
            for (int j=0; j<m_u16width_after_census; j++) {
                // Compute p-r
                int iNorm = i + iDisp; //height
                int jNorm = j + jDisp; //width
                int *Lrpr = Lr+((r*m_u16height_after_census+iNorm)*m_u16width_after_census+jNorm)*m_u16TotalDisp;

                //#######################################################################################
                //         Find min_k{Lr(p-r,k)}
                //#######################################################################################
                //if (d < m_u16TotalDisp) {
                for (int d=0; d<m_u16TotalDisp; d++) {
                    int Cpd = initCost[(i*m_u16width_after_census+j)*m_u16TotalDisp+d];

                    int tmp;
                    if ( (((r==0)||(r==1))&&(jNorm<0)) || (((r==1)||(r==2)||(r==3))&&(i==0)) || ((r==3)&&(j==m_u16width_after_census-1)))
                    {
                        tmp = Cpd;
                    } else {
                        int minLri = find_minLri(Lrpr, m_u16TotalDisp);
                        int Lrpdm1, Lrpdp1;
                        if (d==0)
                            Lrpdm1 = INT_MAX-m_u16P1;
                        else
                            Lrpdm1 = Lrpr[d-1];
                        if (d==m_u16TotalDisp-1)
                            Lrpdp1 = INT_MAX-m_u16P1;
                        else
                            Lrpdp1 = Lrpr[d+1];

                        int v1 = find_min(Lrpr[d], Lrpdm1+m_u16P1, Lrpdp1+m_u16P1, minLri+m_u16P2);

                        tmp = Cpd + v1 - minLri;
                    }
                    Lr[((r*m_u16height_after_census+i)*m_u16width_after_census+j)*m_u16TotalDisp+d] = tmp;
                }
            }
        }
    }
} // end cost_computation()

__device__ int compute_hamming_distance (uint64_t a, uint64_t b)
{
    //#######################################################################################
    //Hamming Distance as cost initialization
    //#######################################################################################
    uint64_t tmp;
    int sum = 0;

    tmp = a^b;
    for(int i=0;i<64;i++){
        if(tmp&0x1<<i){
            sum ++;
        }
    }
    return sum;
} // end compute_hamming_distance()



__global__ void compute_hamming(uint64_t *ct1, uint64_t *ct2, int *accumulatedCost,
                                uint64_t m_u16yMin, uint64_t m_u16yMax, uint64_t m_u16xMin, uint64_t m_u16xMax,
                                uint64_t m_u16TotalDisp, uint64_t m_u16width_after_census, uint64_t m_s16MinDisp)
{
    //#######################################################################################
    //Hamming Distance as cost initialization
    //#######################################################################################

    int d = blockIdx.x * blockDim.x + threadIdx.x;

    for (int i=m_u16yMin; i<m_u16yMax; i++) {
        for (int j=m_u16xMin; j<m_u16xMax; j++) {
            //for (int d=0; d<m_u16TotalDisp; d++) {
            if (d < m_u16TotalDisp) {
                int dist = compute_hamming_distance(ct1[i*m_u16width_after_census+j], ct2[i*m_u16width_after_census+j-(d+m_s16MinDisp)]);
                int Loop = (i*m_u16width_after_census+j)*m_u16TotalDisp + d;
                accumulatedCost[Loop] = dist;
            }
        }
    }
} // end compute_cost()


__global__ void cost_aggregation(int *aggregatedCost, int *Lr, uint16_t m_u16height_after_census,
                                 uint16_t m_u16width_after_census, uint16_t m_u16TotalDisp, uint16_t m_u8Directions)
{
    //#######################################################################################
    //          SGBM Cost Aggregation
    //#######################################################################################
    int i = blockIdx.x * blockDim.x + threadIdx.x;
    if (i < m_u16height_after_census) {
    //for (int i=0; i<m_u16height_after_census; i++) {
        for (int j=0; j<m_u16width_after_census; j++)
        {
            for (int d=0; d<m_u16TotalDisp; d++)
            {
                int *ptr = aggregatedCost + (i*m_u16width_after_census+j)*m_u16TotalDisp+d;
                ptr[0] = 0;

                for (int r=0; r<m_u8Directions; r++)
                {
                    ptr[0] += Lr[((r*m_u16height_after_census+i)*m_u16width_after_census+j)*m_u16TotalDisp+d];
                }
            }
        }
    }
}// end cost_aggregation()

	.text
	.file	"cuda_interface.hip"
	.globl	_Z31__device_stub__cost_computationPiS_hhttthh # -- Begin function _Z31__device_stub__cost_computationPiS_hhttthh
	.type	_Z31__device_stub__cost_computationPiS_hhttthh,@function
_Z31__device_stub__cost_computationPiS_hhttthh: # @_Z31__device_stub__cost_computationPiS_hhttthh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	11(%rsp), %rsi
	movb	%dl, (%rsi)
	leaq	10(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	14(%rsp), %rcx
	movw	%r8w, (%rcx)
	leaq	12(%rsp), %r8
	movw	%r9w, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	216(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16cost_computationPiS_hhttthh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__cost_computationPiS_hhttthh, .Lfunc_end0-_Z31__device_stub__cost_computationPiS_hhttthh
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__compute_hammingPmS_Pimmmmmmm # -- Begin function _Z30__device_stub__compute_hammingPmS_Pimmmmmmm
	.type	_Z30__device_stub__compute_hammingPmS_Pimmmmmmm,@function
_Z30__device_stub__compute_hammingPmS_Pimmmmmmm: # @_Z30__device_stub__compute_hammingPmS_Pimmmmmmm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15compute_hammingPmS_Pimmmmmmm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z30__device_stub__compute_hammingPmS_Pimmmmmmm, .Lfunc_end1-_Z30__device_stub__compute_hammingPmS_Pimmmmmmm
	.cfi_endproc
                                        # -- End function
	.globl	_Z31__device_stub__cost_aggregationPiS_tttt # -- Begin function _Z31__device_stub__cost_aggregationPiS_tttt
	.type	_Z31__device_stub__cost_aggregationPiS_tttt,@function
_Z31__device_stub__cost_aggregationPiS_tttt: # @_Z31__device_stub__cost_aggregationPiS_tttt
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	14(%rsp), %rsi
	movw	%dx, (%rsi)
	leaq	12(%rsp), %rdx
	movw	%cx, (%rdx)
	leaq	10(%rsp), %rcx
	movw	%r8w, (%rcx)
	leaq	8(%rsp), %r8
	movw	%r9w, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16cost_aggregationPiS_tttt, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z31__device_stub__cost_aggregationPiS_tttt, .Lfunc_end2-_Z31__device_stub__cost_aggregationPiS_tttt
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16cost_computationPiS_hhttthh, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15compute_hammingPmS_Pimmmmmmm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16cost_aggregationPiS_tttt, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16cost_computationPiS_hhttthh,@object # @_Z16cost_computationPiS_hhttthh
	.section	.rodata,"a",@progbits
	.globl	_Z16cost_computationPiS_hhttthh
	.p2align	3, 0x0
_Z16cost_computationPiS_hhttthh:
	.quad	_Z31__device_stub__cost_computationPiS_hhttthh
	.size	_Z16cost_computationPiS_hhttthh, 8

	.type	_Z15compute_hammingPmS_Pimmmmmmm,@object # @_Z15compute_hammingPmS_Pimmmmmmm
	.globl	_Z15compute_hammingPmS_Pimmmmmmm
	.p2align	3, 0x0
_Z15compute_hammingPmS_Pimmmmmmm:
	.quad	_Z30__device_stub__compute_hammingPmS_Pimmmmmmm
	.size	_Z15compute_hammingPmS_Pimmmmmmm, 8

	.type	_Z16cost_aggregationPiS_tttt,@object # @_Z16cost_aggregationPiS_tttt
	.globl	_Z16cost_aggregationPiS_tttt
	.p2align	3, 0x0
_Z16cost_aggregationPiS_tttt:
	.quad	_Z31__device_stub__cost_aggregationPiS_tttt
	.size	_Z16cost_aggregationPiS_tttt, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z16cost_computationPiS_hhttthh"
	.size	.L__unnamed_1, 32

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z15compute_hammingPmS_Pimmmmmmm"
	.size	.L__unnamed_2, 33

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z16cost_aggregationPiS_tttt"
	.size	.L__unnamed_3, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__cost_computationPiS_hhttthh
	.addrsig_sym _Z30__device_stub__compute_hammingPmS_Pimmmmmmm
	.addrsig_sym _Z31__device_stub__cost_aggregationPiS_tttt
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16cost_computationPiS_hhttthh
	.addrsig_sym _Z15compute_hammingPmS_Pimmmmmmm
	.addrsig_sym _Z16cost_aggregationPiS_tttt
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16cost_computationPiS_hhttthh ; -- Begin function _Z16cost_computationPiS_hhttthh
	.globl	_Z16cost_computationPiS_hhttthh
	.p2align	8
	.type	_Z16cost_computationPiS_hhttthh,@function
_Z16cost_computationPiS_hhttthh:        ; @_Z16cost_computationPiS_hhttthh
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_and_b32 s3, s2, 0xff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_40
; %bb.1:                                ; %NodeBlock134
	s_mov_b32 s4, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr0
	v_cmpx_lt_i32_e32 1, v1
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_13
; %bb.2:                                ; %NodeBlock132
	s_mov_b32 s5, 0
	s_mov_b32 s4, exec_lo
                                        ; implicit-def: $vgpr0
	v_cmpx_lt_i32_e32 2, v1
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_10
; %bb.3:                                ; %NodeBlock130
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $sgpr7
	v_cmpx_lt_i32_e32 3, v1
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %LeafBlock128
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $sgpr7
	v_cmpx_eq_u32_e32 4, v1
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s5, exec_lo
	s_mov_b32 s7, 1
	ds_store_b32 v0, v0
.LBB0_6:                                ; %Flow145
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s5, exec_lo
.LBB0_7:                                ; %Flow144
	s_or_saveexec_b32 s6, s6
	v_mov_b32_e32 v0, s7
	s_xor_b32 exec_lo, exec_lo, s6
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_dual_mov_b32 v2, -1 :: v_dual_mov_b32 v3, 0
	v_mov_b32_e32 v0, 1
	s_or_b32 s5, s5, exec_lo
	ds_store_b32 v3, v2
.LBB0_9:                                ; %Flow146
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s5, s5, exec_lo
.LBB0_10:                               ; %Flow143
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mov_b32_e32 v2, -1
	v_mov_b32_e32 v0, 0
	s_or_b32 s5, s5, exec_lo
	ds_store_b32 v0, v2
.LBB0_12:                               ; %Flow147
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s5, exec_lo
.LBB0_13:                               ; %Flow142
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB0_21
; %bb.14:                               ; %NodeBlock
	s_mov_b32 s5, s4
	s_mov_b32 s6, exec_lo
                                        ; implicit-def: $sgpr7
	v_cmpx_lt_i32_e32 0, v1
	s_xor_b32 s6, exec_lo, s6
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_mov_b32_e32 v0, -1
	v_mov_b32_e32 v2, 0
	s_mov_b32 s7, -1
	s_or_b32 s5, s4, exec_lo
	ds_store_b32 v2, v0
.LBB0_16:                               ; %Flow149
	s_or_saveexec_b32 s6, s6
	v_mov_b32_e32 v0, s7
	s_xor_b32 exec_lo, exec_lo, s6
	s_cbranch_execz .LBB0_20
; %bb.17:                               ; %LeafBlock
	s_mov_b32 s7, s5
	s_mov_b32 s8, exec_lo
                                        ; implicit-def: $sgpr9
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_mov_b32_e32 v0, 0
	s_bfe_u32 s2, s2, 0x80008
	s_or_b32 s7, s5, exec_lo
	s_sub_i32 s9, 0, s2
	ds_store_b32 v0, v0
.LBB0_19:                               ; %Flow151
	s_or_b32 exec_lo, exec_lo, s8
	v_mov_b32_e32 v0, s9
	s_and_not1_b32 s2, s5, exec_lo
	s_and_b32 s5, s7, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s2, s5
.LBB0_20:                               ; %Flow150
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s4, s5, exec_lo
	s_or_b32 s4, s2, s4
.LBB0_21:                               ; %Flow148
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_23
; %bb.22:                               ; %.sink.split
	v_mov_b32_e32 v2, 0
	ds_store_b32 v2, v0 offset:4
.LBB0_23:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mov_b32 s9, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s11, s2, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s11, 0
	s_cbranch_scc1 .LBB0_40
; %bb.24:                               ; %.preheader.lr.ph
	v_mul_lo_u32 v8, v1, s11
	v_mov_b32_e32 v7, 0
	s_load_b64 s[14:15], s[0:1], 0x14
	s_and_b32 s12, s3, 0xffff
	v_add_nc_u32_e32 v5, -1, v1
	v_cmp_eq_u32_e64 s2, 3, v1
	ds_load_b64 v[2:3], v7
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s8, s[0:1], 0x18
	v_cmp_gt_u32_e64 s0, 2, v1
	v_cmp_gt_u32_e64 s1, 3, v5
	v_cmp_ne_u16_e64 s3, s3, 0
	s_mov_b32 s21, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s13, s14, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s13, 0
	s_mul_i32 s20, s13, s12
	v_add_nc_u32_e32 v0, v2, v8
	v_readfirstlane_b32 s10, v3
	s_cselect_b32 s14, -1, 0
	s_and_b32 s15, s15, 0xff
	s_add_i32 s16, s12, -1
	s_xor_b32 s17, s15, 0x7fffffff
	v_mad_u64_u32 v[3:4], null, v0, s12, s[10:11]
	s_add_i32 s18, s13, -1
	s_bfe_u32 s19, s8, 0x80008
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v9, v3, s13
.LBB0_25:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_27 Depth 2
                                        ;       Child Loop BB0_29 Depth 3
                                        ;         Child Loop BB0_31 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_39
; %bb.26:                               ; %.lr.ph100
                                        ;   in Loop: Header=BB0_25 Depth=1
	v_add_nc_u32_e32 v0, s21, v8
	s_cmp_eq_u32 s21, 0
	s_mul_i32 s22, s21, s12
	s_cselect_b32 s8, -1, 0
	s_mov_b32 s23, 0
	v_add_nc_u32_e32 v1, v0, v2
	v_mul_lo_u32 v11, v0, s12
	v_mov_b32_e32 v0, v9
	s_and_b32 s24, s1, s8
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v10, v1, s12
.LBB0_27:                               ;   Parent Loop BB0_25 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_29 Depth 3
                                        ;         Child Loop BB0_31 Depth 4
	s_and_not1_b32 vcc_lo, exec_lo, s14
	s_cbranch_vccnz .LBB0_38
; %bb.28:                               ; %.lr.ph
                                        ;   in Loop: Header=BB0_27 Depth=2
	s_add_i32 s8, s10, s23
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v3, s8, v10
	v_add_nc_u32_e32 v12, s23, v11
	s_add_i32 s25, s23, s22
	s_cmp_lt_i32 s8, 0
	v_lshlrev_b64 v[5:6], 2, v[0:1]
	v_mul_lo_u32 v3, v3, s13
	v_mul_lo_u32 v1, v12, s13
	s_cselect_b32 s8, -1, 0
	s_mul_i32 s25, s25, s13
	s_and_b32 s8, s0, s8
	s_cmp_eq_u32 s23, s16
	s_cselect_b32 s26, -1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v4, 31, v3
	s_or_b32 s8, s8, s24
	s_and_b32 s26, s2, s26
	s_or_b32 s26, s8, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
	s_mov_b32 s8, 0
	v_add_co_u32 v12, vcc_lo, s4, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
	s_xor_b32 s26, s26, -1
	v_add_co_u32 v14, vcc_lo, v12, -4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, -1, v13, vcc_lo
	v_add_co_u32 v16, vcc_lo, v12, 4
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v13, vcc_lo
.LBB0_29:                               ;   Parent Loop BB0_25 Depth=1
                                        ;     Parent Loop BB0_27 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_31 Depth 4
	s_add_i32 s28, s8, s25
	s_mov_b32 s29, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[28:29], s[28:29], 2
	s_add_u32 s28, s6, s28
	s_addc_u32 s29, s7, s29
	global_load_b32 v18, v7, s[28:29]
	s_and_saveexec_b32 s27, s26
	s_cbranch_execz .LBB0_37
; %bb.30:                               ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB0_29 Depth=3
	v_bfrev_b32_e32 v19, -2
	v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
	s_mov_b32 s28, s13
.LBB0_31:                               ; %.lr.ph.i
                                        ;   Parent Loop BB0_25 Depth=1
                                        ;     Parent Loop BB0_27 Depth=2
                                        ;       Parent Loop BB0_29 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b32 v20, v[5:6], off
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_add_i32 s28, s28, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s28, 0
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v19, v19, v20
	s_cbranch_scc1 .LBB0_31
; %bb.32:                               ; %_Z11find_minLriPit.exit.loopexit
                                        ;   in Loop: Header=BB0_29 Depth=3
	v_mov_b32_e32 v5, s17
	s_cmp_eq_u32 s8, 0
	s_cbranch_scc1 .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_29 Depth=3
	s_lshl_b64 s[28:29], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v5, vcc_lo, v14, s28
	v_add_co_ci_u32_e32 v6, vcc_lo, s29, v15, vcc_lo
	global_load_b32 v5, v[5:6], off
.LBB0_34:                               ;   in Loop: Header=BB0_29 Depth=3
	v_mov_b32_e32 v6, s17
	s_cmp_eq_u32 s8, s18
	s_cbranch_scc1 .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_29 Depth=3
	s_lshl_b64 s[28:29], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v20, vcc_lo, v16, s28
	v_add_co_ci_u32_e32 v21, vcc_lo, s29, v17, vcc_lo
	global_load_b32 v6, v[20:21], off
.LBB0_36:                               ; %._crit_edge108
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_lshl_b64 s[28:29], s[8:9], 2
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, s15, v5
	v_add_co_u32 v20, vcc_lo, v12, s28
	v_add_co_ci_u32_e32 v21, vcc_lo, s29, v13, vcc_lo
	v_add_nc_u32_e32 v6, s15, v6
	global_load_b32 v20, v[20:21], off
	v_add_nc_u32_e32 v21, s19, v19
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v5, v20, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v5, v5, v6, v21
	v_sub_nc_u32_e32 v6, v18, v19
	v_add_nc_u32_e32 v18, v6, v5
.LBB0_37:                               ; %Flow
                                        ;   in Loop: Header=BB0_29 Depth=3
	s_or_b32 exec_lo, exec_lo, s27
	v_add_nc_u32_e32 v5, s8, v1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s8, s13
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[5:6], v18, off
	s_cbranch_scc0 .LBB0_29
.LBB0_38:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_27 Depth=2
	v_add_nc_u32_e32 v0, s13, v0
	s_add_i32 s23, s23, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s23, s12
	s_cbranch_scc0 .LBB0_27
.LBB0_39:                               ; %._crit_edge101
                                        ;   in Loop: Header=BB0_25 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v9, s20, v9
	s_add_i32 s21, s21, 1
	s_cmp_eq_u32 s21, s11
	s_cbranch_scc0 .LBB0_25
.LBB0_40:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16cost_computationPiS_hhttthh
		.amdhsa_group_segment_fixed_size 8
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16cost_computationPiS_hhttthh, .Lfunc_end0-_Z16cost_computationPiS_hhttthh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1260
; NumSgprs: 32
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15compute_hammingPmS_Pimmmmmmm ; -- Begin function _Z15compute_hammingPmS_Pimmmmmmm
	.globl	_Z15compute_hammingPmS_Pimmmmmmm
	.p2align	8
	.type	_Z15compute_hammingPmS_Pimmmmmmm,@function
_Z15compute_hammingPmS_Pimmmmmmm:       ; @_Z15compute_hammingPmS_Pimmmmmmm
; %bb.0:
	s_load_b512 s[16:31], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_bfe_i64 s[2:3], s[22:23], 0x200000
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_u64_e64 s4, s[2:3], s[24:25]
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_10
; %bb.1:                                ; %.lr.ph40
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x5c
	s_load_b128 s[4:7], s[0:1], 0x40
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s8, 0xffff
	s_bfe_i64 s[8:9], s[26:27], 0x200000
	v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
	v_cmp_lt_u64_e64 s1, s[8:9], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_co_u32 v0, vcc_lo, v1, s6
	v_cmp_gt_u64_e64 s0, s[30:31], v[1:2]
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
                                        ;       Child Loop BB1_6 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_9
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_mul_i32 s6, s2, s5
	s_mul_hi_u32 s7, s2, s4
	s_mul_i32 s3, s3, s4
	s_add_i32 s6, s7, s6
	s_mul_i32 s12, s2, s4
	s_add_i32 s3, s6, s3
	s_mov_b64 s[6:7], s[8:9]
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_6 Depth 3
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_8
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=2
	s_add_u32 s10, s6, s12
	s_addc_u32 s11, s7, s3
	v_sub_co_u32 v3, vcc_lo, s10, v0
	v_sub_co_ci_u32_e32 v4, vcc_lo, s11, v2, vcc_lo
	s_lshl_b64 s[14:15], s[10:11], 3
	s_mov_b32 s7, 0
	s_add_u32 s14, s16, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_addc_u32 s15, s17, s15
	s_load_b64 s[14:15], s[14:15], 0x0
	v_add_co_u32 v3, vcc_lo, s18, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_xor_b32_e32 v4, s15, v4
	v_xor_b32_e32 v5, s14, v3
	v_mov_b32_e32 v3, 0
.LBB1_6:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_lshl_b32 s11, 1, s7
	s_add_i32 s7, s7, 1
	s_ashr_i32 s14, s11, 31
	v_and_b32_e32 v6, s11, v5
	v_and_b32_e32 v7, s14, v4
	s_cmp_lg_u32 s7, 64
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_cbranch_scc1 .LBB1_6
; %bb.7:                                ; %_Z24compute_hamming_distancemm.exit
                                        ;   in Loop: Header=BB1_4 Depth=2
	v_mad_u64_u32 v[4:5], null, s10, s30, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s20, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s21, v5, vcc_lo
	global_store_b32 v[4:5], v3, off
.LBB1_8:                                ; %Flow
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s13
	s_add_i32 s6, s6, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s7, s6, 31
	v_cmp_ge_u64_e64 s10, s[6:7], s[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s10
	s_cbranch_vccz .LBB1_4
.LBB1_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s3, s2, 31
	v_cmp_ge_u64_e64 s6, s[2:3], s[24:25]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s6
	s_cbranch_vccz .LBB1_2
.LBB1_10:                               ; %._crit_edge41
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15compute_hammingPmS_Pimmmmmmm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z15compute_hammingPmS_Pimmmmmmm, .Lfunc_end1-_Z15compute_hammingPmS_Pimmmmmmm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 34
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z16cost_aggregationPiS_tttt ; -- Begin function _Z16cost_aggregationPiS_tttt
	.globl	_Z16cost_aggregationPiS_tttt
	.p2align	8
	.type	_Z16cost_aggregationPiS_tttt,@function
_Z16cost_aggregationPiS_tttt:           ; @_Z16cost_aggregationPiS_tttt
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_and_b32 s4, s3, 0xffff
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB2_10
; %bb.1:                                ; %.preheader34
	s_load_b64 s[6:7], s[0:1], 0x10
	s_mov_b32 s5, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s6, s6, 16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB2_10
; %bb.2:                                ; %.preheader.lr.ph
	s_clause 0x1
	s_load_b32 s9, s[0:1], 0x14
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mul_lo_u32 v4, v1, s6
	s_and_b32 s8, s7, 0xffff
	v_cmp_ne_u16_e64 s7, s7, 0
	v_mov_b32_e32 v5, 0
	s_mul_i32 s11, s8, s6
	s_mov_b32 s12, 0
	s_mul_i32 s11, s11, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v6, v4, s8
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s9, s9, 16
	s_cmp_lg_u32 s9, 0
	s_cselect_b32 s10, -1, 0
.LBB2_3:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_5 Depth 2
                                        ;       Child Loop BB2_7 Depth 3
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB2_9
; %bb.4:                                ; %.lr.ph37
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v9, v6 :: v_dual_add_nc_u32 v0, s12, v4
	s_mov_b32 s4, 0
	v_mul_lo_u32 v0, v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v8, vcc_lo, s1, v1, vcc_lo
.LBB2_5:                                ;   Parent Loop BB2_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB2_7 Depth 3
	s_lshl_b64 s[14:15], s[4:5], 2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v0, vcc_lo, v7, s14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s15, v8, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s10
	global_store_b32 v[0:1], v5, off
	s_cbranch_vccnz .LBB2_8
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB2_5 Depth=2
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v2, v9
	s_mov_b32 s13, s9
.LBB2_7:                                ; %.lr.ph
                                        ;   Parent Loop BB2_3 Depth=1
                                        ;     Parent Loop BB2_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_i32 s13, s13, -1
	s_cmp_eq_u32 s13, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[11:12], 2, v[2:3]
	v_add_nc_u32_e32 v2, s11, v2
	v_add_co_u32 v11, vcc_lo, s2, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
	global_load_b32 v3, v[11:12], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v10, v10, v3
	global_store_b32 v[0:1], v10, off
	s_cbranch_scc0 .LBB2_7
.LBB2_8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB2_5 Depth=2
	v_add_nc_u32_e32 v9, 1, v9
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, s8
	s_cbranch_scc0 .LBB2_5
.LBB2_9:                                ; %._crit_edge38
                                        ;   in Loop: Header=BB2_3 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s8, v6
	s_add_i32 s12, s12, 1
	s_cmp_eq_u32 s12, s6
	s_cbranch_scc0 .LBB2_3
.LBB2_10:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16cost_aggregationPiS_tttt
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z16cost_aggregationPiS_tttt, .Lfunc_end2-_Z16cost_aggregationPiS_tttt
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           1
        .value_kind:     by_value
      - .offset:         17
        .size:           1
        .value_kind:     by_value
      - .offset:         18
        .size:           2
        .value_kind:     by_value
      - .offset:         20
        .size:           2
        .value_kind:     by_value
      - .offset:         22
        .size:           2
        .value_kind:     by_value
      - .offset:         24
        .size:           1
        .value_kind:     by_value
      - .offset:         25
        .size:           1
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16cost_computationPiS_hhttthh
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z16cost_computationPiS_hhttthh.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     22
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
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    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
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    .max_flat_workgroup_size: 1024
    .name:           _Z15compute_hammingPmS_Pimmmmmmm
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z15compute_hammingPmS_Pimmmmmmm.kd
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    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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    .symbol:         _Z16cost_aggregationPiS_tttt.kd
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
