#include <stdio.h>
#include <cuda.h>


// Initialize host vectors
void init(int *a, int *b, int n) {
  for (int i=0; i < n; ++i) {
    a[i] = i;
    b[i] = n-i;
  }
}


// Check result correctness
void check(int *c, int n) {
  int i = 0;
  while (i < n && c[i] == n) {
    ++i;
  }
  if (i == n)
    printf("Ok\n");
  else
    printf("Non ok\n");
}


// Cuda kernel
__global__ void add(int *a, int *b, int *c, int n) {
  //@TODO@ : complete kernel code
    int i = threadIdx.x + blockDim.x * blockIdx.x;
	if(i < n) {
		c[i]=a[i]+b[i];
	}
}

int main(int argc, char **argv)
{	

  if(argc<2) {printf("Give the vector size as first parameter\n");;exit(2);}


  int n = atoi(argv[1]);
  printf("Vector size is %d\n",n);

  // host pointers
  int *host_a, *host_b, *host_c;
  int STREAM_NB=4;
  int STREAM_SIZE=512;


  // Allocations on host
  //@TODO@ : 
	cudaHostAlloc((void **) &host_a, n*sizeof(int), cudaHostAllocDefault);
    cudaHostAlloc((void **) &host_b, n*sizeof(int), cudaHostAllocDefault);
    cudaHostAlloc((void **) &host_c, n*sizeof(int), cudaHostAllocDefault);


  // Initialize vectors
  init(host_a,host_b,n);


  cudaStream_t streams[STREAM_NB];
  int *d_A[STREAM_NB];
  int *d_B[STREAM_NB];
  int *d_C[STREAM_NB];


   for(int i=0;i<STREAM_NB;i++)
  {
    cudaStreamCreate(&streams[i]); 
    cudaMalloc((void**)&d_A[i],STREAM_SIZE*sizeof(int));
    cudaMalloc((void**)&d_B[i],STREAM_SIZE*sizeof(int));
    cudaMalloc((void**)&d_C[i],STREAM_SIZE*sizeof(int));
  }


for (int i=0; i<n; i+=STREAM_SIZE*STREAM_NB) 
{
  for(int j=0;j<STREAM_NB;j++)
 {
     cudaMemcpyAsync(d_A[j], host_a+i+STREAM_SIZE*j,STREAM_SIZE*sizeof(int),cudaMemcpyHostToDevice,streams[j]);
     
     cudaMemcpyAsync(d_B[j], host_b+i+STREAM_SIZE*j, STREAM_SIZE*sizeof(int),cudaMemcpyHostToDevice,streams[j]);

     add<<<STREAM_SIZE/256, 256, 0, streams[j]>>>(d_A[j], d_B[j],d_C[j],STREAM_SIZE);

     cudaMemcpyAsync(host_c+i+STREAM_SIZE*j,d_C[j], STREAM_SIZE*sizeof(int),cudaMemcpyDeviceToHost,streams[j]);
 }
}
  cudaDeviceSynchronize();


  // Check result
  check(host_c,n);


  // Free device memory in a loop :
  for(int i=0;i<STREAM_NB;i++)
{
  cudaFree(d_A[i]); 
  cudaFree(d_B[i]); 
  cudaFree(d_C[i]);
}


 cudaFree(host_a);
 cudaFree(host_b); 
 cudaFree(host_b);
  return 0;
}

	.file	"tmpxft_002ffabe_00000000-6_1-vectorAdd_old.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4initPiS_i
	.type	_Z4initPiS_i, @function
_Z4initPiS_i:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	cmpl	%eax, %edx
	jle	.L6
	movl	%edx, %ecx
	movl	%eax, (%rdi,%rax,4)
	subl	%eax, %ecx
	movl	%ecx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z4initPiS_i, .-_Z4initPiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Ok\n"
.LC1:
	.string	"Non ok\n"
	.text
	.globl	_Z5checkPii
	.type	_Z5checkPii, @function
_Z5checkPii:
.LFB2028:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L11:
	cmpl	%eax, %esi
	jg	.L8
.L12:
	cmpl	%eax, %esi
	jne	.L14
	leaq	.LC0(%rip), %rsi
	jmp	.L15
.L8:
	leaq	1(%rax), %rdx
	cmpl	%esi, (%rdi,%rax,4)
	jne	.L12
	movq	%rdx, %rax
	jmp	.L11
.L14:
	leaq	.LC1(%rip), %rsi
.L15:
	movl	$2, %edi
	xorl	%eax, %eax
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z5checkPii, .-_Z5checkPii
	.globl	_Z27__device_stub__Z3addPiS_S_iPiS_S_i
	.type	_Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3addPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L16:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
	.globl	_Z3addPiS_S_i
	.type	_Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3addPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z3addPiS_S_i, .-_Z3addPiS_S_i
	.section	.rodata.str1.1
.LC2:
	.string	"Give the vector size as first parameter\n"
.LC3:
	.string	"Vector size is %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	decl	%edi
	jg	.L22
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	call	__printf_chk@PLT
	movl	$2, %edi
	call	exit@PLT
.L22:
	movq	8(%rsi), %rdi
	leaq	72(%rsp), %r14
	call	atoi@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movl	%eax, %edx
	movl	%eax, 12(%rsp)
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movslq	12(%rsp), %rbx
	leaq	24(%rsp), %rdi
	xorl	%edx, %edx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	cudaHostAlloc@PLT
	movq	%rbx, %rsi
	leaq	32(%rsp), %rdi
	xorl	%edx, %edx
	call	cudaHostAlloc@PLT
	movq	%rbx, %rsi
	leaq	40(%rsp), %rdi
	xorl	%edx, %edx
	call	cudaHostAlloc@PLT
	movl	12(%rsp), %edx
	movq	32(%rsp), %rsi
	xorl	%ebx, %ebx
	movq	24(%rsp), %rdi
	call	_Z4initPiS_i
.L23:
	leaq	(%rbx,%r14), %rdi
	leaq	104(%rsp), %r12
	call	cudaStreamCreate@PLT
	leaq	(%r12,%rbx), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	leaq	136(%rsp,%rbx), %rdi
	movl	$2048, %esi
	call	cudaMalloc@PLT
	leaq	168(%rsp,%rbx), %rdi
	movl	$2048, %esi
	addq	$8, %rbx
	call	cudaMalloc@PLT
	cmpq	$32, %rbx
	jne	.L23
	xorl	%r13d, %r13d
.L24:
	cmpl	%r13d, 12(%rsp)
	jle	.L34
	leaq	0(,%r13,4), %rbp
	movq	%r14, %rbx
	xorl	%r15d, %r15d
.L26:
	movq	24(%rsp), %rsi
	movq	(%r12,%r15), %rdi
	movl	$1, %ecx
	movl	$2048, %edx
	movq	(%rbx), %r8
	addq	%rbp, %rsi
	call	cudaMemcpyAsync@PLT
	movq	32(%rsp), %rsi
	movq	(%rbx), %r8
	movl	$1, %ecx
	movq	136(%rsp,%r15), %rdi
	movl	$2048, %edx
	addq	%rbp, %rsi
	call	cudaMemcpyAsync@PLT
	movl	$16777217, %eax
	movq	(%rbx), %r9
	xorl	%r8d, %r8d
	salq	$8, %rax
	movl	$2147483649, %edi
	movl	$1, %ecx
	movl	$1, %esi
	addq	%rdi, %rdi
	movq	%rax, %rdx
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	movq	%rdi, 48(%rsp)
	movl	$1, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	168(%rsp,%r15), %rdx
	movq	(%r12,%r15), %rdi
	movl	$512, %ecx
	movq	136(%rsp,%r15), %rsi
	call	_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.L25:
	movq	40(%rsp), %rdi
	movq	(%rbx), %r8
	movl	$2, %ecx
	movl	$2048, %edx
	movq	168(%rsp,%r15), %rsi
	addq	$8, %r15
	addq	$8, %rbx
	addq	%rbp, %rdi
	addq	$2048, %rbp
	call	cudaMemcpyAsync@PLT
	cmpq	$32, %r15
	jne	.L26
	addq	$2048, %r13
	jmp	.L24
.L34:
	call	cudaDeviceSynchronize@PLT
	movl	12(%rsp), %esi
	movq	40(%rsp), %rdi
	xorl	%ebx, %ebx
	call	_Z5checkPii
.L28:
	movq	(%r12,%rbx), %rdi
	call	cudaFree@PLT
	movq	136(%rsp,%rbx), %rdi
	call	cudaFree@PLT
	movq	168(%rsp,%rbx), %rdi
	addq	$8, %rbx
	call	cudaFree@PLT
	cmpq	$32, %rbx
	jne	.L28
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z3addPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3addPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>


// Initialize host vectors
void init(int *a, int *b, int n) {
  for (int i=0; i < n; ++i) {
    a[i] = i;
    b[i] = n-i;
  }
}


// Check result correctness
void check(int *c, int n) {
  int i = 0;
  while (i < n && c[i] == n) {
    ++i;
  }
  if (i == n)
    printf("Ok\n");
  else
    printf("Non ok\n");
}


// Cuda kernel
__global__ void add(int *a, int *b, int *c, int n) {
  //@TODO@ : complete kernel code
    int i = threadIdx.x + blockDim.x * blockIdx.x;
	if(i < n) {
		c[i]=a[i]+b[i];
	}
}

int main(int argc, char **argv)
{	

  if(argc<2) {printf("Give the vector size as first parameter\n");;exit(2);}


  int n = atoi(argv[1]);
  printf("Vector size is %d\n",n);

  // host pointers
  int *host_a, *host_b, *host_c;
  int STREAM_NB=4;
  int STREAM_SIZE=512;


  // Allocations on host
  //@TODO@ : 
	hipHostAlloc((void **) &host_a, n*sizeof(int), hipHostMallocDefault);
    hipHostAlloc((void **) &host_b, n*sizeof(int), hipHostMallocDefault);
    hipHostAlloc((void **) &host_c, n*sizeof(int), hipHostMallocDefault);


  // Initialize vectors
  init(host_a,host_b,n);


  hipStream_t streams[STREAM_NB];
  int *d_A[STREAM_NB];
  int *d_B[STREAM_NB];
  int *d_C[STREAM_NB];


   for(int i=0;i<STREAM_NB;i++)
  {
    hipStreamCreate(&streams[i]); 
    hipMalloc((void**)&d_A[i],STREAM_SIZE*sizeof(int));
    hipMalloc((void**)&d_B[i],STREAM_SIZE*sizeof(int));
    hipMalloc((void**)&d_C[i],STREAM_SIZE*sizeof(int));
  }


for (int i=0; i<n; i+=STREAM_SIZE*STREAM_NB) 
{
  for(int j=0;j<STREAM_NB;j++)
 {
     hipMemcpyAsync(d_A[j], host_a+i+STREAM_SIZE*j,STREAM_SIZE*sizeof(int),hipMemcpyHostToDevice,streams[j]);
     
     hipMemcpyAsync(d_B[j], host_b+i+STREAM_SIZE*j, STREAM_SIZE*sizeof(int),hipMemcpyHostToDevice,streams[j]);

     add<<<STREAM_SIZE/256, 256, 0, streams[j]>>>(d_A[j], d_B[j],d_C[j],STREAM_SIZE);

     hipMemcpyAsync(host_c+i+STREAM_SIZE*j,d_C[j], STREAM_SIZE*sizeof(int),hipMemcpyDeviceToHost,streams[j]);
 }
}
  hipDeviceSynchronize();


  // Check result
  check(host_c,n);


  // Free device memory in a loop :
  for(int i=0;i<STREAM_NB;i++)
{
  hipFree(d_A[i]); 
  hipFree(d_B[i]); 
  hipFree(d_C[i]);
}


 hipFree(host_a);
 hipFree(host_b); 
 hipFree(host_b);
  return 0;
}

	.text
	.file	"1-vectorAdd_old.hip"
	.globl	_Z4initPiS_i                    # -- Begin function _Z4initPiS_i
	.type	_Z4initPiS_i,@function
_Z4initPiS_i:                           # @_Z4initPiS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorl	%ecx, %ecx
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%ecx, (%rdi,%rcx,4)
	movl	%eax, (%rsi,%rcx,4)
	incq	%rcx
	decq	%rax
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z4initPiS_i, .Lfunc_end0-_Z4initPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z5checkPii                     # -- Begin function _Z5checkPii
	.type	_Z5checkPii,@function
_Z5checkPii:                            # @_Z5checkPii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB1_1
# %bb.3:                                # %.lr.ph.preheader
	movl	%esi, %ecx
	xorl	%eax, %eax
.LBB1_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	cmpl	%ecx, (%rdi,%rax,4)
	jne	.LBB1_2
# %bb.5:                                #   in Loop: Header=BB1_4 Depth=1
	incq	%rax
	cmpq	%rax, %rcx
	jne	.LBB1_4
# %bb.6:
	movl	$.Lstr.1, %edi
	jmp	puts@PLT                        # TAILCALL
.LBB1_1:
	xorl	%eax, %eax
.LBB1_2:                                # %.critedge
	cmpl	%esi, %eax
	movl	$.Lstr.1, %eax
	movl	$.Lstr, %edi
	cmoveq	%rax, %rdi
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end1:
	.size	_Z5checkPii, .Lfunc_end1-_Z5checkPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__addPiS_S_i   # -- Begin function _Z18__device_stub__addPiS_S_i
	.type	_Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i:          # @_Z18__device_stub__addPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3addPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z18__device_stub__addPiS_S_i, .Lfunc_end2-_Z18__device_stub__addPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$88, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$1, %edi
	jle	.LBB3_23
# %bb.1:
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	movl	%eax, %r12d
	movl	$.L.str.3, %edi
	movl	%eax, %esi
	xorl	%eax, %eax
	callq	printf
	movslq	%ebx, %r14
	leaq	(,%r14,4), %rbx
	leaq	-72(%rbp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostAlloc
	leaq	-48(%rbp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostAlloc
	leaq	-88(%rbp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostAlloc
	testl	%r14d, %r14d
	jle	.LBB3_4
# %bb.2:                                # %.lr.ph.preheader.i
	movq	-72(%rbp), %rax
	movq	-48(%rbp), %rcx
	xorl	%edx, %edx
	movq	%r12, %rsi
.LBB3_3:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movl	%edx, (%rax,%rdx,4)
	movl	%esi, (%rcx,%rdx,4)
	incq	%rdx
	decq	%rsi
	jne	.LBB3_3
.LBB3_4:                                # %_Z4initPiS_i.exit
	movq	%rsp, -56(%rbp)                 # 8-byte Spill
	movq	%rsp, %rbx
	addq	$-32, %rbx
	movq	%rbx, %rsp
	movq	%rsp, %rax
	addq	$-32, %rax
	movq	%rax, -80(%rbp)                 # 8-byte Spill
	movq	%rax, %rsp
	movq	%rsp, %r15
	addq	$-32, %r15
	movq	%r15, %rsp
	movq	%rsp, %r13
	addq	$-32, %r13
	movq	%r13, %rsp
	xorl	%r14d, %r14d
.LBB3_5:                                # =>This Inner Loop Header: Depth=1
	leaq	(%rbx,%r14), %rdi
	callq	hipStreamCreate
	movq	-80(%rbp), %rax                 # 8-byte Reload
	leaq	(%rax,%r14), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	leaq	(%r15,%r14), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	leaq	(%r14,%r13), %rdi
	movl	$2048, %esi                     # imm = 0x800
	callq	hipMalloc
	addq	$8, %r14
	cmpq	$32, %r14
	jne	.LBB3_5
# %bb.6:                                # %.preheader76
	movq	%r13, -64(%rbp)                 # 8-byte Spill
	movq	%r15, %r14
	movq	-80(%rbp), %r15                 # 8-byte Reload
	testl	%r12d, %r12d
	jle	.LBB3_24
# %bb.7:                                # %.preheader.preheader
	movabsq	$4294967298, %rax               # imm = 0x100000002
	xorl	%r13d, %r13d
	addq	$254, %rax
	movq	%rax, -120(%rbp)                # 8-byte Spill
	xorl	%eax, %eax
	movq	%r12, -96(%rbp)                 # 8-byte Spill
.LBB3_8:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_9 Depth 2
	movq	%rax, -104(%rbp)                # 8-byte Spill
	movq	%r13, -112(%rbp)                # 8-byte Spill
	xorl	%r12d, %r12d
.LBB3_9:                                #   Parent Loop BB3_8 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	(%r15,%r12), %rdi
	movq	-72(%rbp), %rsi
	addq	%r13, %rsi
	movq	(%rbx,%r12), %r8
	movl	$2048, %edx                     # imm = 0x800
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%r14,%r12), %rdi
	movq	-48(%rbp), %rsi
	addq	%r13, %rsi
	movq	(%rbx,%r12), %r8
	movl	$2048, %edx                     # imm = 0x800
	movl	$1, %ecx
	callq	hipMemcpyAsync
	movq	(%rbx,%r12), %r9
	movabsq	$4294967298, %rdi               # imm = 0x100000002
	movl	$1, %esi
	movq	-120(%rbp), %rdx                # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_11
# %bb.10:                               #   in Loop: Header=BB3_9 Depth=2
	movq	(%r15,%r12), %rdi
	movq	(%r14,%r12), %rsi
	movq	-64(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12), %rdx
	movl	$512, %ecx                      # imm = 0x200
	callq	_Z18__device_stub__addPiS_S_i
.LBB3_11:                               #   in Loop: Header=BB3_9 Depth=2
	movq	-88(%rbp), %rdi
	addq	%r13, %rdi
	movq	-64(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r12), %rsi
	movq	(%rbx,%r12), %r8
	movl	$2048, %edx                     # imm = 0x800
	movl	$2, %ecx
	callq	hipMemcpyAsync
	addq	$8, %r12
	addq	$2048, %r13                     # imm = 0x800
	cmpq	$32, %r12
	jne	.LBB3_9
# %bb.12:                               #   in Loop: Header=BB3_8 Depth=1
	movq	-104(%rbp), %rax                # 8-byte Reload
	addq	$2048, %rax                     # imm = 0x800
	movq	-112(%rbp), %r13                # 8-byte Reload
	addq	$8192, %r13                     # imm = 0x2000
	movq	-96(%rbp), %r12                 # 8-byte Reload
	cmpl	%eax, %r12d
	jg	.LBB3_8
# %bb.13:                               # %._crit_edge
	callq	hipDeviceSynchronize
	testl	%r12d, %r12d
	jle	.LBB3_14
# %bb.16:                               # %.lr.ph.preheader.i67
	movq	-88(%rbp), %rcx
	xorl	%eax, %eax
	movq	-56(%rbp), %r13                 # 8-byte Reload
.LBB3_17:                               # %.lr.ph.i69
                                        # =>This Inner Loop Header: Depth=1
	cmpl	%r12d, (%rcx,%rax,4)
	jne	.LBB3_15
# %bb.18:                               #   in Loop: Header=BB3_17 Depth=1
	incq	%rax
	cmpq	%rax, %r12
	jne	.LBB3_17
# %bb.19:
	movl	$.Lstr.1, %edi
	jmp	.LBB3_20
.LBB3_24:                               # %._crit_edge.thread
	callq	hipDeviceSynchronize
.LBB3_14:
	xorl	%eax, %eax
	movq	-56(%rbp), %r13                 # 8-byte Reload
.LBB3_15:                               # %.critedge.i
	cmpl	%r12d, %eax
	movl	$.Lstr.1, %eax
	movl	$.Lstr, %edi
	cmoveq	%rax, %rdi
.LBB3_20:                               # %_Z5checkPii.exit
	callq	puts@PLT
	xorl	%ebx, %ebx
	movq	-64(%rbp), %r12                 # 8-byte Reload
.LBB3_21:                               # =>This Inner Loop Header: Depth=1
	movq	(%r15,%rbx,8), %rdi
	callq	hipFree
	movq	(%r14,%rbx,8), %rdi
	callq	hipFree
	movq	(%r12,%rbx,8), %rdi
	callq	hipFree
	incq	%rbx
	cmpq	$4, %rbx
	jne	.LBB3_21
# %bb.22:
	movq	-72(%rbp), %rdi
	callq	hipFree
	movq	-48(%rbp), %rdi
	callq	hipFree
	movq	-48(%rbp), %rdi
	callq	hipFree
	movq	%r13, %rsp
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.LBB3_23:
	.cfi_def_cfa %rbp, 16
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movl	$2, %edi
	callq	exit
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3addPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3addPiS_S_i,@object           # @_Z3addPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z3addPiS_S_i
	.p2align	3, 0x0
_Z3addPiS_S_i:
	.quad	_Z18__device_stub__addPiS_S_i
	.size	_Z3addPiS_S_i, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"Vector size is %d\n"
	.size	.L.str.3, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3addPiS_S_i"
	.size	.L__unnamed_1, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Non ok"
	.size	.Lstr, 7

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Ok"
	.size	.Lstr.1, 3

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"Give the vector size as first parameter"
	.size	.Lstr.2, 40

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__addPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3addPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3addPiS_S_i           ; -- Begin function _Z3addPiS_S_i
	.globl	_Z3addPiS_S_i
	.p2align	8
	.type	_Z3addPiS_S_i,@function
_Z3addPiS_S_i:                          ; @_Z3addPiS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b32 s3, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s3, v1
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, v3, v2
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3addPiS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 180
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3addPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3addPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
