//******************************************************
// Project
// Names: Anthony Enem
// Parallel Programming Date: 12/05/16
//******************************************************
// This program implements the cooley tukey fft algorithm
// and computes the values fro X_k from 0 to N in parallel. 
//******************************************************

#include<cuda.h>
#include<sys/time.h>
#include<stdio.h>
#include<math.h>
#include<time.h>

//define struct for complex numbers
typedef struct complex{
    double real;
    double imaginary;
} complex;

#define N 16384
#define PI 3.14159265359

//******************************************************
// Parameters: two complex structs a and b
// This function multiplies 2 complex structs and returns
// the result as a complex struct
//******************************************************

__device__
complex multiplyComplex(complex a, complex b)
{
    complex result;
    result.real = a.real*b.real - a.imaginary*b.imaginary;
    result.imaginary = a.real*b.imaginary + b.real*a.imaginary;

    return result;
}

//******************************************************
// Parameters: two complex structs a and b
// This function adds 2 complex structs and returns
// the result as a complex struct
//******************************************************
__device__
complex addComplex(complex a, complex b)
{
    complex result = {a.real+b.real, a.imaginary+b.imaginary};
    return result;
}

//******************************************************
// Parameters: two complex structs a and b
// This function subtracts 2 complex structs and returns
// the result as a complex struct
//******************************************************
__device__
complex subtractComplex(complex a, complex b)
{
    complex result = {a.real-b.real, a.imaginary-b.imaginary};
    return result;
}

//******************************************************
// Each thread for this kernel computes the even and odd portions of the
// fft formula
//******************************************************
__global__
void compute_Even_Odd(complex* xInput_d, complex *even_d, complex* odd_d)
{	
	int idx = blockIdx.x*1024 + threadIdx.x;
	int k = idx / (N/2);
	int m = idx % (N/2);
	
	//compute exponent
    double exp = -4.0 * PI * m * k / N;
	
	complex e_part;    

    //compute part with e^(i * exponent)
    e_part.real = cos(exp);
    e_part.imaginary = sin(exp);
        
    //save even part
	even_d[idx] = multiplyComplex(xInput_d[2*m], e_part);
	
    //save odd part
    odd_d[idx] = multiplyComplex(xInput_d[2*m+1], e_part);
}

//******************************************************
// Parameters: pointer to complex twiddle and integer k
// This function computes the twiddle factor for given
// N and k values
//******************************************************
__device__
void compute_twiddle(complex* twiddle, int* k)
{
    double exp = -2.0 * PI * (*k) / N;
	twiddle->real = cos(exp);
	twiddle->imaginary = sin(exp);
}

//******************************************************
// This computes the summation for the fft algorithm 
// using regression
//******************************************************
__global__
void sum_Regression(complex* even_d, complex* odd_d, complex* result_d)
{	
	int n = N/2;
	int idx = blockIdx.x*1024 + threadIdx.x;
	int k = idx / (n/2); //we only need half the number of threads for regression
	int m = idx % (n/2);
	int z = k*n + m;
	
	while(n > 1)
	{
		__syncthreads();		
		if(m < n/2)
		{
			even_d[z] = addComplex(even_d[z], even_d[z + n/2]);
			odd_d[z] = addComplex(odd_d[z], odd_d[z + n/2]);
		}		
		n = n/2;
	}
	if(m == 0)
	{
		compute_twiddle(result_d + k, &k);
		//calculate twiddle * O_k
		odd_d[z] = multiplyComplex(odd_d[z], result_d[k]);
		
		//compute X_k and X_k + N/2
		result_d[k] = addComplex(even_d[z], odd_d[z]);
		result_d[k + N/2] = subtractComplex(even_d[z], odd_d[z]);
	}
}

int main()
{	
	complex* xInput, *result;
	
	complex* xInput_d, *result_d;
	complex *even_d, *odd_d;

	//allocate memory
	xInput = (complex *)malloc(N * sizeof(complex));
	result = (complex *)malloc(N * sizeof(complex));
	
	cudaMalloc((void**)&xInput_d, N*sizeof(complex));
	cudaMalloc((void**)&result_d, N*sizeof(complex));
	
	//set defined values from 0 to 7 for xInput
	xInput[0].real = 3.6;
	xInput[0].imaginary = 2.6;
	xInput[1].real = 2.9;
	xInput[1].imaginary = 6.3;
	xInput[2].real = 5.6;
	xInput[2].imaginary = 4;
	xInput[3].real = 4.8;
	xInput[3].imaginary = 9.1;
	xInput[4].real = 3.3;
	xInput[4].imaginary = 0.4;
	xInput[5].real = 5.9;
	xInput[5].imaginary = 4.8;
	xInput[6].real = 5;
	xInput[6].imaginary = 2.6;
	xInput[7].real = 4.3;
	xInput[7].imaginary = 4.1;
	
	//set defined values for x[8] to x[N-1] as 0
	for (int i = 8; i < N; i++)
	{
		xInput[i].real = 0;
		xInput[i].imaginary = 0;
	}
	
	clock_t st = clock();
	cudaMemcpy(xInput_d, xInput, sizeof(complex)*N, cudaMemcpyHostToDevice);
	
	int m_blocks, m_threads;
	m_threads = (N/2)*(N/2); //k goes 0 to N - 1 (but same values used 2ice),
							//m goes 0 to N/2-1 for each k value
	
	cudaMalloc((void**)&even_d, sizeof(complex)*m_threads);
	cudaMalloc((void**)&odd_d, sizeof(complex)*m_threads);
	
	m_blocks = (m_threads)/1024; //number of blocks we need
	
	if(m_blocks == 0){
		m_blocks = 1;
	}
	else{
		m_threads = 1024;
	}
	
	//Use half the number of blocks to compute results using regression
	dim3 dimSumGrid(m_blocks/2, 1);
	dim3 dimSumBlock(m_threads, 1);
	if(m_blocks == 1)
	{
		dimSumGrid = dim3(m_blocks, 1);
		dimSumBlock = dim3(m_threads/2, 1);
	}
		
	
	cudaEvent_t start, stop;
	float elapsedTime;

	cudaEventCreate(&start);
	cudaEventRecord(start,0);
	
	compute_Even_Odd<<<m_blocks, m_threads>>>(xInput_d, even_d, odd_d);
	
	sum_Regression<<<dimSumGrid, dimSumBlock>>>(even_d, odd_d, result_d);
	
	clock_t end = clock();
	cudaEventCreate(&stop);
	cudaEventRecord(stop,0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&elapsedTime, start,stop);
	
	printf("Cuda time : %f milli secs\n", elapsedTime);	
	
	cudaMemcpy(result, result_d, sizeof(complex)*N, cudaMemcpyDeviceToHost);
	
	cudaFree(xInput_d);
	cudaFree(result_d);
	cudaFree(even_d);
	cudaFree(odd_d);
	
	printf("PARALLEL VERSION\n\n");
	printf("TOTAL PROCESSED SAMPLES: %d\n", N);
	
	for(int i = 0; i < 8; i++)
	{
		printf("==================\n");
		printf("XR[%d]: %f\n", i, result[i].real);
		printf("XI[%d]: %f\n", i, result[i].imaginary);
	}
	
	printf("==================\n");
	
	//printf("\nC clock Time: %f\n", ((double)(end - st)) / CLOCKS_PER_SEC);
	
	
	return 0;
	
}
	.file	"tmpxft_0037f13a_00000000-6_FFT_Parallel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15multiplyComplex7complexS_
	.type	_Z15multiplyComplex7complexS_, @function
_Z15multiplyComplex7complexS_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z15multiplyComplex7complexS_, .-_Z15multiplyComplex7complexS_
	.globl	_Z10addComplex7complexS_
	.type	_Z10addComplex7complexS_, @function
_Z10addComplex7complexS_:
.LFB2178:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z15multiplyComplex7complexS_
	.cfi_endproc
.LFE2178:
	.size	_Z10addComplex7complexS_, .-_Z10addComplex7complexS_
	.globl	_Z15subtractComplex7complexS_
	.type	_Z15subtractComplex7complexS_, @function
_Z15subtractComplex7complexS_:
.LFB2180:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z15multiplyComplex7complexS_
	.cfi_endproc
.LFE2180:
	.size	_Z15subtractComplex7complexS_, .-_Z15subtractComplex7complexS_
	.globl	_Z15compute_twiddleP7complexPi
	.type	_Z15compute_twiddleP7complexPi, @function
_Z15compute_twiddleP7complexPi:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2030:
	.size	_Z15compute_twiddleP7complexPi, .-_Z15compute_twiddleP7complexPi
	.globl	_Z49__device_stub__Z16compute_Even_OddP7complexS0_S0_P7complexS0_S0_
	.type	_Z49__device_stub__Z16compute_Even_OddP7complexS0_S0_P7complexS0_S0_, @function
_Z49__device_stub__Z16compute_Even_OddP7complexS0_S0_P7complexS0_S0_:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z16compute_Even_OddP7complexS0_S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L10:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z49__device_stub__Z16compute_Even_OddP7complexS0_S0_P7complexS0_S0_, .-_Z49__device_stub__Z16compute_Even_OddP7complexS0_S0_P7complexS0_S0_
	.globl	_Z16compute_Even_OddP7complexS0_S0_
	.type	_Z16compute_Even_OddP7complexS0_S0_, @function
_Z16compute_Even_OddP7complexS0_S0_:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z16compute_Even_OddP7complexS0_S0_P7complexS0_S0_
	.cfi_endproc
.LFE2057:
	.size	_Z16compute_Even_OddP7complexS0_S0_, .-_Z16compute_Even_OddP7complexS0_S0_
	.globl	_Z47__device_stub__Z14sum_RegressionP7complexS0_S0_P7complexS0_S0_
	.type	_Z47__device_stub__Z14sum_RegressionP7complexS0_S0_P7complexS0_S0_, @function
_Z47__device_stub__Z14sum_RegressionP7complexS0_S0_P7complexS0_S0_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z14sum_RegressionP7complexS0_S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L16:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z47__device_stub__Z14sum_RegressionP7complexS0_S0_P7complexS0_S0_, .-_Z47__device_stub__Z14sum_RegressionP7complexS0_S0_P7complexS0_S0_
	.globl	_Z14sum_RegressionP7complexS0_S0_
	.type	_Z14sum_RegressionP7complexS0_S0_, @function
_Z14sum_RegressionP7complexS0_S0_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z14sum_RegressionP7complexS0_S0_P7complexS0_S0_
	.cfi_endproc
.LFE2059:
	.size	_Z14sum_RegressionP7complexS0_S0_, .-_Z14sum_RegressionP7complexS0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC15:
	.string	"Cuda time : %f milli secs\n"
.LC16:
	.string	"PARALLEL VERSION\n\n"
.LC17:
	.string	"TOTAL PROCESSED SAMPLES: %d\n"
.LC18:
	.string	"==================\n"
.LC19:
	.string	"XR[%d]: %f\n"
.LC20:
	.string	"XI[%d]: %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$262144, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$112, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$262144, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$262144, %esi
	movq	%rax, %rbp
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$262144, %esi
	call	cudaMalloc@PLT
	movq	.LC0(%rip), %rax
	movsd	.LC1(%rip), %xmm0
	movsd	.LC6(%rip), %xmm1
	movq	%rax, (%rbx)
	movq	.LC2(%rip), %rax
	movsd	%xmm0, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	.LC3(%rip), %rax
	movsd	%xmm1, 48(%rbx)
	movq	%rax, 24(%rbx)
	movq	.LC4(%rip), %rax
	movsd	%xmm1, 88(%rbx)
	movq	%rax, 32(%rbx)
	movq	.LC5(%rip), %rax
	movsd	%xmm0, 104(%rbx)
	movq	%rax, 40(%rbx)
	movq	.LC7(%rip), %rax
	movq	%rax, 56(%rbx)
	movq	.LC8(%rip), %rax
	movq	%rax, 64(%rbx)
	movq	.LC9(%rip), %rax
	movq	%rax, 72(%rbx)
	movq	.LC10(%rip), %rax
	movq	%rax, 80(%rbx)
	movq	.LC11(%rip), %rax
	movq	%rax, 96(%rbx)
	movq	.LC12(%rip), %rax
	movq	%rax, 112(%rbx)
	movq	.LC13(%rip), %rax
	movq	%rax, 120(%rbx)
	xorl	%eax, %eax
.L22:
	movq	$0x000000000, 128(%rbx,%rax)
	movq	$0x000000000, 136(%rbx,%rax)
	addq	$16, %rax
	cmpq	$262016, %rax
	jne	.L22
	call	clock@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$262144, %edx
	movl	$4194305, %ebx
	call	cudaMemcpy@PLT
	leaq	24(%rsp), %rdi
	movl	$1073741824, %esi
	salq	$10, %rbx
	call	cudaMalloc@PLT
	movl	$1073741824, %esi
	leaq	32(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$131073, %eax
	leaq	40(%rsp), %rdi
	movl	$1, 60(%rsp)
	salq	$15, %rax
	movq	%rbx, 64(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 72(%rsp)
	call	cudaEventCreate@PLT
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$65537, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$16, %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rbx, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rdi, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z49__device_stub__Z16compute_Even_OddP7complexS0_S0_P7complexS0_S0_
.L23:
	movl	72(%rsp), %ecx
	movq	64(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	52(%rsp), %rdi
	movl	60(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	16(%rsp), %rdx
	movq	32(%rsp), %rsi
	movq	24(%rsp), %rdi
	call	_Z47__device_stub__Z14sum_RegressionP7complexS0_S0_P7complexS0_S0_
.L24:
	call	clock@PLT
	leaq	88(%rsp), %rdi
	movq	%rbp, %rbx
	leaq	.LC18(%rip), %r12
	call	cudaEventCreate@PLT
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	88(%rsp), %rdx
	movq	40(%rsp), %rsi
	leaq	76(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC15(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	76(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movl	$262144, %edx
	movq	%rbp, %rdi
	xorl	%ebp, %ebp
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC16(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$16384, %edx
	leaq	.LC17(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
.L25:
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	addq	$16, %rbx
	call	__printf_chk@PLT
	movsd	-16(%rbx), %xmm0
	movl	%ebp, %edx
	movb	$1, %al
	leaq	.LC19(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movsd	-8(%rbx), %xmm0
	movl	%ebp, %edx
	movb	$1, %al
	leaq	.LC20(%rip), %rsi
	movl	$2, %edi
	incl	%ebp
	call	__printf_chk@PLT
	cmpl	$8, %ebp
	jne	.L25
	xorl	%eax, %eax
	movq	%r12, %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$112, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC21:
	.string	"_Z14sum_RegressionP7complexS0_S0_"
.LC22:
	.string	"_Z16compute_Even_OddP7complexS0_S0_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z14sum_RegressionP7complexS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z16compute_Even_OddP7complexS0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2061:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	-858993459
	.long	1074580684
	.align 8
.LC1:
	.long	-858993459
	.long	1074056396
	.align 8
.LC2:
	.long	858993459
	.long	1074213683
	.align 8
.LC3:
	.long	858993459
	.long	1075393331
	.align 8
.LC4:
	.long	1717986918
	.long	1075209830
	.align 8
.LC5:
	.long	0
	.long	1074790400
	.align 8
.LC6:
	.long	858993459
	.long	1075000115
	.align 8
.LC7:
	.long	858993459
	.long	1075983155
	.align 8
.LC8:
	.long	1717986918
	.long	1074423398
	.align 8
.LC9:
	.long	-1717986918
	.long	1071225241
	.align 8
.LC10:
	.long	-1717986918
	.long	1075288473
	.align 8
.LC11:
	.long	0
	.long	1075052544
	.align 8
.LC12:
	.long	858993459
	.long	1074869043
	.align 8
.LC13:
	.long	1717986918
	.long	1074816614
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//******************************************************
// Project
// Names: Anthony Enem
// Parallel Programming Date: 12/05/16
//******************************************************
// This program implements the cooley tukey fft algorithm
// and computes the values fro X_k from 0 to N in parallel. 
//******************************************************

#include<hip/hip_runtime.h>
#include<sys/time.h>
#include<stdio.h>
#include<math.h>
#include<time.h>

//define struct for complex numbers
typedef struct complex{
    double real;
    double imaginary;
} complex;

#define N 16384
#define PI 3.14159265359

//******************************************************
// Parameters: two complex structs a and b
// This function multiplies 2 complex structs and returns
// the result as a complex struct
//******************************************************

__device__
complex multiplyComplex(complex a, complex b)
{
    complex result;
    result.real = a.real*b.real - a.imaginary*b.imaginary;
    result.imaginary = a.real*b.imaginary + b.real*a.imaginary;

    return result;
}

//******************************************************
// Parameters: two complex structs a and b
// This function adds 2 complex structs and returns
// the result as a complex struct
//******************************************************
__device__
complex addComplex(complex a, complex b)
{
    complex result = {a.real+b.real, a.imaginary+b.imaginary};
    return result;
}

//******************************************************
// Parameters: two complex structs a and b
// This function subtracts 2 complex structs and returns
// the result as a complex struct
//******************************************************
__device__
complex subtractComplex(complex a, complex b)
{
    complex result = {a.real-b.real, a.imaginary-b.imaginary};
    return result;
}

//******************************************************
// Each thread for this kernel computes the even and odd portions of the
// fft formula
//******************************************************
__global__
void compute_Even_Odd(complex* xInput_d, complex *even_d, complex* odd_d)
{	
	int idx = blockIdx.x*1024 + threadIdx.x;
	int k = idx / (N/2);
	int m = idx % (N/2);
	
	//compute exponent
    double exp = -4.0 * PI * m * k / N;
	
	complex e_part;    

    //compute part with e^(i * exponent)
    e_part.real = cos(exp);
    e_part.imaginary = sin(exp);
        
    //save even part
	even_d[idx] = multiplyComplex(xInput_d[2*m], e_part);
	
    //save odd part
    odd_d[idx] = multiplyComplex(xInput_d[2*m+1], e_part);
}

//******************************************************
// Parameters: pointer to complex twiddle and integer k
// This function computes the twiddle factor for given
// N and k values
//******************************************************
__device__
void compute_twiddle(complex* twiddle, int* k)
{
    double exp = -2.0 * PI * (*k) / N;
	twiddle->real = cos(exp);
	twiddle->imaginary = sin(exp);
}

//******************************************************
// This computes the summation for the fft algorithm 
// using regression
//******************************************************
__global__
void sum_Regression(complex* even_d, complex* odd_d, complex* result_d)
{	
	int n = N/2;
	int idx = blockIdx.x*1024 + threadIdx.x;
	int k = idx / (n/2); //we only need half the number of threads for regression
	int m = idx % (n/2);
	int z = k*n + m;
	
	while(n > 1)
	{
		__syncthreads();		
		if(m < n/2)
		{
			even_d[z] = addComplex(even_d[z], even_d[z + n/2]);
			odd_d[z] = addComplex(odd_d[z], odd_d[z + n/2]);
		}		
		n = n/2;
	}
	if(m == 0)
	{
		compute_twiddle(result_d + k, &k);
		//calculate twiddle * O_k
		odd_d[z] = multiplyComplex(odd_d[z], result_d[k]);
		
		//compute X_k and X_k + N/2
		result_d[k] = addComplex(even_d[z], odd_d[z]);
		result_d[k + N/2] = subtractComplex(even_d[z], odd_d[z]);
	}
}

int main()
{	
	complex* xInput, *result;
	
	complex* xInput_d, *result_d;
	complex *even_d, *odd_d;

	//allocate memory
	xInput = (complex *)malloc(N * sizeof(complex));
	result = (complex *)malloc(N * sizeof(complex));
	
	hipMalloc((void**)&xInput_d, N*sizeof(complex));
	hipMalloc((void**)&result_d, N*sizeof(complex));
	
	//set defined values from 0 to 7 for xInput
	xInput[0].real = 3.6;
	xInput[0].imaginary = 2.6;
	xInput[1].real = 2.9;
	xInput[1].imaginary = 6.3;
	xInput[2].real = 5.6;
	xInput[2].imaginary = 4;
	xInput[3].real = 4.8;
	xInput[3].imaginary = 9.1;
	xInput[4].real = 3.3;
	xInput[4].imaginary = 0.4;
	xInput[5].real = 5.9;
	xInput[5].imaginary = 4.8;
	xInput[6].real = 5;
	xInput[6].imaginary = 2.6;
	xInput[7].real = 4.3;
	xInput[7].imaginary = 4.1;
	
	//set defined values for x[8] to x[N-1] as 0
	for (int i = 8; i < N; i++)
	{
		xInput[i].real = 0;
		xInput[i].imaginary = 0;
	}
	
	clock_t st = clock();
	hipMemcpy(xInput_d, xInput, sizeof(complex)*N, hipMemcpyHostToDevice);
	
	int m_blocks, m_threads;
	m_threads = (N/2)*(N/2); //k goes 0 to N - 1 (but same values used 2ice),
							//m goes 0 to N/2-1 for each k value
	
	hipMalloc((void**)&even_d, sizeof(complex)*m_threads);
	hipMalloc((void**)&odd_d, sizeof(complex)*m_threads);
	
	m_blocks = (m_threads)/1024; //number of blocks we need
	
	if(m_blocks == 0){
		m_blocks = 1;
	}
	else{
		m_threads = 1024;
	}
	
	//Use half the number of blocks to compute results using regression
	dim3 dimSumGrid(m_blocks/2, 1);
	dim3 dimSumBlock(m_threads, 1);
	if(m_blocks == 1)
	{
		dimSumGrid = dim3(m_blocks, 1);
		dimSumBlock = dim3(m_threads/2, 1);
	}
		
	
	hipEvent_t start, stop;
	float elapsedTime;

	hipEventCreate(&start);
	hipEventRecord(start,0);
	
	compute_Even_Odd<<<m_blocks, m_threads>>>(xInput_d, even_d, odd_d);
	
	sum_Regression<<<dimSumGrid, dimSumBlock>>>(even_d, odd_d, result_d);
	
	clock_t end = clock();
	hipEventCreate(&stop);
	hipEventRecord(stop,0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&elapsedTime, start,stop);
	
	printf("Cuda time : %f milli secs\n", elapsedTime);	
	
	hipMemcpy(result, result_d, sizeof(complex)*N, hipMemcpyDeviceToHost);
	
	hipFree(xInput_d);
	hipFree(result_d);
	hipFree(even_d);
	hipFree(odd_d);
	
	printf("PARALLEL VERSION\n\n");
	printf("TOTAL PROCESSED SAMPLES: %d\n", N);
	
	for(int i = 0; i < 8; i++)
	{
		printf("==================\n");
		printf("XR[%d]: %f\n", i, result[i].real);
		printf("XI[%d]: %f\n", i, result[i].imaginary);
	}
	
	printf("==================\n");
	
	//printf("\nC clock Time: %f\n", ((double)(end - st)) / CLOCKS_PER_SEC);
	
	
	return 0;
	
}
	.text
	.file	"FFT_Parallel.hip"
	.globl	_Z31__device_stub__compute_Even_OddP7complexS0_S0_ # -- Begin function _Z31__device_stub__compute_Even_OddP7complexS0_S0_
	.type	_Z31__device_stub__compute_Even_OddP7complexS0_S0_,@function
_Z31__device_stub__compute_Even_OddP7complexS0_S0_: # @_Z31__device_stub__compute_Even_OddP7complexS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z16compute_Even_OddP7complexS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z31__device_stub__compute_Even_OddP7complexS0_S0_, .Lfunc_end0-_Z31__device_stub__compute_Even_OddP7complexS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__sum_RegressionP7complexS0_S0_ # -- Begin function _Z29__device_stub__sum_RegressionP7complexS0_S0_
	.type	_Z29__device_stub__sum_RegressionP7complexS0_S0_,@function
_Z29__device_stub__sum_RegressionP7complexS0_S0_: # @_Z29__device_stub__sum_RegressionP7complexS0_S0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14sum_RegressionP7complexS0_S0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__sum_RegressionP7complexS0_S0_, .Lfunc_end1-_Z29__device_stub__sum_RegressionP7complexS0_S0_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$56, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movabsq	$4294968320, %r14               # imm = 0x100000400
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %r15
	movl	$262144, %edi                   # imm = 0x40000
	callq	malloc
	movq	%rax, %rbx
	leaq	24(%rsp), %r12
	movl	$262144, %esi                   # imm = 0x40000
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$262144, %esi                   # imm = 0x40000
	callq	hipMalloc
	movabsq	$4615288898129284301, %rax      # imm = 0x400CCCCCCCCCCCCD
	movq	%rax, (%r15)
	movabsq	$4613037098315599053, %rax      # imm = 0x4004CCCCCCCCCCCD
	movq	%rax, 8(%r15)
	movabsq	$4613712638259704627, %rcx      # imm = 0x4007333333333333
	movq	%rcx, 16(%r15)
	movabsq	$4618779187840496435, %rcx      # imm = 0x4019333333333333
	movq	%rcx, 24(%r15)
	movabsq	$4617991057905706598, %rcx      # imm = 0x4016666666666666
	movq	%rcx, 32(%r15)
	movabsq	$4616189618054758400, %rcx      # imm = 0x4010000000000000
	movq	%rcx, 40(%r15)
	movabsq	$4617090337980232499, %rcx      # imm = 0x4013333333333333
	movq	%rcx, 48(%r15)
	movabsq	$4621312462630892339, %rdx      # imm = 0x4022333333333333
	movq	%rdx, 56(%r15)
	movabsq	$4614613358185178726, %rdx      # imm = 0x400A666666666666
	movq	%rdx, 64(%r15)
	movabsq	$4600877379321698714, %rdx      # imm = 0x3FD999999999999A
	movq	%rdx, 72(%r15)
	movabsq	$4618328827877759386, %rdx      # imm = 0x401799999999999A
	movq	%rdx, 80(%r15)
	movq	%rcx, 88(%r15)
	movabsq	$4617315517961601024, %rcx      # imm = 0x4014000000000000
	movq	%rcx, 96(%r15)
	movq	%rax, 104(%r15)
	movabsq	$4616527388026811187, %rax      # imm = 0x4011333333333333
	movq	%rax, 112(%r15)
	movabsq	$4616302208045442662, %rax      # imm = 0x4010666666666666
	movq	%rax, 120(%r15)
	leaq	128(%r15), %rdi
	movl	$262016, %edx                   # imm = 0x3FF80
	xorl	%esi, %esi
	callq	memset@PLT
	callq	clock
	movq	(%r12), %rdi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%r15, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	8(%rsp), %rdi
	movl	$1073741824, %esi               # imm = 0x40000000
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$1073741824, %esi               # imm = 0x40000000
	callq	hipMalloc
	leaq	32(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	64512(%r14), %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	24(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	callq	_Z31__device_stub__compute_Even_OddP7complexS0_S0_
.LBB2_2:
	leaq	31744(%r14), %rdi
	movl	$1, %esi
	movq	%r14, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movq	16(%rsp), %rdx
	callq	_Z29__device_stub__sum_RegressionP7complexS0_S0_
.LBB2_4:
	callq	clock
	leaq	48(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	movq	(%r15), %rdi
	xorl	%r14d, %r14d
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r15), %rdi
	callq	hipEventSynchronize
	movq	32(%rsp), %rsi
	movq	(%r15), %rdx
	leaq	44(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%r15), %xmm0
	movl	$.L.str, %edi
	movb	$1, %al
	callq	printf
	movq	16(%rsp), %rsi
	movl	$262144, %edx                   # imm = 0x40000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	$.L.str.2, %edi
	movl	$16384, %esi                    # imm = 0x4000
	xorl	%eax, %eax
	callq	printf
	addq	$8, %rbx
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	movsd	-8(%rbx), %xmm0                 # xmm0 = mem[0],zero
	movl	$.L.str.4, %edi
	movl	%r14d, %esi
	movb	$1, %al
	callq	printf
	movsd	(%rbx), %xmm0                   # xmm0 = mem[0],zero
	movl	$.L.str.5, %edi
	movl	%r14d, %esi
	movb	$1, %al
	callq	printf
	incq	%r14
	addq	$16, %rbx
	cmpq	$8, %r14
	jne	.LBB2_5
# %bb.6:
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z16compute_Even_OddP7complexS0_S0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14sum_RegressionP7complexS0_S0_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z16compute_Even_OddP7complexS0_S0_,@object # @_Z16compute_Even_OddP7complexS0_S0_
	.section	.rodata,"a",@progbits
	.globl	_Z16compute_Even_OddP7complexS0_S0_
	.p2align	3, 0x0
_Z16compute_Even_OddP7complexS0_S0_:
	.quad	_Z31__device_stub__compute_Even_OddP7complexS0_S0_
	.size	_Z16compute_Even_OddP7complexS0_S0_, 8

	.type	_Z14sum_RegressionP7complexS0_S0_,@object # @_Z14sum_RegressionP7complexS0_S0_
	.globl	_Z14sum_RegressionP7complexS0_S0_
	.p2align	3, 0x0
_Z14sum_RegressionP7complexS0_S0_:
	.quad	_Z29__device_stub__sum_RegressionP7complexS0_S0_
	.size	_Z14sum_RegressionP7complexS0_S0_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Cuda time : %f milli secs\n"
	.size	.L.str, 27

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"TOTAL PROCESSED SAMPLES: %d\n"
	.size	.L.str.2, 29

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"XR[%d]: %f\n"
	.size	.L.str.4, 12

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"XI[%d]: %f\n"
	.size	.L.str.5, 12

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z16compute_Even_OddP7complexS0_S0_"
	.size	.L__unnamed_1, 36

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z14sum_RegressionP7complexS0_S0_"
	.size	.L__unnamed_2, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"PARALLEL VERSION\n"
	.size	.Lstr, 18

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"=================="
	.size	.Lstr.2, 19

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z31__device_stub__compute_Even_OddP7complexS0_S0_
	.addrsig_sym _Z29__device_stub__sum_RegressionP7complexS0_S0_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z16compute_Even_OddP7complexS0_S0_
	.addrsig_sym _Z14sum_RegressionP7complexS0_S0_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z16compute_Even_OddP7complexS0_S0_ ; -- Begin function _Z16compute_Even_OddP7complexS0_S0_
	.globl	_Z16compute_Even_OddP7complexS0_S0_
	.p2align	8
	.type	_Z16compute_Even_OddP7complexS0_S0_,@function
_Z16compute_Even_OddP7complexS0_S0_:    ; @_Z16compute_Even_OddP7complexS0_S0_
; %bb.0:
	v_lshl_or_b32 v0, s15, 10, v0
	s_mov_b32 s2, 0x54442eea
	s_mov_b32 s3, 0xc02921fb
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr6_vgpr7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshrrev_b32_e32 v2, 19, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v0, v2
	v_ashrrev_i32_e32 v4, 13, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_i32_i24_e32 v2, 0x2000, v4
	v_cvt_f64_i32_e32 v[4:5], v4
	v_sub_nc_u32_e32 v20, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[2:3], v20
	v_mul_f64 v[2:3], v[2:3], s[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[4:5]
                                        ; implicit-def: $vgpr4_vgpr5
	v_ldexp_f64 v[2:3], v[2:3], -14
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s3, 0x41d00000, |v[2:3]|
	v_trig_preop_f64 v[16:17], |v[2:3]|, 0
	v_trig_preop_f64 v[12:13], |v[2:3]|, 1
	v_ldexp_f64 v[18:19], |v[2:3]|, 0xffffff80
	v_trig_preop_f64 v[8:9], |v[2:3]|, 2
	v_and_b32_e32 v23, 0x7fffffff, v3
	s_and_saveexec_b32 s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s2
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_mov_b32_e32 v34, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v5, v23, v19 :: v_dual_cndmask_b32 v4, v2, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[6:7], v[16:17], v[4:5]
	v_mul_f64 v[10:11], v[12:13], v[4:5]
	v_mul_f64 v[30:31], v[8:9], v[4:5]
	v_fma_f64 v[14:15], v[16:17], v[4:5], -v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[32:33], v[12:13], v[4:5], -v[10:11]
	v_fma_f64 v[4:5], v[8:9], v[4:5], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[10:11], v[14:15]
	v_add_f64 v[24:25], v[21:22], -v[10:11]
	v_add_f64 v[28:29], v[6:7], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[21:22], -v[24:25]
	v_add_f64 v[14:15], v[14:15], -v[24:25]
	v_ldexp_f64 v[24:25], v[28:29], -2
	v_add_f64 v[6:7], v[28:29], -v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[10:11], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[32:33]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[24:25]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[6:7], v[21:22], -v[6:7]
	v_add_f64 v[10:11], v[14:15], v[10:11]
	v_fract_f64_e32 v[14:15], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[26:27], v[10:11]
	v_dual_cndmask_b32 v15, 0, v15 :: v_dual_cndmask_b32 v14, 0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[14:15], v[14:15], 2
	v_add_f64 v[24:25], v[6:7], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[24:25], v[14:15]
	v_add_f64 v[6:7], v[24:25], -v[6:7]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[21:22], -v[6:7]
	v_cndmask_b32_e64 v35, 0, 0x40100000, vcc_lo
	v_add_f64 v[39:40], v[26:27], -v[28:29]
	v_add_f64 v[28:29], v[32:33], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[14:15], v[34:35]
	v_add_f64 v[35:36], v[21:22], -v[26:27]
	v_add_f64 v[32:33], v[30:31], -v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[24:25], v[14:15]
	v_add_f64 v[41:42], v[21:22], -v[35:36]
	v_add_f64 v[10:11], v[10:11], -v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], v[32:33]
	v_cvt_i32_f64_e32 v37, v[37:38]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[26:27], -v[41:42]
	v_cvt_f64_i32_e32 v[35:36], v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[26:27]
	v_add_f64 v[14:15], v[14:15], -v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[28:29], v[10:11]
	v_add_f64 v[26:27], v[24:25], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[10:11]
	v_add_f64 v[10:11], v[26:27], -v[14:15]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	v_add_f64 v[6:7], v[24:25], -v[10:11]
	v_cndmask_b32_e64 v35, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v21, s2, 0, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[26:27], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[6:7], v[4:5]
	v_mul_f64 v[14:15], v[10:11], s[6:7]
	v_add_f64 v[6:7], v[10:11], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[24:25], v[10:11], s[6:7], -v[14:15]
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[10:11], s[8:9], v[24:25]
	v_fma_f64 v[6:7], v[4:5], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[14:15], v[6:7]
	v_add_f64 v[10:11], v[4:5], -v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
.LBB0_2:                                ; %Flow44
	s_and_not1_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[4:5], |v[2:3]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[10:11], v[4:5]
	v_fma_f64 v[4:5], v[10:11], s[4:5], |v[2:3]|
	v_mul_f64 v[6:7], v[10:11], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[10:11], s[6:7], v[4:5]
	v_add_f64 v[14:15], v[4:5], v[6:7]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[14:15]
	v_add_f64 v[14:15], v[14:15], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7]
	v_add_f64 v[4:5], v[14:15], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_fma_f64 v[6:7], v[10:11], s[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[21:22], v[6:7]
	v_add_f64 v[14:15], v[4:5], -v[21:22]
	v_cvt_i32_f64_e32 v21, v[10:11]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[14:15]
.LBB0_4:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s2
	s_cbranch_execz .LBB0_6
; %bb.5:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_mov_b32_e32 v32, 0
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v11, v23, v19 :: v_dual_cndmask_b32 v10, v2, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[16:17], v[10:11]
	v_mul_f64 v[18:19], v[12:13], v[10:11]
	v_mul_f64 v[30:31], v[8:9], v[10:11]
	v_fma_f64 v[16:17], v[16:17], v[10:11], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[12:13], v[10:11], -v[18:19]
	v_fma_f64 v[8:9], v[8:9], v[10:11], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[18:19], v[16:17]
	v_add_f64 v[24:25], v[22:23], -v[18:19]
	v_add_f64 v[28:29], v[14:15], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[22:23], -v[24:25]
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	v_ldexp_f64 v[24:25], v[28:29], -2
	v_add_f64 v[14:15], v[28:29], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[12:13]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[24:25]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[22:23], -v[14:15]
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_fract_f64_e32 v[18:19], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[16:17]
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[18:19], v[18:19], 2
	v_add_f64 v[24:25], v[14:15], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[24:25], v[18:19]
	v_add_f64 v[10:11], v[24:25], -v[14:15]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[22:23], -v[10:11]
	v_cndmask_b32_e64 v33, 0, 0x40100000, vcc_lo
	v_add_f64 v[37:38], v[26:27], -v[28:29]
	v_add_f64 v[12:13], v[12:13], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[32:33]
	v_add_f64 v[33:34], v[22:23], -v[26:27]
	v_add_f64 v[28:29], v[30:31], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[24:25], v[18:19]
	v_add_f64 v[39:40], v[22:23], -v[33:34]
	v_add_f64 v[16:17], v[16:17], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], v[28:29]
	v_cvt_i32_f64_e32 v35, v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[26:27], -v[39:40]
	v_cvt_f64_i32_e32 v[33:34], v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_add_f64 v[14:15], v[24:25], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], v[12:13]
	v_add_f64 v[12:13], v[14:15], -v[18:19]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[10:11], v[8:9]
	v_add_f64 v[10:11], v[24:25], -v[12:13]
	v_cndmask_b32_e64 v33, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v22, s2, 0, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_f64 v[10:11], v[14:15], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[10:11], v[8:9]
	v_mul_f64 v[14:15], v[12:13], s[4:5]
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[12:13], s[4:5], -v[14:15]
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[12:13], s[6:7], v[16:17]
	v_fma_f64 v[8:9], v[8:9], s[4:5], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[14:15], v[8:9]
	v_add_f64 v[12:13], v[10:11], -v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[8:9], -v[12:13]
.LBB0_6:                                ; %Flow
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_8
; %bb.7:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[8:9], |v[2:3]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[8:9], v[8:9]
	v_fma_f64 v[10:11], v[8:9], s[4:5], |v[2:3]|
	v_mul_f64 v[12:13], v[8:9], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v22, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[8:9], s[6:7], v[10:11]
	v_add_f64 v[14:15], v[10:11], v[12:13]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_fma_f64 v[12:13], v[8:9], s[6:7], v[12:13]
	v_add_f64 v[10:11], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	v_fma_f64 v[12:13], v[8:9], s[4:5], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[16:17], v[12:13]
	v_add_f64 v[14:15], v[10:11], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[12:13], -v[14:15]
.LBB0_8:                                ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_f64 v[8:9], v[4:5], v[4:5]
	v_mul_f64 v[12:13], v[10:11], v[10:11]
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_lshlrev_b32_e32 v16, 1, v20
	s_mov_b32 s8, 0xb42fdfa7
	s_mov_b32 s10, 0xf9a43bb8
	s_mov_b32 s9, 0xbe5ae600
	s_mov_b32 s11, 0x3de5e0b2
	v_ashrrev_i32_e32 v17, 31, v16
	s_mov_b32 s0, 0x9037ab78
	s_mov_b32 s1, 0x3e21eeb6
	v_mul_f64 v[41:42], v[6:7], 0.5
	v_mul_f64 v[47:48], v[14:15], 0.5
	v_lshlrev_b64 v[16:17], 4, v[16:17]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, s4, v16
	v_add_co_ci_u32_e32 v26, vcc_lo, s5, v17, vcc_lo
	s_mov_b32 s4, 0x46cc5e42
	s_mov_b32 s5, 0xbda907db
	global_load_b128 v[16:19], v[25:26], off
	v_fma_f64 v[23:24], v[8:9], s[10:11], s[8:9]
	v_fma_f64 v[27:28], v[12:13], s[10:11], s[8:9]
	s_mov_b32 s8, 0x796cde01
	s_mov_b32 s9, 0x3ec71de3
	v_fma_f64 v[29:30], v[8:9], s[4:5], s[0:1]
	v_mul_f64 v[31:32], v[8:9], 0.5
	v_fma_f64 v[33:34], v[12:13], s[4:5], s[0:1]
	v_mul_f64 v[35:36], v[12:13], 0.5
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s4, 0x19e83e5c
	s_mov_b32 s1, 0xbe927e4f
	s_mov_b32 s5, 0xbf2a01a0
	v_mul_f64 v[43:44], v[4:5], -v[8:9]
	v_mul_f64 v[49:50], v[10:11], -v[12:13]
	v_fma_f64 v[23:24], v[8:9], v[23:24], s[8:9]
	v_fma_f64 v[27:28], v[12:13], v[27:28], s[8:9]
	v_fma_f64 v[29:30], v[8:9], v[29:30], s[0:1]
	v_add_f64 v[37:38], -v[31:32], 1.0
	v_fma_f64 v[33:34], v[12:13], v[33:34], s[0:1]
	v_add_f64 v[39:40], -v[35:36], 1.0
	s_mov_b32 s0, 0x19f4ec90
	s_mov_b32 s1, 0x3efa01a0
	v_fma_f64 v[23:24], v[8:9], v[23:24], s[4:5]
	v_fma_f64 v[27:28], v[12:13], v[27:28], s[4:5]
	s_mov_b32 s4, 0x11110bb3
	s_mov_b32 s5, 0x3f811111
	v_fma_f64 v[29:30], v[8:9], v[29:30], s[0:1]
	v_add_f64 v[45:46], -v[37:38], 1.0
	v_fma_f64 v[33:34], v[12:13], v[33:34], s[0:1]
	v_add_f64 v[51:52], -v[39:40], 1.0
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	v_fma_f64 v[23:24], v[8:9], v[23:24], s[4:5]
	v_fma_f64 v[27:28], v[12:13], v[27:28], s[4:5]
	v_fma_f64 v[29:30], v[8:9], v[29:30], s[0:1]
	v_add_f64 v[31:32], v[45:46], -v[31:32]
	v_fma_f64 v[33:34], v[12:13], v[33:34], s[0:1]
	v_add_f64 v[35:36], v[51:52], -v[35:36]
	s_mov_b32 s0, 0x55555555
	s_mov_b32 s1, 0x3fa55555
	v_fma_f64 v[23:24], v[43:44], v[23:24], v[41:42]
	v_fma_f64 v[27:28], v[49:50], v[27:28], v[47:48]
	v_mul_f64 v[41:42], v[8:9], v[8:9]
	v_fma_f64 v[29:30], v[8:9], v[29:30], s[0:1]
	v_fma_f64 v[31:32], v[4:5], -v[6:7], v[31:32]
	v_fma_f64 v[6:7], v[8:9], v[23:24], -v[6:7]
	v_mul_f64 v[8:9], v[12:13], v[12:13]
	v_fma_f64 v[23:24], v[12:13], v[33:34], s[0:1]
	v_fma_f64 v[33:34], v[10:11], -v[14:15], v[35:36]
	v_fma_f64 v[12:13], v[12:13], v[27:28], -v[14:15]
	s_mov_b32 s1, 0xbfc55555
	v_fma_f64 v[14:15], v[41:42], v[29:30], v[31:32]
	v_fma_f64 v[6:7], v[43:44], s[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[8:9], v[8:9], v[23:24], v[33:34]
	v_fma_f64 v[12:13], v[49:50], s[0:1], v[12:13]
	v_cmp_class_f64_e64 s0, v[2:3], 0x1f8
	v_add_f64 v[14:15], v[37:38], v[14:15]
	v_lshlrev_b32_e32 v2, 30, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v3
	v_and_b32_e32 v2, 0x80000000, v2
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_add_f64 v[6:7], v[39:40], v[8:9]
	v_add_f64 v[8:9], v[10:11], -v[12:13]
	v_and_b32_e32 v10, 1, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_and_b32_e32 v10, 1, v22
	v_cmp_eq_u32_e64 s1, 0, v10
	v_cndmask_b32_e32 v4, v4, v14, vcc_lo
	v_xor_b32_e32 v5, 0x80000000, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v6, v8, s1
	v_cndmask_b32_e64 v6, v7, v9, s1
	v_cndmask_b32_e32 v5, v5, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, 0, v3, s0
	v_xor_b32_e32 v2, v6, v2
	v_cndmask_b32_e64 v6, 0, v4, s0
	v_lshlrev_b32_e32 v4, 30, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v9, 0x7ff80000, v2, s0
	v_and_b32_e32 v4, 0x80000000, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[2:3], v[18:19], v[8:9]
	v_mul_f64 v[10:11], v[16:17], v[8:9]
	v_xor_b32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 0x7ff80000, v4, s0
	v_fma_f64 v[2:3], v[16:17], v[6:7], -v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[18:19], v[6:7], v[10:11]
	v_lshlrev_b64 v[10:11], 4, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v11, vcc_lo
	global_store_b128 v[0:1], v[2:5], off
	global_load_b128 v[0:3], v[25:26], off offset:16
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[2:3], v[8:9]
	v_mul_f64 v[8:9], v[0:1], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], v[6:7], -v[4:5]
	v_fma_f64 v[2:3], v[2:3], v[6:7], v[8:9]
	v_add_co_u32 v4, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v11, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z16compute_Even_OddP7complexS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 53
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z16compute_Even_OddP7complexS0_S0_, .Lfunc_end0-_Z16compute_Even_OddP7complexS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2944
; NumSgprs: 18
; NumVgprs: 53
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 53
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14sum_RegressionP7complexS0_S0_ ; -- Begin function _Z14sum_RegressionP7complexS0_S0_
	.globl	_Z14sum_RegressionP7complexS0_S0_
	.p2align	8
	.type	_Z14sum_RegressionP7complexS0_S0_,@function
_Z14sum_RegressionP7complexS0_S0_:      ; @_Z14sum_RegressionP7complexS0_S0_
; %bb.0:
	v_lshl_or_b32 v0, s15, 10, v0
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mov_b32 s1, 0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 20, v1
	v_add_nc_u32_e32 v1, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 12, v1
	v_mul_i32_i24_e32 v1, 0x1000, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v1
	v_lshl_add_u32 v0, v6, 13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 4, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	s_movk_i32 s4, 0x2000
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshr_b32 s0, s4, 1
	s_mov_b32 s5, exec_lo
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	v_cmpx_gt_i32_e64 s0, v4
	s_cbranch_execz .LBB1_3
; %bb.2:                                ;   in Loop: Header=BB1_1 Depth=1
	s_lshl_b64 s[6:7], s[0:1], 4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v11, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v3, vcc_lo
	s_clause 0x1
	global_load_b128 v[7:10], v[2:3], off
	global_load_b128 v[11:14], v[11:12], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[11:12]
	v_add_f64 v[9:10], v[9:10], v[13:14]
	v_add_co_u32 v11, vcc_lo, v0, s6
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v1, vcc_lo
	global_store_b128 v[2:3], v[7:10], off
	s_clause 0x1
	global_load_b128 v[7:10], v[0:1], off
	global_load_b128 v[11:14], v[11:12], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[7:8], v[7:8], v[11:12]
	v_add_f64 v[9:10], v[9:10], v[13:14]
	global_store_b128 v[0:1], v[7:10], off
.LBB1_3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_cmp_gt_u32 s4, 3
	s_mov_b32 s4, s0
	s_cbranch_scc1 .LBB1_1
; %bb.4:
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_14
; %bb.5:
	v_cvt_f64_i32_e32 v[4:5], v6
	s_mov_b32 s0, 0x54442eea
	s_mov_b32 s1, 0xc01921fb
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr18_vgpr19
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[4:5], v[4:5], s[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[4:5], v[4:5], -14
	v_cmp_ngt_f64_e64 s1, 0x41d00000, |v[4:5]|
	v_trig_preop_f64 v[12:13], |v[4:5]|, 0
	v_trig_preop_f64 v[10:11], |v[4:5]|, 1
	v_ldexp_f64 v[14:15], |v[4:5]|, 0xffffff80
	v_trig_preop_f64 v[8:9], |v[4:5]|, 2
	v_and_b32_e32 v24, 0x7fffffff, v5
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB1_7
; %bb.6:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[4:5]|
	v_mov_b32_e32 v37, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_cndmask_b32_e32 v17, v24, v15, vcc_lo
	v_cndmask_b32_e32 v16, v4, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[12:13], v[16:17]
	v_mul_f64 v[20:21], v[10:11], v[16:17]
	v_fma_f64 v[22:23], v[12:13], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[10:11], v[16:17], -v[20:21]
	v_add_f64 v[25:26], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[25:26], -v[20:21]
	v_add_f64 v[31:32], v[18:19], v[25:26]
	v_add_f64 v[29:30], v[25:26], -v[27:28]
	v_add_f64 v[22:23], v[22:23], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[27:28], v[31:32], -2
	v_add_f64 v[18:19], v[31:32], -v[18:19]
	v_add_f64 v[20:21], v[20:21], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[27:28]|
	v_add_f64 v[18:19], v[25:26], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[20:21]
	v_fract_f64_e32 v[22:23], v[27:28]
	v_dual_cndmask_b32 v23, 0, v23 :: v_dual_cndmask_b32 v22, 0, v22
	v_mul_f64 v[33:34], v[8:9], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[22:23], v[22:23], 2
	v_add_f64 v[29:30], v[33:34], v[35:36]
	v_fma_f64 v[16:17], v[8:9], v[16:17], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[25:26], v[29:30], v[20:21]
	v_add_f64 v[27:28], v[18:19], v[25:26]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[27:28], v[22:23]
	v_add_f64 v[18:19], v[27:28], -v[18:19]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[31:32]
	v_add_f64 v[31:32], v[29:30], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[25:26], -v[18:19]
	v_cndmask_b32_e64 v38, 0, 0x40100000, vcc_lo
	v_add_f64 v[42:43], v[29:30], -v[31:32]
	v_add_f64 v[31:32], v[35:36], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], v[37:38]
	v_add_f64 v[38:39], v[25:26], -v[29:30]
	v_add_f64 v[35:36], v[33:34], -v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[40:41], v[27:28], v[22:23]
	v_add_f64 v[44:45], v[25:26], -v[38:39]
	v_add_f64 v[20:21], v[20:21], -v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[31:32], v[31:32], v[35:36]
	v_cvt_i32_f64_e32 v7, v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[29:30], -v[44:45]
	v_cvt_f64_i32_e32 v[38:39], v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[29:30]
	v_add_f64 v[22:23], v[22:23], -v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[31:32], v[20:21]
	v_add_f64 v[29:30], v[27:28], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_add_f64 v[20:21], v[29:30], -v[22:23]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[18:19], v[16:17]
	v_add_f64 v[18:19], v[27:28], -v[20:21]
	v_cndmask_b32_e64 v38, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v7, s0, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[29:30], -v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[18:19], v[16:17]
	v_mul_f64 v[22:23], v[20:21], s[6:7]
	v_add_f64 v[18:19], v[20:21], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], v[20:21], s[6:7], -v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[20:21], s[8:9], v[25:26]
	v_fma_f64 v[18:19], v[16:17], s[6:7], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[22:23], v[18:19]
	v_add_f64 v[20:21], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[20:21]
.LBB1_7:                                ; %Flow111
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB1_9
; %bb.8:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[16:17], |v[4:5]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[20:21], v[16:17]
	v_fma_f64 v[16:17], v[20:21], s[4:5], |v[4:5]|
	v_mul_f64 v[18:19], v[20:21], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v7, v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[20:21], s[6:7], v[16:17]
	v_add_f64 v[22:23], v[16:17], v[18:19]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[22:23]
	v_add_f64 v[22:23], v[22:23], -v[25:26]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_fma_f64 v[18:19], v[20:21], s[6:7], v[18:19]
	v_add_f64 v[16:17], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_fma_f64 v[18:19], v[20:21], s[4:5], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[25:26], v[18:19]
	v_add_f64 v[22:23], v[16:17], -v[25:26]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
.LBB1_9:                                ; %_ZL3cosd.exit.i
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[20:21], v[16:17], v[16:17]
	s_mov_b32 s4, 0xb42fdfa7
	s_mov_b32 s6, 0xf9a43bb8
	s_mov_b32 s5, 0xbe5ae600
	s_mov_b32 s7, 0x3de5e0b2
	s_mov_b32 s8, 0x796cde01
	s_mov_b32 s9, 0x3ec71de3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[31:32], v[18:19], 0.5
	v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x1f8
	v_fma_f64 v[22:23], v[20:21], s[6:7], s[4:5]
	v_mul_f64 v[27:28], v[20:21], 0.5
	s_mov_b32 s4, 0x9037ab78
	s_mov_b32 s6, 0x46cc5e42
	s_mov_b32 s5, 0x3e21eeb6
	s_mov_b32 s7, 0xbda907db
	v_mul_f64 v[33:34], v[16:17], -v[20:21]
	v_fma_f64 v[25:26], v[20:21], s[6:7], s[4:5]
	s_mov_b32 s6, 0x19e83e5c
	s_mov_b32 s7, 0xbf2a01a0
	s_mov_b32 s4, 0xa17f65f6
	s_mov_b32 s5, 0xbe927e4f
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[8:9]
	v_add_f64 v[29:30], -v[27:28], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[20:21], v[25:26], s[4:5]
	s_mov_b32 s4, 0x19f4ec90
	s_mov_b32 s5, 0x3efa01a0
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[6:7]
	s_mov_b32 s6, 0x11110bb3
	s_mov_b32 s7, 0x3f811111
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], -v[29:30], 1.0
	v_fma_f64 v[25:26], v[20:21], v[25:26], s[4:5]
	s_mov_b32 s4, 0x16c16967
	s_mov_b32 s5, 0xbf56c16c
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[6:7]
	v_add_f64 v[27:28], v[35:36], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[25:26], v[20:21], v[25:26], s[4:5]
	s_mov_b32 s5, 0x3fa55555
	s_mov_b32 s4, 0x55555555
	v_fma_f64 v[22:23], v[33:34], v[22:23], v[31:32]
	v_mul_f64 v[31:32], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[27:28], v[16:17], -v[18:19], v[27:28]
	v_fma_f64 v[25:26], v[20:21], v[25:26], s[4:5]
	s_mov_b32 s5, 0xbfc55555
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[20:21], v[22:23], -v[18:19]
                                        ; implicit-def: $vgpr22_vgpr23
	v_fma_f64 v[20:21], v[31:32], v[25:26], v[27:28]
                                        ; implicit-def: $vgpr25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[33:34], s[4:5], v[18:19]
	v_add_f64 v[20:21], v[29:30], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_and_b32_e32 v18, 1, v7
	v_cmp_eq_u32_e64 s0, 0, v18
	v_lshlrev_b32_e32 v18, 30, v7
	v_ashrrev_i32_e32 v7, 31, v6
	v_xor_b32_e32 v17, 0x80000000, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v16, v20, s0
	v_and_b32_e32 v20, 0x80000000, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[18:19], 4, v[6:7]
	v_cndmask_b32_e64 v17, v17, v21, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_add_co_u32 v6, s0, s2, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v17, v17, v20
	v_add_co_ci_u32_e64 v7, s0, s3, v19, s0
                                        ; implicit-def: $vgpr20_vgpr21
	v_cndmask_b32_e32 v17, 0x7ff80000, v17, vcc_lo
	global_store_b64 v[6:7], v[16:17], off
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB1_11
; %bb.10:
	v_cmp_le_f64_e64 s0, 0x7b000000, |v[4:5]|
	v_mov_b32_e32 v34, 0
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, v24, v15, s0
	v_cndmask_b32_e64 v14, v4, v14, s0
	v_mul_f64 v[20:21], v[12:13], v[14:15]
	v_mul_f64 v[22:23], v[10:11], v[14:15]
	v_mul_f64 v[32:33], v[8:9], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[12:13], v[14:15], -v[20:21]
	v_fma_f64 v[10:11], v[10:11], v[14:15], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[8:9], v[8:9], v[14:15], -v[32:33]
	v_add_f64 v[24:25], v[22:23], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[24:25], -v[22:23]
	v_add_f64 v[30:31], v[20:21], v[24:25]
	v_add_f64 v[28:29], v[24:25], -v[26:27]
	v_add_f64 v[12:13], v[12:13], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[26:27], v[30:31], -2
	v_add_f64 v[20:21], v[30:31], -v[20:21]
	v_add_f64 v[22:23], v[22:23], -v[28:29]
	v_add_f64 v[28:29], v[32:33], v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[26:27]|
	v_add_f64 v[20:21], v[24:25], -v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[22:23]
	v_fract_f64_e32 v[22:23], v[26:27]
	v_add_f64 v[24:25], v[28:29], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v23, 0, v23, s0
	v_cndmask_b32_e64 v22, 0, v22, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[22:23], v[22:23], 2
	v_add_f64 v[26:27], v[20:21], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[26:27], v[22:23]
	v_add_f64 v[14:15], v[26:27], -v[20:21]
	v_cmp_gt_f64_e64 s0, 0, v[30:31]
	v_add_f64 v[30:31], v[28:29], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[24:25], -v[14:15]
	v_cndmask_b32_e64 v35, 0, 0x40100000, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[39:40], v[28:29], -v[30:31]
	v_add_f64 v[10:11], v[10:11], -v[30:31]
	v_add_f64 v[22:23], v[22:23], v[34:35]
	v_add_f64 v[35:36], v[24:25], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[32:33], -v[39:40]
	v_add_f64 v[37:38], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[41:42], v[24:25], -v[35:36]
	v_add_f64 v[12:13], v[12:13], -v[35:36]
	v_add_f64 v[10:11], v[10:11], v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v37, v[37:38]
	v_add_f64 v[28:29], v[28:29], -v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[35:36], v37
	v_add_f64 v[12:13], v[12:13], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], -v[35:36]
	v_add_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[26:27], v[22:23]
	v_add_f64 v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[12:13], -v[22:23]
	v_cmp_le_f64_e64 s0, 0.5, v[12:13]
	v_add_f64 v[8:9], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[26:27], -v[10:11]
	v_cndmask_b32_e64 v35, 0, 0x3ff00000, s0
	v_add_co_ci_u32_e64 v25, s1, 0, v37, s0
	s_mov_b32 s0, 0x54442d18
	s_mov_b32 s1, 0x3ff921fb
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], v[10:11]
	v_add_f64 v[10:11], v[12:13], -v[34:35]
	v_add_f64 v[12:13], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[12:13], s[0:1]
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	v_fma_f64 v[20:21], v[12:13], s[0:1], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[8:9], -v[10:11]
	v_fma_f64 v[10:11], v[12:13], s[6:7], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], s[0:1], v[10:11]
	v_add_f64 v[20:21], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[20:21], -v[14:15]
	v_add_f64 v[22:23], v[8:9], -v[10:11]
.LBB1_11:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB1_13
; %bb.12:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[8:9], |v[4:5]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[8:9], v[8:9]
	v_fma_f64 v[10:11], v[8:9], s[4:5], |v[4:5]|
	v_mul_f64 v[12:13], v[8:9], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v25, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[8:9], s[6:7], v[10:11]
	v_add_f64 v[14:15], v[10:11], v[12:13]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_fma_f64 v[12:13], v[8:9], s[6:7], v[12:13]
	v_add_f64 v[10:11], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	v_fma_f64 v[10:11], v[8:9], s[4:5], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[22:23], v[10:11]
	v_add_f64 v[12:13], v[20:21], -v[22:23]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[22:23], v[10:11], -v[12:13]
.LBB1_13:                               ; %_Z15compute_twiddleP7complexPi.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[8:9], v[20:21], v[20:21]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s4, 0xf9a43bb8
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s5, 0x3de5e0b2
	s_mov_b32 s6, 0x796cde01
	s_mov_b32 s7, 0x3ec71de3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[28:29], v[22:23], 0.5
	v_lshlrev_b32_e32 v4, 30, v25
	v_xor_b32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v4, 0x80000000, v4
	v_fma_f64 v[10:11], v[8:9], s[4:5], s[0:1]
	s_mov_b32 s0, 0x9037ab78
	s_mov_b32 s4, 0x46cc5e42
	s_mov_b32 s1, 0x3e21eeb6
	s_mov_b32 s5, 0xbda907db
	v_mul_f64 v[14:15], v[8:9], 0.5
	v_fma_f64 v[12:13], v[8:9], s[4:5], s[0:1]
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s4, 0x19e83e5c
	s_mov_b32 s1, 0xbe927e4f
	s_mov_b32 s5, 0xbf2a01a0
	v_mul_f64 v[30:31], v[20:21], -v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[6:7]
	v_add_f64 v[26:27], -v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[0:1]
	s_mov_b32 s0, 0x19f4ec90
	s_mov_b32 s1, 0x3efa01a0
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[4:5]
	s_mov_b32 s4, 0x11110bb3
	s_mov_b32 s5, 0x3f811111
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], -v[26:27], 1.0
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[4:5]
	v_add_f64 v[14:15], v[32:33], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[0:1]
	s_mov_b32 s1, 0x3fa55555
	s_mov_b32 s0, 0x55555555
	v_fma_f64 v[10:11], v[30:31], v[10:11], v[28:29]
	v_mul_f64 v[28:29], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[14:15], v[20:21], -v[22:23], v[14:15]
	v_fma_f64 v[12:13], v[8:9], v[12:13], s[0:1]
	s_mov_b32 s1, 0xbfc55555
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], v[10:11], -v[22:23]
	v_fma_f64 v[10:11], v[28:29], v[12:13], v[14:15]
	v_and_b32_e32 v12, 1, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[30:31], s[0:1], v[8:9]
	v_cmp_eq_u32_e64 s0, 0, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[26:27], v[10:11]
	v_add_f64 v[8:9], v[20:21], -v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, v11, v9, s0
	v_cndmask_b32_e64 v8, v10, v8, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v9, v5, v4
	v_add_co_u32 v4, s0, s2, v18
	v_add_co_ci_u32_e64 v5, s0, s3, v19, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v12, 0, v8, vcc_lo
	v_cndmask_b32_e32 v13, 0x7ff80000, v9, vcc_lo
	global_store_b64 v[4:5], v[12:13], off offset:8
	global_load_b128 v[8:11], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[4:5], v[10:11], v[12:13]
	v_mul_f64 v[12:13], v[8:9], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[8:9], v[16:17], -v[4:5]
	v_fma_f64 v[10:11], v[10:11], v[16:17], v[12:13]
	global_store_b128 v[0:1], v[8:11], off
	global_load_b128 v[12:15], v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[8:9], v[8:9], v[12:13]
	v_add_f64 v[10:11], v[10:11], v[14:15]
	global_store_b128 v[6:7], v[8:11], off
	global_load_b128 v[2:5], v[2:3], off
	global_load_b128 v[8:11], v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[2:3], -v[8:9]
	v_add_f64 v[2:3], v[4:5], -v[10:11]
	v_add_co_u32 v4, vcc_lo, 0x20000, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
.LBB1_14:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14sum_RegressionP7complexS0_S0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 24
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z14sum_RegressionP7complexS0_S0_, .Lfunc_end1-_Z14sum_RegressionP7complexS0_S0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3504
; NumSgprs: 18
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z16compute_Even_OddP7complexS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z16compute_Even_OddP7complexS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     53
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 24
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14sum_RegressionP7complexS0_S0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14sum_RegressionP7complexS0_S0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
